August 2015 - U-Boot

[U-Boot] pull request: u-boot-uniphier/master
by Masahiro Yamada 30 Aug '15

30 Aug '15

Hi Tom, This pull request fixes three boards that have been broken since the recent nand-flash pull-req. Some other fixes, OF_CONTROL on SPL, and new SoC code, too. The following changes since commit a679cc0118f6bec16c82d2c44f8a980f6f319bde: tools/atmelimage.c: Fix warning when debug is enabled (2015-08-28 14:01:11 -0400) are available in the git repository at: git://git.denx.de/u-boot-uniphier.git master for you to fetch changes up to f875bbb49111c308b90b9ca74d1b79f69498b278: ARM: dts: uniphier: add ProXstream2 and PH1-LD6b SoC/board support (2015-08-31 00:29:23 +0900) ---------------------------------------------------------------- Masahiro Yamada (9): mtd: denali_spl: do not allocate page_buffer in .bss section ARM: uniphier: fix build error when CONFIG_DEBUG_LL is defined ARM: uniphier: remove unused macro ARM: uniphier: select SPL_DM rather than default in defconfig ARM: uniphier: enable SPL_OF_CONTROL serial: uniphier: drop platform data support ARM: dts: uniphier: sync with Linux ARM: dts: uniphier: add PH1-Pro5 SoC support ARM: dts: uniphier: add ProXstream2 and PH1-LD6b SoC/board support arch/arm/Kconfig | 2 + arch/arm/dts/Makefile | 5 +- arch/arm/dts/uniphier-ph1-ld4-ref.dts | 29 +++--- arch/arm/dts/uniphier-ph1-ld4.dtsi | 95 +++++++++++++++---- arch/arm/dts/uniphier-ph1-ld6b-ref.dts | 59 ++++++++++++ arch/arm/dts/uniphier-ph1-ld6b.dtsi | 31 +++++++ arch/arm/dts/uniphier-ph1-pro4-ref.dts | 37 +++++--- arch/arm/dts/uniphier-ph1-pro4.dtsi | 108 ++++++++++++++++++---- arch/arm/dts/uniphier-ph1-pro5.dtsi | 216 +++++++++++++++++++++++++++++++++++++++++++ arch/arm/dts/uniphier-ph1-sld3-ref.dts | 39 +++++--- arch/arm/dts/uniphier-ph1-sld3.dtsi | 66 +++++++++---- arch/arm/dts/uniphier-ph1-sld8-ref.dts | 33 ++++--- arch/arm/dts/uniphier-ph1-sld8.dtsi | 95 +++++++++++++++---- arch/arm/dts/uniphier-pinctrl.dtsi | 105 +++++++++++++++++++++ arch/arm/dts/uniphier-proxstream2.dtsi | 241 ++++++++++++++++++++++++++++++++++++++++++++++++ arch/arm/mach-uniphier/ph1-ld4/Makefile | 1 - arch/arm/mach-uniphier/ph1-ld4/platdevice.c | 15 --- arch/arm/mach-uniphier/ph1-pro4/Makefile | 1 - arch/arm/mach-uniphier/ph1-pro4/platdevice.c | 15 --- arch/arm/mach-uniphier/ph1-sld3/Makefile | 1 - arch/arm/mach-uniphier/ph1-sld3/lowlevel_debug.S | 2 + arch/arm/mach-uniphier/ph1-sld3/platdevice.c | 1 - arch/arm/mach-uniphier/ph1-sld8/platdevice.c | 15 --- configs/ph1_ld4_defconfig | 1 - configs/ph1_pro4_defconfig | 1 - configs/ph1_sld3_defconfig | 1 - configs/ph1_sld8_defconfig | 1 - doc/README.uniphier | 10 +- drivers/mtd/nand/denali_spl.c | 32 +++---- drivers/serial/serial_uniphier.c | 41 +++----- include/configs/uniphier.h | 4 +- include/dm/platform_data/serial-uniphier.h | 18 ---- 32 files changed, 1079 insertions(+), 242 deletions(-) create mode 100644 arch/arm/dts/uniphier-ph1-ld6b-ref.dts create mode 100644 arch/arm/dts/uniphier-ph1-ld6b.dtsi create mode 100644 arch/arm/dts/uniphier-ph1-pro5.dtsi create mode 100644 arch/arm/dts/uniphier-pinctrl.dtsi create mode 100644 arch/arm/dts/uniphier-proxstream2.dtsi delete mode 100644 arch/arm/mach-uniphier/ph1-ld4/platdevice.c delete mode 100644 arch/arm/mach-uniphier/ph1-pro4/platdevice.c delete mode 100644 arch/arm/mach-uniphier/ph1-sld3/platdevice.c delete mode 100644 arch/arm/mach-uniphier/ph1-sld8/platdevice.c delete mode 100644 include/dm/platform_data/serial-uniphier.h -- Best Regards Masahiro Yamada

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[U-Boot] [PATCH 1/3] ARM: dts: uniphier: sync with Linux
by Masahiro Yamada 30 Aug '15

30 Aug '15

This commit imports device tree updates from Linux. It eventually adds pinctrl-related nodes and properties. Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- arch/arm/dts/uniphier-ph1-ld4-ref.dts | 22 ++++--- arch/arm/dts/uniphier-ph1-ld4.dtsi | 95 +++++++++++++++++++++++------ arch/arm/dts/uniphier-ph1-pro4-ref.dts | 30 ++++++--- arch/arm/dts/uniphier-ph1-pro4.dtsi | 108 +++++++++++++++++++++++++++------ arch/arm/dts/uniphier-ph1-sld3-ref.dts | 32 +++++++--- arch/arm/dts/uniphier-ph1-sld3.dtsi | 66 ++++++++++++++------ arch/arm/dts/uniphier-ph1-sld8-ref.dts | 26 +++++--- arch/arm/dts/uniphier-ph1-sld8.dtsi | 95 +++++++++++++++++++++++------ arch/arm/dts/uniphier-pinctrl.dtsi | 105 ++++++++++++++++++++++++++++++++ 9 files changed, 472 insertions(+), 107 deletions(-) create mode 100644 arch/arm/dts/uniphier-pinctrl.dtsi diff --git a/arch/arm/dts/uniphier-ph1-ld4-ref.dts b/arch/arm/dts/uniphier-ph1-ld4-ref.dts index 7c36581..20f2e9a 100644 --- a/arch/arm/dts/uniphier-ph1-ld4-ref.dts +++ b/arch/arm/dts/uniphier-ph1-ld4-ref.dts @@ -20,15 +20,15 @@ }; chosen { - bootargs = "console=ttyPS0,115200 earlyprintk"; - stdout-path = &uart0; + bootargs = "console=ttyS0,115200"; + stdout-path = &serial0; }; aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + serial3 = &serial3; i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2; @@ -36,11 +36,15 @@ }; }; -&uart0 { +&serial0 { status = "okay"; }; -&uart1 { +&serial2 { + status = "okay"; +}; + +&serial3 { status = "okay"; }; @@ -57,6 +61,6 @@ }; /* for U-boot only */ -&uart0 { +&serial0 { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/uniphier-ph1-ld4.dtsi b/arch/arm/dts/uniphier-ph1-ld4.dtsi index 39d7b24..5f12e10 100644 --- a/arch/arm/dts/uniphier-ph1-ld4.dtsi +++ b/arch/arm/dts/uniphier-ph1-ld4.dtsi @@ -28,6 +28,18 @@ compatible = "fixed-clock"; clock-frequency = <50000000>; }; + + uart_clk: uart_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <36864000>; + }; + + iobus_clk: iobus_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + }; }; soc { @@ -43,68 +55,100 @@ #size-cells = <1>; }; - uart0: serial@54006800 { + serial0: serial@54006800 { compatible = "socionext,uniphier-uart"; status = "disabled"; - reg = <0x54006800 0x20>; + reg = <0x54006800 0x40>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + interrupts = <0 33 4>; + clocks = <&uart_clk>; clock-frequency = <36864000>; }; - uart1: serial@54006900 { + serial1: serial@54006900 { compatible = "socionext,uniphier-uart"; status = "disabled"; - reg = <0x54006900 0x20>; + reg = <0x54006900 0x40>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + interrupts = <0 35 4>; + clocks = <&uart_clk>; clock-frequency = <36864000>; }; - uart2: serial@54006a00 { + serial2: serial@54006a00 { compatible = "socionext,uniphier-uart"; status = "disabled"; - reg = <0x54006a00 0x20>; + reg = <0x54006a00 0x40>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + interrupts = <0 37 4>; + clocks = <&uart_clk>; clock-frequency = <36864000>; }; - uart3: serial@54006b00 { + serial3: serial@54006b00 { compatible = "socionext,uniphier-uart"; status = "disabled"; - reg = <0x54006b00 0x20>; + reg = <0x54006b00 0x40>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + interrupts = <0 29 4>; + clocks = <&uart_clk>; clock-frequency = <36864000>; }; i2c0: i2c@58400000 { compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58400000 0x40>; #address-cells = <1>; #size-cells = <0>; - reg = <0x58400000 0x40>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + interrupts = <0 41 1>; + clocks = <&iobus_clk>; clock-frequency = <100000>; - status = "disabled"; }; i2c1: i2c@58480000 { compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58480000 0x40>; #address-cells = <1>; #size-cells = <0>; - reg = <0x58480000 0x40>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + interrupts = <0 42 1>; + clocks = <&iobus_clk>; clock-frequency = <100000>; - status = "disabled"; }; + /* chip-internal connection for DMD */ i2c2: i2c@58500000 { compatible = "socionext,uniphier-i2c"; + reg = <0x58500000 0x40>; #address-cells = <1>; #size-cells = <0>; - reg = <0x58500000 0x40>; - clock-frequency = <100000>; - status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + interrupts = <0 43 1>; + clocks = <&iobus_clk>; + clock-frequency = <400000>; }; i2c3: i2c@58580000 { compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58580000 0x40>; #address-cells = <1>; #size-cells = <0>; - reg = <0x58580000 0x40>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + interrupts = <0 44 1>; + clocks = <&iobus_clk>; clock-frequency = <100000>; - status = "disabled"; }; system-bus-controller-misc@59800000 { @@ -117,18 +161,33 @@ compatible = "socionext,uniphier-ehci", "generic-ehci"; status = "disabled"; reg = <0x5a800100 0x100>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>; + interrupts = <0 80 4>; }; usb1: usb@5a810100 { compatible = "socionext,uniphier-ehci", "generic-ehci"; status = "disabled"; reg = <0x5a810100 0x100>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + interrupts = <0 81 4>; }; usb2: usb@5a820100 { compatible = "socionext,uniphier-ehci", "generic-ehci"; status = "disabled"; reg = <0x5a820100 0x100>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2>; + interrupts = <0 82 4>; + }; + + pinctrl: pinctrl@5f801000 { + compatible = "socionext,ph1-ld4-pinctrl", + "syscon"; + reg = <0x5f801000 0xe00>; }; timer@60000200 { @@ -160,3 +219,5 @@ }; }; }; + +/include/ "uniphier-pinctrl.dtsi" diff --git a/arch/arm/dts/uniphier-ph1-pro4-ref.dts b/arch/arm/dts/uniphier-ph1-pro4-ref.dts index fd3e8c6..ec1117d 100644 --- a/arch/arm/dts/uniphier-ph1-pro4-ref.dts +++ b/arch/arm/dts/uniphier-ph1-pro4-ref.dts @@ -20,15 +20,15 @@ }; chosen { - bootargs = "console=ttyPS0,115200 earlyprintk"; - stdout-path = &uart0; + bootargs = "console=ttyS0,115200"; + stdout-path = &serial0; }; aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + serial3 = &serial3; i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2; @@ -39,11 +39,15 @@ }; }; -&uart0 { +&serial0 { status = "okay"; }; -&uart1 { +&serial1 { + status = "okay"; +}; + +&serial2 { status = "okay"; }; @@ -55,7 +59,15 @@ status = "okay"; }; +&usb2 { + status = "okay"; +}; + +&usb3 { + status = "okay"; +}; + /* for U-boot only */ -&uart0 { +&serial0 { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/uniphier-ph1-pro4.dtsi b/arch/arm/dts/uniphier-ph1-pro4.dtsi index f06906c..a57f8ae 100644 --- a/arch/arm/dts/uniphier-ph1-pro4.dtsi +++ b/arch/arm/dts/uniphier-ph1-pro4.dtsi @@ -35,6 +35,18 @@ compatible = "fixed-clock"; clock-frequency = <50000000>; }; + + uart_clk: uart_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <73728000>; + }; + + i2c_clk: i2c_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; }; soc { @@ -50,88 +62,124 @@ #size-cells = <1>; }; - uart0: serial@54006800 { + serial0: serial@54006800 { compatible = "socionext,uniphier-uart"; status = "disabled"; - reg = <0x54006800 0x20>; + reg = <0x54006800 0x40>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + interrupts = <0 33 4>; + clocks = <&uart_clk>; clock-frequency = <73728000>; }; - uart1: serial@54006900 { + serial1: serial@54006900 { compatible = "socionext,uniphier-uart"; status = "disabled"; - reg = <0x54006900 0x20>; + reg = <0x54006900 0x40>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + interrupts = <0 35 4>; + clocks = <&uart_clk>; clock-frequency = <73728000>; }; - uart2: serial@54006a00 { + serial2: serial@54006a00 { compatible = "socionext,uniphier-uart"; status = "disabled"; - reg = <0x54006a00 0x20>; + reg = <0x54006a00 0x40>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + interrupts = <0 37 4>; + clocks = <&uart_clk>; clock-frequency = <73728000>; }; - uart3: serial@54006b00 { + serial3: serial@54006b00 { compatible = "socionext,uniphier-uart"; status = "disabled"; - reg = <0x54006b00 0x20>; + reg = <0x54006b00 0x40>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + interrupts = <0 29 4>; + clocks = <&uart_clk>; clock-frequency = <73728000>; }; i2c0: i2c@58780000 { compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58780000 0x80>; #address-cells = <1>; #size-cells = <0>; - reg = <0x58780000 0x80>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + interrupts = <0 41 4>; + clocks = <&i2c_clk>; clock-frequency = <100000>; - status = "disabled"; }; i2c1: i2c@58781000 { compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58781000 0x80>; #address-cells = <1>; #size-cells = <0>; - reg = <0x58781000 0x80>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + interrupts = <0 42 4>; + clocks = <&i2c_clk>; clock-frequency = <100000>; - status = "disabled"; }; i2c2: i2c@58782000 { compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58782000 0x80>; #address-cells = <1>; #size-cells = <0>; - reg = <0x58782000 0x80>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + interrupts = <0 43 4>; + clocks = <&i2c_clk>; clock-frequency = <100000>; - status = "disabled"; }; i2c3: i2c@58783000 { compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58783000 0x80>; #address-cells = <1>; #size-cells = <0>; - reg = <0x58783000 0x80>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + interrupts = <0 44 4>; + clocks = <&i2c_clk>; clock-frequency = <100000>; - status = "disabled"; }; /* i2c4 does not exist */ + /* chip-internal connection for DMD */ i2c5: i2c@58785000 { compatible = "socionext,uniphier-fi2c"; + reg = <0x58785000 0x80>; #address-cells = <1>; #size-cells = <0>; - reg = <0x58785000 0x80>; + interrupts = <0 25 4>; + clocks = <&i2c_clk>; clock-frequency = <400000>; - status = "ok"; }; + /* chip-internal connection for HDMI */ i2c6: i2c@58786000 { compatible = "socionext,uniphier-fi2c"; + reg = <0x58786000 0x80>; #address-cells = <1>; #size-cells = <0>; - reg = <0x58786000 0x80>; + interrupts = <0 26 4>; + clocks = <&i2c_clk>; clock-frequency = <400000>; - status = "ok"; }; system-bus-controller-misc@59800000 { @@ -144,24 +192,42 @@ compatible = "socionext,uniphier-ehci", "generic-ehci"; status = "disabled"; reg = <0x5a800100 0x100>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2>; + interrupts = <0 80 4>; }; usb3: usb@5a810100 { compatible = "socionext,uniphier-ehci", "generic-ehci"; status = "disabled"; reg = <0x5a810100 0x100>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb3>; + interrupts = <0 81 4>; }; usb0: usb@65a00000 { compatible = "socionext,uniphier-xhci", "generic-xhci"; status = "disabled"; reg = <0x65a00000 0x100>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>; + interrupts = <0 134 4>; }; usb1: usb@65c00000 { compatible = "socionext,uniphier-xhci", "generic-xhci"; status = "disabled"; reg = <0x65c00000 0x100>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + interrupts = <0 135 4>; + }; + + pinctrl: pinctrl@5f801000 { + compatible = "socionext,ph1-pro4-pinctrl", + "syscon"; + reg = <0x5f801000 0xe00>; }; timer@60000200 { @@ -193,3 +259,5 @@ }; }; }; + +/include/ "uniphier-pinctrl.dtsi" diff --git a/arch/arm/dts/uniphier-ph1-sld3-ref.dts b/arch/arm/dts/uniphier-ph1-sld3-ref.dts index 2406bfc..c760b6d 100644 --- a/arch/arm/dts/uniphier-ph1-sld3-ref.dts +++ b/arch/arm/dts/uniphier-ph1-sld3-ref.dts @@ -16,30 +16,36 @@ memory { device_type = "memory"; - reg = <0x80000000 0x40000000>; + reg = <0x80000000 0x20000000 + 0xc0000000 0x20000000>; }; chosen { - bootargs = "console=ttyPS0,115200 earlyprintk"; - stdout-path = &uart0; + bootargs = "console=ttyS0,115200"; + stdout-path = &serial0; }; aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2; i2c3 = &i2c3; + i2c4 = &i2c4; }; }; -&uart0 { +&serial0 { status = "okay"; }; -&uart1 { +&serial1 { + status = "okay"; +}; + +&serial2 { status = "okay"; }; @@ -55,7 +61,15 @@ status = "okay"; }; +&usb2 { + status = "okay"; +}; + +&usb3 { + status = "okay"; +}; + /* for U-boot only */ -&uart0 { +&serial0 { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/uniphier-ph1-sld3.dtsi b/arch/arm/dts/uniphier-ph1-sld3.dtsi index 5e29436..f481521 100644 --- a/arch/arm/dts/uniphier-ph1-sld3.dtsi +++ b/arch/arm/dts/uniphier-ph1-sld3.dtsi @@ -35,6 +35,18 @@ compatible = "fixed-clock"; clock-frequency = <50000000>; }; + + uart_clk: uart_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <36864000>; + }; + + iobus_clk: iobus_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + }; }; soc { @@ -72,70 +84,86 @@ <0x20000100 0x100>; }; - uart0: serial@54006800 { + serial0: serial@54006800 { compatible = "socionext,uniphier-uart"; status = "disabled"; - reg = <0x54006800 0x20>; + reg = <0x54006800 0x40>; + interrupts = <0 33 4>; + clocks = <&uart_clk>; clock-frequency = <36864000>; }; - uart1: serial@54006900 { + serial1: serial@54006900 { compatible = "socionext,uniphier-uart"; status = "disabled"; - reg = <0x54006900 0x20>; + reg = <0x54006900 0x40>; + interrupts = <0 35 4>; + clocks = <&uart_clk>; clock-frequency = <36864000>; }; - uart2: serial@54006a00 { + serial2: serial@54006a00 { compatible = "socionext,uniphier-uart"; status = "disabled"; - reg = <0x54006a00 0x20>; + reg = <0x54006a00 0x40>; + interrupts = <0 37 4>; + clocks = <&uart_clk>; clock-frequency = <36864000>; }; i2c0: i2c@58400000 { compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58400000 0x40>; #address-cells = <1>; #size-cells = <0>; - reg = <0x58400000 0x40>; + interrupts = <0 41 1>; + clocks = <&iobus_clk>; clock-frequency = <100000>; - status = "disabled"; }; i2c1: i2c@58480000 { compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58480000 0x40>; #address-cells = <1>; #size-cells = <0>; - reg = <0x58480000 0x40>; + interrupts = <0 42 1>; + clocks = <&iobus_clk>; clock-frequency = <100000>; - status = "disabled"; }; i2c2: i2c@58500000 { compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58500000 0x40>; #address-cells = <1>; #size-cells = <0>; - reg = <0x58500000 0x40>; + interrupts = <0 43 1>; + clocks = <&iobus_clk>; clock-frequency = <100000>; - status = "disabled"; }; i2c3: i2c@58580000 { compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58580000 0x40>; #address-cells = <1>; #size-cells = <0>; - reg = <0x58580000 0x40>; + interrupts = <0 44 1>; + clocks = <&iobus_clk>; clock-frequency = <100000>; - status = "disabled"; }; + /* chip-internal connection for DMD */ i2c4: i2c@58600000 { - compatible = "panasonic,uniphier-i2c"; + compatible = "socionext,uniphier-i2c"; + reg = <0x58600000 0x40>; #address-cells = <1>; #size-cells = <0>; - reg = <0x58600000 0x40>; + interrupts = <0 45 1>; + clocks = <&iobus_clk>; clock-frequency = <400000>; - status = "okay"; }; system-bus-controller-misc@59800000 { @@ -148,24 +176,28 @@ compatible = "socionext,uniphier-ehci", "generic-ehci"; status = "disabled"; reg = <0x5a800100 0x100>; + interrupts = <0 80 4>; }; usb1: usb@5a810100 { compatible = "socionext,uniphier-ehci", "generic-ehci"; status = "disabled"; reg = <0x5a810100 0x100>; + interrupts = <0 81 4>; }; usb2: usb@5a820100 { compatible = "socionext,uniphier-ehci", "generic-ehci"; status = "disabled"; reg = <0x5a820100 0x100>; + interrupts = <0 82 4>; }; usb3: usb@5a830100 { compatible = "socionext,uniphier-ehci", "generic-ehci"; status = "disabled"; reg = <0x5a830100 0x100>; + interrupts = <0 83 4>; }; nand: nand@f8000000 { diff --git a/arch/arm/dts/uniphier-ph1-sld8-ref.dts b/arch/arm/dts/uniphier-ph1-sld8-ref.dts index b7ed275..6269f9a 100644 --- a/arch/arm/dts/uniphier-ph1-sld8-ref.dts +++ b/arch/arm/dts/uniphier-ph1-sld8-ref.dts @@ -20,15 +20,15 @@ }; chosen { - bootargs = "console=ttyPS0,115200 earlyprintk"; - stdout-path = &uart0; + bootargs = "console=ttyS0,115200"; + stdout-path = &serial0; }; aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + serial3 = &serial3; i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2; @@ -36,11 +36,15 @@ }; }; -&uart0 { +&serial0 { status = "okay"; }; -&uart1 { +&serial2 { + status = "okay"; +}; + +&serial3 { status = "okay"; }; @@ -56,7 +60,11 @@ status = "okay"; }; +&usb2 { + status = "okay"; +}; + /* for U-boot only */ -&uart0 { +&serial0 { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/uniphier-ph1-sld8.dtsi b/arch/arm/dts/uniphier-ph1-sld8.dtsi index 15df50f..7d06f7e 100644 --- a/arch/arm/dts/uniphier-ph1-sld8.dtsi +++ b/arch/arm/dts/uniphier-ph1-sld8.dtsi @@ -28,6 +28,18 @@ compatible = "fixed-clock"; clock-frequency = <50000000>; }; + + uart_clk: uart_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <80000000>; + }; + + iobus_clk: iobus_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + }; }; soc { @@ -43,68 +55,100 @@ #size-cells = <1>; }; - uart0: serial@54006800 { + serial0: serial@54006800 { compatible = "socionext,uniphier-uart"; status = "disabled"; - reg = <0x54006800 0x20>; + reg = <0x54006800 0x40>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + interrupts = <0 33 4>; + clocks = <&uart_clk>; clock-frequency = <80000000>; }; - uart1: serial@54006900 { + serial1: serial@54006900 { compatible = "socionext,uniphier-uart"; status = "disabled"; - reg = <0x54006900 0x20>; + reg = <0x54006900 0x40>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + interrupts = <0 35 4>; + clocks = <&uart_clk>; clock-frequency = <80000000>; }; - uart2: serial@54006a00 { + serial2: serial@54006a00 { compatible = "socionext,uniphier-uart"; status = "disabled"; - reg = <0x54006a00 0x20>; + reg = <0x54006a00 0x40>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + interrupts = <0 37 4>; + clocks = <&uart_clk>; clock-frequency = <80000000>; }; - uart3: serial@54006b00 { + serial3: serial@54006b00 { compatible = "socionext,uniphier-uart"; status = "disabled"; - reg = <0x54006b00 0x20>; + reg = <0x54006b00 0x40>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + interrupts = <0 29 4>; + clocks = <&uart_clk>; clock-frequency = <80000000>; }; i2c0: i2c@58400000 { compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58400000 0x40>; #address-cells = <1>; #size-cells = <0>; - reg = <0x58400000 0x40>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + interrupts = <0 41 1>; + clocks = <&iobus_clk>; clock-frequency = <100000>; - status = "disabled"; }; i2c1: i2c@58480000 { compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58480000 0x40>; #address-cells = <1>; #size-cells = <0>; - reg = <0x58480000 0x40>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + interrupts = <0 42 1>; + clocks = <&iobus_clk>; clock-frequency = <100000>; - status = "disabled"; }; + /* chip-internal connection for DMD */ i2c2: i2c@58500000 { compatible = "socionext,uniphier-i2c"; + reg = <0x58500000 0x40>; #address-cells = <1>; #size-cells = <0>; - reg = <0x58500000 0x40>; - clock-frequency = <100000>; - status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + interrupts = <0 43 1>; + clocks = <&iobus_clk>; + clock-frequency = <400000>; }; i2c3: i2c@58580000 { compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58580000 0x40>; #address-cells = <1>; #size-cells = <0>; - reg = <0x58580000 0x40>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + interrupts = <0 44 1>; + clocks = <&iobus_clk>; clock-frequency = <100000>; - status = "disabled"; }; system-bus-controller-misc@59800000 { @@ -117,18 +161,33 @@ compatible = "socionext,uniphier-ehci", "generic-ehci"; status = "disabled"; reg = <0x5a800100 0x100>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>; + interrupts = <0 80 4>; }; usb1: usb@5a810100 { compatible = "socionext,uniphier-ehci", "generic-ehci"; status = "disabled"; reg = <0x5a810100 0x100>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + interrupts = <0 81 4>; }; usb2: usb@5a820100 { compatible = "socionext,uniphier-ehci", "generic-ehci"; status = "disabled"; reg = <0x5a820100 0x100>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2>; + interrupts = <0 82 4>; + }; + + pinctrl: pinctrl@5f801000 { + compatible = "socionext,ph1-sld8-pinctrl", + "syscon"; + reg = <0x5f801000 0xe00>; }; timer@60000200 { @@ -160,3 +219,5 @@ }; }; }; + +/include/ "uniphier-pinctrl.dtsi" diff --git a/arch/arm/dts/uniphier-pinctrl.dtsi b/arch/arm/dts/uniphier-pinctrl.dtsi new file mode 100644 index 0000000..f67445f --- /dev/null +++ b/arch/arm/dts/uniphier-pinctrl.dtsi @@ -0,0 +1,105 @@ +/* + * Device Tree Source for UniPhier SoCs default pinctrl settings + * + * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro(a)socionext.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +&pinctrl { + pinctrl_i2c0: i2c0_grp { + groups = "i2c0"; + function = "i2c0"; + }; + + pinctrl_i2c1: i2c1_grp { + groups = "i2c1"; + function = "i2c1"; + }; + + pinctrl_i2c2: i2c2_grp { + groups = "i2c2"; + function = "i2c2"; + }; + + pinctrl_i2c3: i2c3_grp { + groups = "i2c3"; + function = "i2c3"; + }; + + pinctrl_uart0: uart0_grp { + groups = "uart0"; + function = "uart0"; + }; + + pinctrl_uart1: uart1_grp { + groups = "uart1"; + function = "uart1"; + }; + + pinctrl_uart2: uart2_grp { + groups = "uart2"; + function = "uart2"; + }; + + pinctrl_uart3: uart3_grp { + groups = "uart3"; + function = "uart3"; + }; + + pinctrl_usb0: usb0_grp { + groups = "usb0"; + function = "usb0"; + }; + + pinctrl_usb1: usb1_grp { + groups = "usb1"; + function = "usb1"; + }; + + pinctrl_usb2: usb2_grp { + groups = "usb2"; + function = "usb2"; + }; + + pinctrl_usb3: usb3_grp { + groups = "usb3"; + function = "usb3"; + }; +}; -- 1.9.1

1 5

[U-Boot] [PATCH 1/3] ARM: uniphier: select SPL_DM rather than default in defconfig
by Masahiro Yamada 30 Aug '15

30 Aug '15

Now UniPhier SoCs highly depend on Driver Model for SPL, too. Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- arch/arm/Kconfig | 1 + configs/ph1_ld4_defconfig | 1 - configs/ph1_pro4_defconfig | 1 - configs/ph1_sld3_defconfig | 1 - configs/ph1_sld8_defconfig | 1 - 5 files changed, 1 insertion(+), 4 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index a99ae28..5f3af77 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -817,6 +817,7 @@ config ARCH_UNIPHIER select SPL select OF_CONTROL select DM + select SPL_DM select DM_SERIAL select DM_I2C help diff --git a/configs/ph1_ld4_defconfig b/configs/ph1_ld4_defconfig index f84dcdf..56c215f 100644 --- a/configs/ph1_ld4_defconfig +++ b/configs/ph1_ld4_defconfig @@ -17,7 +17,6 @@ CONFIG_CMD_PING=y CONFIG_CMD_TIME=y # CONFIG_CMD_MISC is not set CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM=y CONFIG_NAND_DENALI=y CONFIG_SYS_NAND_DENALI_64BIT=y CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8 diff --git a/configs/ph1_pro4_defconfig b/configs/ph1_pro4_defconfig index 2fc844d..7624c54 100644 --- a/configs/ph1_pro4_defconfig +++ b/configs/ph1_pro4_defconfig @@ -16,7 +16,6 @@ CONFIG_CMD_PING=y CONFIG_CMD_TIME=y # CONFIG_CMD_MISC is not set CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM=y CONFIG_NAND_DENALI=y CONFIG_SYS_NAND_DENALI_64BIT=y CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8 diff --git a/configs/ph1_sld3_defconfig b/configs/ph1_sld3_defconfig index 386a0d1..d495132 100644 --- a/configs/ph1_sld3_defconfig +++ b/configs/ph1_sld3_defconfig @@ -17,7 +17,6 @@ CONFIG_CMD_PING=y CONFIG_CMD_TIME=y # CONFIG_CMD_MISC is not set CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM=y CONFIG_NAND_DENALI=y CONFIG_SYS_NAND_DENALI_64BIT=y CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8 diff --git a/configs/ph1_sld8_defconfig b/configs/ph1_sld8_defconfig index 2af45d2..1a35a77 100644 --- a/configs/ph1_sld8_defconfig +++ b/configs/ph1_sld8_defconfig @@ -17,7 +17,6 @@ CONFIG_CMD_PING=y CONFIG_CMD_TIME=y # CONFIG_CMD_MISC is not set CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM=y CONFIG_NAND_DENALI=y CONFIG_SYS_NAND_DENALI_64BIT=y CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8 -- 1.9.1

3 12

[U-Boot] [PATCH] ARM: uniphier: remove unused macro
by Masahiro Yamada 30 Aug '15

30 Aug '15

This macro is not referenced at all. Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- include/configs/uniphier.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 908be26..b0a7daa 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -299,8 +299,6 @@ /* Open Firmware flat tree */ #define CONFIG_OF_LIBFDT -#define CONFIG_HAVE_ARM_SECURE - /* Memory Size & Mapping */ #define CONFIG_SYS_SDRAM_BASE CONFIG_SDRAM0_BASE -- 1.9.1

1 1

[U-Boot] [PATCH] ARM: uniphier: fix build error when CONFIG_DEBUG_LL is defined
by Masahiro Yamada 30 Aug '15

30 Aug '15

The build error happens if CONFIG_DEBUG_LL and CONFIG_MACH_PH1_SLD3 are both enabled. Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- arch/arm/mach-uniphier/ph1-sld3/lowlevel_debug.S | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-uniphier/ph1-sld3/lowlevel_debug.S b/arch/arm/mach-uniphier/ph1-sld3/lowlevel_debug.S index 9d1fd2c..41f67b7 100644 --- a/arch/arm/mach-uniphier/ph1-sld3/lowlevel_debug.S +++ b/arch/arm/mach-uniphier/ph1-sld3/lowlevel_debug.S @@ -10,6 +10,8 @@ #include <mach/bcu-regs.h> #include <mach/sc-regs.h> #include <mach/sg-regs.h> + +#define UART_CLK 36864000 #include <mach/debug-uart.S> ENTRY(setup_lowlevel_debug) -- 1.9.1

1 1

[U-Boot] [PATCH] mtd: denali: do not allocate page_buffer in .bss section
by Masahiro Yamada 30 Aug '15

30 Aug '15

Since commit 2580a2a7e719 ("mtd: nand: Increase max sizes of OOB and Page size"), three boards (ph1_ld4, ph1_pro4, ph1_sld8) fail to build with the following error message: arm-linux-gnueabi-ld.bfd: SPL image plus BSS too big They compile drivers/mtd/nand/denali_spl.c and it has a page_buffer as static data: static uint8_t page_buffer[NAND_MAX_PAGESIZE]; This buffer required 8KB in .bss section before that commit and now it has been increased to 16KB. Given limited code/memory size for SPL, it is not a good idea to allocate a page buffer statically. In the first place, the load address 'dst' can be used as a page buffer. Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- drivers/mtd/nand/denali_spl.c | 31 +++++++++++-------------------- 1 file changed, 11 insertions(+), 20 deletions(-) diff --git a/drivers/mtd/nand/denali_spl.c b/drivers/mtd/nand/denali_spl.c index e98f537..04c59b9 100644 --- a/drivers/mtd/nand/denali_spl.c +++ b/drivers/mtd/nand/denali_spl.c @@ -22,7 +22,6 @@ static void __iomem *denali_flash_reg = (void __iomem *)CONFIG_SYS_NAND_REGS_BASE; static const int flash_bank; -static uint8_t page_buffer[NAND_MAX_PAGESIZE]; static int page_size, oob_size, pages_per_block; static void index_addr(uint32_t address, uint32_t data) @@ -144,15 +143,15 @@ static int nand_read_page(void *buf, int page) return 0; } -static int nand_block_isbad(int block) +static int nand_block_isbad(void *buf, int block) { int ret; - ret = nand_read_oob(page_buffer, block * pages_per_block); + ret = nand_read_oob(buf, block * pages_per_block); if (ret < 0) return ret; - return page_buffer[CONFIG_SYS_NAND_BAD_BLOCK_POS] != 0xff; + return *((uint8_t *)buf + CONFIG_SYS_NAND_BAD_BLOCK_POS) != 0xff; } /* nand_init() - initialize data to make nand usable by SPL */ @@ -184,7 +183,7 @@ int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst) while (size) { if (force_bad_block_check || page == 0) { - ret = nand_block_isbad(block); + ret = nand_block_isbad(dst, block); if (ret < 0) return ret; @@ -196,24 +195,16 @@ int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst) force_bad_block_check = 0; - if (unlikely(column || size < page_size)) { - /* Partial page read */ - ret = nand_read_page(page_buffer, - block * pages_per_block + page); - if (ret < 0) - return ret; + ret = nand_read_page(dst, block * pages_per_block + page); + if (ret < 0) + return ret; - readlen = min(page_size - column, (int)size); - memcpy(dst, page_buffer, readlen); + readlen = min(page_size - column, (int)size); + if (unlikely(column)) { + /* Partial page read */ + memmove(dst, dst + column, readlen); column = 0; - } else { - ret = nand_read_page(dst, - block * pages_per_block + page); - if (ret < 0) - return ret; - - readlen = page_size; } size -= readlen; -- 1.9.1

1 1

[U-Boot] Uboot
by Antonio 30 Aug '15

30 Aug '15

I'm trying to upgrade a mk802II armv7 a10 to debian 8.1 but I'm having difficulity upgrading the kernel. I believe the kernel is compiling correctly but maybe it's the uboot that's incorrect. I realize that these boards have little to no support but I still enjoy working with them. Is there any information or solution that can help suceed in upgrading the kernel and uboot ? Respectfully, Antonio ____________________________________________________________ FREE ONLINE PHOTOSHARING - Share your photos online with your friends and family! Visit http://www.inbox.com/photosharing to find out more!

2 1

[U-Boot] [PATCH 0/2] Enable EXT support in SPL for all TI armv7 boards
by Guillaume GARDET 29 Aug '15

29 Aug '15

First patch enables EXT support in SPL for all boards including 'ti_armv7_common.h' file, mostly TI armv7 boards and some OMAP boards from other vendors. To reduce size of MLO/SPL, in order to fit in SRAM (especially on OMAP3 boards), thumb build is used to build MLO/SPL. Second patch remove CONFIG_SPL_EXT_SUPPORT from ti_omap4_common.h since it is now in ti_armv7_common.h. Tested on Pandaboard (rev. A3) and Beagleboard xM (rev. B). Compilation tested on TI armv7 boards and OMAP boards from other vendors. Signed-off-by: Guillaume GARDET <guillaume.gardet(a)free.fr> Cc: Tom Rini <trini(a)konsulko.com> --- Guillaume GARDET (2): ti: armv7: enable EXT support in SPL ti: omap4: remove CONFIG_SPL_EXT_SUPPORT from ti_omap4_common.h since it is now in ti_armv7_common.h include/configs/ti_armv7_common.h | 5 +++++ include/configs/ti_omap4_common.h | 3 --- 2 files changed, 5 insertions(+), 3 deletions(-) -- 1.8.4.5

4 17

[U-Boot] [PATCH] thermal: imx: add imx7d soc thermal support
by Adrian Alonso 29 Aug '15

29 Aug '15

Add imx7 SoC thermal driver support Signed-off-by: Adrian Alonso <aalonso(a)freescale.com> --- drivers/thermal/imx_thermal.c | 86 ++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 81 insertions(+), 5 deletions(-) diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c index 7848dc3..1ef345f 100644 --- a/drivers/thermal/imx_thermal.c +++ b/drivers/thermal/imx_thermal.c @@ -25,6 +25,9 @@ #define FACTOR1 15976 #define FACTOR2 4297157 #define MEASURE_FREQ 327 +#define TEMPERATURE_MIN -40 +#define TEMPERATURE_HOT 85 +#define TEMPERATURE_MAX 125 #define TEMPSENSE0_TEMP_CNT_SHIFT 8 #define TEMPSENSE0_TEMP_CNT_MASK (0xfff << TEMPSENSE0_TEMP_CNT_SHIFT) @@ -41,7 +44,8 @@ struct thermal_data { int maxc; }; -static int read_cpu_temperature_mx6(struct udevice *dev) +#if CONFIG_MX6 +static int read_cpu_temperature(struct udevice *dev) { int temperature; unsigned int reg, n_meas; @@ -123,22 +127,87 @@ static int read_cpu_temperature_mx6(struct udevice *dev) return temperature; } +#elif defined(CONFIG_MX7) +static int read_cpu_temperature(struct udevice *dev) +{ + unsigned int reg, tmp, start; + unsigned int raw_25c, te1; + int temperature; + unsigned int *priv = dev_get_priv(dev); + u32 fuse = *priv; + struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *) + ANATOP_BASE_ADDR; + /* + * fuse data layout: + * [31:21] sensor value @ 25C + * [20:18] hot temperature value + * [17:9] sensor value of room + * [8:0] sensor value of hot + */ + + raw_25c = fuse >> 21; + if (raw_25c == 0) + raw_25c = 25; + + te1 = (fuse >> 9) & 0x1ff; + + /* + * now we only use single measure, every time we read + * the temperature, we will power on/down anadig thermal + * module + */ + writel(TEMPMON_HW_ANADIG_TEMPSENSE1_POWER_DOWN_MASK, &ccm_anatop->tempsense1_clr); + writel(PMU_REF_REFTOP_SELFBIASOFF_MASK, &ccm_anatop->ref_set); + + /* write measure freq */ + reg = readl(&ccm_anatop->tempsense1); + reg &= ~TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ_MASK; + reg |= TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ(MEASURE_FREQ); + writel(reg, &ccm_anatop->tempsense1); + + writel(TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_TEMP_MASK, &ccm_anatop->tempsense1_clr); + writel(TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK, &ccm_anatop->tempsense1_clr); + writel(TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_TEMP_MASK, &ccm_anatop->tempsense1_set); + + start = get_timer(0); + /* Wait max 100ms */ + do { + /* + * Since we can not rely on finish bit, use 1ms delay to get + * temperature. From RM, 17us is enough to get data, but + * to gurantee to get the data, delay 100ms here. + */ + reg = readl(&ccm_anatop->tempsense1); + tmp = (reg & TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_MASK) + >> TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_SHIFT; + } while (get_timer(0) < (start + 100)); + + writel(TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK, &ccm_anatop->tempsense1_clr); + + /* power down anatop thermal sensor */ + writel(TEMPMON_HW_ANADIG_TEMPSENSE1_POWER_DOWN_MASK, &ccm_anatop->tempsense1_set); + writel(PMU_REF_REFTOP_SELFBIASOFF_MASK, &ccm_anatop->ref_clr); + + /* Single point */ + temperature = tmp - (te1 - raw_25c); + + return temperature; +} +#endif int imx_thermal_get_temp(struct udevice *dev, int *temp) { struct thermal_data *priv = dev_get_priv(dev); int cpu_tmp = 0; - if (is_soc_type(MXC_SOC_MX6)) - cpu_tmp = read_cpu_temperature_mx6(dev); + cpu_tmp = read_cpu_temperature(dev); while (cpu_tmp >= priv->critical) { printf("CPU Temperature (%dC) too close to max (%dC)", cpu_tmp, priv->maxc); puts(" waiting...\n"); udelay(5000000); - if (is_soc_type(MXC_SOC_MX6)) - cpu_tmp = read_cpu_temperature_mx6(dev); + cpu_tmp = read_cpu_temperature(dev); } *temp = cpu_tmp; @@ -167,6 +236,13 @@ static int imx_thermal_probe(struct udevice *dev) fuse); return -EPERM; } + } else if (is_soc_type(MXC_SOC_MX7)) { + /* No Calibration data in FUSE? */ + if ((fuse & 0x3ffff) == 0) + return -EPERM; + /* We do not support 105C TE2 */ + if (((fuse & 0x1c0000) >> 18) == 0x6) + return -EPERM; } /* set critical cooling temp */ -- 2.1.4

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[U-Boot] [PATCH][v6] imx: imx7d: Add SoC system support
by Adrian Alonso 29 Aug '15

29 Aug '15

Add imx7d basic SoC system support Misc arch dependent functions for system bring up Signed-off-by: Adrian Alonso <aalonso(a)freescale.com> Signed-off-by: Peng Fan <Peng.Fan(a)freescale.com> Signed-off-by: Ye.Li <B37916(a)freescale.com> --- Changes for V2: Split from patch imx: imx7d: initial arch level support Changes for V3: Resend Changes for V4: Resend Changes for V5: Resend Changes for V6: - Remove set_epdc_qos, epdc support to be added in separate patch - Rework to reuse common code (cache settins, common init settings) - Add tem and speed get helper functions arch/arm/cpu/armv7/mx7/soc.c | 269 ++++++++++++++++++++++++++++ arch/arm/include/asm/arch-imx/cpu.h | 2 + arch/arm/include/asm/imx-common/boot_mode.h | 21 +++ 3 files changed, 292 insertions(+) create mode 100644 arch/arm/cpu/armv7/mx7/soc.c diff --git a/arch/arm/cpu/armv7/mx7/soc.c b/arch/arm/cpu/armv7/mx7/soc.c new file mode 100644 index 0000000..8d50149 --- /dev/null +++ b/arch/arm/cpu/armv7/mx7/soc.c @@ -0,0 +1,269 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <asm/imx-common/boot_mode.h> +#include <asm/imx-common/dma.h> +#include <asm/arch/crm_regs.h> +#include <dm.h> +#include <imx_thermal.h> + +struct src *src_reg = (struct src *)SRC_BASE_ADDR; + +#if defined(CONFIG_IMX_THERMAL) +static const struct imx_thermal_plat imx7_thermal_plat = { + .regs = (void *)ANATOP_BASE_ADDR, + .fuse_bank = 3, + .fuse_word = 3, +}; + +U_BOOT_DEVICE(imx7_thermal) = { + .name = "imx_thermal", + .platdata = &imx7_thermal_plat, +}; +#endif + +/* + * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440) + * defines a 2-bit SPEED_GRADING + */ +#define OCOTP_TESTER3_SPEED_SHIFT 8 +#define OCOTP_TESTER3_SPEED_800MHZ 0 +#define OCOTP_TESTER3_SPEED_850MHZ 1 +#define OCOTP_TESTER3_SPEED_1GHZ 2 + +u32 get_cpu_speed_grade_hz(void) +{ + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; + struct fuse_bank *bank = &ocotp->bank[1]; + struct fuse_bank1_regs *fuse = + (struct fuse_bank1_regs *)bank->fuse_regs; + uint32_t val; + + val = readl(&fuse->tester3); + val >>= OCOTP_TESTER3_SPEED_SHIFT; + val &= 0x3; + + switch(val) { + case OCOTP_TESTER3_SPEED_800MHZ: + return 792000000; + case OCOTP_TESTER3_SPEED_850MHZ: + return 852000000; + case OCOTP_TESTER3_SPEED_1GHZ: + return 996000000; + } + return 0; +} + +/* + * OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440) + * defines a 2-bit SPEED_GRADING + */ +#define OCOTP_TESTER3_TEMP_SHIFT 6 + +u32 get_cpu_temp_grade(int *minc, int *maxc) +{ + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; + struct fuse_bank *bank = &ocotp->bank[1]; + struct fuse_bank1_regs *fuse = + (struct fuse_bank1_regs *)bank->fuse_regs; + uint32_t val; + + val = readl(&fuse->tester3); + val >>= OCOTP_TESTER3_TEMP_SHIFT; + val &= 0x3; + + if (minc && maxc) { + if ( val == TEMP_AUTOMOTIVE) { + *minc = -40; + *maxc = 125; + } else if (val == TEMP_INDUSTRIAL) { + *minc = -40; + *maxc = 105; + } else if (val == TEMP_EXTCOMMERCIAL) { + *minc = -20; + *maxc = 105; + } else { + *minc = 0; + *maxc = 95; + } + } + return val; +} + +u32 get_cpu_rev(void) +{ + struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *) + ANATOP_BASE_ADDR; + u32 reg = readl(&ccm_anatop->digprog); + u32 type = (reg >> 16) & 0xff; + + reg &= 0xff; + return (type << 12) | reg; +} + +#ifdef CONFIG_REVISION_TAG +u32 __weak get_board_rev(void) +{ + return get_cpu_rev(); +} +#endif + +int arch_cpu_init(void) +{ + init_aips(); + + /* Disable PDE bit of WMCR register */ + imx_set_wdog_powerdown(false); + +#ifdef CONFIG_APBH_DMA + /* Start APBH DMA */ + mxs_dma_init(); +#endif + + return 0; +} + +#ifdef CONFIG_SERIAL_TAG +void get_board_serial(struct tag_serialnr *serialnr) +{ + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; + struct fuse_bank *bank = &ocotp->bank[0]; + struct fuse_bank0_regs *fuse = + (struct fuse_bank0_regs *)bank->fuse_regs; + + serialnr->low = fuse->tester0; + serialnr->high = fuse->tester1; +} +#endif + +#if defined(CONFIG_FEC_MXC) +void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) +{ + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; + struct fuse_bank *bank = &ocotp->bank[9]; + struct fuse_bank9_regs *fuse = + (struct fuse_bank9_regs *)bank->fuse_regs; + + if (0 == dev_id) { + u32 value = readl(&fuse->mac_addr1); + mac[0] = (value >> 8); + mac[1] = value; + + value = readl(&fuse->mac_addr0); + mac[2] = value >> 24; + mac[3] = value >> 16; + mac[4] = value >> 8; + mac[5] = value; + } else { + u32 value = readl(&fuse->mac_addr2); + mac[0] = value >> 24; + mac[1] = value >> 16; + mac[2] = value >> 8; + mac[3] = value; + + value = readl(&fuse->mac_addr1); + mac[4] = value >> 24; + mac[5] = value >> 16; + } +} +#endif + +void set_wdog_reset(struct wdog_regs *wdog) +{ + u32 reg = readw(&wdog->wcr); + /* + * Output WDOG_B signal to reset external pmic or POR_B decided by + * the board desgin. Without external reset, the peripherals/DDR/ + * PMIC are not reset, that may cause system working abnormal. + */ + reg = readw(&wdog->wcr); + reg |= 1 << 3; + /* + * WDZST bit is write-once only bit. Align this bit in kernel, + * otherwise kernel code will have no chance to set this bit. + */ + reg |= 1 << 0; + writew(reg, &wdog->wcr); +} + +/* + * cfg_val will be used for + * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0] + * After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0] + * to SBMR1, which will determine the boot device. + */ +const struct boot_mode soc_boot_modes[] = { + {"ecspi1:0", MAKE_CFGVAL(0x00, 0x60, 0x00, 0x00)}, + {"ecspi1:1", MAKE_CFGVAL(0x40, 0x62, 0x00, 0x00)}, + {"ecspi1:2", MAKE_CFGVAL(0x80, 0x64, 0x00, 0x00)}, + {"ecspi1:3", MAKE_CFGVAL(0xc0, 0x66, 0x00, 0x00)}, + + {"weim", MAKE_CFGVAL(0x00, 0x50, 0x00, 0x00)}, + {"qspi1", MAKE_CFGVAL(0x10, 0x40, 0x00, 0x00)}, + /* 4 bit bus width */ + {"usdhc1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)}, + {"usdhc2", MAKE_CFGVAL(0x10, 0x14, 0x00, 0x00)}, + {"usdhc3", MAKE_CFGVAL(0x10, 0x18, 0x00, 0x00)}, + {"mmc1", MAKE_CFGVAL(0x10, 0x20, 0x00, 0x00)}, + {"mmc2", MAKE_CFGVAL(0x10, 0x24, 0x00, 0x00)}, + {"mmc3", MAKE_CFGVAL(0x10, 0x28, 0x00, 0x00)}, + {NULL, 0}, +}; + +enum boot_device get_boot_device(void) +{ + struct bootrom_sw_info **p = + (struct bootrom_sw_info **)ROM_SW_INFO_ADDR; + + enum boot_device boot_dev = SD1_BOOT; + u8 boot_type = (*p)->boot_dev_type; + u8 boot_instance = (*p)->boot_dev_instance; + + switch (boot_type) { + case BOOT_TYPE_SD: + boot_dev = boot_instance + SD1_BOOT; + break; + case BOOT_TYPE_MMC: + boot_dev = boot_instance + MMC1_BOOT; + break; + case BOOT_TYPE_NAND: + boot_dev = NAND_BOOT; + break; + case BOOT_TYPE_QSPI: + boot_dev = QSPI_BOOT; + break; + case BOOT_TYPE_WEIM: + boot_dev = WEIM_NOR_BOOT; + break; + case BOOT_TYPE_SPINOR: + boot_dev = SPI_NOR_BOOT; + break; + default: + break; + } + + return boot_dev; +} + +void s_init(void) +{ +#if !defined CONFIG_SPL_BUILD + /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */ + asm volatile( + "mrc p15, 0, r0, c1, c0, 1\n" + "orr r0, r0, #1 << 6\n" + "mcr p15, 0, r0, c1, c0, 1\n"); +#endif + /* clock configuration. */ + clock_init(); + + return; +} diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index 033cd27..0292be7 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -15,8 +15,10 @@ #define MXC_CPU_MX6D 0x67 #define MXC_CPU_MX6DP 0x68 #define MXC_CPU_MX6QP 0x69 +#define MXC_CPU_MX7D 0x72 #define MXC_SOC_MX6 0x60 +#define MXC_SOC_MX7 0x70 #define CS0_128 0 #define CS0_64M_CS1_64M 1 diff --git a/arch/arm/include/asm/imx-common/boot_mode.h b/arch/arm/include/asm/imx-common/boot_mode.h index de0205c..a8239f2 100644 --- a/arch/arm/include/asm/imx-common/boot_mode.h +++ b/arch/arm/include/asm/imx-common/boot_mode.h @@ -9,6 +9,27 @@ #define MAKE_CFGVAL(cfg1, cfg2, cfg3, cfg4) \ ((cfg4) << 24) | ((cfg3) << 16) | ((cfg2) << 8) | (cfg1) +enum boot_device { + WEIM_NOR_BOOT, + ONE_NAND_BOOT, + PATA_BOOT, + SATA_BOOT, + I2C_BOOT, + SPI_NOR_BOOT, + SD1_BOOT, + SD2_BOOT, + SD3_BOOT, + SD4_BOOT, + MMC1_BOOT, + MMC2_BOOT, + MMC3_BOOT, + MMC4_BOOT, + NAND_BOOT, + QSPI_BOOT, + UNKNOWN_BOOT, + BOOT_DEV_NUM = UNKNOWN_BOOT, +}; + struct boot_mode { const char *name; unsigned cfg_val; -- 2.1.4

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