August 2015 - U-Boot

[U-Boot] [PATCH 2/2] armv8/ls2085aqds: enable 32KHz rtc output
by Priyanka Jain 02 Sep '15

02 Sep '15

Signed-off-by: Priyanka Jain <Priyanka.Jain(a)freescale.com> --- Based on git://git.denx.de/u-boot-fsl-qoriq board/freescale/ls2085aqds/ls2085aqds.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/board/freescale/ls2085aqds/ls2085aqds.c b/board/freescale/ls2085aqds/ls2085aqds.c index c492c7e..60cf480 100644 --- a/board/freescale/ls2085aqds/ls2085aqds.c +++ b/board/freescale/ls2085aqds/ls2085aqds.c @@ -16,6 +16,7 @@ #include <fsl-mc/fsl_mc.h> #include <environment.h> #include <i2c.h> +#include <rtc.h> #include <asm/arch-fsl-lsch3/soc.h> #include "../common/qixis.h" @@ -161,6 +162,7 @@ int board_init(void) gd->env_addr = (ulong)&default_environment[0]; #endif select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + rtc_enable_32khz_output(); return 0; } -- 1.7.4.1

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[U-Boot] [PATCH 1/2] rtc:ds3232/ds3231: Add support to generate 32KHz output
by Priyanka Jain 02 Sep '15

02 Sep '15

RTC devices can generate 32KHz output if for -DS3232 device, EN32KHz bit and BB32KHz bit are set -DS3231 device, EN32KHz bit is set, BB32KHz bit is don't care Patch adds rtc_enable_32khz_output() which when called will enable 32KHz output on 32KHz pin Signed-off-by: Priyanka Jain <Priyanka.Jain(a)freescale.com> --- Based on git://git.denx.de/u-boot-fsl-qoriq drivers/rtc/ds3231.c | 10 ++++++++++ include/rtc.h | 1 + 2 files changed, 11 insertions(+), 0 deletions(-) diff --git a/drivers/rtc/ds3231.c b/drivers/rtc/ds3231.c index c84bbc6..e5e1be1 100644 --- a/drivers/rtc/ds3231.c +++ b/drivers/rtc/ds3231.c @@ -49,6 +49,8 @@ #define RTC_STAT_BIT_A1F 0x1 /* Alarm 1 flag */ #define RTC_STAT_BIT_A2F 0x2 /* Alarm 2 flag */ #define RTC_STAT_BIT_OSF 0x80 /* Oscillator stop flag */ +#define RTC_STAT_BIT_BB32KHZ 0x40 /* Battery backed 32KHz Output */ +#define RTC_STAT_BIT_EN32KHZ 0x8 /* Enable 32KHz Output */ static uchar rtc_read (uchar reg); @@ -141,6 +143,14 @@ void rtc_reset (void) rtc_write (RTC_CTL_REG_ADDR, RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2); } +/* + * Enable 32KHz output + */ +void rtc_enable_32khz_output(void) +{ + rtc_write(RTC_STAT_REG_ADDR, + RTC_STAT_BIT_BB32KHZ | RTC_STAT_BIT_EN32KHZ); +} /* * Helper functions diff --git a/include/rtc.h b/include/rtc.h index bd8621d..69fe8d4 100644 --- a/include/rtc.h +++ b/include/rtc.h @@ -151,6 +151,7 @@ int rtc_write32(struct udevice *dev, unsigned int reg, u32 value); int rtc_get (struct rtc_time *); int rtc_set (struct rtc_time *); void rtc_reset (void); +void rtc_enable_32khz_output(void); /** * rtc_read8() - Read an 8-bit register -- 1.7.4.1

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[U-Boot] [PATCH][v2] thermal: imx: add imx7d soc thermal support
by Adrian Alonso 01 Sep '15

01 Sep '15

Add imx7 SoC thermal driver support Signed-off-by: Adrian Alonso <aalonso(a)freescale.com> --- Changes for V2: Fix build error for missin macro check ;P drivers/thermal/imx_thermal.c | 86 ++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 81 insertions(+), 5 deletions(-) diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c index 7848dc3..f3b0ac3 100644 --- a/drivers/thermal/imx_thermal.c +++ b/drivers/thermal/imx_thermal.c @@ -25,6 +25,9 @@ #define FACTOR1 15976 #define FACTOR2 4297157 #define MEASURE_FREQ 327 +#define TEMPERATURE_MIN -40 +#define TEMPERATURE_HOT 85 +#define TEMPERATURE_MAX 125 #define TEMPSENSE0_TEMP_CNT_SHIFT 8 #define TEMPSENSE0_TEMP_CNT_MASK (0xfff << TEMPSENSE0_TEMP_CNT_SHIFT) @@ -41,7 +44,8 @@ struct thermal_data { int maxc; }; -static int read_cpu_temperature_mx6(struct udevice *dev) +#if defined(CONFIG_MX6) +static int read_cpu_temperature(struct udevice *dev) { int temperature; unsigned int reg, n_meas; @@ -123,22 +127,87 @@ static int read_cpu_temperature_mx6(struct udevice *dev) return temperature; } +#elif defined(CONFIG_MX7) +static int read_cpu_temperature(struct udevice *dev) +{ + unsigned int reg, tmp, start; + unsigned int raw_25c, te1; + int temperature; + unsigned int *priv = dev_get_priv(dev); + u32 fuse = *priv; + struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *) + ANATOP_BASE_ADDR; + /* + * fuse data layout: + * [31:21] sensor value @ 25C + * [20:18] hot temperature value + * [17:9] sensor value of room + * [8:0] sensor value of hot + */ + + raw_25c = fuse >> 21; + if (raw_25c == 0) + raw_25c = 25; + + te1 = (fuse >> 9) & 0x1ff; + + /* + * now we only use single measure, every time we read + * the temperature, we will power on/down anadig thermal + * module + */ + writel(TEMPMON_HW_ANADIG_TEMPSENSE1_POWER_DOWN_MASK, &ccm_anatop->tempsense1_clr); + writel(PMU_REF_REFTOP_SELFBIASOFF_MASK, &ccm_anatop->ref_set); + + /* write measure freq */ + reg = readl(&ccm_anatop->tempsense1); + reg &= ~TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ_MASK; + reg |= TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ(MEASURE_FREQ); + writel(reg, &ccm_anatop->tempsense1); + + writel(TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_TEMP_MASK, &ccm_anatop->tempsense1_clr); + writel(TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK, &ccm_anatop->tempsense1_clr); + writel(TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_TEMP_MASK, &ccm_anatop->tempsense1_set); + + start = get_timer(0); + /* Wait max 100ms */ + do { + /* + * Since we can not rely on finish bit, use 1ms delay to get + * temperature. From RM, 17us is enough to get data, but + * to gurantee to get the data, delay 100ms here. + */ + reg = readl(&ccm_anatop->tempsense1); + tmp = (reg & TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_MASK) + >> TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_SHIFT; + } while (get_timer(0) < (start + 100)); + + writel(TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK, &ccm_anatop->tempsense1_clr); + + /* power down anatop thermal sensor */ + writel(TEMPMON_HW_ANADIG_TEMPSENSE1_POWER_DOWN_MASK, &ccm_anatop->tempsense1_set); + writel(PMU_REF_REFTOP_SELFBIASOFF_MASK, &ccm_anatop->ref_clr); + + /* Single point */ + temperature = tmp - (te1 - raw_25c); + + return temperature; +} +#endif int imx_thermal_get_temp(struct udevice *dev, int *temp) { struct thermal_data *priv = dev_get_priv(dev); int cpu_tmp = 0; - if (is_soc_type(MXC_SOC_MX6)) - cpu_tmp = read_cpu_temperature_mx6(dev); + cpu_tmp = read_cpu_temperature(dev); while (cpu_tmp >= priv->critical) { printf("CPU Temperature (%dC) too close to max (%dC)", cpu_tmp, priv->maxc); puts(" waiting...\n"); udelay(5000000); - if (is_soc_type(MXC_SOC_MX6)) - cpu_tmp = read_cpu_temperature_mx6(dev); + cpu_tmp = read_cpu_temperature(dev); } *temp = cpu_tmp; @@ -167,6 +236,13 @@ static int imx_thermal_probe(struct udevice *dev) fuse); return -EPERM; } + } else if (is_soc_type(MXC_SOC_MX7)) { + /* No Calibration data in FUSE? */ + if ((fuse & 0x3ffff) == 0) + return -EPERM; + /* We do not support 105C TE2 */ + if (((fuse & 0x1c0000) >> 18) == 0x6) + return -EPERM; } /* set critical cooling temp */ -- 2.1.4

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[U-Boot] [PATCH v5 0/5] Add support for Thumb-1 builds
by Albert ARIBAUD 01 Sep '15

01 Sep '15

This series implements essential changes for thumb-1 support and activates thumb-1 build for openrd and tricorder as a proof of concept as well as a fix to bring the image sizes of openrd and tricorder targets back under an acceptable limit. For other targets, some additional files might need to be forced to ARM building, notably architecture-specific instances of lowlevel_init.S or of cpu.c. This should be handled on a case-by-case basis. IMPORTANT NOTE: The whole set has been build-tested across all ARM targets and no build regression was detected. Patch 1 has been confirmed to be binary-invariant. Patch 2 has been build- and run-tested on ED Mini V2 (switched temporarily to Thumb build) and confirmed to be binary-invariant for non-thumb target Wireless Space. Patches 3, 4 and 5 have been build-tested BUT HAVE NOT BEEN RUN-TESTED. ********************************************************* Open-RD and Tricorder owners, PLEASE run-test this series and report on the mailing list whether the target works. ********************************************************* Changes in v5: - switched tricorder[_flash] to Thumb-1 build Changes in v4: - Made stm32f429-discovery explicitly state that it builds for Thumb Changes in v3: - added arch/arm/lib/mem{set,cpy}.S to the list of modules which should always be built in ARM state. - Selected HAS_THUMB2 for CPU_V7M. - Fixed invalidate_l2_cache() when building for Thumb-1. Changes in v2: - fixed a typo in the commit message - added file arch/arm/thumb1/include/asm/proc-armv/system.h, which overrides arch/arm/include/asm/proc-armv/system.h when building for Thumb-1 and provides non-functional but Thumb-compilable IRQ and FIQ related macros and functions. Albert ARIBAUD (5): stm32f429-discovery: add CONFIG_SYS_THUMB_BUILD arm: support Thumb-1 with CONFIG_SYS_THUMB_BUILD kirkwood: support CONFIG_SYS_THUMB_BUILD openrd: switch to CONFIG_SYS_THUMB_BUILD tricorder: switch to CONFIG_SYS_THUMB_BUILD Makefile | 2 + arch/arm/Kconfig | 5 ++ arch/arm/cpu/arm926ejs/Makefile | 11 ++++ arch/arm/cpu/arm926ejs/cache.c | 5 ++ arch/arm/include/asm/cache.h | 4 ++ arch/arm/lib/Makefile | 24 +++++++++ arch/arm/lib/cache.c | 11 ++++ arch/arm/lib/memcpy.S | 4 +- arch/arm/lib/memset.S | 2 +- arch/arm/mach-kirkwood/Makefile | 6 +++ arch/arm/mach-orion5x/Makefile | 10 ++++ arch/arm/thumb1/include/asm/proc-armv/system.h | 69 ++++++++++++++++++++++++++ examples/standalone/Makefile | 10 ++++ include/configs/openrd.h | 1 + include/configs/stm32f429-discovery.h | 1 + include/configs/tricorder.h | 1 + scripts/Makefile.lib | 3 +- 17 files changed, 165 insertions(+), 4 deletions(-) create mode 100644 arch/arm/thumb1/include/asm/proc-armv/system.h -- 2.1.0

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[U-Boot] [PATCH V2] mxc: ocotp fix hole in shadow registers
by Peng Fan 01 Sep '15

01 Sep '15

There is a hole in shadow registers address map of size 0x100 between bank 5 and bank 6 on iMX6QP, iMX6DQ, iMX6SDL, iMX6SX and iMX6UL. Bank 5 ends at 0x6F0 and Bank 6 starts at 0x800. When reading the fuses, we should account for this hole in address space. Similar hole exists between bank 14 and bank 15 of size 0x80 on iMX6QP, iMX6DQ, iMX6SDL and iMX6SX. Note: iMX6SL has only 0-7 banks and there is no hole. Note: iMX6UL doesn't have this one. When reading, we use register offset, so need to account for holes to get the correct address. When writing, we use bank/word index, there is no need to account for holes, always use bank/word index from fuse map. Signed-off-by: Peng Fan <Peng.Fan(a)freescale.com> Cc: Stefano Babic <sbabic(a)denx.de> Cc: Fabio Estevam <fabio.estevam(a)freescale.com> --- Changes v2: Discard is_cpu_type(MXC_CPU_MX7D), since 7D cpu type is still not upstreamed. arch/arm/include/asm/arch-mx6/imx-regs.h | 3 +- drivers/misc/mxc_ocotp.c | 78 ++++++++++++++++++++++++++++++-- 2 files changed, 75 insertions(+), 6 deletions(-) diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 4d84a9b..a685ed2 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -630,9 +630,10 @@ struct ocotp_regs { u32 version; u32 rsvd7[0xdb]; + /* fuse banks */ struct fuse_bank { u32 fuse_regs[0x20]; - } bank[16]; + } bank[0]; }; struct fuse_bank0_regs { diff --git a/drivers/misc/mxc_ocotp.c b/drivers/misc/mxc_ocotp.c index d9b02c7..65ff815 100644 --- a/drivers/misc/mxc_ocotp.c +++ b/drivers/misc/mxc_ocotp.c @@ -57,6 +57,68 @@ #define WRITE_POSTAMBLE_US 2 +#if defined(CONFIG_MX6) || defined(CONFIG_VF610) +#define FUSE_BANK_SIZE 0x80 +#ifdef CONFIG_MX6SL +#define FUSE_BANKS 8 +#else +#define FUSE_BANKS 16 +#endif +#elif defined CONFIG_MX7 +#define FUSE_BANK_SIZE 0x40 +#define FUSE_BANKS 16 +#else +#error "Unsupported architecture\n" +#endif + +#if defined(CONFIG_MX6) +#include <asm/arch/sys_proto.h> + +/* + * There is a hole in shadow registers address map of size 0x100 + * between bank 5 and bank 6 on iMX6QP, iMX6DQ, iMX6SDL, iMX6SX and iMX6UL. + * Bank 5 ends at 0x6F0 and Bank 6 starts at 0x800. When reading the fuses, + * we should account for this hole in address space. + * + * Similar hole exists between bank 14 and bank 15 of size + * 0x80 on iMX6QP, iMX6DQ, iMX6SDL and iMX6SX. + * Note: iMX6SL has only 0-7 banks and there is no hole. + * Note: iMX6UL doesn't have this one. + * + * This function is to covert user input to physical bank index. + * Only needed when read fuse, because we use register offset, so + * need to calculate real register offset. + * When write, no need to consider hole, always use the bank/word + * index from fuse map. + */ +u32 fuse_bank_physical(int index) +{ + u32 phy_index; + + if (is_cpu_type(MXC_CPU_MX6SL)) { + phy_index = index; + } else if (is_cpu_type(MXC_CPU_MX6UL)) { + if (index >= 6) + phy_index = fuse_bank_physical(5) + (index - 6) + 3; + else + phy_index = index; + } else { + if (index >= 15) + phy_index = fuse_bank_physical(14) + (index - 15) + 2; + else if (index >= 6) + phy_index = fuse_bank_physical(5) + (index - 6) + 3; + else + phy_index = index; + } + return phy_index; +} +#else +u32 fuse_bank_physical(int index) +{ + return index; +} +#endif + static void wait_busy(struct ocotp_regs *regs, unsigned int delay_us) { while (readl(&regs->ctrl) & BM_CTRL_BUSY) @@ -73,9 +135,9 @@ static int prepare_access(struct ocotp_regs **regs, u32 bank, u32 word, { *regs = (struct ocotp_regs *)OCOTP_BASE_ADDR; - if (bank >= ARRAY_SIZE((*regs)->bank) || - word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 2 || - !assert) { + if (bank >= FUSE_BANKS || + word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 2 || + !assert) { printf("mxc_ocotp %s(): Invalid argument\n", caller); return -EINVAL; } @@ -113,12 +175,15 @@ int fuse_read(u32 bank, u32 word, u32 *val) { struct ocotp_regs *regs; int ret; + u32 phy_bank; ret = prepare_read(&regs, bank, word, val, __func__); if (ret) return ret; - *val = readl(&regs->bank[bank].fuse_regs[word << 2]); + phy_bank = fuse_bank_physical(bank); + + *val = readl(&regs->bank[phy_bank].fuse_regs[word << 2]); return finish_access(regs, __func__); } @@ -259,12 +324,15 @@ int fuse_override(u32 bank, u32 word, u32 val) { struct ocotp_regs *regs; int ret; + u32 phy_bank; ret = prepare_write(&regs, bank, word, __func__); if (ret) return ret; - writel(val, &regs->bank[bank].fuse_regs[word << 2]); + phy_bank = fuse_bank_physical(bank); + + writel(val, &regs->bank[phy_bank].fuse_regs[word << 2]); return finish_access(regs, __func__); } -- 1.8.4

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[U-Boot] [PATCH V2 1/3] imx: clock support enet2 anatop clock support
by Peng Fan 01 Sep '15

01 Sep '15

To i.MX6SX/UL, two ethernet interfaces are supported. Add ENET2 clock support: 1. Introduce a new input parameter "fec_id", only 0 and 1 are allowed. To value 1, only i.MX6SX/UL can pass the check. 2. Modify board code who use this api to follow new api prototype. Signed-off-by: Peng Fan <Peng.Fan(a)freescale.com> Cc: Heiko Schocher <hs(a)denx.de> Cc: Fabio Estevam <fabio.estevam(a)freescale.com> Cc: Stefan Roese <sr(a)denx.de> Cc: Nikolaos Pasaloukos <Nikolaos.Pasaloukos(a)imgtec.com> Cc: Stefano Babic <sbabic(a)denx.de> --- Changes v2: Addressed Fabio's comments. Using "fec_id == 0", but not "0 == fec_id". arch/arm/cpu/armv7/mx6/clock.c | 23 ++++++++++++++++++----- arch/arm/include/asm/arch-mx6/clock.h | 2 +- arch/arm/include/asm/arch-mx6/crm_regs.h | 6 ++++++ board/aristainetos/aristainetos-v1.c | 2 +- board/barco/platinum/platinum_picon.c | 2 +- board/freescale/mx6qsabreauto/mx6qsabreauto.c | 2 +- board/freescale/mx6slevk/mx6slevk.c | 2 +- board/freescale/mx6sxsabresd/mx6sxsabresd.c | 2 +- board/solidrun/mx6cuboxi/mx6cuboxi.c | 2 +- 9 files changed, 31 insertions(+), 12 deletions(-) diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 9cf4eec..ba6cc75 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -524,7 +524,7 @@ void enable_qspi_clk(int qspi_num) #endif #ifdef CONFIG_FEC_MXC -int enable_fec_anatop_clock(enum enet_freq freq) +int enable_fec_anatop_clock(int fec_id, enum enet_freq freq) { u32 reg = 0; s32 timeout = 100000; @@ -535,9 +535,19 @@ int enable_fec_anatop_clock(enum enet_freq freq) if (freq < ENET_25MHZ || freq > ENET_125MHZ) return -EINVAL; - reg = readl(&anatop->pll_enet); - reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT; - reg |= freq; + if (fec_id == 0) { + reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT; + reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq); + } else if (fec_id == 1) { + /* Only i.MX6SX/UL support ENET2 */ + if (!(is_cpu_type(MXC_CPU_MX6SX) || + is_cpu_type(MXC_CPU_MX6UL))) + return -EINVAL; + reg &= ~BM_ANADIG_PLL_ENET2_DIV_SELECT; + reg |= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq); + } else { + return -EINVAL; + } if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) || (!(reg & BM_ANADIG_PLL_ENET_LOCK))) { @@ -552,7 +562,10 @@ int enable_fec_anatop_clock(enum enet_freq freq) } /* Enable FEC clock */ - reg |= BM_ANADIG_PLL_ENET_ENABLE; + if (fec_id == 0) + reg |= BM_ANADIG_PLL_ENET_ENABLE; + else + reg |= BM_ANADIG_PLL_ENET2_ENABLE; reg &= ~BM_ANADIG_PLL_ENET_BYPASS; writel(reg, &anatop->pll_enet); diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h index 7b3bbb8..2b220d6 100644 --- a/arch/arm/include/asm/arch-mx6/clock.h +++ b/arch/arm/include/asm/arch-mx6/clock.h @@ -64,7 +64,7 @@ int enable_pcie_clock(void); int enable_i2c_clk(unsigned char enable, unsigned i2c_num); int enable_spi_clk(unsigned char enable, unsigned spi_num); void enable_ipu_clock(void); -int enable_fec_anatop_clock(enum enet_freq freq); +int enable_fec_anatop_clock(int fec_id, enum enet_freq freq); void enable_enet_clk(unsigned char enable); void enable_qspi_clk(int qspi_num); void enable_thermal_clk(void); diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index fe75da4..10306cd 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -1052,6 +1052,12 @@ struct mxc_ccm_reg { #define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \ (((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT) +/* ENET2 for i.MX6SX/UL */ +#define BM_ANADIG_PLL_ENET2_ENABLE 0x00100000 +#define BM_ANADIG_PLL_ENET2_DIV_SELECT 0x0000000C +#define BF_ANADIG_PLL_ENET2_DIV_SELECT(v) \ + (((v) << 2) & BM_ANADIG_PLL_ENET2_DIV_SELECT) + #define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000 #define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000 #define BP_ANADIG_PFD_480_PFD3_FRAC 24 diff --git a/board/aristainetos/aristainetos-v1.c b/board/aristainetos/aristainetos-v1.c index d6a7614..b8fed2e 100644 --- a/board/aristainetos/aristainetos-v1.c +++ b/board/aristainetos/aristainetos-v1.c @@ -185,7 +185,7 @@ int board_eth_init(bd_t *bis) /* clear gpr1[14], gpr1[18:17] to select anatop clock */ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0); - ret = enable_fec_anatop_clock(ENET_50MHZ); + ret = enable_fec_anatop_clock(0, ENET_50MHZ); if (ret) return ret; diff --git a/board/barco/platinum/platinum_picon.c b/board/barco/platinum/platinum_picon.c index b2eab76..0384a26 100644 --- a/board/barco/platinum/platinum_picon.c +++ b/board/barco/platinum/platinum_picon.c @@ -148,7 +148,7 @@ int platinum_setup_enet(void) /* set GPIO_16 as ENET_REF_CLK_OUT */ setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK); - return enable_fec_anatop_clock(ENET_50MHZ); + return enable_fec_anatop_clock(0, ENET_50MHZ); } int platinum_setup_i2c(void) diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c index 98602f8..7c0e90a 100644 --- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c +++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c @@ -361,7 +361,7 @@ static void setup_fec(void) * select ENET MAC0 TX clock from PLL */ imx_iomux_set_gpr_register(5, 9, 1, 1); - enable_fec_anatop_clock(ENET_125MHZ); + enable_fec_anatop_clock(0, ENET_125MHZ); } setup_iomux_enet(); diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c index 7c18c90..98e3ef0 100644 --- a/board/freescale/mx6slevk/mx6slevk.c +++ b/board/freescale/mx6slevk/mx6slevk.c @@ -279,7 +279,7 @@ static int setup_fec(void) /* clear gpr1[14], gpr1[18:17] to select anatop clock */ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0); - return enable_fec_anatop_clock(ENET_50MHZ); + return enable_fec_anatop_clock(0, ENET_50MHZ); } #endif diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c index d58a79a..ffc0046 100644 --- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c +++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c @@ -170,7 +170,7 @@ static int setup_fec(void) reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE; writel(reg, &anatop->pll_enet); - return enable_fec_anatop_clock(ENET_125MHZ); + return enable_fec_anatop_clock(0, ENET_125MHZ); } int board_eth_init(bd_t *bis) diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c index 9b1ecf0..8247e43 100644 --- a/board/solidrun/mx6cuboxi/mx6cuboxi.c +++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c @@ -164,7 +164,7 @@ int board_eth_init(bd_t *bis) struct mii_dev *bus; struct phy_device *phydev; - int ret = enable_fec_anatop_clock(ENET_25MHZ); + int ret = enable_fec_anatop_clock(0, ENET_25MHZ); if (ret) return ret; -- 1.8.4

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[U-Boot] TFTP Timeout Interval problem
by Gong Q.Y. 01 Sep '15

01 Sep '15

Hi, I got a problem with tftp and found this patch. ------------- commit 620776d734e4b126c407f636bda825a594a17723 Author: Pavel Machek <pavel(a)denx.de> Date: Tue Aug 18 14:34:26 2015 +0200 tftp: adjust settings to be suitable for 100Mbit ethernet -------------- The default timeout is changed to 100 (ms) and this causes "TFTP error: 'Unsupported option(s) requested' (8)". Because the option is equal to timeout/1000, now it's zero(100/1000 -> 0) which is not supported. Actually I find in an original doc RFC-2349 which specifies this value should range between "1" and "255" seconds. So I think there may be a conflict? Look forward to your help. This is my test log: => tftp a0000000 gqy/bootscript Using FM1@DTSEC3 device TFTP from server 10.192.208.233; our IP address is 10.193.20.130 Filename 'gqy/bootscript'. Load address: 0xa0000000 Loading: * TFTP error: 'Unsupported option(s) requested' (8) Starting again => setenv tftptimeout 1000 => tftp a0000000 gqy/bootscript Using FM1@DTSEC3 device TFTP from server 10.192.208.233; our IP address is 10.193.20.130 Filename 'gqy/bootscript'. Load address: 0xa0000000 Loading: # 44.9 KiB/s done Bytes transferred = 92 (5c hex) => Regards, Qianyu

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[U-Boot] [RFC PATCH v2] arm: cache_v7: fix dcache invalidation
by Markus Niebel 01 Sep '15

01 Sep '15

From: Markus Niebel <Markus.Niebel(a)tq-group.com> according to http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka14802.ht… and the clarification given by Marc Rutland of ARM data cache invalidation should go from outer to inner cache. This patch corrects the order in flush_dcache_range flush_dcache_all Signed-off-by: Markus Niebel <Markus.Niebel(a)tq-group.com> --- Changes for v2: - delete non related stuff (thanks to Hannes Schmelzer) arch/arm/cpu/armv7/cache_v7.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c index a5aa4fa..81eb286 100644 --- a/arch/arm/cpu/armv7/cache_v7.c +++ b/arch/arm/cpu/armv7/cache_v7.c @@ -235,9 +235,9 @@ static void v7_inval_tlb(void) void invalidate_dcache_all(void) { - v7_maint_dcache_all(ARMV7_DCACHE_INVAL_ALL); - v7_outer_cache_inval_all(); + + v7_maint_dcache_all(ARMV7_DCACHE_INVAL_ALL); } /* @@ -257,9 +257,9 @@ void flush_dcache_all(void) */ void invalidate_dcache_range(unsigned long start, unsigned long stop) { - v7_dcache_maint_range(start, stop, ARMV7_DCACHE_INVAL_RANGE); - v7_outer_cache_inval_range(start, stop); + + v7_dcache_maint_range(start, stop, ARMV7_DCACHE_INVAL_RANGE); } /* -- 2.3.0

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[U-Boot] ls2085ardb not booting
by Scott Wood 01 Sep '15

01 Sep '15

I'm unable to boot ls2085ardb on the current tree. I get no console output. v2015.07 gives some output, but hangs at: > U-Boot 2015.07 (Aug 27 2015 - 16:24:43 -0500) LS2085A-RDB > > Clock Configuration: > CPU0(A57):1600 MHz CPU1(A57):1600 MHz CPU2(A57):1600 MHz > CPU3(A57):1600 MHz CPU4(A57):1600 MHz CPU5(A57):1600 MHz > CPU6(A57):1600 MHz CPU7(A57):1600 MHz > Bus: 600 MHz DDR: 1333.333 MHz DP-DDR: 1333.333 MHz > Reset Configuration Word (RCW): > 00: 40282830 40400040 00000000 00000000 > 10: 00000000 00200000 00200000 00000000 > 20: 00c12980 00002580 00000000 00000000 > 30: 00000e0b 00000000 00000000 00000000 > 40: 00000000 00000000 00000000 00000000 > 50: 00000000 00000000 00000000 00000000 > 60: 00000000 00000000 00027000 00000000 > 70: 412a0000 00000000 00000000 00000000 > Board: LS2085A-RDB, Board Arch: V1, Board version: C, boot from vBank: 4 > FPGA: v1.18 > SERDES1 Reference : Clock1 = 156.25MHz Clock2 = 156.25MHz > SERDES2 Reference : Clock1 = 100MHz Clock2 = 100MHz > I2C: ready > DRAM: Initializing DDR....using SPD > Detected UDIMM 18ASF1G72AZ-2G1A1 > Detected UDIMM 18ASF1G72AZ-2G1A1 > There is no rank on CS0 for controller 1. > Controler 1 timeout, debug_2 = 2100 > Controler 1 timeout, debug_2 = 2500 > Waiting for D_INIT timeout. Memory may not work. > DP-DDR: Detected UDIMM 18ASF1G72AZ-2G1A1 > 19.5 GiB > DDR 15.5 GiB (DDR4, 64-bit, CL=9, ECC on) > DDR Chip-Select Interleaving Mode: CS0+CS1 > DP-DDR 4 GiB (DDR4, 32-bit, CL=9, ECC on) > DDR Chip-Select Interleaving Mode: CS0+CS1 The internal bringup branch does boot on the same board, with the same RCW. -Scott

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[U-Boot] [PATCH] Revert "patman: use -D option for git format-patch"
by Masahiro Yamada 01 Sep '15

01 Sep '15

This reverts commit 19b4a3369876f9215e2b861f211e8df1a75e26ca. Since that commit, patman generates useless patches for file removal; "git format -D" prints only the header but not the diff when deleting files, and "git am" always refuses such patches. The following is the quotation from "man git-format-patch": -D, --irreversible-delete Omit the preimage for deletes, i.e. print only the header but not the diff between the preimage and /dev/null. The resulting patch is not meant to be applied with patch nor git apply; this is solely for people who want to just concentrate on reviewing the text after the change. In addition, the output obviously lack enough information to apply such a patch in reverse, even manually, hence the name of the option. Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- tools/patman/gitutil.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/patman/gitutil.py b/tools/patman/gitutil.py index 67b086b..9e739d8 100644 --- a/tools/patman/gitutil.py +++ b/tools/patman/gitutil.py @@ -264,7 +264,7 @@ def CreatePatches(start, count, series): """ if series.get('version'): version = '%s ' % series['version'] - cmd = ['git', 'format-patch', '-D', '-M', '--signoff'] + cmd = ['git', 'format-patch', '-M', '--signoff'] if series.get('cover'): cmd.append('--cover-letter') prefix = series.GetPatchPrefix() -- 1.9.1

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