July 2015 - U-Boot

Re: [U-Boot] [PATCH 3/3] crypto/fsl: clean-up - use fdt_setprop_u32 helper
by Ruchika Gupta 22 Jul '15

22 Jul '15

Acked-by: Ruchika Gupta<ruchika.gupta(a)freescale.com> > -----Original Message----- > From: Sun York-R58495 > Sent: Sunday, July 19, 2015 3:44 AM > To: Gupta Ruchika-R66431 > Subject: Re: [PATCH 3/3] crypto/fsl: clean-up - use fdt_setprop_u32 helper > > Ruchika, > > Please comment/ack. > > York > > On 07/08/2015 07:24 AM, Horia Geantă wrote: > > Signed-off-by: Horia Geantă <horia.geanta(a)freescale.com> > > --- > > drivers/crypto/fsl/sec.c | 17 ++++++++--------- > > 1 file changed, 8 insertions(+), 9 deletions(-) > > > > diff --git a/drivers/crypto/fsl/sec.c b/drivers/crypto/fsl/sec.c index > > b25b1a4052d2..0940faf768cc 100644 > > --- a/drivers/crypto/fsl/sec.c > > +++ b/drivers/crypto/fsl/sec.c > > @@ -60,27 +60,26 @@ void fdt_fixup_crypto_node(void *blob, int > sec_rev) > > return; > > } > > > > - val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].num_channels); > > - err = fdt_setprop(blob, crypto_node, "fsl,num-channels", &val, 4); > > + err = fdt_setprop_u32(blob, crypto_node, "fsl,num-channels", > > + sec_rev_prop_list[sec_idx].num_channels); > > if (err < 0) > > printf("WARNING: could not set crypto property: %s\n", > > fdt_strerror(err)); > > > > - val = > cpu_to_fdt32(sec_rev_prop_list[sec_idx].descriptor_types_mask); > > - err = fdt_setprop(blob, crypto_node, "fsl,descriptor-types-mask", > > - &val, 4); > > + err = fdt_setprop_u32(blob, crypto_node, "fsl,descriptor-types- > mask", > > + > sec_rev_prop_list[sec_idx].descriptor_types_mask); > > if (err < 0) > > printf("WARNING: could not set crypto property: %s\n", > > fdt_strerror(err)); > > > > - val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].exec_units_mask); > > - err = fdt_setprop(blob, crypto_node, "fsl,exec-units-mask", &val, 4); > > + err = fdt_setprop_u32(blob, crypto_node, "fsl,exec-units-mask", > > + sec_rev_prop_list[sec_idx].exec_units_mask); > > if (err < 0) > > printf("WARNING: could not set crypto property: %s\n", > > fdt_strerror(err)); > > > > - val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].channel_fifo_len); > > - err = fdt_setprop(blob, crypto_node, "fsl,channel-fifo-len", &val, 4); > > + err = fdt_setprop_u32(blob, crypto_node, "fsl,channel-fifo-len", > > + sec_rev_prop_list[sec_idx].channel_fifo_len); > > if (err < 0) > > printf("WARNING: could not set crypto property: %s\n", > > fdt_strerror(err)); > >

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Re: [U-Boot] [PATCH 2/3] crypto/fsl: fix snooping for write transactions
by Ruchika Gupta 22 Jul '15

22 Jul '15

Acked-by: Ruchika Gupta<ruchika.gupta(a)freescale.com> > -----Original Message----- > From: Sun York-R58495 > Sent: Sunday, July 19, 2015 3:44 AM > To: Gupta Ruchika-R66431 > Subject: Re: [PATCH 2/3] crypto/fsl: fix snooping for write transactions > > Ruchika, > > Please comment/ack. > > York > > On 07/08/2015 07:24 AM, Horia Geantă wrote: > > HW coherency won't work properly for CAAM write transactions if > > AWCACHE is left to default (POR) value - 4'b0001. > > It has to be programmed to 4'b0010. > > > > For platforms that have HW coherency support: > > -PPC-based: the update has no effect; CAAM coherency already works due > > to the IOMMU (PAMU) driver setting the correct memory coherency > > attributes > > -ARM-based: the update fixes cache coherency issues, since IOMMU > > (SMMU) driver is not programmed to behave similar to PAMU > > > > Fixes: b9eebfade974c ("fsl_sec: Add hardware accelerated SHA256 and > > SHA1") > > Signed-off-by: Horia Geantă <horia.geanta(a)freescale.com> > > Reviewed-by: Aneesh Bansal <aneesh.bansal(a)freescale.com> > > Reviewed-by: Mingkai Hu <Mingkai.Hu(a)freescale.com> > > --- > > drivers/crypto/fsl/jr.c | 10 ++++++---- drivers/crypto/fsl/jr.h | 2 > > ++ > > 2 files changed, 8 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index > > f99d59480c81..e2bd913aa259 100644 > > --- a/drivers/crypto/fsl/jr.c > > +++ b/drivers/crypto/fsl/jr.c > > @@ -459,14 +459,16 @@ static int rng_init(void) > > > > int sec_init(void) > > { > > - int ret = 0; > > - > > -#ifdef CONFIG_PHYS_64BIT > > ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; > > uint32_t mcr = sec_in32(&sec->mcfgr); > > + int ret = 0; > > > > - sec_out32(&sec->mcfgr, mcr | 1 << MCFGR_PS_SHIFT); > > + mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0x2 << > MCFGR_AWCACHE_SHIFT); > > +#ifdef CONFIG_PHYS_64BIT > > + mcr |= (1 << MCFGR_PS_SHIFT); > > #endif > > + sec_out32(&sec->mcfgr, mcr); > > + > > ret = jr_init(); > > if (ret < 0) { > > printf("SEC initialization failed\n"); diff --git > > a/drivers/crypto/fsl/jr.h b/drivers/crypto/fsl/jr.h index > > cce2c589ce0b..152606008845 100644 > > --- a/drivers/crypto/fsl/jr.h > > +++ b/drivers/crypto/fsl/jr.h > > @@ -21,6 +21,8 @@ > > #define MCFGR_SWRST ((uint32_t)(1)<<31) /* Software Reset */ > > #define MCFGR_DMA_RST ((uint32_t)(1)<<28) /* DMA Reset */ > > #define MCFGR_PS_SHIFT 16 > > +#define MCFGR_AWCACHE_SHIFT 8 > > +#define MCFGR_AWCACHE_MASK (0xf << MCFGR_AWCACHE_SHIFT) > > #define JR_INTMASK 0x00000001 > > #define JRCR_RESET 0x01 > > #define JRINT_ERR_HALT_INPROGRESS 0x4 > >

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Re: [U-Boot] [PATCH 1/3] crypto/fsl: fix "era" property value on LE platforms
by Ruchika Gupta 22 Jul '15

22 Jul '15

Acked-by: Ruchika Gupta<ruchika.gupta(a)freescale.com> > -----Original Message----- > From: Sun York-R58495 > Sent: Sunday, July 19, 2015 3:44 AM > To: Gupta Ruchika-R66431 > Subject: Re: [PATCH 1/3] crypto/fsl: fix "era" property value on LE platforms > > Ruchika, > > Please comment/ack. > > York > > On 07/08/2015 07:24 AM, Horia Geantă wrote: > > Use fdt_setprop_u32() instead of fdt_setprop(). > > > > Fixes: 0181937fa371a ("crypto/fsl: Add fixup for crypto node") > > Signed-off-by: Horia Geantă <horia.geanta(a)freescale.com> > > Reviewed-by: Mingkai Hu <Mingkai.Hu(a)freescale.com> > > --- > > drivers/crypto/fsl/sec.c | 3 +-- > > 1 file changed, 1 insertion(+), 2 deletions(-) > > > > diff --git a/drivers/crypto/fsl/sec.c b/drivers/crypto/fsl/sec.c index > > 443ee964feae..b25b1a4052d2 100644 > > --- a/drivers/crypto/fsl/sec.c > > +++ b/drivers/crypto/fsl/sec.c > > @@ -155,8 +155,7 @@ static void fdt_fixup_crypto_era(void *blob, u32 > era) > > return; > > } > > > > - err = fdt_setprop(blob, crypto_node, "fsl,sec-era", &era, > > - sizeof(era)); > > + err = fdt_setprop_u32(blob, crypto_node, "fsl,sec-era", era); > > if (err < 0) { > > printf("ERROR: could not set fsl,sec-era property: %s\n", > > fdt_strerror(err)); > >

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Re: [U-Boot] [PATCH 3/3] crypto/fsl - enable raw data instead of von Neumann data
by Ruchika Gupta 22 Jul '15

22 Jul '15

Acked-by: Ruchika Gupta<ruchika.gupta(a)freescale.com> > -----Original Message----- > From: Sun York-R58495 > Sent: Sunday, July 19, 2015 3:43 AM > To: Gupta Ruchika-R66431 > Subject: Re: [PATCH 3/3] crypto/fsl - enable raw data instead of von > Neumann data > > Ruchika, > > Please comment/ack. > > York > > On 05/05/2015 06:48 AM, Alex Porosanu wrote: > > The sampling of the oscillator can be done in multiple modes for > > generating the entropy value. By default, this is set to von Neumann. > > This patch changes the sampling to raw data, since it has been > > discovered that the generated entropy has a better 'quality'. > > > > Signed-off-by: Alex Porosanu <alexandru.porosanu(a)freescale.com> > > --- > > drivers/crypto/fsl/jr.c | 11 ++++++++++- > > include/fsl_sec.h | 10 ++++++++++ > > 2 files changed, 20 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index > > aa527ec..3560668 100644 > > --- a/drivers/crypto/fsl/jr.c > > +++ b/drivers/crypto/fsl/jr.c > > @@ -408,8 +408,17 @@ static void kick_trng(int ent_delay) > > sec_out32(&rng->rtfreqmin, ent_delay >> 2); > > /* disable maximum frequency count */ > > sec_out32(&rng->rtfreqmax, RTFRQMAX_DISABLE); > > + /* read the control register */ > > + val = sec_in32(&rng->rtmctl); > > + /* > > + * select raw sampling in both entropy shifter > > + * and statistical checker > > + */ > > + sec_setbits32(&val, RTMCTL_SAMP_MODE_RAW_ES_SC); > > /* put RNG4 into run mode */ > > - sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM); > > + sec_clrbits32(&val, RTMCTL_PRGM); > > + /* write back the control register */ > > + sec_out32(&rng->rtmctl, val); > > } > > > > static int rng_init(void) > > diff --git a/include/fsl_sec.h b/include/fsl_sec.h index > > c84b6ad..672bcef 100644 > > --- a/include/fsl_sec.h > > +++ b/include/fsl_sec.h > > @@ -32,6 +32,16 @@ > > /* RNG4 TRNG test registers */ > > struct rng4tst { > > #define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode > */ > > +#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC 0 /* use von > Neumann data in > > + both entropy shifter and > > + statistical checker */ > > +#define RTMCTL_SAMP_MODE_RAW_ES_SC 1 /* use raw data in > both > > + entropy shifter and > > + statistical checker */ > > +#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_RAW_SC 2 /* use > von Neumann data in > > + entropy shifter, raw data > > + in statistical checker */ > > +#define RTMCTL_SAMP_MODE_INVALID 3 /* invalid combination > */ > > u32 rtmctl; /* misc. control register */ > > u32 rtscmisc; /* statistical check misc. register */ > > u32 rtpkrrng; /* poker range register */ > >

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Re: [U-Boot] [PATCH 1/3] crypto/fsl - disable RNG oscillator maximum frequency check
by Ruchika Gupta 22 Jul '15

22 Jul '15

Acked-by: Ruchika Gupta<ruchika.gupta(a)freescale.com> > -----Original Message----- > From: Sun York-R58495 > Sent: Sunday, July 19, 2015 3:43 AM > To: Gupta Ruchika-R66431 > Subject: Re: [PATCH 1/3] crypto/fsl - disable RNG oscillator maximum > frequency check > > Ruchika, > > Please comment/ack this patch and others in this set. > > York > > > On 05/05/2015 06:48 AM, Alex Porosanu wrote: > > The rtfrqmax & rtfrqmin set the bounds of the expected frequency of > > the oscillator, when SEC runs at its maximum frequency. For certain > > platforms (f.i. T2080), the oscillator is very fast and thus if the > > SEC runs at a lower than normal frequency, the ring oscillator is > > incorrectly detected as being out of bounds. > > > > This patch effectively disables the maximum frequency check, by > > setting a high enough maximum allowable frequency for the oscillator. > > The reasoning behind this is that usually a broken oscillator will run > > too slow (i.e. not run at all) rather than run too fast. > > > > Signed-off-by: Alex Porosanu <alexandru.porosanu(a)freescale.com> > > --- > > drivers/crypto/fsl/jr.c | 4 ++-- > > include/fsl_sec.h | 1 + > > 2 files changed, 3 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index > > f99d594..aa527ec 100644 > > --- a/drivers/crypto/fsl/jr.c > > +++ b/drivers/crypto/fsl/jr.c > > @@ -406,8 +406,8 @@ static void kick_trng(int ent_delay) > > sec_out32(&rng->rtsdctl, val); > > /* min. freq. count, equal to 1/4 of the entropy sample length */ > > sec_out32(&rng->rtfreqmin, ent_delay >> 2); > > - /* max. freq. count, equal to 8 times the entropy sample length */ > > - sec_out32(&rng->rtfreqmax, ent_delay << 3); > > + /* disable maximum frequency count */ > > + sec_out32(&rng->rtfreqmax, RTFRQMAX_DISABLE); > > /* put RNG4 into run mode */ > > sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM); } diff --git > > a/include/fsl_sec.h b/include/fsl_sec.h index ebb1ac6..14f6633 100644 > > --- a/include/fsl_sec.h > > +++ b/include/fsl_sec.h > > @@ -49,6 +49,7 @@ struct rng4tst { > > u32 rttotsam; /* PRGM=0: total samples register */ > > }; > > u32 rtfreqmin; /* frequency count min. limit register */ > > +#define RTFRQMAX_DISABLE (1 << 20) > > union { > > u32 rtfreqmax; /* PRGM=1: freq. count max. limit register */ > > u32 rtfreqcnt; /* PRGM=0: freq. count register */ > >

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Re: [U-Boot] [PATCH 2/3] crypto/fsl - change starting entropy delay value
by Ruchika Gupta 22 Jul '15

22 Jul '15

Acked-by: Ruchika Gupta<ruchika.gupta(a)freescale.com> > -----Original Message----- > From: Sun York-R58495 > Sent: Sunday, July 19, 2015 3:43 AM > To: Gupta Ruchika-R66431 > Subject: Re: [PATCH 2/3] crypto/fsl - change starting entropy delay value > > Ruchika, > > Please comment/ack this patch and others in this set. > > York > > On 05/05/2015 06:48 AM, Alex Porosanu wrote: > > The entropy delay (the length in system clocks of each entropy sample) > > for the RNG4 block of CAAM is dependent on the frequency of the SoC. > > By elaborate methods, it has been determined that a good starting > > value for all platforms integrating the CAAM IP is 3200. Using a > > higher value has additional benefit of speeding up the process of > > instantiating the RNG, since the entropy delay will be increased and > > instantiation of the RNG state handles will be reattempted by the > > driver. If the starting value is low, for certain platforms, this can > > lead to a quite lengthy process. > > This patch changes the starting value of the length of the entropy > > sample to 3200 system clocks. > > In addition to this change, the attempted entropy delay values are now > > printed on the console upon initialization of the RNG block. > > > > Signed-off-by: Alex Porosanu <alexandru.porosanu(a)freescale.com> > > --- > > include/fsl_sec.h | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/include/fsl_sec.h b/include/fsl_sec.h index > > 14f6633..c84b6ad 100644 > > --- a/include/fsl_sec.h > > +++ b/include/fsl_sec.h > > @@ -35,7 +35,7 @@ struct rng4tst { > > u32 rtmctl; /* misc. control register */ > > u32 rtscmisc; /* statistical check misc. register */ > > u32 rtpkrrng; /* poker range register */ > > -#define RTSDCTL_ENT_DLY_MIN 1200 > > +#define RTSDCTL_ENT_DLY_MIN 3200 > > #define RTSDCTL_ENT_DLY_MAX 12800 > > union { > > u32 rtpkrmax; /* PRGM=1: poker max. limit register */ > >

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[U-Boot] [PATCH 1/2] zynqmp: mp: Simplify set_r5_start handling
by Michal Simek 22 Jul '15

22 Jul '15

Pass directly boot_addr which is LOVEC (0) or HIVEC (0xffff0000). No reason to use magic values 0 and 1. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- arch/arm/cpu/armv8/zynqmp/mp.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/arch/arm/cpu/armv8/zynqmp/mp.c b/arch/arm/cpu/armv8/zynqmp/mp.c index 17e32a7b7ce8..dcb80b522ead 100644 --- a/arch/arm/cpu/armv8/zynqmp/mp.c +++ b/arch/arm/cpu/armv8/zynqmp/mp.c @@ -216,12 +216,7 @@ int cpu_release(int nr, int argc, char * const argv[]) printf("R5 lockstep mode\n"); set_r5_tcm_mode(LOCK); set_r5_halt_mode(HALT, LOCK); - - if (boot_addr == 0) - set_r5_start(0); - else - set_r5_start(1); - + set_r5_start(boot_addr); enable_clock_r5(); release_r5_reset(LOCK); set_r5_halt_mode(RELEASE, LOCK); -- 2.3.5

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[U-Boot] [PATCH V3 0/8] configs: make keystone2 config to start using arm_v7_common header
by Nishanth Menon 22 Jul '15

22 Jul '15

For legacy reasons, keystone2 had kind of stayed completely seperated from the rest of the TI SoC families. This makes no sense since there are a lot of common definitions that can be reused between all SoC configuration allowing for a consistent user experience. So make keystone2 follow the rest of the TI SoCs based on OMAP architecture as well. Test log: http://pastebin.ubuntu.com/11899472/ using ( http://pastebin.ubuntu.com/11899472/) Changes in V3: - Cleanup MMC as part of review comments - Started using common addresses and got rid of fdt_addr_high. - Additional consolidation - picked up acks from previous patches V2: http://marc.info/?l=u-boot&m=143707376106583&w=2 V1: http://marc.info/?l=u-boot&m=143706008602124&w=2 Nishanth Menon (8): configs: split ti_armv7_common into a omap generic header board: ks2_evm: get rid of bogus CONFIG_LINUX_BOOT_PARAM_ADDR configs: rename ks2_evm into ti_armv7_keystone2 configs: ti_armv7_keystone2: start using armv7_common configs: ti_armv7_keystone2: switch addresses to generic addresses ti_armv7_keystone2: switch to using kernel zImage configs: k2*_evm: rename skernel binary names to generated file names configs: keystone2: remove distro specific ramdisk name board/ti/ks2_evm/board.c | 2 +- include/configs/am43xx_evm.h | 2 +- include/configs/k2e_evm.h | 9 +-- include/configs/k2hk_evm.h | 9 +-- include/configs/k2l_evm.h | 9 +-- include/configs/ti_am335x_common.h | 2 +- include/configs/ti_armv7_common.h | 26 ++----- .../configs/{ks2_evm.h => ti_armv7_keystone2.h} | 82 ++++++++-------------- include/configs/ti_armv7_omap.h | 49 +++++++++++++ include/configs/ti_omap3_common.h | 2 +- include/configs/ti_omap4_common.h | 2 +- include/configs/ti_omap5_common.h | 2 +- 12 files changed, 97 insertions(+), 99 deletions(-) rename include/configs/{ks2_evm.h => ti_armv7_keystone2.h} (82%) create mode 100644 include/configs/ti_armv7_omap.h -- 2.1.4

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[U-Boot] [PATCH 0/4] sunxi: nand: Basic NAND driver with SPL support
by Piotr Zierhoffer 22 Jul '15

22 Jul '15

This is a basic driver for the sunxi NAND controller for Allwinner A20. It supports both SPL and U-Boot. The driver uses DMA for data transfers. It does not support writing. To enable user reading from NADN, the a20_nandread command was added. Piotr Zierhoffer (4): sunxi: nand: Add basic sunxi NAND driver with DMA support sunxi: nand: Add board configuration options sunxi: nand: Add a20_nandread command to load image from NAND in SPL sunxi: nand: Add information to sunxi that it was run from NAND in SPL arch/arm/cpu/armv7/sunxi/board.c | 4 + board/sunxi/Kconfig | 10 ++ board/sunxi/Makefile | 1 + board/sunxi/nand.c | 315 +++++++++++++++++++++++++++++++++++++++ board/sunxi/nand.h | 146 ++++++++++++++++++ common/Makefile | 1 + common/cmd_a20_nandread.c | 25 ++++ include/configs/sunxi-common.h | 13 ++ 8 files changed, 515 insertions(+) create mode 100644 board/sunxi/nand.c create mode 100644 board/sunxi/nand.h create mode 100644 common/cmd_a20_nandread.c -- 2.3.6

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[U-Boot] [PATCH] keystone2: add high memory test
by Vitaly Andrianov 22 Jul '15

22 Jul '15

Keystone2 SOC physical DDR3 address range is outside the first 4GB and cannot be entirely accessible without MMU enabled. Only first 2GB of the physical memory have 32-bits aliased addresses. This patch adds u-boot shell command that allows to enable/disable MMU and map the 1GB of 36bits physical memory to the first 4GB address range. Signed-off-by: Vitaly Andrianov <vitalya(a)ti.com> --- arch/arm/mach-keystone/Makefile | 3 +- arch/arm/mach-keystone/highmem.c | 162 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 164 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-keystone/highmem.c diff --git a/arch/arm/mach-keystone/Makefile b/arch/arm/mach-keystone/Makefile index ed030db..56b6457 100644 --- a/arch/arm/mach-keystone/Makefile +++ b/arch/arm/mach-keystone/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2012-2014 +# (C) Copyright 2012-2015 # Texas Instruments Incorporated, <www.ti.com> # # SPDX-License-Identifier: GPL-2.0+ @@ -16,3 +16,4 @@ obj-y += cmd_mon.o obj-y += msmc.o obj-y += ddr3.o cmd_ddr3.o obj-y += keystone.o +obj-y += highmem.o diff --git a/arch/arm/mach-keystone/highmem.c b/arch/arm/mach-keystone/highmem.c new file mode 100644 index 0000000..d024e04 --- /dev/null +++ b/arch/arm/mach-keystone/highmem.c @@ -0,0 +1,162 @@ +/* + * Keystone2: High Memory Test + * + * (C) Copyright 2013-2015 + * Texas Instruments Incorporated, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +/* + * Keysone2 systems which have more then 2GB of DDR2A memory + * cannot access that memory without MMU enable. In order to test + * the entire memory we need to create MMU translation table, + * enable MMU and test the memory in portions. After the test + * we need to disable MMU. + * + * We assume that the memory size >= 2GB and u-boot code is relocated + * to the upper GB of the PA address range and the 0x80000000-0xbfffffff + * address range is available to use for testing. + * + * The code will create simple 1 level page table with 4 entries of + * 1GB blocks. The block with VA 0x80000000-0xbfffffff will be used + * to map different portions of the DDR3a. + * + */ + +#include <common.h> +#include <asm/armv7.h> + +static unsigned long long pgd_table[4] __aligned(0x1000); +static unsigned long sctlr_save; +static int mmu_enabled; + +/* Invalidate TLB */ +void my_v7_inval_tlb(void) +{ + /* Invalidate entire unified TLB */ + asm volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0)); + /* Invalidate entire data TLB */ + asm volatile ("mcr p15, 0, %0, c8, c6, 0" : : "r" (0)); + /* Invalidate entire instruction TLB */ + asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0)); + /* Full system DSB - make sure that the invalidation is complete */ + CP15DSB; + /* Full system ISB - make sure the instruction stream sees it */ + CP15ISB; +} + +static unsigned long enable_mmu(unsigned long long *ttbr0) +{ + unsigned long ret; + asm ( + "stmfd r13!, {r10, r11}\n" + /* set ttbr0 */ + "mov r10, %1\n" + "mov r11, #0\n" + "mcrr p15, 0, r10, r11, c2\n" + /* ttbcr = 0x80000000 */ + "mov r10, #0\n" + "orr r10, r10, #(1 << 31)\n" + "mcr p15, 0, r10, c2, c0, 2\n" + /* save current SCTLR value */ + "mrc p15, #0, r10, c1, c0, #0\n" + "mov %0, r10\n" + /* disable cache */ + "bic r10, r10,#(1 << 12)\n" + "bic r10, r10,#(1 << 2)\n" + "mcr p15, #0, r10, c1, c0, #0\n" + "isb\n" + "dsb\n" + "bl invalidate_dcache_all\n" + "bl my_v7_inval_tlb\n" + /* enable mmu */ + "mrc p15, #0, r10, c1, c0, #0\n" + "orr r10, r10,#1\n" + "mcr p15, #0, r10, c1, c0, #0\n" + "ldmfd r13!, {r10, r11}\n" + : "=r" (ret) : "r" (ttbr0) : "r10", "r11", "cc" + ); + + return ret; +} + +static void disable_mmu(unsigned long sctlr_old) +{ + asm volatile ( + "mov r10, %0\n" + "bic r10, r10,#1\n" + "mcr p15, #0, r10, c1, c0, #0\n" + : : "r" (sctlr_old) : "r10", "cc" + ); +} + + +static void pgd_table_init(void) +{ + /* + * we create identical mapping for the whole 4GB address range + * this table maps 0x0-0xffffffff VA to aliased PA range + * 0x0_0000_0000 - 0x0_ffff_ffff; + */ + + pgd_table[0] = 0x000000000000071dULL; + pgd_table[1] = 0x000000004000071dULL; + pgd_table[2] = 0x000000008000071dULL; + pgd_table[3] = 0x00000000c000071dULL; +} + +int do_highmem_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + unsigned long pgd2_pa; + unsigned long long pgd_val; + int j; + + if (argc < 2) + goto highmem_cmd_usage; + + if (strcmp(argv[1], "mmuon") == 0) { + if (mmu_enabled) { + printf("MMU already enabled\n"); + } else { + pgd_table_init(); + sctlr_save = enable_mmu(pgd_table); + mmu_enabled = 1; + printf("MMU enabled\n"); + } + } else if (strcmp(argv[1], "mmuoff") == 0) { + if (mmu_enabled == 0) { + printf("MMU already disabled\n"); + } else { + disable_mmu(sctlr_save); + mmu_enabled = 0; + printf("MMU disabled\n"); + } + } else if (strcmp(argv[1], "pgd2") == 0) { + if (argc == 3) { + pgd2_pa = simple_strtoul(argv[2], NULL, 16); + pgd_val = pgd2_pa; + pgd_val <<= 4; + pgd_val |= 0x71dull; + pgd_table[2] = pgd_val; + my_v7_inval_tlb(); + } + for (j = 0; j < 4; j++) + printf("pgd%d - 0x%016llX\n", j, pgd_table[j]); + } else { + goto highmem_cmd_usage; + } + + return 0; + +highmem_cmd_usage: + return cmd_usage(cmdtp); +} + +U_BOOT_CMD( + highmem, 3, 0, do_highmem_cmd, + "highmem test", + "highmem <mmuon|mmuoff|pgd2> [<pgd2_pa >> 4> in hex]\n" +); + -- 1.9.1

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