July 2015 - U-Boot

[U-Boot] [PATCH 2/6] dm: pci: Correct primary/secondary/subordinate bus number assignment
by Bin Meng 21 Jul '15

21 Jul '15

In driver model, each pci bridge device has its own hose structure. hose->first_busno points to the bridge device's device number, so we should not substract hose->first_busno before programming the bridge device's primary/secondary/subordinate bus number registers. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- drivers/pci/pci_auto.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c index e034ed1..ef6dc4f 100644 --- a/drivers/pci/pci_auto.c +++ b/drivers/pci/pci_auto.c @@ -224,10 +224,15 @@ void pciauto_prescan_setup_bridge(struct pci_controller *hose, prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK; /* Configure bus number registers */ +#ifdef CONFIG_DM_PCI + pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS, PCI_BUS(dev)); + pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS, sub_bus); +#else pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS, PCI_BUS(dev) - hose->first_busno); pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS, sub_bus - hose->first_busno); +#endif pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff); if (pci_mem) { @@ -295,8 +300,12 @@ void pciauto_postscan_setup_bridge(struct pci_controller *hose, struct pci_region *pci_io = hose->pci_io; /* Configure bus number registers */ +#ifdef CONFIG_DM_PCI + pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, sub_bus); +#else pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, sub_bus - hose->first_busno); +#endif if (pci_mem) { /* Round memory allocator to 1MB boundary */ -- 1.8.2.1

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[U-Boot] [PATCH v2 0/6] dcache support for Raspberry Pi 1
by Alexander Stein 21 Jul '15

21 Jul '15

This patchset enables dcache support for Raspberry Pi 1. First the cache support code for arm1136 and 1176 was merged. CONFIG_SYS_CACHELINE_SIZE is defined as 32 bytes which is used as alignment for mailbox buffer allocations. Then rpi mailbox code has now dcache flush for writing the mailbox request and a dcache invalidation for receiving the mailbox answer. Finally the CONFIG_SYS_DCACHE_OFF switch got removed from rpi1 config. It is still set for rpi2 config. dcache supprt increases the MMC read performance on RPI 1 from 5,4 MiB/s to 12.3 MiB/s. This was tested by the following command: > fatload mmc 0:1 ${kernel_addr_r} zImage Changes in v2: * Merge arm1136/1176 cache code * Use cacheline size as mailbox buffer alignment * Flush/invalidate mailbox buffer up to cacheline size Alexander Stein (6): arm1136: Remove dead code arm1136/arm1176: Merge cache handling code ARM: bcm283x: Define CONFIG_SYS_CACHELINE_SIZE ARM: bcm283x: Allocate all mailbox buffers cacheline aligned arm/mach-bcm283x/mbox: Flush and invalidate dcache when using fw mailbox arm/rpi: Enable dcache arch/arm/cpu/arm11/Makefile | 8 ++ arch/arm/cpu/arm11/cpu.c | 150 ++++++++++++++++++++++++++++ arch/arm/cpu/arm1136/Makefile | 1 - arch/arm/cpu/arm1136/cpu.c | 160 ------------------------------ arch/arm/cpu/arm1176/Makefile | 4 +- arch/arm/cpu/arm1176/cpu.c | 51 ---------- arch/arm/mach-bcm283x/include/mach/mbox.h | 4 + arch/arm/mach-bcm283x/mbox.c | 9 ++ board/raspberrypi/rpi/rpi.c | 10 +- drivers/video/bcm2835.c | 4 +- include/configs/rpi-common.h | 2 +- include/configs/rpi_2.h | 1 + 12 files changed, 183 insertions(+), 221 deletions(-) create mode 100644 arch/arm/cpu/arm11/Makefile create mode 100644 arch/arm/cpu/arm11/cpu.c delete mode 100644 arch/arm/cpu/arm1136/cpu.c delete mode 100644 arch/arm/cpu/arm1176/cpu.c -- 2.4.6

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[U-Boot] [PATCH v2 7/7] x86: Reserve PCIe ECAM address range in the E820 table
by Bin Meng 21 Jul '15

21 Jul '15

We should mark PCIe ECAM address range in the E820 table as reserved otherwise kernel will not attempt to use ECAM. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- Changes in v2: - New patch to reserve PCIe ECAM address range in the E820 table arch/x86/Kconfig | 10 ++++++++++ arch/x86/lib/fsp/fsp_dram.c | 6 ++++++ arch/x86/lib/zimage.c | 5 ++++- 3 files changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index cbbaa4f..e8968a7 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -369,4 +369,14 @@ config PCIE_ECAM_BASE assigned to PCI devices - i.e. the memory and prefetch regions, as passed to pci_set_region(). +config PCIE_ECAM_SIZE + hex + default 0x10000000 + help + This is the size of memory-mapped address of PCI configuration space, + which is only available through the Enhanced Configuration Access + Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory, + so a default 0x10000000 size covers all of the 256 buses which is the + maximum number of PCI buses as defined by the PCI specification. + endmenu diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c index 4c0a7c8..28552fa 100644 --- a/arch/x86/lib/fsp/fsp_dram.c +++ b/arch/x86/lib/fsp/fsp_dram.c @@ -77,5 +77,11 @@ unsigned install_e820_map(unsigned max_entries, struct e820entry *entries) num_entries++; } + /* Mark PCIe ECAM address range as reserved */ + entries[num_entries].addr = CONFIG_PCIE_ECAM_BASE; + entries[num_entries].size = CONFIG_PCIE_ECAM_SIZE; + entries[num_entries].type = E820_RESERVED; + num_entries++; + return num_entries; } diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c index 144471c..a1ec57e 100644 --- a/arch/x86/lib/zimage.c +++ b/arch/x86/lib/zimage.c @@ -61,8 +61,11 @@ __weak unsigned install_e820_map(unsigned max_entries, entries[2].addr = ISA_END_ADDRESS; entries[2].size = gd->ram_size - ISA_END_ADDRESS; entries[2].type = E820_RAM; + entries[3].addr = CONFIG_PCIE_ECAM_BASE; + entries[3].size = CONFIG_PCIE_ECAM_SIZE; + entries[3].type = E820_RESERVED; - return 3; + return 4; } static void build_command_line(char *command_line, int auto_boot) -- 1.8.2.1

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[U-Boot] [PATCH v2 5/7] x86: qemu: Enable writing MP table
by Bin Meng 21 Jul '15

21 Jul '15

Enable writing MP table for QEMU boads (i440fx and q35). Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- Changes in v2: - Drop QEMU mp_init patch - Change /cpus node to include just one cpu arch/x86/cpu/qemu/pci.c | 34 +++++++++++++++++++++++++++++++--- arch/x86/dts/qemu-x86_i440fx.dts | 12 ++++++++++++ arch/x86/dts/qemu-x86_q35.dts | 12 ++++++++++++ configs/qemu-x86_defconfig | 3 +++ 4 files changed, 58 insertions(+), 3 deletions(-) diff --git a/arch/x86/cpu/qemu/pci.c b/arch/x86/cpu/qemu/pci.c index ab93e76..acbd922 100644 --- a/arch/x86/cpu/qemu/pci.c +++ b/arch/x86/cpu/qemu/pci.c @@ -13,6 +13,8 @@ DECLARE_GLOBAL_DATA_PTR; +static bool i440fx; + void board_pci_setup_hose(struct pci_controller *hose) { hose->first_busno = 0; @@ -61,7 +63,8 @@ int board_pci_post_scan(struct pci_controller *hose) * PCI device ID. */ device = x86_pci_read_config16(PCI_BDF(0, 0, 0), PCI_DEVICE_ID); - pam = (device == PCI_DEVICE_ID_INTEL_82441) ? I440FX_PAM : Q35_PAM; + i440fx = (device == PCI_DEVICE_ID_INTEL_82441); + pam = i440fx ? I440FX_PAM : Q35_PAM; /* * Initialize Programmable Attribute Map (PAM) Registers @@ -71,7 +74,7 @@ int board_pci_post_scan(struct pci_controller *hose) for (i = 0; i < PAM_NUM; i++) x86_pci_write_config8(PCI_BDF(0, 0, 0), pam + i, PAM_RW); - if (device == PCI_DEVICE_ID_INTEL_82441) { + if (i440fx) { /* * Enable legacy IDE I/O ports decode * @@ -97,10 +100,35 @@ int board_pci_post_scan(struct pci_controller *hose) * board, it shows as device 2, while for Q35 and ICH9 chipset board, * it shows as device 1. */ - vga = (device == PCI_DEVICE_ID_INTEL_82441) ? I440FX_VGA : Q35_VGA; + vga = i440fx ? I440FX_VGA : Q35_VGA; start = get_timer(0); ret = pci_run_vga_bios(vga, NULL, PCI_ROM_USE_NATIVE); debug("BIOS ran in %lums\n", get_timer(start)); return ret; } + +#ifdef CONFIG_GENERATE_MP_TABLE +int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq) +{ + u8 irq; + + if (i440fx) { + /* + * Not like most x86 platforms, the PIRQ[A-D] on PIIX3 are not + * connected to I/O APIC INTPIN#16-19. Instead they are routed + * to an irq number controled by the PIRQ routing register. + */ + irq = x86_pci_read_config8(PCI_BDF(bus, dev, func), + PCI_INTERRUPT_LINE); + } else { + /* + * ICH9's PIRQ[A-H] are not consecutive numbers from 0 to 7. + * PIRQ[A-D] still maps to [0-3] but PIRQ[E-H] maps to [8-11]. + */ + irq = pirq < 8 ? pirq + 16 : pirq + 12; + } + + return irq; +} +#endif diff --git a/arch/x86/dts/qemu-x86_i440fx.dts b/arch/x86/dts/qemu-x86_i440fx.dts index 0c522c8..c26c71b 100644 --- a/arch/x86/dts/qemu-x86_i440fx.dts +++ b/arch/x86/dts/qemu-x86_i440fx.dts @@ -24,6 +24,18 @@ stdout-path = "/serial"; }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "cpu-x86"; + reg = <0>; + intel,apic-id = <0>; + }; + }; + pci { compatible = "pci-x86"; #address-cells = <3>; diff --git a/arch/x86/dts/qemu-x86_q35.dts b/arch/x86/dts/qemu-x86_q35.dts index 5fbabc2..2e785fa 100644 --- a/arch/x86/dts/qemu-x86_q35.dts +++ b/arch/x86/dts/qemu-x86_q35.dts @@ -35,6 +35,18 @@ stdout-path = "/serial"; }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "cpu-x86"; + reg = <0>; + intel,apic-id = <0>; + }; + }; + pci { compatible = "pci-x86"; #address-cells = <3>; diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig index a4c20bd..4b18d51 100644 --- a/configs/qemu-x86_defconfig +++ b/configs/qemu-x86_defconfig @@ -1,6 +1,8 @@ CONFIG_X86=y CONFIG_DEFAULT_DEVICE_TREE="qemu-x86_i440fx" CONFIG_GENERATE_PIRQ_TABLE=y +CONFIG_GENERATE_MP_TABLE=y +CONFIG_CMD_CPU=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set @@ -9,6 +11,7 @@ CONFIG_BOOTSTAGE=y CONFIG_BOOTSTAGE_REPORT=y CONFIG_CMD_BOOTSTAGE=y CONFIG_OF_CONTROL=y +CONFIG_CPU=y CONFIG_SPI_FLASH=y CONFIG_VIDEO_VESA=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y -- 1.8.2.1

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[U-Boot] [PATCH v2 1/7] x86: mpspec: Allow platform to determine how PIRQ is connected to I/O APIC
by Bin Meng 21 Jul '15

21 Jul '15

Currently during writing MP table I/O interrupt assignment entry, we assume the PIRQ is directly mapped to I/O APIC INTPIN#16-23, which however is not always the case on some platforms. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- Changes in v2: - Drop patches that are already applied - Add a TODO comment above mp_determine_pci_dstirq() arch/x86/include/asm/mpspec.h | 17 +++++++++++++++++ arch/x86/lib/mpspec.c | 24 +++++++++++++++++------- 2 files changed, 34 insertions(+), 7 deletions(-) diff --git a/arch/x86/include/asm/mpspec.h b/arch/x86/include/asm/mpspec.h index efa9231..ad8eba9 100644 --- a/arch/x86/include/asm/mpspec.h +++ b/arch/x86/include/asm/mpspec.h @@ -432,6 +432,23 @@ void mp_write_compat_address_space(struct mp_config_table *mc, int busid, u32 mptable_finalize(struct mp_config_table *mc); /** + * mp_determine_pci_dstirq() - Determine PCI device's int pin on the I/O APIC + * + * This determines a PCI device's interrupt pin number on the I/O APIC. + * + * This can be implemented by platform codes to handle specifal cases, which + * do not conform to the normal chipset/board design where PIRQ[A-H] are mapped + * directly to I/O APIC INTPIN#16-23. + * + * @bus: bus number of the pci device + * @dev: device number of the pci device + * @func: function number of the pci device + * @pirq: PIRQ number the PCI device's interrupt pin is routed to + * @return: interrupt pin number on the I/O APIC + */ +int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq); + +/** * write_mp_table() - Write MP table * * This writes MP table at a given address. diff --git a/arch/x86/lib/mpspec.c b/arch/x86/lib/mpspec.c index f16fbcb..9b2a59b 100644 --- a/arch/x86/lib/mpspec.c +++ b/arch/x86/lib/mpspec.c @@ -269,6 +269,13 @@ static bool check_dup_entry(struct mpc_config_intsrc *intsrc_base, return (i == entry_num) ? false : true; } +/* TODO: move this to driver model */ +__weak int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq) +{ + /* PIRQ[A-H] are connected to I/O APIC INTPIN#16-23 */ + return pirq + 16; +} + static int mptable_add_intsrc(struct mp_config_table *mc, int bus_isa, int apicid) { @@ -304,24 +311,27 @@ static int mptable_add_intsrc(struct mp_config_table *mc, for (i = 0; i < count; i++) { struct pirq_routing pr; + int bus, dev, func; + int dstirq; pr.bdf = fdt_addr_to_cpu(cell[0]); pr.pin = fdt_addr_to_cpu(cell[1]); pr.pirq = fdt_addr_to_cpu(cell[2]); + bus = PCI_BUS(pr.bdf); + dev = PCI_DEV(pr.bdf); + func = PCI_FUNC(pr.bdf); if (check_dup_entry(intsrc_base, intsrc_entries, - PCI_BUS(pr.bdf), PCI_DEV(pr.bdf), pr.pin)) { + bus, dev, pr.pin)) { debug("found entry for bus %d device %d INT%c, skipping\n", - PCI_BUS(pr.bdf), PCI_DEV(pr.bdf), - 'A' + pr.pin - 1); + bus, dev, 'A' + pr.pin - 1); cell += sizeof(struct pirq_routing) / sizeof(u32); continue; } - /* PIRQ[A-H] are always connected to I/O APIC INTPIN#16-23 */ - mp_write_pci_intsrc(mc, MP_INT, PCI_BUS(pr.bdf), - PCI_DEV(pr.bdf), pr.pin, apicid, - pr.pirq + 16); + dstirq = mp_determine_pci_dstirq(bus, dev, func, pr.pirq); + mp_write_pci_intsrc(mc, MP_INT, bus, dev, pr.pin, + apicid, dstirq); intsrc_entries++; cell += sizeof(struct pirq_routing) / sizeof(u32); } -- 1.8.2.1

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[U-Boot] am33xx: Drop timer_init call from s_init - udelay is wrong at ddr configuration
by Egli, Samuel 21 Jul '15

21 Jul '15

Hi Tom, I stumbled over your commit b352dde1ea715e8481946ec7d8086b3c3eb126ae where you removed timer_init() from .../am33xx/board.c. In the commit message it's written that timer_init will be called earlier. However, since this commit udelay will not generate correct delays in spl code in our am335xx based boards. I'm wondering where the timer_init shold be placed. grep-ing the code I see that we have a call in spl.c but I this is too late. Doing some measurements, with this commit udelay is not correct at the time of: * board_init_ddr() * spl_siemens_board_init() I'm guessing that it might be a problem for other am33xx boards too, but I didn't verify this. Right now I just put it back into am33xx/board.c but maybe you have a better idea. Kind regards Sam

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[U-Boot] [PATCH v2] ARM: tegra: Add Tegra20 SPI device nodes
by Mirza Krak 21 Jul '15

21 Jul '15

From: Mirza Krak <mirza.krak(a)hostmobility.com> Add the device tree node for the SPI controllers found on Tegra20 SOCs. Signed-off-by: Mirza Krak <mirza.krak(a)hostmobility.com> --- Changes in v2: * Dropped tegra30-slink compatible string, based on comment from Thierry Reding on v1 patch arch/arm/dts/tegra20.dtsi | 44 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi index b8c8a923017e..e4d7c7a83473 100644 --- a/arch/arm/dts/tegra20.dtsi +++ b/arch/arm/dts/tegra20.dtsi @@ -268,6 +268,50 @@ #pwm-cells = <2>; }; + spi@7000d400 { + compatible = "nvidia,tegra20-slink"; + reg = <0x7000d400 0x200>; + interrupts = <0 59 0x04>; + nvidia,dma-request-selector = <&apbdma 15>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car 41>; + status = "disabled"; + }; + + spi@7000d600 { + compatible = "nvidia,tegra20-slink"; + reg = <0x7000d600 0x200>; + interrupts = <0 82 0x04>; + nvidia,dma-request-selector = <&apbdma 16>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car 44>; + status = "disabled"; + }; + + spi@7000d800 { + compatible = "nvidia,tegra20-slink"; + reg = <0x7000d480 0x200>; + interrupts = <0 83 0x04>; + nvidia,dma-request-selector = <&apbdma 17>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car 46>; + status = "disabled"; + }; + + spi@7000da00 { + compatible = "nvidia,tegra20-slink"; + reg = <0x7000da00 0x200>; + interrupts = <0 93 0x04>; + nvidia,dma-request-selector = <&apbdma 18>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car 68>; + status = "disabled"; + }; + i2c@7000c000 { #address-cells = <1>; #size-cells = <0>; -- 2.1.0

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[U-Boot] (no subject)
by Samuel Egli 21 Jul '15

21 Jul '15

Hi all, this is a re-submission of Bin Liu's patch that was reverted by the commit 16b61d13bab361853564da401b15fc34ae1dfea7 from Daniel Mack. It is not OK to set the MUSB_POWER_HSENAB unconditionally because there are sometimes some HW limitations that allow only FULL SPEED. In our case we have some bad wiring protection in our USB circuit that acts as a filter an will not allow signals to pass that are faster than FULL SPEED. I suggest to use CONFIG_USB_GADGET_DUALSPEED define to enable HIGH SPEED as it was done previously, which is by default enabled. Kind regards Sam

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[U-Boot] [PATCH 03/15][v2] imx: mmc: fsl_esdhc fix dcache issue
by Adrian Alonso 21 Jul '15

21 Jul '15

DCIMVAC is upgraded to DCCIMVAC for the individual processor (Cortex-A7) that the DCIMVAC is executed on. We should follow the linux dma follow. Before DMA read, first invalidate dcache then after DMA read, invalidate dcache again. With the DMA direction DMA_FROM_DEVICE, the dcache need be invalidated again after the DMA completion. The reason is that we need explicity make sure the dcache been invalidated thus to get the DMA'ed memory correctly from the physical memory. Any cache-line fill during the DMA operations such as the pre-fetching can cause the DMA coherency issue, thus CPU get the stale data. Signed-off-by: Peng Fan <Peng.Fan(a)freescale.com> Signed-off-by: Ye.Li <B37916(a)freescale.com> Signed-off-by: Nitin Garg <nitin.garg(a)freescale.com> Signed-off-by: Jason Liu <r64343(a)freescale.com> Signed-off-by: Adrian Alonso <aalonso(a)freescale.com> --- Changes for V2: Resend drivers/mmc/fsl_esdhc.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index c4719e6..0510bf0 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -341,6 +341,9 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) err = esdhc_setup_data(mmc, data); if(err) return err; + + if (data->flags & MMC_DATA_READ) + check_and_invalidate_dcache_range(cmd, data); } /* Figure out the transfer arguments */ @@ -437,6 +440,11 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) } } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE); + /* + * Need invalidate the dcache here again to avoid any + * cache-fill during the DMA operations such as the + * speculative pre-fetching etc. + */ if (data->flags & MMC_DATA_READ) check_and_invalidate_dcache_range(cmd, data); #endif -- 2.1.4

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[U-Boot] Please pull u-boot-fsl-qoriq master
by York Sun 21 Jul '15

21 Jul '15

Tom, The following changes since commit 605e15db2b54302364a2528d3c6604fbc57be846: Merge git://git.denx.de/u-boot-x86 (2015-07-15 10:41:20 -0400) are available in the git repository at: git://git.denx.de/u-boot-fsl-qoriq.git master for you to fetch changes up to db14f11dfe348550d8c10c6609277488d9f500d6: armv8/fsl-lsch3: Fix TCR_EL3 for the final MMU setup. (2015-07-20 11:44:40 -0700) ---------------------------------------------------------------- Alison Wang (2): arm: ls1021a: Remove the inappropriate use of the function 'sprintf' arm/ls102xa: Add little-endian mode support for audio IPs Bhupesh Sharma (4): armv8/ls2085a: Increase the supported kernel size armv8/ls2085a: Expose all DDR region(s) to Linux driver/fsl_debug_server: Fix the DDR hide logic for LS2085a arm/errata: Update required bits for A57 cores erratas Haikun Wang (7): arm/dts/ls2085a: Bring in ls2085a dts files from linux kernel arm/dts/ls2085a: Add DSPI dts node arm/dts/ls2085a: Add dts files for LS2085AQDS and LS2085ARDB armv8/ls2085a: Enable DSPI get input clk form 'mxc_get_clock' armv8/ls2085aqds: DSPI pin muxing configure through QIXIS armv8/ls2085aqds: Enable DSPI flash support for LS2085AQDS armv8/ls2085ardb: Enable DSPI flash support for LS2085ARDB Haikun.Wang(a)freescale.com (2): armv8/ls2085ardb: DSPI pin muxing configure through QIXIS CPLD armv8/ls2085a/defconfig: Enable FSL_DSPI, OF_CONTROL and DM support J. German Rivera (2): drivers/fsl-mc: Make MC boot error messages more readable drivers/fsl-mc: Autoload AOIP image from NOR flash Jaiprakash Singh (1): board/fsl/common: Fix eeprom system version endianness Prabhakar Kushwaha (21): armv8/ls2085ardb: Add eth & phy firmware loading support armv8/ls2085aqds: Add support of SerDes protocol 0x49 armv8/ls2085a: Update LS2085a PCIe compatible armv8/ls2085a: call ft_pcie_setup() to change dts status armv8/ls2085qds: Update SFP TX bit as "0" to enable XFI armv8/ls2085rdb: Update PCA9547PW slave address armv8/ls2085RDB: Update board version print logic armv8/fsl-ch3: Add support to print SoC personality armv8/ls2085a: Avoid hard-coding for board name print armv8/ls2085a: Update SoC README for DDR layout armv8/fsl-lsch3: Support 256M mem split for MC & dbg-srvr driver/ldpaa_eth:Flush buffer before seeding BMAN after TX_conf drivers: fsl-mc: Update flibs to mc-0.6.0.1 drivers: fsl-mc: Update qbman driver drivers: fsl-mc: Return error for major version mismatch driver/ldpaa_eth: Retry enqueue if portal was busy driver/ldpaa_eth: Add timeout handling DQRR entry read driver/ldpaa_eth: Avoid TX conf frames driver/ldpaa_eth:Avoid infinite loop in ldpaa_eth_rx board/ls2085rdb: Export functions for standalone AQ FW load apps board/ls2085a: Increase kernel_size value in env variable Priyanka Jain (1): armv8/ls2085a: Enable "date" command for QDS and RDB Stuart Yoder (4): armv8/ls2085a: enable debug server armv8/fsl-lsch3: partition stream IDs drivers/fsl-mc: dynamically create ICID pool in DPC armv8/fsl-lsch3: device tree fixups for PCI stream IDs Wang Dongsheng (2): ARMv7: Factor out reusable timer_wait from sunxi/psci_sun7i.S arm/ls102xa: Add PSCI support for ls102xa Yangbo Lu (1): armv8/ls2085ardb: add hwconfig setting for eSDHC York Sun (3): armv8/fsl-lsch3: Fix DDR speed message driver/ddr/fsl: Add a hook to update SPD address armv8/ls2085ardb: Fix SPD address error on early boards Zhichun Hua (2): armv8: Fix TCR macros for shareability attribute armv8/fsl-lsch3: Fix TCR_EL3 for the final MMU setup. README | 15 ++ arch/arm/cpu/armv7/ls102xa/Makefile | 4 + arch/arm/cpu/armv7/ls102xa/fdt.c | 21 +-- arch/arm/cpu/armv7/ls102xa/psci.S | 126 +++++++++++++++ arch/arm/cpu/armv7/sunxi/psci_sun6i.S | 22 +-- arch/arm/cpu/armv7/sunxi/psci_sun7i.S | 22 +-- arch/arm/cpu/armv8/fsl-lsch3/README | 25 +++ arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 64 ++++++-- arch/arm/cpu/armv8/fsl-lsch3/fdt.c | 114 ++++++++++++++ arch/arm/cpu/armv8/fsl-lsch3/speed.c | 2 + arch/arm/cpu/armv8/start.S | 8 +- arch/arm/dts/Makefile | 2 + arch/arm/dts/fsl-ls2085a-qds.dts | 53 +++++++ arch/arm/dts/fsl-ls2085a-rdb.dts | 35 +++++ arch/arm/dts/fsl-ls2085a.dtsi | 129 ++++++++++++++++ arch/arm/include/asm/arch-armv7/generictimer.h | 50 ++++++ arch/arm/include/asm/arch-fsl-lsch3/clock.h | 1 + arch/arm/include/asm/arch-fsl-lsch3/config.h | 2 + arch/arm/include/asm/arch-fsl-lsch3/fdt.h | 10 ++ .../include/asm/arch-fsl-lsch3/ls2085a_stream_id.h | 64 ++++++++ arch/arm/include/asm/arch-fsl-lsch3/soc.h | 20 +++ arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 3 +- arch/arm/include/asm/armv8/mmu.h | 4 +- board/freescale/common/sys_eeprom.c | 8 +- board/freescale/ls1021aqds/ls1021aqds.c | 3 + board/freescale/ls1021atwr/ls1021atwr.c | 3 + board/freescale/ls2085a/README | 11 ++ board/freescale/ls2085a/ls2085a.c | 17 +- board/freescale/ls2085aqds/README | 19 +++ board/freescale/ls2085aqds/eth.c | 4 +- board/freescale/ls2085aqds/ls2085aqds.c | 71 ++++++++- board/freescale/ls2085ardb/Makefile | 2 +- board/freescale/ls2085ardb/README | 11 ++ board/freescale/ls2085ardb/eth_ls2085rdb.c | 148 ++++++++++++++++++ board/freescale/ls2085ardb/ls2085ardb.c | 111 +++++++++++--- common/exports.c | 7 + configs/ls2085aqds_defconfig | 7 + configs/ls2085ardb_defconfig | 7 + drivers/ddr/fsl/main.c | 8 + drivers/misc/fsl_debug_server.c | 5 + drivers/net/fsl-mc/dpio/qbman_portal.c | 66 ++++---- drivers/net/fsl-mc/dpio/qbman_portal.h | 22 ++- drivers/net/fsl-mc/dpio/qbman_private.h | 2 +- drivers/net/fsl-mc/dpni.c | 2 +- drivers/net/fsl-mc/mc.c | 121 +++++++++++---- drivers/net/ldpaa_eth/ldpaa_eth.c | 162 ++++++-------------- drivers/net/ldpaa_eth/ldpaa_eth.h | 1 - drivers/pci/pcie_layerscape.c | 62 ++++++++ include/_exports.h | 13 ++ include/configs/ls1021aqds.h | 2 + include/configs/ls1021atwr.h | 2 + include/configs/ls2085a_common.h | 28 +++- include/configs/ls2085aqds.h | 17 +- include/configs/ls2085ardb.h | 49 +++++- include/exports.h | 13 +- include/fsl-mc/fsl_dpio.h | 32 ++-- include/fsl-mc/fsl_dpmng.h | 2 +- include/fsl-mc/fsl_dpni.h | 144 ++++++++++++++--- include/fsl-mc/fsl_dprc.h | 64 ++++++-- include/fsl-mc/fsl_mc.h | 5 +- include/fsl_ddr.h | 3 + 61 files changed, 1673 insertions(+), 377 deletions(-) create mode 100644 arch/arm/cpu/armv7/ls102xa/psci.S create mode 100644 arch/arm/dts/fsl-ls2085a-qds.dts create mode 100644 arch/arm/dts/fsl-ls2085a-rdb.dts create mode 100644 arch/arm/dts/fsl-ls2085a.dtsi create mode 100644 arch/arm/include/asm/arch-armv7/generictimer.h create mode 100644 arch/arm/include/asm/arch-fsl-lsch3/fdt.h create mode 100644 arch/arm/include/asm/arch-fsl-lsch3/ls2085a_stream_id.h create mode 100644 board/freescale/ls2085ardb/eth_ls2085rdb.c Thanks. York

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