July 2015 - U-Boot

[U-Boot] [PATCH v2] arm: mvebu: add multiple usb-hostcontroller support for AXP
by Anton Schubert 23 Jul '15

23 Jul '15

This patch adds support for multiple hostcontrollers to the ehci-marvell driver and enables all 3 usb-hcs on the db-mv784mp-gp board. It depends on the initial Armada XP usb support patch from Stefan. Signed-off-by: Anton Schubert <anton.schubert(a)gmx.de> Reviewed-by: Stefan Roese <sr(a)denx.de> Cc: Luka Perkov <luka.perkov(a)sartura.hr> --- Changes in v2: - don't use the wrl accessor function - use the correct hccr pointer drivers/usb/host/ehci-marvell.c | 17 +++++++++-------- include/configs/db-mv784mp-gp.h | 1 + 2 files changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/usb/host/ehci-marvell.c b/drivers/usb/host/ehci-marvell.c index fda812e..daff0d7 100644 --- a/drivers/usb/host/ehci-marvell.c +++ b/drivers/usb/host/ehci-marvell.c @@ -38,13 +38,14 @@ DECLARE_GLOBAL_DATA_PTR; #define MVUSB0_BASE \ (mvebu_soc_family() == MVEBU_SOC_A38X ? \ MVEBU_USB20_BASE : MVEBU_AXP_USB_BASE) +#define MVUSB_BASE(port) MVUSB0_BASE + ((port) << 12) /* * Once all the older Marvell SoC's (Orion, Kirkwood) are converted * to the common mvebu archticture including the mbus setup, this * will be the only function needed to configure the access windows */ -static void usb_brg_adrdec_setup(void) +static void usb_brg_adrdec_setup(int index) { const struct mbus_dram_target_info *dram; int i; @@ -52,8 +53,8 @@ static void usb_brg_adrdec_setup(void) dram = mvebu_mbus_dram_info(); for (i = 0; i < 4; i++) { - writel(0, MVUSB0_BASE + USB_WINDOW_CTRL(i)); - writel(0, MVUSB0_BASE + USB_WINDOW_BASE(i)); + writel(0, MVUSB_BASE(index) + USB_WINDOW_CTRL(i)); + writel(0, MVUSB_BASE(index) + USB_WINDOW_BASE(i)); } for (i = 0; i < dram->num_cs; i++) { @@ -62,14 +63,14 @@ static void usb_brg_adrdec_setup(void) /* Write size, attributes and target id to control register */ writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) | (dram->mbus_dram_target_id << 4) | 1, - MVUSB0_BASE + USB_WINDOW_CTRL(i)); + MVUSB_BASE(index) + USB_WINDOW_CTRL(i)); /* Write base address to base register */ - writel(cs->base, MVUSB0_BASE + USB_WINDOW_BASE(i)); + writel(cs->base, MVUSB_BASE(index) + USB_WINDOW_BASE(i)); } } #else -static void usb_brg_adrdec_setup(void) +static void usb_brg_adrdec_setup(int index) { int i; u32 size, base, attrib; @@ -118,9 +119,9 @@ static void usb_brg_adrdec_setup(void) int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr, struct ehci_hcor **hcor) { - usb_brg_adrdec_setup(); + usb_brg_adrdec_setup(index); - *hccr = (struct ehci_hccr *)(MVUSB0_BASE + 0x100); + *hccr = (struct ehci_hccr *)(MVUSB_BASE(index) + 0x100); *hcor = (struct ehci_hcor *)((uint32_t) *hccr + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h index 1314fd3..21581e2 100644 --- a/include/configs/db-mv784mp-gp.h +++ b/include/configs/db-mv784mp-gp.h @@ -47,6 +47,7 @@ #define CONFIG_USB_STORAGE #define CONFIG_USB_EHCI_MARVELL #define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 /* SPI NOR flash default params, used by sf commands */ #define CONFIG_SF_DEFAULT_SPEED 1000000 -- 2.3.6

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[U-Boot] [PATCH 0/7] UniPhier SoC changes for v2015.10-rc1
by Masahiro Yamada 23 Jul '15

23 Jul '15

Masahiro Yamada (7): ARM: UniPhier: add environment sets for non-FIT Linux boot ARM: UniPhier: add environment variable for TFTP boot ARM: UniPhier: disable CONFIG_FIT ARM: UniPhier: update CONFIG_BOOTARGS ARM: UniPhier: add PH1-sLD3 SoC support ARM: dts: UniPhier: add I2C ch4 device node for PH1-sLD3 ARM: UniPhier: document reference support card arch/arm/dts/uniphier-ph1-sld3.dtsi | 9 ++ arch/arm/mach-uniphier/Kconfig | 12 ++- arch/arm/mach-uniphier/Makefile | 7 +- arch/arm/mach-uniphier/include/mach/sc-regs.h | 6 +- arch/arm/mach-uniphier/include/mach/sg-regs.h | 5 +- arch/arm/mach-uniphier/ph1-sld3/Makefile | 16 ++++ arch/arm/mach-uniphier/ph1-sld3/bcu_init.c | 36 +++++++ arch/arm/mach-uniphier/ph1-sld3/boot-mode.c | 97 +++++++++++++++++++ arch/arm/mach-uniphier/ph1-sld3/clkrst_init.c | 1 + .../arm/mach-uniphier/ph1-sld3/early_clkrst_init.c | 1 + arch/arm/mach-uniphier/ph1-sld3/early_pinctrl.c | 23 +++++ arch/arm/mach-uniphier/ph1-sld3/lowlevel_debug.S | 31 +++++++ arch/arm/mach-uniphier/ph1-sld3/memconf.c | 52 +++++++++++ arch/arm/mach-uniphier/ph1-sld3/pinctrl.c | 24 +++++ arch/arm/mach-uniphier/ph1-sld3/platdevice.c | 1 + arch/arm/mach-uniphier/ph1-sld3/pll_init.c | 10 ++ arch/arm/mach-uniphier/ph1-sld3/pll_spectrum.c | 18 ++++ arch/arm/mach-uniphier/ph1-sld3/sbc_init.c | 45 +++++++++ arch/arm/mach-uniphier/ph1-sld3/sbc_init_3cs.c | 37 ++++++++ arch/arm/mach-uniphier/ph1-sld3/sg_init.c | 9 ++ arch/arm/mach-uniphier/ph1-sld3/umc_init.c | 15 +++ configs/ph1_ld4_defconfig | 2 - configs/ph1_pro4_defconfig | 2 - configs/ph1_sld3_defconfig | 28 ++++++ configs/ph1_sld8_defconfig | 2 - doc/README.uniphier | 54 ++++++++++- include/configs/uniphier.h | 103 ++++++++++++++++----- 27 files changed, 602 insertions(+), 44 deletions(-) create mode 100644 arch/arm/mach-uniphier/ph1-sld3/Makefile create mode 100644 arch/arm/mach-uniphier/ph1-sld3/bcu_init.c create mode 100644 arch/arm/mach-uniphier/ph1-sld3/boot-mode.c create mode 100644 arch/arm/mach-uniphier/ph1-sld3/clkrst_init.c create mode 100644 arch/arm/mach-uniphier/ph1-sld3/early_clkrst_init.c create mode 100644 arch/arm/mach-uniphier/ph1-sld3/early_pinctrl.c create mode 100644 arch/arm/mach-uniphier/ph1-sld3/lowlevel_debug.S create mode 100644 arch/arm/mach-uniphier/ph1-sld3/memconf.c create mode 100644 arch/arm/mach-uniphier/ph1-sld3/pinctrl.c create mode 100644 arch/arm/mach-uniphier/ph1-sld3/platdevice.c create mode 100644 arch/arm/mach-uniphier/ph1-sld3/pll_init.c create mode 100644 arch/arm/mach-uniphier/ph1-sld3/pll_spectrum.c create mode 100644 arch/arm/mach-uniphier/ph1-sld3/sbc_init.c create mode 100644 arch/arm/mach-uniphier/ph1-sld3/sbc_init_3cs.c create mode 100644 arch/arm/mach-uniphier/ph1-sld3/sg_init.c create mode 100644 arch/arm/mach-uniphier/ph1-sld3/umc_init.c create mode 100644 configs/ph1_sld3_defconfig -- 1.9.1

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[U-Boot] [PATCH] ARM: dts: UniPhier: add device-specific compatible string for EEPROM
by Masahiro Yamada 23 Jul '15

23 Jul '15

For the record, describe exactly which device of which vendor is used on this board. I2C EEPROM is bound by the generic compatible string, "i2c-eeprom", so this commit has no impact on the functionality. Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- arch/arm/dts/uniphier-ref-daughter.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/uniphier-ref-daughter.dtsi b/arch/arm/dts/uniphier-ref-daughter.dtsi index 84b2206..b8960fd 100644 --- a/arch/arm/dts/uniphier-ref-daughter.dtsi +++ b/arch/arm/dts/uniphier-ref-daughter.dtsi @@ -8,7 +8,7 @@ &i2c0 { eeprom { - compatible = "i2c-eeprom"; + compatible = "microchip,24lc128", "i2c-eeprom"; reg = <0x50>; u-boot,i2c-offset-len = <2>; }; -- 1.9.1

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[U-Boot] [PATCH 1/1] driver: net: keystone_net: fix phy mode configuration
by Mugunthan V N 23 Jul '15

23 Jul '15

Phy mode is a board property and it can be different between multiple board and ports, so it should not be hardcoded in driver to one specific mode. So adding a field in eth_priv_t structure to pass phy mode to driver. Cc: Murali Karicheri <m-karicheri2(a)ti.com> Cc: Lokesh Vutla <lokeshvutla(a)ti.com> Cc: Vitaly Andrianov <vitalya(a)ti.com> Cc: Joe Hershberger <joe.hershberger(a)ni.com> Signed-off-by: Mugunthan V N <mugunthanvnm(a)ti.com> --- arch/arm/include/asm/ti-common/keystone_net.h | 2 ++ board/ti/ks2_evm/board_k2e.c | 8 ++++++++ board/ti/ks2_evm/board_k2hk.c | 4 ++++ board/ti/ks2_evm/board_k2l.c | 4 ++++ drivers/net/keystone_net.c | 4 ++-- 5 files changed, 20 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/ti-common/keystone_net.h b/arch/arm/include/asm/ti-common/keystone_net.h index 011c03c..235a9fa 100644 --- a/arch/arm/include/asm/ti-common/keystone_net.h +++ b/arch/arm/include/asm/ti-common/keystone_net.h @@ -11,6 +11,7 @@ #define _KEYSTONE_NET_H_ #include <asm/io.h> +#include <phy.h> /* EMAC */ #ifdef CONFIG_KSNET_NETCP_V1_0 @@ -239,6 +240,7 @@ struct eth_priv_t { int phy_addr; int slave_port; int sgmii_link_type; + phy_interface_t phy_if; struct phy_device *phy_dev; }; diff --git a/board/ti/ks2_evm/board_k2e.c b/board/ti/ks2_evm/board_k2e.c index 43dfc48..59c6516 100644 --- a/board/ti/ks2_evm/board_k2e.c +++ b/board/ti/ks2_evm/board_k2e.c @@ -47,6 +47,7 @@ struct eth_priv_t eth_priv_cfg[] = { .phy_addr = 0, .slave_port = 1, .sgmii_link_type = SGMII_LINK_MAC_PHY, + .phy_if = PHY_INTERFACE_MODE_SGMII, }, { .int_name = "K2E_EMAC1", @@ -54,6 +55,7 @@ struct eth_priv_t eth_priv_cfg[] = { .phy_addr = 1, .slave_port = 2, .sgmii_link_type = SGMII_LINK_MAC_PHY, + .phy_if = PHY_INTERFACE_MODE_SGMII, }, { .int_name = "K2E_EMAC2", @@ -61,6 +63,7 @@ struct eth_priv_t eth_priv_cfg[] = { .phy_addr = 2, .slave_port = 3, .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + .phy_if = PHY_INTERFACE_MODE_SGMII, }, { .int_name = "K2E_EMAC3", @@ -68,6 +71,7 @@ struct eth_priv_t eth_priv_cfg[] = { .phy_addr = 3, .slave_port = 4, .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + .phy_if = PHY_INTERFACE_MODE_SGMII, }, { .int_name = "K2E_EMAC4", @@ -75,6 +79,7 @@ struct eth_priv_t eth_priv_cfg[] = { .phy_addr = 4, .slave_port = 5, .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + .phy_if = PHY_INTERFACE_MODE_SGMII, }, { .int_name = "K2E_EMAC5", @@ -82,6 +87,7 @@ struct eth_priv_t eth_priv_cfg[] = { .phy_addr = 5, .slave_port = 6, .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + .phy_if = PHY_INTERFACE_MODE_SGMII, }, { .int_name = "K2E_EMAC6", @@ -89,6 +95,7 @@ struct eth_priv_t eth_priv_cfg[] = { .phy_addr = 6, .slave_port = 7, .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + .phy_if = PHY_INTERFACE_MODE_SGMII, }, { .int_name = "K2E_EMAC7", @@ -96,6 +103,7 @@ struct eth_priv_t eth_priv_cfg[] = { .phy_addr = 7, .slave_port = 8, .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + .phy_if = PHY_INTERFACE_MODE_SGMII, }, }; diff --git a/board/ti/ks2_evm/board_k2hk.c b/board/ti/ks2_evm/board_k2hk.c index ed181f4..acd4205 100644 --- a/board/ti/ks2_evm/board_k2hk.c +++ b/board/ti/ks2_evm/board_k2hk.c @@ -54,6 +54,7 @@ struct eth_priv_t eth_priv_cfg[] = { .phy_addr = 0, .slave_port = 1, .sgmii_link_type = SGMII_LINK_MAC_PHY, + .phy_if = PHY_INTERFACE_MODE_SGMII, }, { .int_name = "K2HK_EMAC1", @@ -61,6 +62,7 @@ struct eth_priv_t eth_priv_cfg[] = { .phy_addr = 1, .slave_port = 2, .sgmii_link_type = SGMII_LINK_MAC_PHY, + .phy_if = PHY_INTERFACE_MODE_SGMII, }, { .int_name = "K2HK_EMAC2", @@ -68,6 +70,7 @@ struct eth_priv_t eth_priv_cfg[] = { .phy_addr = 2, .slave_port = 3, .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + .phy_if = PHY_INTERFACE_MODE_SGMII, }, { .int_name = "K2HK_EMAC3", @@ -75,6 +78,7 @@ struct eth_priv_t eth_priv_cfg[] = { .phy_addr = 3, .slave_port = 4, .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + .phy_if = PHY_INTERFACE_MODE_SGMII, }, }; diff --git a/board/ti/ks2_evm/board_k2l.c b/board/ti/ks2_evm/board_k2l.c index 729a193..41e7f70 100644 --- a/board/ti/ks2_evm/board_k2l.c +++ b/board/ti/ks2_evm/board_k2l.c @@ -50,6 +50,7 @@ struct eth_priv_t eth_priv_cfg[] = { .phy_addr = 0, .slave_port = 1, .sgmii_link_type = SGMII_LINK_MAC_PHY, + .phy_if = PHY_INTERFACE_MODE_SGMII, }, { .int_name = "K2L_EMAC1", @@ -57,6 +58,7 @@ struct eth_priv_t eth_priv_cfg[] = { .phy_addr = 1, .slave_port = 2, .sgmii_link_type = SGMII_LINK_MAC_PHY, + .phy_if = PHY_INTERFACE_MODE_SGMII, }, { .int_name = "K2L_EMAC2", @@ -64,6 +66,7 @@ struct eth_priv_t eth_priv_cfg[] = { .phy_addr = 2, .slave_port = 3, .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + .phy_if = PHY_INTERFACE_MODE_SGMII, }, { .int_name = "K2L_EMAC3", @@ -71,6 +74,7 @@ struct eth_priv_t eth_priv_cfg[] = { .phy_addr = 3, .slave_port = 4, .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + .phy_if = PHY_INTERFACE_MODE_SGMII, }, }; diff --git a/drivers/net/keystone_net.c b/drivers/net/keystone_net.c index 0c5fdee..21e17bf 100644 --- a/drivers/net/keystone_net.c +++ b/drivers/net/keystone_net.c @@ -559,11 +559,11 @@ int keystone2_emac_initialize(struct eth_priv_t *eth_priv) /* Create phy device and bind it with driver */ #ifdef CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE phy_dev = phy_connect(mdio_bus, eth_priv->phy_addr, - dev, PHY_INTERFACE_MODE_SGMII); + dev, eth_priv->phy_if); phy_config(phy_dev); #else phy_dev = phy_find_by_mask(mdio_bus, 1 << eth_priv->phy_addr, - PHY_INTERFACE_MODE_SGMII); + eth_priv->phy_if); phy_dev->dev = dev; #endif eth_priv->phy_dev = phy_dev; -- 2.5.0.rc2.13.g961abca

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[U-Boot] [PATCH] arm: mvebu: add multiple usb-hostcontroller support for AXP
by Anton Schubert 23 Jul '15

23 Jul '15

This patch adds support for multiple hostcontrollers to the ehci-marvell driver and enables all 3 usb-hcs on the db-mv784mp-gp board. It depends on the initial Armada XP usb support patch from Stefan. Signed-off-by: Anton Schubert <anton.schubert(a)gmx.de> Cc: Stefan Roese <sr(a)denx.de> Cc: Luka Perkov <luka.perkov(a)sartura.hr> --- drivers/usb/host/ehci-marvell.c | 23 ++++++++++++----------- include/configs/db-mv784mp-gp.h | 1 + 2 files changed, 13 insertions(+), 11 deletions(-) diff --git a/drivers/usb/host/ehci-marvell.c b/drivers/usb/host/ehci-marvell.c index 826e7f7..6548cb2 100644 --- a/drivers/usb/host/ehci-marvell.c +++ b/drivers/usb/host/ehci-marvell.c @@ -22,7 +22,8 @@ DECLARE_GLOBAL_DATA_PTR; #define rdl(off) readl(MVUSB0_BASE + (off)) -#define wrl(off, val) writel((val), MVUSB0_BASE + (off)) +#define wrl(port, off, val) writel((val), MVUSB0_BASE + (off) + \ + ((port) << 12)) #define USB_WINDOW_CTRL(i) (0x320 + ((i) << 4)) #define USB_WINDOW_BASE(i) (0x324 + ((i) << 4)) @@ -47,7 +48,7 @@ DECLARE_GLOBAL_DATA_PTR; * to the common mvebu archticture including the mbus setup, this * will be the only function needed to configure the access windows */ -static void usb_brg_adrdec_setup(void) +static void usb_brg_adrdec_setup(int index) { const struct mbus_dram_target_info *dram; int i; @@ -55,24 +56,24 @@ static void usb_brg_adrdec_setup(void) dram = mvebu_mbus_dram_info(); for (i = 0; i < 4; i++) { - wrl(USB_WINDOW_CTRL(i), 0); - wrl(USB_WINDOW_BASE(i), 0); + wrl(index, USB_WINDOW_CTRL(i), 0); + wrl(index, USB_WINDOW_BASE(i), 0); } for (i = 0; i < dram->num_cs; i++) { const struct mbus_dram_window *cs = dram->cs + i; /* Write size, attributes and target id to control register */ - wrl(USB_WINDOW_CTRL(i), + wrl(index, USB_WINDOW_CTRL(i), ((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) | (dram->mbus_dram_target_id << 4) | 1); /* Write base address to base register */ - wrl(USB_WINDOW_BASE(i), cs->base); + wrl(index, USB_WINDOW_BASE(i), cs->base); } } #else -static void usb_brg_adrdec_setup(void) +static void usb_brg_adrdec_setup(int index) { int i; u32 size, base, attrib; @@ -102,13 +103,13 @@ static void usb_brg_adrdec_setup(void) size = gd->bd->bi_dram[i].size; base = gd->bd->bi_dram[i].start; if ((size) && (attrib)) - wrl(USB_WINDOW_CTRL(i), + wrl(index, USB_WINDOW_CTRL(i), MVCPU_WIN_CTRL_DATA(size, USB_TARGET_DRAM, attrib, MVCPU_WIN_ENABLE)); else - wrl(USB_WINDOW_CTRL(i), MVCPU_WIN_DISABLE); + wrl(index, USB_WINDOW_CTRL(i), MVCPU_WIN_DISABLE); - wrl(USB_WINDOW_BASE(i), base); + wrl(index, USB_WINDOW_BASE(i), base); } } #endif @@ -120,7 +121,7 @@ static void usb_brg_adrdec_setup(void) int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr, struct ehci_hcor **hcor) { - usb_brg_adrdec_setup(); + usb_brg_adrdec_setup(index); *hccr = (struct ehci_hccr *)(MVUSB0_BASE + 0x100); *hcor = (struct ehci_hcor *)((uint32_t) *hccr diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h index 1314fd3..21581e2 100644 --- a/include/configs/db-mv784mp-gp.h +++ b/include/configs/db-mv784mp-gp.h @@ -47,6 +47,7 @@ #define CONFIG_USB_STORAGE #define CONFIG_USB_EHCI_MARVELL #define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 /* SPI NOR flash default params, used by sf commands */ #define CONFIG_SF_DEFAULT_SPEED 1000000 -- 2.3.6

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[U-Boot] [PATCH 1/3] ARM: zynqmp: Wire up ethernet controllers
by Michal Simek 23 Jul '15

23 Jul '15

Wire up ethernet controllers and enable MII and BOOTP options. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- arch/arm/include/asm/arch-zynqmp/hardware.h | 5 +++++ arch/arm/include/asm/arch-zynqmp/sys_proto.h | 5 +++++ board/xilinx/zynqmp/zynqmp.c | 25 +++++++++++++++++++++++++ include/configs/xilinx_zynqmp.h | 21 +++++++++++++++++++++ 4 files changed, 56 insertions(+) diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h index 15bd519bfbe1..5d191e848cca 100644 --- a/arch/arm/include/asm/arch-zynqmp/hardware.h +++ b/arch/arm/include/asm/arch-zynqmp/hardware.h @@ -11,6 +11,11 @@ #define ZYNQ_SERIAL_BASEADDR0 0xFF000000 #define ZYNQ_SERIAL_BASEADDR1 0xFF001000 +#define ZYNQ_GEM_BASEADDR0 0xFF0B0000 +#define ZYNQ_GEM_BASEADDR1 0xFF0C0000 +#define ZYNQ_GEM_BASEADDR2 0xFF0D0000 +#define ZYNQ_GEM_BASEADDR3 0xFF0E0000 + #define ZYNQ_SPI_BASEADDR0 0xFF040000 #define ZYNQ_SPI_BASEADDR1 0xFF050000 diff --git a/arch/arm/include/asm/arch-zynqmp/sys_proto.h b/arch/arm/include/asm/arch-zynqmp/sys_proto.h index 3ca15cb6e588..f5c90d11dc40 100644 --- a/arch/arm/include/asm/arch-zynqmp/sys_proto.h +++ b/arch/arm/include/asm/arch-zynqmp/sys_proto.h @@ -8,6 +8,11 @@ #ifndef _ASM_ARCH_SYS_PROTO_H #define _ASM_ARCH_SYS_PROTO_H +/* Setup clk for network */ +static inline void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate) +{ +} + int zynq_sdhci_init(unsigned long regbase); int zynq_slcr_get_mio_pin_status(const char *periph); diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index f5ff64d988e5..fb43cb0b9aa2 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -51,6 +51,31 @@ void reset_cpu(ulong addr) { } +int board_eth_init(bd_t *bis) +{ + u32 ret = 0; + +#if defined(CONFIG_ZYNQ_GEM) +# if defined(CONFIG_ZYNQ_GEM0) + ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0, + CONFIG_ZYNQ_GEM_PHY_ADDR0, 0); +# endif +# if defined(CONFIG_ZYNQ_GEM1) + ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1, + CONFIG_ZYNQ_GEM_PHY_ADDR1, 0); +# endif +# if defined(CONFIG_ZYNQ_GEM2) + ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR2, + CONFIG_ZYNQ_GEM_PHY_ADDR2, 0); +# endif +# if defined(CONFIG_ZYNQ_GEM3) + ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR3, + CONFIG_ZYNQ_GEM_PHY_ADDR3, 0); +# endif +#endif + return ret; +} + #ifdef CONFIG_CMD_MMC int board_mmc_init(bd_t *bd) { diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 8cb276ca709d..9ed8771ff507 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -76,6 +76,16 @@ #define CONFIG_CMD_ELF #define CONFIG_MP +#define CONFIG_CMD_MII + +/* BOOTP options */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_MAY_FAIL +#define CONFIG_BOOTP_SERVERIP + /* SPI */ #ifdef CONFIG_ZYNQ_SPI # define CONFIG_SPI_FLASH_SST @@ -130,6 +140,17 @@ #define CONFIG_CMDLINE_EDITING #define CONFIG_SYS_MAXARGS 64 +/* Ethernet driver */ +#if defined(CONFIG_ZYNQ_GEM0) || defined(CONFIG_ZYNQ_GEM1) || \ + defined(CONFIG_ZYNQ_GEM2) || defined(CONFIG_ZYNQ_GEM3) +# define CONFIG_NET_MULTI +# define CONFIG_ZYNQ_GEM +# define CONFIG_MII +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +# define CONFIG_PHYLIB +# define CONFIG_PHY_MARVELL +#endif + /* I2C */ #if defined(CONFIG_SYS_I2C_ZYNQ) # define CONFIG_CMD_I2C -- 2.3.5

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[U-Boot] Kconfig for SPL
by Simon Glass 23 Jul '15

23 Jul '15

HI Masahiro, In my fiddling with Rockchip in SPL I found that the current single config is simple, but a little too limited. You discussed this briefly with someone from Marvell also. At present we effectively have two options: 1. decide for all boards that a uclass should be supported in SPL (and put it in Makefile.spl, or not) 2. ugly #undefs to try to fix things up after the fact (i.e. #ifdef CONFIG_SPL_BUILD...#undef CONFIG_PINCTRL) You mentioned the idea of allowing something like this: spl-$(CONFIG_FRED) += file.o In practice I assume you would generate two config headers from the same input: one for SPL and one for U-Boot proper. Another option would be to allow several states for the same config. At present in the .config files we have: CONFIG_FRED=y We could allow: CONFIG_FRED=yyn meaning yes for U-Boot proper, yes for SPL, no for TPL (assuming these are enabled for the board). For this we would need a new type, similar to tristate which allows cycling through the options. In the Makefile we could have obj-$(CONFIG_FRED) += file.o and then Kbuild would do the right thing - i.e. include the file for U-Boot proper, SPL but not TPL. What do you think about this? I fear that we need to figure something out... Regards, Simon

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[U-Boot] [PATCH 07/10 v2] arm: mvebu: Enable NAND controller on MVEBU SoC's
by Stefan Roese 23 Jul '15

23 Jul '15

This patch enables the NAND controller on the Armada XP/38x and provides a new function that returns the NAND controller input clock. This function will be used by the MVEBU NAND driver. As part of this patch, the multiple BIT macro definitions are moved to a common place in soc.h. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Peter Morrow <peter(a)senient.com> Cc: Luka Perkov <luka.perkov(a)sartura.hr> --- v2: - Use clrsetbits_le32() arch/arm/mach-mvebu/cpu.c | 17 +++++++++++++++++ arch/arm/mach-mvebu/include/mach/cpu.h | 1 + arch/arm/mach-mvebu/include/mach/soc.h | 22 ++++++++++++++++++++++ arch/arm/mach-mvebu/mbus.c | 2 -- board/Marvell/db-88f6820-gp/db-88f6820-gp.c | 2 -- board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c | 2 -- drivers/net/mvneta.c | 1 - 7 files changed, 40 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index fa82067..38e15aa 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -241,6 +241,16 @@ int arch_cpu_init(void) */ mvebu_mbus_probe(windows, ARRAY_SIZE(windows)); + if (mvebu_soc_family() == MVEBU_SOC_AXP) { + /* Enable GBE0, GBE1, LCD and NFC PUP */ + clrsetbits_le32(ARMADA_XP_PUP_ENABLE, 0, + GE0_PUP_EN | GE1_PUP_EN | LCD_PUP_EN | + NAND_PUP_EN | SPI_PUP_EN); + } + + /* Enable NAND and NAND arbiter */ + clrsetbits_le32(MVEBU_SOC_DEV_MUX_REG, 0, NAND_EN | NAND_ARBITER_EN); + /* Disable MBUS error propagation */ clrsetbits_le32(SOC_COHERENCY_FABRIC_CTRL_REG, MBUS_ERR_PROP_EN, 0); @@ -248,6 +258,13 @@ int arch_cpu_init(void) } #endif /* CONFIG_ARCH_CPU_INIT */ +u32 mvebu_get_nand_clock(void) +{ + return CONFIG_SYS_MVEBU_PLL_CLOCK / + ((readl(MVEBU_CORE_DIV_CLK_CTRL(1)) & + NAND_ECC_DIVCKL_RATIO_MASK) >> NAND_ECC_DIVCKL_RATIO_OFFS); +} + /* * SOC specific misc init */ diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h index 674fdaa..6fa4173 100644 --- a/arch/arm/mach-mvebu/include/mach/cpu.h +++ b/arch/arm/mach-mvebu/include/mach/cpu.h @@ -117,6 +117,7 @@ unsigned int mvebu_sdram_bs(enum memory_bank bank); void mvebu_sdram_size_adjust(enum memory_bank bank); int mvebu_mbus_probe(struct mbus_win windows[], int count); int mvebu_soc_family(void); +u32 mvebu_get_nand_clock(void); int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks); diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index a29e5dc..6115d6e 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -11,6 +11,8 @@ #ifndef _MVEBU_SOC_H #define _MVEBU_SOC_H +#define BIT(x) (1 << (x)) + #define SOC_MV78460_ID 0x7846 #define SOC_88F6810_ID 0x6810 #define SOC_88F6820_ID 0x6820 @@ -25,6 +27,9 @@ #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ #endif +/* Armada XP PLL frequency (used for NAND clock generation) */ +#define CONFIG_SYS_MVEBU_PLL_CLOCK 2000000000 + /* SOC specific definations */ #define INTREG_BASE 0xd0000000 #define INTREG_BASE_ADDR_REG (INTREG_BASE + 0x20080) @@ -53,6 +58,7 @@ #define MVEBU_GPIO1_BASE (MVEBU_REGISTER(0x18140)) #define MVEBU_GPIO2_BASE (MVEBU_REGISTER(0x18180)) #define MVEBU_SYSTEM_REG_BASE (MVEBU_REGISTER(0x18200)) +#define MVEBU_CLOCK_BASE (MVEBU_REGISTER(0x18700)) #define MVEBU_CPU_WIN_BASE (MVEBU_REGISTER(0x20000)) #define MVEBU_SDRAM_BASE (MVEBU_REGISTER(0x20180)) #define MVEBU_TIMER_BASE (MVEBU_REGISTER(0x20300)) @@ -64,6 +70,7 @@ #define MVEBU_EGIGA1_BASE (MVEBU_REGISTER(0x74000)) #define MVEBU_AXP_SATA_BASE (MVEBU_REGISTER(0xa0000)) #define MVEBU_SATA0_BASE (MVEBU_REGISTER(0xa8000)) +#define MVEBU_NAND_BASE (MVEBU_REGISTER(0xd0000)) #define MVEBU_SDIO_BASE (MVEBU_REGISTER(0xd8000)) #define SOC_COHERENCY_FABRIC_CTRL_REG (MVEBU_REGISTER(0x20200)) @@ -72,6 +79,21 @@ #define MBUS_BRIDGE_WIN_CTRL_REG (MVEBU_REGISTER(0x20250)) #define MBUS_BRIDGE_WIN_BASE_REG (MVEBU_REGISTER(0x20254)) +#define MVEBU_SOC_DEV_MUX_REG (MVEBU_SYSTEM_REG_BASE + 0x08) +#define NAND_EN BIT(0) +#define NAND_ARBITER_EN BIT(27) + +#define ARMADA_XP_PUP_ENABLE (MVEBU_SYSTEM_REG_BASE + 0x44c) +#define GE0_PUP_EN BIT(0) +#define GE1_PUP_EN BIT(1) +#define LCD_PUP_EN BIT(2) +#define NAND_PUP_EN BIT(4) +#define SPI_PUP_EN BIT(5) + +#define MVEBU_CORE_DIV_CLK_CTRL(i) (MVEBU_CLOCK_BASE + ((i) * 0x8)) +#define NAND_ECC_DIVCKL_RATIO_OFFS 8 +#define NAND_ECC_DIVCKL_RATIO_MASK (0x3F << NAND_ECC_DIVCKL_RATIO_OFFS) + #define SDRAM_MAX_CS 4 #define SDRAM_ADDR_MASK 0xFF000000 diff --git a/arch/arm/mach-mvebu/mbus.c b/arch/arm/mach-mvebu/mbus.c index 71fa693..771cce6 100644 --- a/arch/arm/mach-mvebu/mbus.c +++ b/arch/arm/mach-mvebu/mbus.c @@ -55,8 +55,6 @@ #include <linux/compat.h> #include <linux/mbus.h> -#define BIT(nr) (1UL << (nr)) - /* DDR target is the same on all platforms */ #define TARGET_DDR 0 diff --git a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c index e661fa1..0eb17f6 100644 --- a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c +++ b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c @@ -15,8 +15,6 @@ DECLARE_GLOBAL_DATA_PTR; -#define BIT(nr) (1UL << (nr)) - #define ETH_PHY_CTRL_REG 0 #define ETH_PHY_CTRL_POWER_DOWN_BIT 11 #define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT) diff --git a/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c b/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c index 00ca878..78c7b7e 100644 --- a/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c +++ b/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c @@ -12,8 +12,6 @@ DECLARE_GLOBAL_DATA_PTR; -#define BIT(nr) (1UL << (nr)) - #define ETH_PHY_CTRL_REG 0 #define ETH_PHY_CTRL_POWER_DOWN_BIT 11 #define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT) diff --git a/drivers/net/mvneta.c b/drivers/net/mvneta.c index efaae16..38ad14e 100644 --- a/drivers/net/mvneta.c +++ b/drivers/net/mvneta.c @@ -41,7 +41,6 @@ printf(fmt, ##args) #define CONFIG_NR_CPUS 1 -#define BIT(nr) (1UL << (nr)) #define ETH_HLEN 14 /* Total octets in header */ /* 2(HW hdr) 14(MAC hdr) 4(CRC) 32(extra for cache prefetch) */ -- 2.4.6

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[U-Boot] [PATCH 05/10 v2] arm: mvebu: Disable MBUS error propagation
by Stefan Roese 23 Jul '15

23 Jul '15

Accessing MBUS windows not backed-up by e.g. PCIe devices will hang the SoC. Disable MBUS error propagation back to CPU allows to read 0xffffffff instead of hanging the SoC. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Luka Perkov <luka.perkov(a)sartura.hr> --- v2: - Use clrsetbits_le32() arch/arm/mach-mvebu/cpu.c | 3 +++ arch/arm/mach-mvebu/include/mach/soc.h | 3 +++ 2 files changed, 6 insertions(+) diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index 23c2a97..fa82067 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -241,6 +241,9 @@ int arch_cpu_init(void) */ mvebu_mbus_probe(windows, ARRAY_SIZE(windows)); + /* Disable MBUS error propagation */ + clrsetbits_le32(SOC_COHERENCY_FABRIC_CTRL_REG, MBUS_ERR_PROP_EN, 0); + return 0; } #endif /* CONFIG_ARCH_CPU_INIT */ diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index 71254c5..a29e5dc 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -66,6 +66,9 @@ #define MVEBU_SATA0_BASE (MVEBU_REGISTER(0xa8000)) #define MVEBU_SDIO_BASE (MVEBU_REGISTER(0xd8000)) +#define SOC_COHERENCY_FABRIC_CTRL_REG (MVEBU_REGISTER(0x20200)) +#define MBUS_ERR_PROP_EN (1 << 8) + #define MBUS_BRIDGE_WIN_CTRL_REG (MVEBU_REGISTER(0x20250)) #define MBUS_BRIDGE_WIN_BASE_REG (MVEBU_REGISTER(0x20254)) -- 2.4.6

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[U-Boot] [PATCH V3] sf: Add support for flag status register on Micron chips
by Zhiqiang Hou 23 Jul '15

23 Jul '15

From: Hou Zhiqiang <B48286(a)freescale.com> Enter 3 Byte address mode at first, because it may change to 4 Byte address mode in kernel driver and not reset to 3 Byte address mode after reboot. Add clear flag status register operation that some Micron SPI flash chips required after reading the flag status register to check some operations completion. Signed-off-by: Hou Zhiqiang <B48286(a)freescale.com> Signed-off-by: Mingkai.Hu <Mingkai.Hu(a)freescale.com> --- V3: Generate the patch based on the latest tree git://git.denx.de/u-boot.git. V2: Add the operation of enter 3 Byte address mode in probe. V1: Based on git://git.denx.de/u-boot.git. Also can be applied to git://www.denx.de/git/u-boot-mpc85xx.git. Tested on board T2080QDS and T2080RDB. drivers/mtd/spi/sf_internal.h | 17 ++++++++++++ drivers/mtd/spi/sf_ops.c | 64 +++++++++++++++++++++++++++++++++++++------ drivers/mtd/spi/sf_probe.c | 5 ++++ 3 files changed, 78 insertions(+), 8 deletions(-) diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index 4158e13..24a693e 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -73,6 +73,11 @@ enum { #define CMD_WRITE_ENABLE 0x06 #define CMD_READ_CONFIG 0x35 #define CMD_FLAG_STATUS 0x70 +#define CMD_CLEAR_FLAG_STATUS 0x50 + +/* Used for Macronix and Winbond flashes */ +#define CMD_ENTER_4B_ADDR 0xB7 +#define CMD_EXIT_4B_ADDR 0xE9 /* Read commands */ #define CMD_READ_ARRAY_SLOW 0x03 @@ -96,6 +101,8 @@ enum { #define STATUS_QEB_WINSPAN (1 << 1) #define STATUS_QEB_MXIC (1 << 6) #define STATUS_PEC (1 << 7) +#define STATUS_PROT (1 << 1) +#define STATUS_ERASE (1 << 5) /* Flash timeout values */ #define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ) @@ -182,6 +189,12 @@ static inline int spi_flash_cmd_write_disable(struct spi_flash *flash) return spi_flash_cmd(flash->spi, CMD_WRITE_DISABLE, NULL, 0); } +/* Clear flag status register */ +static inline int spi_flash_cmd_clear_flag_status(struct spi_slave *spi) +{ + return spi_flash_cmd(spi, CMD_CLEAR_FLAG_STATUS, NULL, 0); +} + /* * Send the read status command to the device and wait for the wip * (write-in-progress) bit to clear itself. @@ -218,4 +231,8 @@ int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, size_t len, void *data); +#if defined(CONFIG_SPI_FLASH_STMICRO) +int spi_flash_cmd_4B_addr_switch(struct spi_flash *flash, int enable); +#endif + #endif /* _SF_INTERNAL_H_ */ diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c index 38592f5..1ce14d1 100644 --- a/drivers/mtd/spi/sf_ops.c +++ b/drivers/mtd/spi/sf_ops.c @@ -93,6 +93,30 @@ int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc) } #endif +#if defined(CONFIG_SPI_FLASH_STMICRO) +int spi_flash_cmd_4B_addr_switch(struct spi_flash *flash, int enable) +{ + int ret; + u8 cmd; + + cmd = enable ? CMD_ENTER_4B_ADDR : CMD_EXIT_4B_ADDR; + + ret = spi_claim_bus(flash->spi); + if (ret) { + debug("SF: unable to claim SPI bus\n"); + return ret; + } + + ret = spi_flash_cmd_write_enable(flash); + if (ret < 0) { + debug("SF: enabling write failed\n"); + return ret; + } + + return spi_flash_cmd(flash->spi, cmd, NULL, 0); +} +#endif + #ifdef CONFIG_SPI_FLASH_BAR static int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel) { @@ -160,6 +184,7 @@ static int spi_flash_poll_status(struct spi_slave *spi, unsigned long timeout, unsigned long timebase; unsigned long flags = SPI_XFER_BEGIN; int ret; + int out_of_time = 1; u8 status; u8 check_status = 0x0; @@ -182,22 +207,45 @@ static int spi_flash_poll_status(struct spi_slave *spi, unsigned long timeout, WATCHDOG_RESET(); ret = spi_xfer(spi, 8, NULL, &status, 0); - if (ret) + if (ret) { + spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END); return -1; + } - if ((status & poll_bit) == check_status) + if ((status & poll_bit) == check_status) { + out_of_time = 0; break; + } } while (get_timer(timebase) < timeout); spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END); - if ((status & poll_bit) == check_status) - return 0; + if (out_of_time) { + /* Timed out */ + debug("SF: time out!\n"); + if (cmd == CMD_FLAG_STATUS) { + if (spi_flash_cmd_clear_flag_status(spi) < 0) + debug("SF: clear flag status failed\n"); + } + ret = -1; + } +#ifdef CONFIG_SPI_FLASH_STMICRO + else if (cmd == CMD_FLAG_STATUS) { + if (!(status & (STATUS_PROT | STATUS_ERASE))) { + ret = 0; + } else { + debug("SF: flag status error"); + ret = -1; + } - /* Timed out */ - debug("SF: time out!\n"); - return -1; + if (spi_flash_cmd_clear_flag_status(spi) < 0) { + debug("SF: clear flag status failed\n"); + ret = -1; + } + } +#endif + return ret; } int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout) @@ -252,7 +300,7 @@ int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd, ret = spi_flash_cmd_wait_ready(flash, timeout); if (ret < 0) { - debug("SF: write %s timed out\n", + debug("SF: write %s failed\n", timeout == SPI_FLASH_PROG_TIMEOUT ? "program" : "page erase"); return ret; diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c index 201471c..abe148f 100644 --- a/drivers/mtd/spi/sf_probe.c +++ b/drivers/mtd/spi/sf_probe.c @@ -231,6 +231,11 @@ static int spi_flash_validate_params(struct spi_slave *spi, u8 *idcode, #ifdef CONFIG_SPI_FLASH_STMICRO if (params->flags & E_FSR) flash->poll_cmd = CMD_FLAG_STATUS; + + if (flash->size > SPI_FLASH_16MB_BOUN) { + if (spi_flash_cmd_4B_addr_switch(flash, 0) < 0) + debug("SF: enter 3B address mode failed\n"); + } #endif /* Configure the BAR - discover bank cmds and read current bank */ -- 2.1.0.27.g96db324

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