July 2015 - U-Boot

[U-Boot] [PATCH] T104xD4: Add Secure boot support for T104xD4RDB platforms.
by Gaurav Rana 31 Jul '15

31 Jul '15

defconfig files are added and SFP version for these platforms is updated. Signed-off-by: Gaurav Rana <gaurav.rana(a)freescale.com> --- arch/powerpc/include/asm/config_mpc85xx.h | 1 + arch/powerpc/include/asm/fsl_secure_boot.h | 2 ++ board/freescale/t104xrdb/MAINTAINERS | 2 ++ configs/T1040D4RDB_SECURE_BOOT_defconfig | 4 ++++ configs/T1042D4RDB_SECURE_BOOT_defconfig | 4 ++++ 5 files changed, 13 insertions(+) create mode 100644 configs/T1040D4RDB_SECURE_BOOT_defconfig create mode 100644 configs/T1042D4RDB_SECURE_BOOT_defconfig diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 69e0592..f971ffc 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -798,6 +798,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 +#define CONFIG_SYS_FSL_SFP_VER_3_0 #elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) ||\ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 49f6814..aa06f2e 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -37,7 +37,9 @@ defined(CONFIG_T2080QDS) || \ defined(CONFIG_T2080RDB) || \ defined(CONFIG_T1040QDS) || \ + defined(CONFIG_T104xD4QDS) || \ defined(CONFIG_T104xRDB) || \ + defined(CONFIG_T104xD4RDB) || \ defined(CONFIG_PPC_T1023) || \ defined(CONFIG_PPC_T1024) #define CONFIG_SYS_CPC_REINIT_F diff --git a/board/freescale/t104xrdb/MAINTAINERS b/board/freescale/t104xrdb/MAINTAINERS index 13d9be9..6dd3c5e 100644 --- a/board/freescale/t104xrdb/MAINTAINERS +++ b/board/freescale/t104xrdb/MAINTAINERS @@ -21,4 +21,6 @@ T1040RDB_SECURE_BOOT BOARD M: Aneesh Bansal <aneesh.bansal(a)freescale.com> S: Maintained F: configs/T1040RDB_SECURE_BOOT_defconfig +F: configs/T1040D4RDB_SECURE_BOOT_defconfig F: configs/T1042RDB_SECURE_BOOT_defconfig +F: configs/T1042D4RDB_SECURE_BOOT_defconfig diff --git a/configs/T1040D4RDB_SECURE_BOOT_defconfig b/configs/T1040D4RDB_SECURE_BOOT_defconfig new file mode 100644 index 0000000..d2aca80 --- /dev/null +++ b/configs/T1040D4RDB_SECURE_BOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,T104XD4RDB,SYS_FSL_DDR4,SECURE_BOOT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T104XRDB=y diff --git a/configs/T1042D4RDB_SECURE_BOOT_defconfig b/configs/T1042D4RDB_SECURE_BOOT_defconfig new file mode 100644 index 0000000..737bc70 --- /dev/null +++ b/configs/T1042D4RDB_SECURE_BOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,T104XD4RDB,SYS_FSL_DDR4,SECURE_BOOT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T104XRDB=y -- 1.8.1.4

3 2

[U-Boot] [PATCH][v7] mpc85xx/T104xD4RDB: Add T104xD4RDB boards support
by Priyanka Jain 31 Jul '15

31 Jul '15

T1040D4RDB is a Freescale reference board that hosts the T1040 SoC. T1040D4RDB is re-designed T1040RDB board with following changes : - Support of DDR4 memory - Support of 0x66 serdes protocol which can support following interfaces - 2 RGMII's on DTSEC4, DTSEC5 - 1 SGMII on DTSEC3 - Support of QE-TDM Similarily T1042D4RDB is a Freescale reference board that hosts the T1040 SoC. T1042D4RDB is re-designed T1042RDB board with following changes : - Support of DDR4 memory - Support for 0x86 serdes protocol which can support following interfaces - 2 RGMII's on DTSEC4, DTSEC5 - 3 SGMII on DTSEC1, DTSEC2 & DTSEC3 - Support of DIU Signed-off-by: Priyanka Jain <Priyanka.Jain(a)freescale.com> Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu(a)freescale.com> Signed-off-by: Wang Dongsheng <dongsheng.wang(a)freescale.com> --- changes from v2: - adds SGMII suport using CPLD - removes extra endif changes from v3: - removes checkpatch error changes from v4: - wrong use of defined MACRO in eth.c file, adds macro properly changes from v5: - updates README files, t1040d4_rcw.cfg and t1042d4_rcw.cfg - update DDR settings changes from v6: - update DDR settings, config files, cpld code, README - Add QGMII phy addr configs, update DIU_SEL value board/freescale/t104xrdb/MAINTAINERS | 8 +++ board/freescale/t104xrdb/README | 87 ++++++++++++++++++++++++++++- board/freescale/t104xrdb/cpld.c | 4 ++ board/freescale/t104xrdb/cpld.h | 6 ++ board/freescale/t104xrdb/ddr.c | 10 ++++ board/freescale/t104xrdb/ddr.h | 9 +++- board/freescale/t104xrdb/eth.c | 20 ++++++- board/freescale/t104xrdb/t1040d4_rcw.cfg | 7 +++ board/freescale/t104xrdb/t1042d4_rcw.cfg | 7 +++ board/freescale/t104xrdb/t104xrdb.c | 32 +++++++++++ configs/T1040D4RDB_NAND_defconfig | 5 ++ configs/T1040D4RDB_SDCARD_defconfig | 5 ++ configs/T1040D4RDB_SPIFLASH_defconfig | 5 ++ configs/T1040D4RDB_defconfig | 4 ++ configs/T1042D4RDB_NAND_defconfig | 5 ++ configs/T1042D4RDB_SDCARD_defconfig | 5 ++ configs/T1042D4RDB_SPIFLASH_defconfig | 5 ++ configs/T1042D4RDB_defconfig | 4 ++ include/configs/T104xRDB.h | 64 ++++++++++++++++++---- 19 files changed, 276 insertions(+), 16 deletions(-) create mode 100644 board/freescale/t104xrdb/t1040d4_rcw.cfg create mode 100644 board/freescale/t104xrdb/t1042d4_rcw.cfg create mode 100644 configs/T1040D4RDB_NAND_defconfig create mode 100644 configs/T1040D4RDB_SDCARD_defconfig create mode 100644 configs/T1040D4RDB_SPIFLASH_defconfig create mode 100644 configs/T1040D4RDB_defconfig create mode 100644 configs/T1042D4RDB_NAND_defconfig create mode 100644 configs/T1042D4RDB_SDCARD_defconfig create mode 100644 configs/T1042D4RDB_SPIFLASH_defconfig create mode 100644 configs/T1042D4RDB_defconfig diff --git a/board/freescale/t104xrdb/MAINTAINERS b/board/freescale/t104xrdb/MAINTAINERS index 13d9be9..32e044f 100644 --- a/board/freescale/t104xrdb/MAINTAINERS +++ b/board/freescale/t104xrdb/MAINTAINERS @@ -6,7 +6,13 @@ F: include/configs/T104xRDB.h F: configs/T1040RDB_defconfig F: configs/T1040RDB_NAND_defconfig F: configs/T1040RDB_SPIFLASH_defconfig +F: configs/T1040D4RDB_defconfig +F: configs/T1040D4RDB_NAND_defconfig +F: configs/T1040D4RDB_SPIFLASH_defconfig F: configs/T1042RDB_defconfig +F: configs/T1042D4RDB_defconfig +F: configs/T1042D4RDB_NAND_defconfig +F: configs/T1042D4RDB_SPIFLASH_defconfig F: configs/T1042RDB_PI_defconfig F: configs/T1042RDB_PI_NAND_defconfig F: configs/T1042RDB_PI_SPIFLASH_defconfig @@ -15,6 +21,8 @@ T1040RDB_SDCARD BOARD #M: - S: Maintained F: configs/T1040RDB_SDCARD_defconfig +F: configs/T1040D4RDB_SDCARD_defconfig +F: configs/T1042D4RDB_SDCARD_defconfig F: configs/T1042RDB_PI_SDCARD_defconfig T1040RDB_SECURE_BOOT BOARD diff --git a/board/freescale/t104xrdb/README b/board/freescale/t104xrdb/README index ac95b5e..b9d2212 100644 --- a/board/freescale/t104xrdb/README +++ b/board/freescale/t104xrdb/README @@ -12,6 +12,17 @@ The T1042RDB_PI is a Freescale reference board that hosts the T1042 SoC. (a personality of T1040 SoC). The board is similar to T1040RDB but is designed specially with low power features targeted for Printing Image Market. +The T1040D4RDB is a Freescale reference board that hosts the T1040 SoC. +The board is re-designed T1040RDB board with following changes : + - Support of DDR4 memory and some enhancements + +The T1042D4RDB is a Freescale reference board that hosts the T1042 SoC. +The board is re-designed T1040RDB board with following changes : + - Support of DDR4 memory + - Support for 0x86 serdes protocol which can support following interfaces + - 2 RGMII's on DTSEC4, DTSEC5 + - 3 SGMII on DTSEC1, DTSEC2 & DTSEC3 + Basic difference's among T1040RDB, T1042RDB_PI, T1042RDB ------------------------------------------------------------------------- Board Si Protocol Targeted Market @@ -19,6 +30,8 @@ Board Si Protocol Targeted Market T1040RDB T1040 0x66 Networking T1040RDB T1042 0x86 Networking T1042RDB_PI T1042 0x06 Printing & Imaging +T1040D4RDB T1040 0x66 Networking +T1042D4RDB T1042 0x86 Networking T1040 SoC Overview @@ -70,7 +83,6 @@ The T1040/T1042 SoC includes the following function and features: T1040 SoC Personalities ------------------------- - T1022 Personality: T1022 is a reduced personality of T1040 with less core/clusters. @@ -268,8 +280,13 @@ SPI Flash memory Map on T104xRDB Please note QE Firmware is only valid for T1040RDB -Switch Settings: (ON is 0, OFF is 1) -=============== +Switch Settings for T104xRDB boards: (ON is 0, OFF is 1) +========================================================== +NOR boot SW setting: +SW1: 00010011 +SW2: 10111011 +SW3: 11100001 + NAND boot SW setting: SW1: 10001000 SW2: 00111011 @@ -284,3 +301,67 @@ SD boot SW setting: SW1: 00100000 SW2: 00111011 SW3: 11100001 + +Switch Settings for T104xD4RDB boards: (ON is 0, OFF is 1) +============================================================= +NOR boot SW setting: +SW1: 00010011 +SW2: 10111001 +SW3: 11100001 + +NAND boot SW setting: +SW1: 10001000 +SW2: 00111001 +SW3: 11110001 + +SPI boot SW setting: +SW1: 00100010 +SW2: 10111001 +SW3: 11100001 + +SD boot SW setting: +SW1: 00100000 +SW2: 00111001 +SW3: 11100001 + +PBL-based image generation +========================== +Changes only the required register bit in in PBI commands. + +Provides reference code which might needs some +modification as per requirement. +example: +By default PBI_SRC=14 (which is for IFC-NAND/NOR) in rcw.cfg file +which needs to be changed for SPI and SD. + +For SD-boot +============== +1. Set RCW[192:195], PBI_SRC bits as 6 in RCW file (t1040d4_rcw.cfg type files) + +example: + RCW file: board/freescale/t104xrdb/t1040d4_rcw.cfg + +Change +66000002 40000002 ec027000 01000000 +to +66000002 40000002 6c027000 01000000 + +2. SD does not support flush so remove flush from pbl, make changes in + tools/pblimage.c file, Update value of pbl_end_cmd[0] = 0x09138000 + with 0x091380c0 + +For SPI-boot +============== +1. Set RCW[192:195], PBI_SRC bits as 5 in RCW file (t1040d4_rcw.cfg type files) + +example: + RCW file: board/freescale/t104xrdb/t1040d4_rcw.cfg + +Change +66000002 40000002 ec027000 01000000 +to +66000002 40000002 5c027000 01000000 + +2. SPI does not support flush so remove flush from pbl, make changes in + tools/pblimage.c file, Update value of pbl_end_cmd[0] = 0x09138000 + with 0x091380c0 diff --git a/board/freescale/t104xrdb/cpld.c b/board/freescale/t104xrdb/cpld.c index df0e348..0ce4e47 100644 --- a/board/freescale/t104xrdb/cpld.c +++ b/board/freescale/t104xrdb/cpld.c @@ -69,7 +69,11 @@ static void cpld_dump_regs(void) printf("int_status = 0x%02x\n", CPLD_READ(int_status)); printf("flash_ctl_status = 0x%02x\n", CPLD_READ(flash_ctl_status)); printf("fan_ctl_status = 0x%02x\n", CPLD_READ(fan_ctl_status)); +#if defined(CONFIG_T104XD4RDB) + printf("int_mask = 0x%02x\n", CPLD_READ(int_mask)); +#else printf("led_ctl_status = 0x%02x\n", CPLD_READ(led_ctl_status)); +#endif printf("sfp_ctl_status = 0x%02x\n", CPLD_READ(sfp_ctl_status)); printf("misc_ctl_status = 0x%02x\n", CPLD_READ(misc_ctl_status)); printf("boot_override = 0x%02x\n", CPLD_READ(boot_override)); diff --git a/board/freescale/t104xrdb/cpld.h b/board/freescale/t104xrdb/cpld.h index 0da9a01..2fb4105 100644 --- a/board/freescale/t104xrdb/cpld.h +++ b/board/freescale/t104xrdb/cpld.h @@ -21,7 +21,11 @@ struct cpld_data { u8 int_status; /* 0x12 - Interrupt status Register */ u8 flash_ctl_status; /* 0x13 - Flash control and status register */ u8 fan_ctl_status; /* 0x14 - Fan control and status register */ +#if defined(CONFIG_T104XD4RDB) + u8 int_mask; /* 0x15 - Interrupt mask Register */ +#else u8 led_ctl_status; /* 0x15 - LED control and status register */ +#endif u8 sfp_ctl_status; /* 0x16 - SFP control and status register */ u8 misc_ctl_status; /* 0x17 - Miscellanies ctrl & status register*/ u8 boot_override; /* 0x18 - Boot override register */ @@ -38,3 +42,5 @@ void cpld_write(unsigned int reg, u8 value); #define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) #define CPLD_WRITE(reg, value)\ cpld_write(offsetof(struct cpld_data, reg), value) +#define MISC_CTL_SG_SEL 0x80 +#define MISC_CTL_AURORA_SEL 0x02 diff --git a/board/freescale/t104xrdb/ddr.c b/board/freescale/t104xrdb/ddr.c index e1148e5..cf79d2d 100644 --- a/board/freescale/t104xrdb/ddr.c +++ b/board/freescale/t104xrdb/ddr.c @@ -75,7 +75,11 @@ found: * Factors to consider for half-strength driver enable: * - number of DIMMs installed */ +#ifdef CONFIG_SYS_FSL_DDR4 + popts->half_strength_driver_enable = 1; +#else popts->half_strength_driver_enable = 0; +#endif /* * Write leveling override */ @@ -91,8 +95,14 @@ found: popts->zq_en = 1; /* DHC_EN =1, ODT = 75 Ohm */ +#ifdef CONFIG_SYS_FSL_DDR4 + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_120OHM); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_120OHM) | + DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ +#else popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); +#endif } #if defined(CONFIG_DEEP_SLEEP) diff --git a/board/freescale/t104xrdb/ddr.h b/board/freescale/t104xrdb/ddr.h index ab1c32d..b9c02f7 100644 --- a/board/freescale/t104xrdb/ddr.h +++ b/board/freescale/t104xrdb/ddr.h @@ -28,6 +28,9 @@ static const struct board_specific_parameters udimm0[] = { * num| hi| rank| clk| wrlvl | wrlvl * ranks| mhz| GB |adjst| start | ctl2 */ +#ifdef CONFIG_SYS_FSL_DDR4 + {2, 1600, 4, 4, 6, 0x07090A0c, 0x0e0f100a}, +#elif defined(CONFIG_SYS_FSL_DDR3) {2, 833, 4, 4, 6, 0x06060607, 0x08080807}, {2, 833, 0, 4, 6, 0x06060607, 0x08080807}, {2, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09}, @@ -40,10 +43,14 @@ static const struct board_specific_parameters udimm0[] = { {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09}, {1, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A}, {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A}, +#else +#error DDR type not defined +#endif {} }; +#endif + static const struct board_specific_parameters *udimms[] = { udimm0, }; -#endif diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c index 7581a4cd..71d0457 100644 --- a/board/freescale/t104xrdb/eth.c +++ b/board/freescale/t104xrdb/eth.c @@ -43,9 +43,11 @@ int board_eth_init(bd_t *bis) int idx = i - FM1_DTSEC1; switch (fm_info_get_enet_if(i)) { -#ifdef CONFIG_T1040RDB +#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1040D4RDB) case PHY_INTERFACE_MODE_SGMII: - /* T1040RDB only supports SGMII on DTSEC3 */ + /* T1040RDB & T1040D4RDB only supports SGMII on + * DTSEC3 + */ fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_SGMII1_PHY_ADDR); break; @@ -60,6 +62,20 @@ int board_eth_init(bd_t *bis) CONFIG_SYS_SGMII1_PHY_ADDR); break; #endif +#ifdef CONFIG_T1042D4RDB + case PHY_INTERFACE_MODE_SGMII: + /* T1042D4RDB supports SGMII on DTSEC1, DTSEC2 + * & DTSEC3 + */ + if (FM1_DTSEC1 == i) + phy_addr = CONFIG_SYS_SGMII1_PHY_ADDR; + if (FM1_DTSEC2 == i) + phy_addr = CONFIG_SYS_SGMII2_PHY_ADDR; + if (FM1_DTSEC3 == i) + phy_addr = CONFIG_SYS_SGMII3_PHY_ADDR; + fm_info_set_phy_address(i, phy_addr); + break; +#endif case PHY_INTERFACE_MODE_RGMII: if (FM1_DTSEC4 == i) phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR; diff --git a/board/freescale/t104xrdb/t1040d4_rcw.cfg b/board/freescale/t104xrdb/t1040d4_rcw.cfg new file mode 100644 index 0000000..c1034b3 --- /dev/null +++ b/board/freescale/t104xrdb/t1040d4_rcw.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 +# serdes protocol 0x66 +0c18000e 0e000000 00000000 00000000 +66000002 40000002 ec027000 01000000 +00000000 00000000 00000000 00030810 +00000000 0342580f 00000000 00000000 diff --git a/board/freescale/t104xrdb/t1042d4_rcw.cfg b/board/freescale/t104xrdb/t1042d4_rcw.cfg new file mode 100644 index 0000000..9e0ee27 --- /dev/null +++ b/board/freescale/t104xrdb/t1042d4_rcw.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 +# serdes protocol 0x86 +0c18000e 0e000000 00000000 00000000 +86000002 40000002 ec027000 01000000 +00000000 00000000 00000000 00030810 +00000000 0342500f 00000000 00000000 diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c index c34eea6..d982dfc 100644 --- a/board/freescale/t104xrdb/t104xrdb.c +++ b/board/freescale/t104xrdb/t104xrdb.c @@ -28,7 +28,11 @@ int checkboard(void) struct cpu_type *cpu = gd->arch.cpu; u8 sw; +#ifdef CONFIG_T104XD4RDB + printf("Board: %sD4RDB\n", cpu->name); +#else printf("Board: %sRDB\n", cpu->name); +#endif printf("Board rev: 0x%02x CPLD ver: 0x%02x, ", CPLD_READ(hw_ver), CPLD_READ(sw_ver)); @@ -88,6 +92,34 @@ int board_early_init_r(void) int misc_init_r(void) { + ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 srds_s1; + + srds_s1 = in_be32(&gur->rcwsr[4]) >> 24; + + printf("SERDES Reference : 0x%X\n", srds_s1); + + /* select SGMII*/ + if (srds_s1 == 0x86) + CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) | + MISC_CTL_SG_SEL); + + /* select SGMII and Aurora*/ + if (srds_s1 == 0x8E) + CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) | + MISC_CTL_SG_SEL | MISC_CTL_AURORA_SEL); + +#if defined(CONFIG_T1040D4RDB) + /* Mask all CPLD interrupt sources, except QSGMII interrupts */ + if (CPLD_READ(sw_ver) < 0x03) { + debug("CPLD SW version 0x%02x doesn't support int_mask\n", + CPLD_READ(sw_ver)); + } else { + CPLD_WRITE(int_mask, CPLD_INT_MASK_ALL & + ~(CPLD_INT_MASK_QSGMII1 | CPLD_INT_MASK_QSGMII2)); + } +#endif + return 0; } diff --git a/configs/T1040D4RDB_NAND_defconfig b/configs/T1040D4RDB_NAND_defconfig new file mode 100644 index 0000000..c82fde2 --- /dev/null +++ b/configs/T1040D4RDB_NAND_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND,T104XD4RDB,SYS_FSL_DDR4" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T104XRDB=y diff --git a/configs/T1040D4RDB_SDCARD_defconfig b/configs/T1040D4RDB_SDCARD_defconfig new file mode 100644 index 0000000..459b98d --- /dev/null +++ b/configs/T1040D4RDB_SDCARD_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD,T104XD4RDB,SYS_FSL_DDR4" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T104XRDB=y diff --git a/configs/T1040D4RDB_SPIFLASH_defconfig b/configs/T1040D4RDB_SPIFLASH_defconfig new file mode 100644 index 0000000..e2654b8 --- /dev/null +++ b/configs/T1040D4RDB_SPIFLASH_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH,T104XD4RDB,SYS_FSL_DDR4" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T104XRDB=y diff --git a/configs/T1040D4RDB_defconfig b/configs/T1040D4RDB_defconfig new file mode 100644 index 0000000..f9a23cf --- /dev/null +++ b/configs/T1040D4RDB_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,T104XD4RDB,SYS_FSL_DDR4" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T104XRDB=y diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig new file mode 100644 index 0000000..146f4ad --- /dev/null +++ b/configs/T1042D4RDB_NAND_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND,T104XD4RDB,SYS_FSL_DDR4" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T104XRDB=y diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig new file mode 100644 index 0000000..2273637 --- /dev/null +++ b/configs/T1042D4RDB_SDCARD_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD,T104XD4RDB,SYS_FSL_DDR4" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T104XRDB=y diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig new file mode 100644 index 0000000..2edf310 --- /dev/null +++ b/configs/T1042D4RDB_SPIFLASH_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH,T104XD4RDB,SYS_FSL_DDR4" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T104XRDB=y diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig new file mode 100644 index 0000000..3802637 --- /dev/null +++ b/configs/T1042D4RDB_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,T104XD4RDB,SYS_FSL_DDR4" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T104XRDB=y diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 6cc95ef..e856c17 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -29,6 +29,14 @@ #ifdef CONFIG_T1042RDB #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_rcw.cfg #endif +#ifdef CONFIG_T1040D4RDB +#define CONFIG_SYS_FSL_PBL_RCW \ +$(SRCTREE)/board/freescale/t104xrdb/t1040d4_rcw.cfg +#endif +#ifdef CONFIG_T1042D4RDB +#define CONFIG_SYS_FSL_PBL_RCW \ +$(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg +#endif #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT #define CONFIG_SPL_ENV_SUPPORT @@ -220,7 +228,9 @@ #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) #define CONFIG_DDR_SPD +#ifndef CONFIG_SYS_FSL_DDR4 #define CONFIG_SYS_FSL_DDR3 +#endif #define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x51 @@ -278,8 +288,23 @@ #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */ #define CPLD_LBMAP_RESET 0xFF #define CPLD_LBMAP_SHIFT 0x03 -#ifdef CONFIG_T1042RDB_PI + +#if defined(CONFIG_T1042RDB_PI) #define CPLD_DIU_SEL_DFP 0x80 +#elif defined(CONFIG_T1042D4RDB) +#define CPLD_DIU_SEL_DFP 0xc0 +#endif + +#if defined(CONFIG_T1040D4RDB) +#define CPLD_INT_MASK_ALL 0xFF +#define CPLD_INT_MASK_THERM 0x80 +#define CPLD_INT_MASK_DVI_DFP 0x40 +#define CPLD_INT_MASK_QSGMII1 0x20 +#define CPLD_INT_MASK_QSGMII2 0x10 +#define CPLD_INT_MASK_SGMI1 0x08 +#define CPLD_INT_MASK_SGMI2 0x04 +#define CPLD_INT_MASK_TDMR1 0x02 +#define CPLD_INT_MASK_TDMR2 0x01 #endif #define CONFIG_SYS_CPLD_BASE 0xffdf0000 @@ -447,7 +472,7 @@ #define CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#ifdef CONFIG_T1042RDB_PI +#if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T1042D4RDB) /* Video */ #define CONFIG_FSL_DIU_FB @@ -492,11 +517,11 @@ /* I2C bus multiplexer */ #define I2C_MUX_PCA_ADDR 0x70 -#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB) +#if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB) #define I2C_MUX_CH_DEFAULT 0x8 #endif -#ifdef CONFIG_T1042RDB_PI +#if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T104XD4RDB) /* LDI/DVI Encoder for display */ #define CONFIG_SYS_I2C_LDI_ADDR 0x38 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 @@ -665,7 +690,7 @@ #define CONFIG_SYS_DPAA_FMAN #define CONFIG_SYS_DPAA_PME -#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB) +#if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB) #define CONFIG_QE #define CONFIG_U_QE #endif @@ -694,7 +719,7 @@ #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 #endif -#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB) +#if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB) #if defined(CONFIG_SPIFLASH) #define CONFIG_SYS_QE_FW_ADDR 0x130000 #elif defined(CONFIG_SDCARD) @@ -719,17 +744,32 @@ #ifdef CONFIG_FMAN_ENET #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB) -#define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 +#define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 +#elif defined(CONFIG_T1040D4RDB) || defined(CONFIG_T1042D4RDB) +#define CONFIG_SYS_SGMII1_PHY_ADDR 0x02 +#define CONFIG_SYS_SGMII2_PHY_ADDR 0x03 +#define CONFIG_SYS_SGMII3_PHY_ADDR 0x01 +#endif + +#ifdef CONFIG_T104XD4RDB +#define CONFIG_SYS_RGMII1_PHY_ADDR 0x04 +#define CONFIG_SYS_RGMII2_PHY_ADDR 0x05 +#else +#define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 +#define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 #endif -#define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 -#define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 /* Enable VSC9953 L2 Switch driver on T1040 SoC */ -#ifdef CONFIG_T1040RDB +#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1040D4RDB) #define CONFIG_VSC9953 #define CONFIG_VSC9953_CMD +#ifdef CONFIG_T1040RDB #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 +#else +#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08 +#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c +#endif #endif #define CONFIG_MII /* MII PHY management */ @@ -841,6 +881,10 @@ #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb" #elif defined(CONFIG_T1042RDB) #define FDTFILE "t1042rdb/t1042rdb.dtb" +#elif defined(CONFIG_T1040D4RDB) +#define FDTFILE "t1042rdb/t1040d4rdb.dtb" +#elif defined(CONFIG_T1042D4RDB) +#define FDTFILE "t1042rdb/t1042d4rdb.dtb" #endif #ifdef CONFIG_FSL_DIU_FB -- 1.7.4.1

3 5

[U-Boot] [PATCH 1/4][v8] powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041
by Aneesh Bansal 31 Jul '15

31 Jul '15

Secure Boot Target is added for NAND for P3041. Changes: In PowerPC, the core begins execution from address 0xFFFFFFFC. In case of secure boot, this default address maps to Boot ROM. The Boot ROM code requires that the bootloader(U-boot) must lie in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF. In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is configured as SRAM. U-Boot binary will be located on SRAM configured at address 0xBFF00000. In the U-Boot code, TLB entries are created to map the virtual address 0xFFF00000 to physical address 0xBFF00000 of CPC configured as SRAM. Signed-off-by: Aneesh Bansal <aneesh.bansal(a)freescale.com> --- Changes in v8: New Patchset Created Makefile | 4 ++++ arch/powerpc/cpu/mpc85xx/start.S | 11 +++++++++++ arch/powerpc/include/asm/fsl_secure_boot.h | 5 +++++ board/freescale/common/p_corenet/tlb.c | 15 +++++++++++++++ board/freescale/corenet_ds/MAINTAINERS | 5 +++++ configs/P3041DS_NAND_SECURE_BOOT_defconfig | 4 ++++ include/configs/corenet_ds.h | 8 ++++++++ 7 files changed, 52 insertions(+) create mode 100644 configs/P3041DS_NAND_SECURE_BOOT_defconfig diff --git a/Makefile b/Makefile index 394ed09..605003e 100644 --- a/Makefile +++ b/Makefile @@ -736,8 +736,12 @@ ALL-$(CONFIG_ONENAND_U_BOOT) += u-boot-onenand.bin ifeq ($(CONFIG_SPL_FSL_PBL),y) ALL-$(CONFIG_RAMBOOT_PBL) += u-boot-with-spl-pbl.bin else +ifneq ($(CONFIG_SECURE_BOOT), y) +# For Secure Boot The Image needs to be signed and Header must also +# be included. So The image has to be built explicitly ALL-$(CONFIG_RAMBOOT_PBL) += u-boot.pbl endif +endif ALL-$(CONFIG_SPL) += spl/u-boot-spl.bin ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot.img ALL-$(CONFIG_TPL) += tpl/u-boot-tpl.bin diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index e61d8e0..a70fb71 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -1052,6 +1052,17 @@ create_init_ram_area: CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \ CONFIG_SYS_PBI_FLASH_WINDOW & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \ 0, r6 + +#elif defined(CONFIG_RAMBOOT_PBL) && defined(CONFIG_SECURE_BOOT) + /* create a temp mapping in AS = 1 for mapping CONFIG_SYS_MONITOR_BASE + * to L3 Address configured by PBL for ISBC code + */ + create_tlb1_entry 15, \ + 1, BOOKE_PAGESZ_1M, \ + CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \ + CONFIG_SYS_INIT_L3_ADDR & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \ + 0, r6 + #else /* * create a temp mapping in AS=1 to the 1M CONFIG_SYS_MONITOR_BASE space, the main diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 8f794ef..cc33466 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -46,6 +46,11 @@ #define CONFIG_SYS_INIT_L3_ADDR 0xbff00000 #endif +#if defined(CONFIG_RAMBOOT_PBL) +#undef CONFIG_SYS_INIT_L3_ADDR +#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000 +#endif + #if defined(CONFIG_C29XPCIE) #define CONFIG_KEY_REVOCATION #endif diff --git a/board/freescale/common/p_corenet/tlb.c b/board/freescale/common/p_corenet/tlb.c index 8148e46..56e4f63 100644 --- a/board/freescale/common/p_corenet/tlb.c +++ b/board/freescale/common/p_corenet/tlb.c @@ -43,6 +43,8 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 1 */ /* *I*** - Covers boot page */ #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) + +#if !defined(CONFIG_SECURE_BOOT) /* * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the * SRAM is at 0xfff00000, it covered the 0xfffff000. @@ -50,6 +52,19 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_1M, 1), +#else + /* + * *I*G - L3SRAM. When L3 is used as 1M SRAM, in case of Secure Boot + * the physical address of the SRAM is at CONFIG_SYS_INIT_L3_ADDR, + * and virtual address is CONFIG_SYS_MONITOR_BASE + */ + + SET_TLB_ENTRY(1, CONFIG_SYS_MONITOR_BASE & 0xfff00000, + CONFIG_SYS_INIT_L3_ADDR & 0xfff00000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_1M, 1), +#endif + #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) /* * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the diff --git a/board/freescale/corenet_ds/MAINTAINERS b/board/freescale/corenet_ds/MAINTAINERS index 745847c..6855446 100644 --- a/board/freescale/corenet_ds/MAINTAINERS +++ b/board/freescale/corenet_ds/MAINTAINERS @@ -28,3 +28,8 @@ F: configs/P5040DS_NAND_defconfig F: configs/P5040DS_SDCARD_defconfig F: configs/P5040DS_SPIFLASH_defconfig F: configs/P5040DS_SECURE_BOOT_defconfig + +CORENET_DS_SECURE_BOOT BOARD +M: Aneesh Bansal <aneesh.bansal(a)freescale.com> +S: Maintained +F: configs/P3041DS_NAND_SECURE_BOOT_defconfig diff --git a/configs/P3041DS_NAND_SECURE_BOOT_defconfig b/configs/P3041DS_NAND_SECURE_BOOT_defconfig new file mode 100644 index 0000000..757f326 --- /dev/null +++ b/configs/P3041DS_NAND_SECURE_BOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P3041DS=y diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 88750e0..7c8b73d 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -16,6 +16,13 @@ #include "../board/freescale/common/ics307_clk.h" #ifdef CONFIG_RAMBOOT_PBL +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#ifdef CONFIG_NAND +#define CONFIG_RAMBOOT_NAND +#endif +#else #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg @@ -29,6 +36,7 @@ #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg #endif #endif +#endif #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE /* Set 1M boot space */ -- 1.8.1.4

2 2

[U-Boot] U-boot mini-summit @ ELCE 2015, Dublin, date ?
by Hans de Goede 31 Jul '15

31 Jul '15

Hi All, I'm preparing my trip to ELCE in Dublin, Oct 5th - 7th, and I was wondering if it is already known which day the u-boot mini-summit will be. My plan is to travel to Dublin Oct 4th, and back on Oct 8th, so my main question is, will the summit be during ELCE itself, or a day before / after ? Regards, Hans

2 3

[U-Boot] [PATCH] arm: mx6: tqma6: fix build for WRU-IV baseboard
by Stefano Babic 31 Jul '15

31 Jul '15

Fix: undefined reference to `spi_flash_free' undefined reference to `spi_flash_probe' Signed-off-by: Stefano Babic <sbabic(a)denx.de> CC: Stefan Roese <sr(a)denx.de> Cc: Markus Niebel <Markus.Niebel(a)tq-group.com> --- configs/tqma6s_wru4_mmc_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/tqma6s_wru4_mmc_defconfig b/configs/tqma6s_wru4_mmc_defconfig index f362760..66ac0b1 100644 --- a/configs/tqma6s_wru4_mmc_defconfig +++ b/configs/tqma6s_wru4_mmc_defconfig @@ -10,3 +10,4 @@ CONFIG_AUTOBOOT_PROMPT="Enter password in %d seconds to stop autoboot\n" CONFIG_AUTOBOOT_ENCRYPTION=y CONFIG_AUTOBOOT_STOP_STR_SHA256="36a9e7f1c95b82ffb99743e0c5c4ce95d83c9a430aac59f84ef3cbfab6145068" CONFIG_PCA9551_LED=y +CONFIG_SPI_FLASH=y -- 1.9.1

2 1

[U-Boot] Including both EHCI and xHCI does not compile
by Bin Meng 31 Jul '15

31 Jul '15

Hi Marek, With both CONFIG_USB_EHCI and CONFIG_USB_XHCI included, it does not build. drivers/usb/host/xhci.o: In function `submit_control_msg': /git/u-boot/drivers/usb/host/xhci.c:1030: multiple definition of `submit_control_msg' drivers/usb/host/ehci-hcd.o:/git/u-boot/drivers/usb/host/ehci-hcd.c:1552: first defined here drivers/usb/host/xhci.o: In function `submit_bulk_msg': /git/u-boot/drivers/usb/host/xhci.c:1043: multiple definition of `submit_bulk_msg' drivers/usb/host/ehci-hcd.o:/git/u-boot/drivers/usb/host/ehci-hcd.c:1546: first defined here drivers/usb/host/xhci.o: In function `submit_int_msg': /git/u-boot/drivers/usb/host/xhci.c:1051: multiple definition of `submit_int_msg' drivers/usb/host/ehci-hcd.o:/git/u-boot/drivers/usb/host/ehci-hcd.c:1558: first defined here drivers/usb/host/xhci.o: In function `usb_lowlevel_init': /git/u-boot/drivers/usb/host/xhci.c:1061: multiple definition of `usb_lowlevel_init' drivers/usb/host/ehci-hcd.o:/git/u-boot/drivers/usb/host/ehci-hcd.c:1132: first defined here drivers/usb/host/xhci.o: In function `usb_lowlevel_stop': /git/u-boot/drivers/usb/host/xhci.c:1093: multiple definition of `usb_lowlevel_stop' drivers/usb/host/ehci-hcd.o:/git/u-boot/drivers/usb/host/ehci-hcd.c:1126: first defined here Can we get this fixed? Thanks! Regards, Bin

2 2

[U-Boot] BayTrail FSP release v4
by Bin Meng 31 Jul '15

31 Jul '15

Hi Simon, Andrew, Just noticed that Intel has released the FSP for BayTrail version 4. The release notes is at here: http://www.intel.com/content/www/us/en/embedded/software/fsp/atom-e3800-fsp… Like Andrew contacted Intel and got the message, that Intel does not plan to release an FSP spec v2 complaint FSP for BayTrail, which looks like so. The v4 version is still FSP spec v1 :( But we should consider update MinnowMax instructions to use v4? Regards, Bin

2 3

[U-Boot] [PATCH] imx: usb: ehci-mx6: add usb support for imx7d soc
by Adrian Alonso 31 Jul '15

31 Jul '15

Extend ehci-mx6 usb driver to support imx7d usb Signed-off-by: Adrian Alonso <aalonso(a)freescale.com> --- drivers/usb/host/Makefile | 1 + drivers/usb/host/ehci-mx6.c | 125 ++++++++++++++++++++++++++++++++------------ 2 files changed, 92 insertions(+), 34 deletions(-) diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 6cc3bbd..8537b6b 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -36,6 +36,7 @@ obj-$(CONFIG_USB_EHCI_MXC) += ehci-mxc.o obj-$(CONFIG_USB_EHCI_MXS) += ehci-mxs.o obj-$(CONFIG_USB_EHCI_MX5) += ehci-mx5.o obj-$(CONFIG_USB_EHCI_MX6) += ehci-mx6.o +obj-$(CONFIG_USB_EHCI_MX7) += ehci-mx6.o obj-$(CONFIG_USB_EHCI_OMAP) += ehci-omap.o obj-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o obj-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c index 951dd3b..0ea19ec 100644 --- a/drivers/usb/host/ehci-mx6.c +++ b/drivers/usb/host/ehci-mx6.c @@ -45,7 +45,8 @@ #define ANADIG_USB2_PLL_480_CTRL_POWER 0x00001000 #define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS 0x00000040 - +#define USB_NC_OFFSET 0x200 +#define UCTRL_PM (1 << 9) /* OTG Power Mask */ #define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */ #define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */ @@ -53,6 +54,7 @@ #define UCMD_RUN_STOP (1 << 0) /* controller run/stop */ #define UCMD_RESET (1 << 1) /* controller reset */ +#if defined(CONFIG_MX6) static const unsigned phy_bases[] = { USB_PHY0_BASE_ADDR, USB_PHY1_BASE_ADDR, @@ -67,7 +69,7 @@ static void usb_internal_phy_clock_gate(int index, int on) phy_reg = (void __iomem *)phy_bases[index]; phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET; - __raw_writel(USBPHY_CTRL_CLKGATE, phy_reg); + writel(USBPHY_CTRL_CLKGATE, phy_reg); } static void usb_power_config(int index) @@ -100,14 +102,14 @@ static void usb_power_config(int index) * is totally controlled by IC, so the Software only needs * to enable them at initializtion. */ - __raw_writel(ANADIG_USB2_CHRG_DETECT_EN_B | + writel(ANADIG_USB2_CHRG_DETECT_EN_B | ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B, chrg_detect); - __raw_writel(ANADIG_USB2_PLL_480_CTRL_BYPASS, + writel(ANADIG_USB2_PLL_480_CTRL_BYPASS, pll_480_ctrl_clr); - __raw_writel(ANADIG_USB2_PLL_480_CTRL_ENABLE | + writel(ANADIG_USB2_PLL_480_CTRL_ENABLE | ANADIG_USB2_PLL_480_CTRL_POWER | ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS, pll_480_ctrl_set); @@ -119,7 +121,6 @@ static int usb_phy_enable(int index, struct usb_ehci *ehci) void __iomem *phy_reg; void __iomem *phy_ctrl; void __iomem *usb_cmd; - u32 val; if (index >= ARRAY_SIZE(phy_bases)) return 0; @@ -129,36 +130,27 @@ static int usb_phy_enable(int index, struct usb_ehci *ehci) usb_cmd = (void __iomem *)&ehci->usbcmd; /* Stop then Reset */ - val = __raw_readl(usb_cmd); - val &= ~UCMD_RUN_STOP; - __raw_writel(val, usb_cmd); - while (__raw_readl(usb_cmd) & UCMD_RUN_STOP) + clrbits_le32(usb_cmd, UCMD_RUN_STOP); + while (readl(usb_cmd) & UCMD_RUN_STOP) ; - val = __raw_readl(usb_cmd); - val |= UCMD_RESET; - __raw_writel(val, usb_cmd); - while (__raw_readl(usb_cmd) & UCMD_RESET) + setbits_le32(usb_cmd, UCMD_RESET); + while (readl(usb_cmd) & UCMD_RESET) ; /* Reset USBPHY module */ - val = __raw_readl(phy_ctrl); - val |= USBPHY_CTRL_SFTRST; - __raw_writel(val, phy_ctrl); + setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST); udelay(10); /* Remove CLKGATE and SFTRST */ - val = __raw_readl(phy_ctrl); - val &= ~(USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST); - __raw_writel(val, phy_ctrl); + clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST); udelay(10); /* Power up the PHY */ - __raw_writel(0, phy_reg + USBPHY_PWD); + writel(0, phy_reg + USBPHY_PWD); /* enable FS/LS device */ - val = __raw_readl(phy_ctrl); - val |= (USBPHY_CTRL_ENUTMILEVEL2 | USBPHY_CTRL_ENUTMILEVEL3); - __raw_writel(val, phy_ctrl); + setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 | + USBPHY_CTRL_ENUTMILEVEL3); return 0; } @@ -171,28 +163,46 @@ struct usbnc_regs { u32 otg_phy_ctrl_0; u32 uh1_phy_ctrl_0; }; +#elif defined(CONFIG_MX7) +struct usbnc_regs { + u32 ctrl1; + u32 ctrl2; + u32 reserve1[11]; + u32 phy_ctrl2; + u32 reserve2[6]; + u32 adp_cfg1; + u32 reserve3; + u32 adp_status; +}; +#endif static void usb_oc_config(int index) { +#if defined(CONFIG_MX6) struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET); void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]); - u32 val; +#elif defined(CONFIG_MX7) + struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR + + (0x10000 * index) + USB_NC_OFFSET); + void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl1); +#endif - val = __raw_readl(ctrl); #if CONFIG_MACH_TYPE == MACH_TYPE_MX6Q_ARM2 /* mx6qarm2 seems to required a different setting*/ - val &= ~UCTRL_OVER_CUR_POL; + clrbits_le32(ctrl, UCTRL_OVER_CUR_POL); #else - val |= UCTRL_OVER_CUR_POL; + setbits_le32(ctrl, UCTRL_OVER_CUR_POL); #endif - __raw_writel(val, ctrl); - val = __raw_readl(ctrl); - val |= UCTRL_OVER_CUR_DIS; - __raw_writel(val, ctrl); +#if defined(CONFIG_MX6) + setbits_le32(ctrl, UCTRL_OVER_CUR_DIS); +#elif defined(CONFIG_MX7) + setbits_le32(ctrl, UCTRL_OVER_CUR_DIS | UCTRL_PM); +#endif } +#if defined(CONFIG_MX6) int usb_phy_mode(int port) { void __iomem *phy_reg; @@ -202,7 +212,7 @@ int usb_phy_mode(int port) phy_reg = (void __iomem *)phy_bases[port]; phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL); - val = __raw_readl(phy_ctrl); + val = readl(phy_ctrl); if (val & USBPHY_CTRL_OTG_ID) return USB_INIT_DEVICE; @@ -210,16 +220,48 @@ int usb_phy_mode(int port) return USB_INIT_HOST; } +/* + * board_ehci_hcd_init - override usb phy mode + * @port: usb host/otg port + * + * Target board specific, override usb_phy_mode. + * When usb-otg is used as usb host port, iomux pad usb_otg_id can be + * left disconnected in this case usb_phy_mode will not be able to identify + * the phy mode that usb port is used. + * Machine file overrides board_usb_phy_mode. + * + * Return: USB_INIT_DEVICE or USB_INIT_HOST + */ int __weak board_usb_phy_mode(int port) { return usb_phy_mode(port); } +#endif +/* + * board_ehci_hcd_init - set usb vbus voltage + * @port: usb otg port + * + * Target board specific, setup iomux pad to setup supply vbus voltage + * for usb otg port. Machine board file overrides board_ehci_hcd_init + * + * Return: 0 Success + */ int __weak board_ehci_hcd_init(int port) { return 0; } +/* + * board_ehci_power - enables/disables usb vbus voltage + * @port: usb otg port + * @on: on/off vbus voltage + * + * Enables/disables supply vbus voltage for usb otg port. + * Machine board file overrides board_ehci_power + * + * Return: 0 Success + */ int __weak board_ehci_power(int port, int on) { return 0; @@ -228,9 +270,14 @@ int __weak board_ehci_power(int port, int on) int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr, struct ehci_hcor **hcor) { +#if defined(CONFIG_MX6) enum usb_init_type type; struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR + (0x200 * index)); +#elif defined(CONFIG_MX7) + struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR + + (0x10000 * index)); +#endif if (index > 3) return -EINVAL; @@ -240,24 +287,34 @@ int ehci_hcd_init(int index, enum usb_init_type init, /* Do board specific initialization */ board_ehci_hcd_init(index); +#if defined(CONFIG_MX6) usb_power_config(index); +#endif usb_oc_config(index); +#if defined(CONFIG_MX6) usb_internal_phy_clock_gate(index, 1); usb_phy_enable(index, ehci); type = board_usb_phy_mode(index); +#endif *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); *hcor = (struct ehci_hcor *)((uint32_t)*hccr + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); +#if defined(CONFIG_MX6) if ((type == init) || (type == USB_INIT_DEVICE)) board_ehci_power(index, (type == USB_INIT_DEVICE) ? 0 : 1); if (type != init) return -ENODEV; if (type == USB_INIT_DEVICE) return 0; +#elif defined(CONFIG_MX7) + board_ehci_power(index, (init == USB_INIT_DEVICE) ? 0 : 1); + if (init == USB_INIT_DEVICE) + return 0; +#endif setbits_le32(&ehci->usbmode, CM_HOST); - __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); + writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); setbits_le32(&ehci->portsc, USB_EN); mdelay(10); -- 2.1.4

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[U-Boot] [PATCH v2 00/11] USB and sunxi Kconfig and config changes leading up to fastboot support
by Paul Kocialkowski 31 Jul '15

31 Jul '15

This series is based off the following patch: * drivers: hierarchize drivers Kconfig menu that was sent to the list earlier. Please pick it up as well when merging this series.

3 15

[U-Boot] [PATCH 3/3] crypto/fsl: SEC driver cleanup for 64 bit and endianness
by Aneesh Bansal 31 Jul '15

31 Jul '15

The SEC driver code has been cleaned up to work for 64 bit physical addresses and systems where endianess of SEC block is different from the Core. Changes: 1. Descriptor created on Core is modified as per SEC block endianness before the job is submitted. 2. The read/write to Job Rings are done using I/O functions defined for SEC which will take care of the endianness. 3. The 32 bit low and high part of the 64 bit address in descriptor will vary depending on endianness of SEC. Signed-off-by: Aneesh Bansal <aneesh.bansal(a)freescale.com> --- drivers/crypto/fsl/desc_constr.h | 24 ++++++++++++++++++++++++ drivers/crypto/fsl/fsl_hash.c | 7 +------ drivers/crypto/fsl/jr.c | 40 ++++++++++++++++++++++++++-------------- drivers/crypto/fsl/jr.h | 19 +++++++++---------- include/fsl_sec.h | 24 ++++++++++++++---------- 5 files changed, 74 insertions(+), 40 deletions(-) diff --git a/drivers/crypto/fsl/desc_constr.h b/drivers/crypto/fsl/desc_constr.h index f9cae91..ac4a933 100644 --- a/drivers/crypto/fsl/desc_constr.h +++ b/drivers/crypto/fsl/desc_constr.h @@ -36,6 +36,21 @@ LDST_SRCDST_WORD_DECOCTRL | \ (LDOFF_ENABLE_AUTO_NFIFO << LDST_OFFSET_SHIFT)) +#ifdef CONFIG_PHYS_64BIT +union ptr_addr_t { + u64 m_whole; + struct { +#ifdef CONFIG_SYS_FSL_SEC_LE + u32 low; + u32 high; +#else + u32 high; + u32 low; +#endif + } m_halfs; +}; +#endif + static inline int desc_len(u32 *desc) { return *desc & HDR_DESCLEN_MASK; @@ -65,7 +80,16 @@ static inline void append_ptr(u32 *desc, dma_addr_t ptr) { dma_addr_t *offset = (dma_addr_t *)desc_end(desc); +#ifdef CONFIG_PHYS_64BIT + /* The Position of low and high part of 64 bit address + * will depend on the endianness of CAAM Block */ + union ptr_addr_t ptr_addr; + ptr_addr.m_halfs.high = (u32)(ptr >> 32); + ptr_addr.m_halfs.low = (u32)ptr; + *offset = ptr_addr.m_whole; +#else *offset = ptr; +#endif (*desc) += CAAM_PTR_SZ / CAAM_CMD_SZ; } diff --git a/drivers/crypto/fsl/fsl_hash.c b/drivers/crypto/fsl/fsl_hash.c index c298404..9b243f6 100644 --- a/drivers/crypto/fsl/fsl_hash.c +++ b/drivers/crypto/fsl/fsl_hash.c @@ -92,12 +92,7 @@ static int caam_hash_update(void *hash_ctx, const void *buf, return -EINVAL; } -#ifdef CONFIG_PHYS_64BIT - ctx->sg_tbl[ctx->sg_num].addr_hi = addr >> 32; -#else - ctx->sg_tbl[ctx->sg_num].addr_hi = 0x0; -#endif - ctx->sg_tbl[ctx->sg_num].addr_lo = addr; + sec_out64(&ctx->sg_tbl[ctx->sg_num].addr, addr); sec_out32(&ctx->sg_tbl[ctx->sg_num].len_flag, (size & SG_ENTRY_LENGTH_MASK)); diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index f99d594..fcc8a5a 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -11,6 +11,7 @@ #include "fsl_sec.h" #include "jr.h" #include "jobdesc.h" +#include "desc_constr.h" #define CIRC_CNT(head, tail, size) (((head) - (tail)) & (size - 1)) #define CIRC_SPACE(head, tail, size) CIRC_CNT((tail), (head) + 1, (size)) @@ -154,11 +155,25 @@ static int jr_hw_reset(void) /* -1 --- error, can't enqueue -- no space available */ static int jr_enqueue(uint32_t *desc_addr, - void (*callback)(uint32_t desc, uint32_t status, void *arg), + void (*callback)(uint32_t status, void *arg), void *arg) { struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR; - int head = jr.head; + uint32_t head = jr.head; + uint32_t desc_word; + int length = desc_len(desc_addr); + int i; + + /* The descriptor must be submitted to SEC block as per endianness + * of the SEC Block. + * So, if the endianness of Core and SEC block is different, each word + * of the descriptor will be byte-swapped. + */ + for (i = 0; i < length; i++) { + desc_word = desc_addr[i]; + sec_out32((uint32_t *)&desc_addr[i], desc_word); + } + dma_addr_t desc_phys_addr = virt_to_phys(desc_addr); if (sec_in32(&regs->irsa) == 0 || @@ -166,7 +181,6 @@ static int jr_enqueue(uint32_t *desc_addr, return -1; jr.info[head].desc_phys_addr = desc_phys_addr; - jr.info[head].desc_addr = (uint32_t)desc_addr; jr.info[head].callback = (void *)callback; jr.info[head].arg = arg; jr.info[head].op_done = 0; @@ -177,7 +191,7 @@ static int jr_enqueue(uint32_t *desc_addr, ARCH_DMA_MINALIGN); flush_dcache_range(start, end); - jr.input_ring[head] = desc_phys_addr; + sec_out_phys(&jr.input_ring[head], desc_phys_addr); start = (unsigned long)&jr.input_ring[head] & ~(ARCH_DMA_MINALIGN - 1); end = ALIGN(start + sizeof(dma_addr_t), ARCH_DMA_MINALIGN); flush_dcache_range(start, end); @@ -192,10 +206,10 @@ static int jr_enqueue(uint32_t *desc_addr, static int jr_dequeue(void) { struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR; - int head = jr.head; - int tail = jr.tail; - int idx, i, found; - void (*callback)(uint32_t desc, uint32_t status, void *arg); + uint32_t head = jr.head; + uint32_t tail = jr.tail; + uint32_t idx, i, found; + void (*callback)(uint32_t status, void *arg); void *arg = NULL; while (sec_in32(&regs->orsf) && CIRC_CNT(jr.head, jr.tail, jr.size)) { @@ -208,14 +222,12 @@ static int jr_dequeue(void) found = 0; - dma_addr_t op_desc = jr.output_ring[jr.tail].desc; - uint32_t status = jr.output_ring[jr.tail].status; - uint32_t desc_virt; + dma_addr_t op_desc = sec_in_phys(&jr.output_ring[jr.tail].desc); + uint32_t status = sec_in32(&jr.output_ring[jr.tail].status); for (i = 0; CIRC_CNT(head, tail + i, jr.size) >= 1; i++) { idx = (tail + i) & (jr.size - 1); if (op_desc == jr.info[idx].desc_phys_addr) { - desc_virt = jr.info[idx].desc_addr; found = 1; break; } @@ -244,13 +256,13 @@ static int jr_dequeue(void) sec_out32(&regs->orjr, 1); jr.info[idx].op_done = 0; - callback(desc_virt, status, arg); + callback(status, arg); } return 0; } -static void desc_done(uint32_t desc, uint32_t status, void *arg) +static void desc_done(uint32_t status, void *arg) { struct result *x = arg; x->status = status; diff --git a/drivers/crypto/fsl/jr.h b/drivers/crypto/fsl/jr.h index cce2c58..b630590 100644 --- a/drivers/crypto/fsl/jr.h +++ b/drivers/crypto/fsl/jr.h @@ -40,37 +40,36 @@ struct op_ring { } __packed; struct jr_info { - void (*callback)(dma_addr_t desc, uint32_t status, void *arg); + void (*callback)(uint32_t status, void *arg); dma_addr_t desc_phys_addr; - uint32_t desc_addr; uint32_t desc_len; uint32_t op_done; void *arg; }; struct jobring { - int jq_id; - int irq; - int liodn; + uint32_t jq_id; + uint32_t irq; + uint32_t liodn; /* Head is the index where software would enq the descriptor in * the i/p ring */ - int head; + uint32_t head; /* Tail index would be used by s/w ehile enqueuing to determine if * there is any space left in the s/w maintained i/p rings */ /* Also in case of deq tail will be incremented only in case of * in-order job completion */ - int tail; + uint32_t tail; /* Read index of the output ring. It may not match with tail in case * of out of order completetion */ - int read_idx; + uint32_t read_idx; /* Write index to input ring. Would be always equal to head */ - int write_idx; + uint32_t write_idx; /* Size of the rings. */ - int size; + uint32_t size; /* The ip and output rings have to be accessed by SEC. So the * pointers will ahve to point to the housekeeping region provided * by SEC diff --git a/include/fsl_sec.h b/include/fsl_sec.h index ebb1ac6..39c9b3c 100644 --- a/include/fsl_sec.h +++ b/include/fsl_sec.h @@ -12,12 +12,16 @@ #include <asm/io.h> #ifdef CONFIG_SYS_FSL_SEC_LE +#define sec_in64(a) in_le64(a) +#define sec_out64(a, v) out_le64(a, v) #define sec_in32(a) in_le32(a) #define sec_out32(a, v) out_le32(a, v) #define sec_in16(a) in_le16(a) #define sec_clrbits32 clrbits_le32 #define sec_setbits32 setbits_le32 #elif defined(CONFIG_SYS_FSL_SEC_BE) +#define sec_in64(a) in_be64(a) +#define sec_out64(a, v) out_be64(a, v) #define sec_in32(a) in_be32(a) #define sec_out32(a, v) out_be32(a, v) #define sec_in16(a) in_be16(a) @@ -27,6 +31,15 @@ #error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined #endif +#ifdef CONFIG_PHYS_64BIT +#define sec_out_phys sec_out64 +#define sec_in_phys sec_in64 +#else +#define sec_out_phys sec_out32 +#define sec_in_phys sec_in32 +#endif + + /* Security Engine Block (MS = Most Sig., LS = Least Sig.) */ #if CONFIG_SYS_FSL_SEC_COMPAT >= 4 /* RNG4 TRNG test registers */ @@ -180,16 +193,7 @@ struct jr_regs { * related information */ struct sg_entry { -#if defined(CONFIG_SYS_FSL_SEC_LE) && !defined(CONFIG_MX6) - uint32_t addr_lo; /* Memory Address - lo */ - uint16_t addr_hi; /* Memory Address of start of buffer - hi */ - uint16_t reserved_zero; -#else - uint16_t reserved_zero; - uint16_t addr_hi; /* Memory Address of start of buffer - hi */ - uint32_t addr_lo; /* Memory Address - lo */ -#endif - + uint64_t addr; uint32_t len_flag; /* Length of the data in the frame */ #define SG_ENTRY_LENGTH_MASK 0x3FFFFFFF #define SG_ENTRY_EXTENSION_BIT 0x80000000 -- 1.8.1.4

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