July 2015 - U-Boot

[U-Boot] [PATCH 3/3][v7] powerpc/mpc85xx: SECURE BOOT-Copy Boot Script on RAM
by Aneesh Bansal 31 Jul '15

31 Jul '15

For running Chain of Trust when doing Secure Boot from NAND, the Bootscript header and bootscript must be copied from NAND to RAM(DDR). The addresses and commands for the same have been defined. Signed-off-by: Saksham Jain <saksham(a)freescale.com> Signed-off-by: Ruchika Gupta <ruchika.gupta(a)freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal(a)freescale.com> --- Changes in v7: Patchset created. arch/powerpc/include/asm/fsl_secure_boot.h | 14 ++++++++++++++ include/config_fsl_secboot.h | 29 ++++++++++++++++++++++++++++- include/configs/corenet_ds.h | 1 + 3 files changed, 43 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index cc33466..6e55716 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -73,6 +73,18 @@ #endif #ifndef CONFIG_FIT_SIGNATURE +/* If Boot Script is not on NOR and is required to be copied on RAM */ +#ifdef CONFIG_BOOTSCRIPT_COPY_RAM +#define CONFIG_BS_HDR_ADDR_RAM 0x00010000 +#define CONFIG_BS_HDR_ADDR_FLASH 0x00800000 +#define CONFIG_BS_HDR_SIZE 0x00002000 +#define CONFIG_BS_ADDR_RAM 0x00012000 +#define CONFIG_BS_ADDR_FLASH 0x00802000 +#define CONFIG_BS_SIZE 0x00001000 + +#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM +#else + /* The bootscript header address is different for B4860 because the NOR * mapping is different on B4 due to reduced NOR size. */ @@ -88,6 +100,8 @@ #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xee020000 #endif +#endif + #include <config_fsl_secboot.h> #endif diff --git a/include/config_fsl_secboot.h b/include/config_fsl_secboot.h index 050b157..fc6788a 100644 --- a/include/config_fsl_secboot.h +++ b/include/config_fsl_secboot.h @@ -55,6 +55,22 @@ /* For secure boot flow, default environment used will be used */ #if defined(CONFIG_SYS_RAMBOOT) +#ifdef CONFIG_BOOTSCRIPT_COPY_RAM +#define CONFIG_BS_COPY_ENV \ + "setenv bs_hdr_ram " __stringify(CONFIG_BS_HDR_ADDR_RAM)";" \ + "setenv bs_hdr_flash " __stringify(CONFIG_BS_HDR_ADDR_FLASH)";" \ + "setenv bs_hdr_size " __stringify(CONFIG_BS_HDR_SIZE)";" \ + "setenv bs_ram " __stringify(CONFIG_BS_ADDR_RAM)";" \ + "setenv bs_flash " __stringify(CONFIG_BS_ADDR_FLASH)";" \ + "setenv bs_size " __stringify(CONFIG_BS_SIZE)";" + +#if defined(CONFIG_RAMBOOT_NAND) +#define CONFIG_BS_COPY_CMD \ + "nand read $bs_hdr_ram $bs_hdr_flash $bs_hdr_size ;" \ + "nand read $bs_ram $bs_flash $bs_size ;" +#endif /* CONFIG_RAMBOOT_NAND */ +#endif /* CONFIG_BOOTSCRIPT_COPY_RAM */ + #if defined(CONFIG_RAMBOOT_SPIFLASH) #undef CONFIG_ENV_IS_IN_SPI_FLASH #elif defined(CONFIG_RAMBOOT_NAND) @@ -68,6 +84,17 @@ #define CONFIG_ENV_IS_NOWHERE +#ifndef CONFIG_BS_COPY_ENV +#define CONFIG_BS_COPY_ENV +#endif + +#ifndef CONFIG_BS_COPY_CMD +#define CONFIG_BS_COPY_CMD +#endif + +#define CONFIG_SECBOOT_CMD CONFIG_BS_COPY_ENV \ + CONFIG_BS_COPY_CMD \ + CONFIG_SECBOOT /* * We don't want boot delay for secure boot flow * before autoboot starts @@ -75,7 +102,7 @@ #undef CONFIG_BOOTDELAY #define CONFIG_BOOTDELAY 0 #undef CONFIG_BOOTCOMMAND -#define CONFIG_BOOTCOMMAND CONFIG_SECBOOT +#define CONFIG_BOOTCOMMAND CONFIG_SECBOOT_CMD /* * CONFIG_ZERO_BOOTDELAY_CHECK should not be defined for diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 2ec7fd4f..497b58b 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -22,6 +22,7 @@ #ifdef CONFIG_NAND #define CONFIG_RAMBOOT_NAND #endif +#define CONFIG_BOOTSCRIPT_COPY_RAM #else #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -- 1.8.1.4

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[U-Boot] [PATCH 2/3][[v7] powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P5020 and P5040
by Aneesh Bansal 31 Jul '15

31 Jul '15

Secure Boot Target is added for NAND for P5020 and P5040. The Secure boot target has already been added for P3041 by enabling CONFIG_SYS_RAMBOOT and configuring CPC as SRAM. The targets for P5020 and P5040 are added in the same manner. Signed-off-by: Saksham Jain <saksham(a)freescale.com> Signed-off-by: Ruchika Gupta <ruchika.gupta(a)freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal(a)freescale.com> --- Changes in v7: Patchset created. TEXT BASE is defined as 0xFFF40000 as per new design. board/freescale/corenet_ds/MAINTAINERS | 2 ++ configs/P5020DS_NAND_SECURE_BOOT_defconfig | 4 ++++ configs/P5040DS_NAND_SECURE_BOOT_defconfig | 4 ++++ 3 files changed, 10 insertions(+) create mode 100644 configs/P5020DS_NAND_SECURE_BOOT_defconfig create mode 100644 configs/P5040DS_NAND_SECURE_BOOT_defconfig diff --git a/board/freescale/corenet_ds/MAINTAINERS b/board/freescale/corenet_ds/MAINTAINERS index 6855446..73b0553 100644 --- a/board/freescale/corenet_ds/MAINTAINERS +++ b/board/freescale/corenet_ds/MAINTAINERS @@ -33,3 +33,5 @@ CORENET_DS_SECURE_BOOT BOARD M: Aneesh Bansal <aneesh.bansal(a)freescale.com> S: Maintained F: configs/P3041DS_NAND_SECURE_BOOT_defconfig +F: configs/P5020DS_NAND_SECURE_BOOT_defconfig +F: configs/P5040DS_NAND_SECURE_BOOT_defconfig diff --git a/configs/P5020DS_NAND_SECURE_BOOT_defconfig b/configs/P5020DS_NAND_SECURE_BOOT_defconfig new file mode 100644 index 0000000..5edfe45 --- /dev/null +++ b/configs/P5020DS_NAND_SECURE_BOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P5020DS=y diff --git a/configs/P5040DS_NAND_SECURE_BOOT_defconfig b/configs/P5040DS_NAND_SECURE_BOOT_defconfig new file mode 100644 index 0000000..f33d236 --- /dev/null +++ b/configs/P5040DS_NAND_SECURE_BOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P5040DS=y -- 1.8.1.4

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[U-Boot] [PATCH 1/3][v7] powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041
by Aneesh Bansal 31 Jul '15

31 Jul '15

Secure Boot Target is added for NAND for P3041. Changes: In PowerPC, the core begins execution from address 0xFFFFFFFC. In case of secure boot, this default address maps to Boot ROM. The Boot ROM code requires that the bootloader(U-boot) must lie in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF. In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is configured as SRAM. U-Boot binary will be located on SRAM configured at address 0xBFF00000. In the U-Boot code, TLB entries are created to map the virtual address 0xFFF00000 to physical address 0xBFF00000 of CPC configured as SRAM. Signed-off-by: Saksham Jain <saksham(a)freescale.com> Signed-off-by: Ruchika Gupta <ruchika.gupta(a)freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal(a)freescale.com> --- Changes in v7: Created TLB entry to map virtual address 0xFFF00000 to physical address 0xBFF00000 as per discussion. Makefile | 4 ++++ arch/powerpc/cpu/mpc85xx/start.S | 11 +++++++++++ arch/powerpc/include/asm/fsl_secure_boot.h | 5 +++++ board/freescale/common/p_corenet/tlb.c | 15 +++++++++++++++ board/freescale/corenet_ds/MAINTAINERS | 5 +++++ configs/P3041DS_NAND_SECURE_BOOT_defconfig | 4 ++++ include/configs/corenet_ds.h | 8 ++++++++ 7 files changed, 52 insertions(+) create mode 100644 configs/P3041DS_NAND_SECURE_BOOT_defconfig diff --git a/Makefile b/Makefile index 0a674bf..1753709 100644 --- a/Makefile +++ b/Makefile @@ -737,8 +737,12 @@ ALL-$(CONFIG_ONENAND_U_BOOT) += u-boot-onenand.bin ifeq ($(CONFIG_SPL_FSL_PBL),y) ALL-$(CONFIG_RAMBOOT_PBL) += u-boot-with-spl-pbl.bin else +ifneq ($(CONFIG_SECURE_BOOT), y) +# For Secure Boot The Image needs to be signed and Header must also +# be included. So The image has to be built explicitly ALL-$(CONFIG_RAMBOOT_PBL) += u-boot.pbl endif +endif ALL-$(CONFIG_SPL) += spl/u-boot-spl.bin ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot.img ALL-$(CONFIG_TPL) += tpl/u-boot-tpl.bin diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index e61d8e0..a70fb71 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -1052,6 +1052,17 @@ create_init_ram_area: CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \ CONFIG_SYS_PBI_FLASH_WINDOW & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \ 0, r6 + +#elif defined(CONFIG_RAMBOOT_PBL) && defined(CONFIG_SECURE_BOOT) + /* create a temp mapping in AS = 1 for mapping CONFIG_SYS_MONITOR_BASE + * to L3 Address configured by PBL for ISBC code + */ + create_tlb1_entry 15, \ + 1, BOOKE_PAGESZ_1M, \ + CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \ + CONFIG_SYS_INIT_L3_ADDR & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \ + 0, r6 + #else /* * create a temp mapping in AS=1 to the 1M CONFIG_SYS_MONITOR_BASE space, the main diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 8f794ef..cc33466 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -46,6 +46,11 @@ #define CONFIG_SYS_INIT_L3_ADDR 0xbff00000 #endif +#if defined(CONFIG_RAMBOOT_PBL) +#undef CONFIG_SYS_INIT_L3_ADDR +#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000 +#endif + #if defined(CONFIG_C29XPCIE) #define CONFIG_KEY_REVOCATION #endif diff --git a/board/freescale/common/p_corenet/tlb.c b/board/freescale/common/p_corenet/tlb.c index 8148e46..56e4f63 100644 --- a/board/freescale/common/p_corenet/tlb.c +++ b/board/freescale/common/p_corenet/tlb.c @@ -43,6 +43,8 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 1 */ /* *I*** - Covers boot page */ #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) + +#if !defined(CONFIG_SECURE_BOOT) /* * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the * SRAM is at 0xfff00000, it covered the 0xfffff000. @@ -50,6 +52,19 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_1M, 1), +#else + /* + * *I*G - L3SRAM. When L3 is used as 1M SRAM, in case of Secure Boot + * the physical address of the SRAM is at CONFIG_SYS_INIT_L3_ADDR, + * and virtual address is CONFIG_SYS_MONITOR_BASE + */ + + SET_TLB_ENTRY(1, CONFIG_SYS_MONITOR_BASE & 0xfff00000, + CONFIG_SYS_INIT_L3_ADDR & 0xfff00000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_1M, 1), +#endif + #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) /* * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the diff --git a/board/freescale/corenet_ds/MAINTAINERS b/board/freescale/corenet_ds/MAINTAINERS index 745847c..6855446 100644 --- a/board/freescale/corenet_ds/MAINTAINERS +++ b/board/freescale/corenet_ds/MAINTAINERS @@ -28,3 +28,8 @@ F: configs/P5040DS_NAND_defconfig F: configs/P5040DS_SDCARD_defconfig F: configs/P5040DS_SPIFLASH_defconfig F: configs/P5040DS_SECURE_BOOT_defconfig + +CORENET_DS_SECURE_BOOT BOARD +M: Aneesh Bansal <aneesh.bansal(a)freescale.com> +S: Maintained +F: configs/P3041DS_NAND_SECURE_BOOT_defconfig diff --git a/configs/P3041DS_NAND_SECURE_BOOT_defconfig b/configs/P3041DS_NAND_SECURE_BOOT_defconfig new file mode 100644 index 0000000..757f326 --- /dev/null +++ b/configs/P3041DS_NAND_SECURE_BOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P3041DS=y diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index bf765af..2ec7fd4f 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -16,6 +16,13 @@ #include "../board/freescale/common/ics307_clk.h" #ifdef CONFIG_RAMBOOT_PBL +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#ifdef CONFIG_NAND +#define CONFIG_RAMBOOT_NAND +#endif +#else #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg @@ -29,6 +36,7 @@ #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg #endif #endif +#endif #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE /* Set 1M boot space */ -- 1.8.1.4

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[U-Boot] [PATCH 1/1] T102xRDB: Enable ifc nand ecc encode and decode
by Raghav Dogra 31 Jul '15

31 Jul '15

From: Jaiprakash Singh <b44839(a)freescale.com> IFC nand ecc encode and decode mode are not correctly set in CSOR register during nand initialization.Enable ecc encode/decode in 4-bit mode Signed-off-by: Jaiprakash Singh <b44839(a)freescale.com> --- include/configs/T102xRDB.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index deff617..12082c3 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -395,7 +395,9 @@ unsigned long get_board_ddr_clk(void); | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) #elif defined(CONFIG_T1023RDB) -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_RAL_3 /* RAL 3Bytes */ \ +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \ | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \ -- 1.7.9.5

2 1

[U-Boot] [PATCH] powerpc: mpc85xx: Correct CONFIG_USB_MAX_CONTROLLER_COUNT for p1025
by Nikhil Badola 31 Jul '15

31 Jul '15

Correct the value CONFIG_USB_MAX_CONTROLLER_COUNT macro to 1 for p1025 as it has one USB controller Signed-off-by: Nikhil Badola <nikhil.badola(a)freescale.com> --- arch/powerpc/include/asm/config_mpc85xx.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 9d56bc1..349146f 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -334,7 +334,7 @@ #elif defined(CONFIG_P1025) #define CONFIG_MAX_CPUS 2 #define CONFIG_SYS_FSL_NUM_LAWS 12 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM -- 1.7.11.7

2 1

[U-Boot] [PATCH][v3] powerpc/b4860qds:Update README for DIP switch information
by Raghav Dogra 31 Jul '15

31 Jul '15

The board manual desribes ON as boolean 1 and OFF as boolean 0. Updating README with correct boolean values. Signed-off-by: Raghav Dogra <raghav(a)freescale.com> --- Changes for v2: -Reduced the description -Modified the heading Changes for v3: -Modified the description -Modified the subject -Reduced the changes doc/README.b4860qds | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/README.b4860qds b/doc/README.b4860qds index eada0c7..6fcc3bd 100644 --- a/doc/README.b4860qds +++ b/doc/README.b4860qds @@ -119,7 +119,7 @@ B4860QDS Default Settings Switch Settings ---------------- -SW1 OFF [0] OFF [1] OFF [1] OFF [0] OFF [1] OFF [0] OFF [1] OFF [1] +SW1 OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] SW2 ON ON ON ON ON ON OFF OFF SW3 OFF OFF OFF ON OFF OFF ON OFF SW5 OFF OFF OFF OFF OFF OFF ON ON -- 1.9.1

2 1

[U-Boot] [PATCH] powerpc/t1024: update fman liodn for mac1
by Shengzhou Liu 31 Jul '15

31 Jul '15

MAC1 acts as 1G/10G dual-role MAC on T1024. We introduce macro SET_FMAN_RX_10G_TYPE2_LIODN for 10G MACs which have same Port ID and same offset of address with 1G MAC. Update it to match with the setting of fman in t1024 device tree, otherwise there is no 'fsl,liodn' in /proc/device-tree/soc@ffe000000/fman@400000/port@88000/ Signed-off-by: Shengzhou Liu <Shengzhou.Liu(a)freescale.com> --- arch/powerpc/cpu/mpc85xx/t1024_ids.c | 3 +-- arch/powerpc/include/asm/fsl_liodn.h | 6 ++++++ 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/t1024_ids.c b/arch/powerpc/cpu/mpc85xx/t1024_ids.c index 132689b..8a1092e 100644 --- a/arch/powerpc/cpu/mpc85xx/t1024_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t1024_ids.c @@ -51,11 +51,10 @@ int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); #ifdef CONFIG_SYS_DPAA_FMAN struct liodn_id_table fman1_liodn_tbl[] = { - SET_FMAN_RX_1G_LIODN(1, 0, 88), + SET_FMAN_RX_10G_TYPE2_LIODN(1, 0, 88), SET_FMAN_RX_1G_LIODN(1, 1, 89), SET_FMAN_RX_1G_LIODN(1, 2, 90), SET_FMAN_RX_1G_LIODN(1, 3, 91), - SET_FMAN_RX_10G_LIODN(1, 0, 94), }; int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); #endif diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h index 811f034..6206bee 100644 --- a/arch/powerpc/include/asm/fsl_liodn.h +++ b/arch/powerpc/include/asm/fsl_liodn.h @@ -145,6 +145,12 @@ extern void fdt_fixup_liodn(void *blob); FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 16), \ CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET) \ +/* enetNum is 0, 1, 2... so we + 8 for type-2 10g to get to HW Port ID */ +#define SET_FMAN_RX_10G_TYPE2_LIODN(fmNum, enetNum, liodn) \ + SET_LIODN_ENTRY_1("fsl,fman-port-10g-rx", liodn, \ + FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \ + CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET) \ + /* * handle both old and new versioned SEC properties: * "fsl,secX.Y" became "fsl,sec-vX.Y" during development -- 2.1.0.27.g96db324

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[U-Boot] [PATCH] mpc85xx/t104x, t102x: Update CPC debug register value in PBI commands
by Priyanka Jain 31 Jul '15

31 Jul '15

Update PBI command in pbi_cfg files to keep register bit to default reset value while configuring CPC as SRAM Signed-off-by: Priyanka Jain <Priyanka.Jain(a)freescale.com> --- board/freescale/t102xqds/t1024_pbi.cfg | 2 +- board/freescale/t102xrdb/t1024_pbi.cfg | 2 +- board/freescale/t1040qds/t1040_pbi.cfg | 2 +- board/freescale/t104xrdb/t104x_pbi.cfg | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/board/freescale/t102xqds/t1024_pbi.cfg b/board/freescale/t102xqds/t1024_pbi.cfg index 7b9e9b0..98efca2 100644 --- a/board/freescale/t102xqds/t1024_pbi.cfg +++ b/board/freescale/t102xqds/t1024_pbi.cfg @@ -6,7 +6,7 @@ #Configure CPC1 as 256KB SRAM 09010100 00000000 09010104 fffc0007 -09010f00 08000000 +09010f00 081e000d 09010000 80000000 #Configure LAW for CPC1 09000cd0 00000000 diff --git a/board/freescale/t102xrdb/t1024_pbi.cfg b/board/freescale/t102xrdb/t1024_pbi.cfg index 7b9e9b0..98efca2 100644 --- a/board/freescale/t102xrdb/t1024_pbi.cfg +++ b/board/freescale/t102xrdb/t1024_pbi.cfg @@ -6,7 +6,7 @@ #Configure CPC1 as 256KB SRAM 09010100 00000000 09010104 fffc0007 -09010f00 08000000 +09010f00 081e000d 09010000 80000000 #Configure LAW for CPC1 09000cd0 00000000 diff --git a/board/freescale/t1040qds/t1040_pbi.cfg b/board/freescale/t1040qds/t1040_pbi.cfg index 10b1a6d..121b005 100644 --- a/board/freescale/t1040qds/t1040_pbi.cfg +++ b/board/freescale/t1040qds/t1040_pbi.cfg @@ -6,7 +6,7 @@ #Configure CPC1 as 256KB SRAM 09010100 00000000 09010104 fffc0007 -09010f00 08000000 +09010f00 081e000d 09010000 80000000 #Configure LAW for CPC1 09000cf0 00000000 diff --git a/board/freescale/t104xrdb/t104x_pbi.cfg b/board/freescale/t104xrdb/t104x_pbi.cfg index b83b9b7..51945b4 100644 --- a/board/freescale/t104xrdb/t104x_pbi.cfg +++ b/board/freescale/t104xrdb/t104x_pbi.cfg @@ -16,7 +16,7 @@ #Configure CPC1 as 256KB SRAM 09010100 00000000 09010104 fffc0007 -09010f00 08000000 +09010f00 081e000d 09010000 80000000 #Configure LAW for CPC1 09000cd0 00000000 -- 1.7.4.1

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[U-Boot] [PATCH] powerpc/t4rdb: fix cpld reset altbank
by shh.xie＠gmail.com 31 Jul '15

31 Jul '15

From: Shaohui Xie <Shaohui.Xie(a)freescale.com> cpld reset altbank should always reset to bank4 no matter what current bank is. Signed-off-by: Shaohui Xie <Shaohui.Xie(a)freescale.com> --- board/freescale/t4rdb/cpld.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/board/freescale/t4rdb/cpld.c b/board/freescale/t4rdb/cpld.c index d5f3812..d563d0d 100644 --- a/board/freescale/t4rdb/cpld.c +++ b/board/freescale/t4rdb/cpld.c @@ -47,14 +47,8 @@ void cpld_set_altbank(void) switch (curbank) { case CPLD_SELECT_BANK0: - altbank = CPLD_SELECT_BANK4; - CPLD_WRITE(vbank, altbank); - override = CPLD_READ(software_on); - CPLD_WRITE(software_on, override | CPLD_BANK_SEL_EN); - CPLD_WRITE(sys_reset, CPLD_SYSTEM_RESET); - break; case CPLD_SELECT_BANK4: - altbank = CPLD_SELECT_BANK0; + altbank = CPLD_SELECT_BANK4; CPLD_WRITE(vbank, altbank); override = CPLD_READ(software_on); CPLD_WRITE(software_on, override | CPLD_BANK_SEL_EN); -- 2.1.0.27.g96db324

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[U-Boot] [PATCH v2] board/p2020rdb: fix the FDT_ERR_NOTFOUND issue
by ying.zhang＠freescale.com 31 Jul '15

31 Jul '15

From: Ying Zhang <b40530(a)freescale.com> Because the function ft_board_setup() delete the USB2 device node, it leads to can't find the device node and hung up. In fact only P1020RDB needs to delete the USB2 node, this patch fixes this issue. Signed-off-by: Ying Zhang <b40530(a)freescale.com> --- Change from v1: - To define the parameter "err" to eliminate the compiling error. board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index 3f47cfb..61b7a91 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -428,8 +428,13 @@ int ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; phys_size_t size; +#if defined(CONFIG_P1020RDB_PD) || defined(CONFIG_P1020RDB_PC) const char *soc_usb_compat = "fsl-usb2-dr"; - int err, usb1_off, usb2_off; + int usb_err, usb1_off, usb2_off; +#endif +#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) + int err; +#endif ft_cpu_setup(blob, bd); @@ -473,6 +478,7 @@ int ft_board_setup(void *blob, bd_t *bd) } #endif +#if defined(CONFIG_P1020RDB_PD) || defined(CONFIG_P1020RDB_PC) /* Delete USB2 node as it is muxed with eLBC */ usb1_off = fdt_node_offset_by_compatible(blob, -1, soc_usb_compat); @@ -488,11 +494,12 @@ int ft_board_setup(void *blob, bd_t *bd) soc_usb_compat); return usb2_off; } - err = fdt_del_node(blob, usb2_off); - if (err < 0) { + usb_err = fdt_del_node(blob, usb2_off); + if (usb_err < 0) { printf("WARNING: could not remove %s\n", soc_usb_compat); - return err; + return usb_err; } +#endif return 0; } -- 1.8.4.1

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