July 2015 - U-Boot

[U-Boot] [PATCH v2 0/6] Add support for hi6220 SoC and HiKey 96boards CE board.
by Peter Griffin 29 Jul '15

29 Jul '15

Hi Folks, This series adds support for the first 96boards consumer edition HiKey board. More information can be found about this board at the following link https://www.96boards.org/products/hikey/. This initial port adds support for: - 1) Serial 2) eMMC and sd card 3) USB 4) GPIO It has been tested with Arm Trusted Firmware running u-boot as the BL33 executable. Some instructions on exactly how to compile everything (l-loader, with Arm Trusted Firmware, which then loads u-boot) is documented in the README found in the board/hisilicon/hikey directory. A basic SoC datasheet can be found here: - https://github.com/96boards/documentation/blob/master/hikey/ Hi6220V100_Multi-Mode_Application_Processor_Function_Description.pdf Board schematic can be found here: - https://github.com/96boards/documentation/blob/master/hikey/ 96Boards-Hikey-Rev-A1.pdf A rather pleasant side effect of rebasing to v2015.07-rc2 is that the two main bugs with the v1 series (that I new about at least) are resolved. DHCP now works correctly, and USB mass storage devices are also enumerated). I had a quick look at migrating the gpio driver over to DT like Simon suggested. Currently there is a bug in fdtdec_get_addr() for 64bit platforms which I ran into. See patch from Thierry here http://permalink.gmane.org/gmane.comp.boot-loaders.u-boot/215346 Also I'm not sure on the protocol here, but the DT nodes for the gpio controller aren't yet present in upstream Linux kernel, so I think it would be better to wait until they are, so that u-boot and kernel DT don't diverge. Migrating over to DT at that point should then be fairly trivial. Changes since v1: - Rename vendor to hisilicon not 96boards (Rob) - Get rid of aemv8a vexpress leftover (Rob) - Remove __weak on misc_init_r (Rob) - Remove unnecessary LINUX_BOOT_PARAM_ADDR (Rob) - COUNTER_FREQUENCY in decimal to avoid comment (Rob) - Remove leftover V2M* from vexpress (Rob) - Migrate configs/hikey.h over to use config_distro_defaults.h (Rob) - Remove custom u-boot prompt (Rob) - Enable icache - Remove custom delay function, as mdelay/udelay work fine (Rob) - Update CONFIG_SYS_LOAD_ADDR to 0x80000 (Rob) - Use suggested macro for declaring gpio addresses (Marek) - Zap dead Macros (Marek) - Use calloc instead of malloc (Marek) - Reduce PHYS_RAM by 16Mb to accomodate OPTEE in latest ATF code (Peter) - Rebase on v2015.07-rc2 (Peter) - Add CONFIG_NET=y so that env callbacks work (Peter) - Add a README on how to build / flash u-boot (Simon) kind regards, Peter. Peter Griffin (6): dm: gpio: hi6220: Add a hi6220 GPIO driver model driver. ARM: hi6220: Add register and bitfield definition header files. hi6553: Add register definition and bitfield header for 6553 pmic mmc: hi6220_dw_mmc: Add hi6220 glue code for dw_mmc controller. ARM64: hikey: hi6220: Add u-boot support for the 96boards CE HiKey board. ARM64: hikey: Add a README for this board. arch/arm/Kconfig | 8 + arch/arm/include/asm/arch-hi6220/dwmmc.h | 8 + arch/arm/include/asm/arch-hi6220/gpio.h | 29 ++ arch/arm/include/asm/arch-hi6220/hi6220.h | 324 ++++++++++++++++ .../include/asm/arch-hi6220/hi6220_regs_alwayson.h | 349 +++++++++++++++++ arch/arm/include/asm/arch-hi6220/hi6553.h | 75 ++++ board/hisilicon/hikey/Kconfig | 15 + board/hisilicon/hikey/Makefile | 8 + board/hisilicon/hikey/README | 160 ++++++++ board/hisilicon/hikey/hikey.c | 415 +++++++++++++++++++++ configs/hikey_defconfig | 5 + drivers/gpio/Makefile | 2 + drivers/gpio/hi6220_gpio.c | 95 +++++ drivers/mmc/Makefile | 1 + drivers/mmc/hi6220_dw_mmc.c | 56 +++ include/configs/hikey.h | 168 +++++++++ 16 files changed, 1718 insertions(+) create mode 100644 arch/arm/include/asm/arch-hi6220/dwmmc.h create mode 100644 arch/arm/include/asm/arch-hi6220/gpio.h create mode 100644 arch/arm/include/asm/arch-hi6220/hi6220.h create mode 100644 arch/arm/include/asm/arch-hi6220/hi6220_regs_alwayson.h create mode 100644 arch/arm/include/asm/arch-hi6220/hi6553.h create mode 100644 board/hisilicon/hikey/Kconfig create mode 100644 board/hisilicon/hikey/Makefile create mode 100644 board/hisilicon/hikey/README create mode 100644 board/hisilicon/hikey/hikey.c create mode 100644 configs/hikey_defconfig create mode 100644 drivers/gpio/hi6220_gpio.c create mode 100644 drivers/mmc/hi6220_dw_mmc.c create mode 100644 include/configs/hikey.h -- 1.9.1

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[U-Boot] [PATCH v2 2/4] nand: lpc32xx: add hardware ECC support
by slemieux.tyco＠gmail.com 29 Jul '15

29 Jul '15

From: Sylvain Lemieux <slemieux(a)tycoint.com> Incorporate NAND SLC hardware ECC support from legacy LPCLinux NXP BSP. The code taken from the legacy patch are: - lpc32xx SLC NAND driver (hardware ECC support) - lpc3250 header file missing SLC NAND registers definition The legacy driver code was updated to integrate with the esisting NAND SLC driver. Signed-off-by: Sylvain Lemieux <slemieux(a)tycoint.com> --- Changes from v1 to v2: * Moved the NAND SLC patch as the second patch of the series. * As per discussion on mailing list with Vladimir, incorporate NAND SLC hardware ECC support into the following NAND SLC patch: https://patchwork.ozlabs.org/patch/497308/ * As per discussion on mailing list with Vladimir & Albert, add conditional compile option to build the original NAND SLC code using software ECC for SPL build. * Removed ECC layout for small page NAND from this patch. Update to the legacy code to integrate with the NAND SLC patch: 1) Fixed checkpatch script output in legacy code. 2) Use u-boot API for register access to remove the volatile in register definition taken from "lpc3250.h" header file. 3) Use register definition from the NAND SLC patch. The legacy BSP patch (u-boot-2009.03_lpc32x0-v1.07.patch.tar.bz2) was downloaded from the LPCLinux Web site. drivers/mtd/nand/lpc32xx_nand_slc.c | 337 ++++++++++++++++++++++++++++++++++++ 1 file changed, 337 insertions(+) diff --git a/drivers/mtd/nand/lpc32xx_nand_slc.c b/drivers/mtd/nand/lpc32xx_nand_slc.c index 719a74d..b8b33e3 100644 --- a/drivers/mtd/nand/lpc32xx_nand_slc.c +++ b/drivers/mtd/nand/lpc32xx_nand_slc.c @@ -8,10 +8,25 @@ #include <common.h> #include <nand.h> +#include <linux/mtd/nand_ecc.h> #include <asm/errno.h> #include <asm/io.h> #include <asm/arch/clk.h> #include <asm/arch/sys_proto.h> +#include <asm/arch/dma.h> +#include <asm/arch/cpu.h> + +/* Provide default for ECC size / bytes / OOB size for large page) + * if target did not. */ +#if !defined(CONFIG_SYS_NAND_ECCSIZE) +#define CONFIG_SYS_NAND_ECCSIZE 2048 +#endif +#if !defined(CONFIG_SYS_NAND_ECCBYTES) +#define CONFIG_SYS_NAND_ECCBYTES 24 +#endif +#if !defined(CONFIG_SYS_NAND_OOBSIZE) +#define CONFIG_SYS_NAND_OOBSIZE 64 +#endif struct lpc32xx_nand_slc_regs { u32 data; @@ -33,11 +48,18 @@ struct lpc32xx_nand_slc_regs { /* CFG register */ #define CFG_CE_LOW (1 << 5) +#define SLCCFG_DMA_ECC (1 << 4) /* Enable DMA ECC bit */ +#define SLCCFG_ECC_EN (1 << 3) /* ECC enable bit */ +#define SLCCFG_DMA_BURST (1 << 2) /* DMA burst bit */ +#define SLCCFG_DMA_DIR (1 << 1) /* DMA write(0)/read(1) bit */ /* CTRL register */ #define CTRL_SW_RESET (1 << 2) +#define SLCCTRL_ECC_CLEAR (1 << 1) /* Reset ECC bit */ +#define SLCCTRL_DMA_START (1 << 0) /* Start DMA channel bit */ /* STAT register */ +#define SLCSTAT_DMA_FIFO (1 << 2) /* DMA FIFO has data bit */ #define STAT_NAND_READY (1 << 0) /* INT_STAT register */ @@ -54,6 +76,47 @@ struct lpc32xx_nand_slc_regs { #define TAC_R_HOLD(n) (max_t(uint32_t, (n), 0xF) << 4) #define TAC_R_SETUP(n) (max_t(uint32_t, (n), 0xF) << 0) +/* control register definitions */ +#define DMAC_CHAN_INT_TC_EN (1 << 31) /* channel terminal count interrupt */ +#define DMAC_CHAN_DEST_AUTOINC (1 << 27) /* automatic destination increment */ +#define DMAC_CHAN_SRC_AUTOINC (1 << 26) /* automatic source increment */ +#define DMAC_CHAN_DEST_AHB1 (1 << 25) /* AHB1 master for dest. transfer */ +#define DMAC_CHAN_DEST_WIDTH_32 (1 << 22) /* Destination data width selection */ +#define DMAC_CHAN_SRC_WIDTH_32 (1 << 19) /* Source data width selection */ +#define DMAC_CHAN_DEST_BURST_1 0 +#define DMAC_CHAN_DEST_BURST_4 (1 << 15) /* Destination data burst size */ +#define DMAC_CHAN_SRC_BURST_1 0 +#define DMAC_CHAN_SRC_BURST_4 (1 << 12) /* Source data burst size */ + +/* config_ch register definitions + * DMAC_CHAN_FLOW_D_xxx: flow control with DMA as the controller + * DMAC_DEST_PERIP: Macro for loading destination peripheral + * DMAC_SRC_PERIP: Macro for loading source peripheral */ +#define DMAC_CHAN_FLOW_D_M2P (0x1 << 11) +#define DMAC_CHAN_FLOW_D_P2M (0x2 << 11) +#define DMAC_DEST_PERIP(n) (((n) & 0x1F) << 6) +#define DMAC_SRC_PERIP(n) (((n) & 0x1F) << 1) + +/* config_ch register definitions + * (source and destination peripheral ID numbers). + * These can be used with the DMAC_DEST_PERIP and DMAC_SRC_PERIP macros.*/ +#define DMA_PERID_NAND1 1 + +/* Channel enable bit */ +#define DMAC_CHAN_ENABLE (1 << 0) + +#define NAND_LARGE_BLOCK_PAGE_SIZE 2048 +#define NAND_SMALL_BLOCK_PAGE_SIZE 512 + +#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_SPL_BUILD) +/* DMA Descriptors + * For Large Block: 17 descriptors = ((16 Data and ECC Read) + 1 Spare Area) + * For Small Block: 5 descriptors = ((4 Data and ECC Read) + 1 Spare Area) */ +static dmac_ll_t dmalist[(CONFIG_SYS_NAND_ECCSIZE/256) * 2 + 1]; +static uint32_t ecc_buffer[8]; /* MAX ECC size */ +static int dmachan = -1; +#endif + static struct lpc32xx_nand_slc_regs __iomem *lpc32xx_nand_slc_regs = (struct lpc32xx_nand_slc_regs __iomem *)SLC_NAND_BASE; @@ -108,10 +171,255 @@ static int lpc32xx_nand_dev_ready(struct mtd_info *mtd) return readl(&lpc32xx_nand_slc_regs->stat) & STAT_NAND_READY; } +#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_SPL_BUILD) +/* Prepares DMA descriptors for NAND RD/WR operations */ +/* If the size is < 256 Bytes then it is assumed to be + * an OOB transfer */ +static void lpc32xx_nand_dma_configure(struct nand_chip *chip, + const void *buffer, int size, int read) +{ + uint32_t i, dmasrc, ctrl, ecc_ctrl, oob_ctrl, dmadst; + void __iomem *base = chip->IO_ADDR_R; + uint32_t *ecc_gen = ecc_buffer; + + /* CTRL descriptor entry for reading ECC + * Copy Multiple times to sync DMA with Flash Controller + */ + ecc_ctrl = (0x5 | + DMAC_CHAN_SRC_BURST_1 | + DMAC_CHAN_DEST_BURST_1 | + DMAC_CHAN_SRC_WIDTH_32 | + DMAC_CHAN_DEST_WIDTH_32 | + DMAC_CHAN_DEST_AHB1); + + /* CTRL descriptor entry for reading/writing Data */ + ctrl = 64 | /* 256/4 */ + DMAC_CHAN_SRC_BURST_4 | + DMAC_CHAN_DEST_BURST_4 | + DMAC_CHAN_SRC_WIDTH_32 | + DMAC_CHAN_DEST_WIDTH_32 | + DMAC_CHAN_DEST_AHB1; + + /* CTRL descriptor entry for reading/writing Spare Area */ + oob_ctrl = ((CONFIG_SYS_NAND_OOBSIZE / 4) | + DMAC_CHAN_SRC_BURST_4 | + DMAC_CHAN_DEST_BURST_4 | + DMAC_CHAN_SRC_WIDTH_32 | + DMAC_CHAN_DEST_WIDTH_32 | + DMAC_CHAN_DEST_AHB1); + + if (read) { + dmasrc = (uint32_t)(base + + offsetof(struct lpc32xx_nand_slc_regs, + dma_data)); + dmadst = (uint32_t)(buffer); + ctrl |= DMAC_CHAN_DEST_AUTOINC; + } else { + dmadst = (uint32_t)(base + + offsetof(struct lpc32xx_nand_slc_regs, + dma_data)); + dmasrc = (uint32_t)(buffer); + ctrl |= DMAC_CHAN_SRC_AUTOINC; + } + + /* + * Write Operation Sequence for Small Block NAND + * ---------------------------------------------------------- + * 1. X'fer 256 bytes of data from Memory to Flash. + * 2. Copy generated ECC data from Register to Spare Area + * 3. X'fer next 256 bytes of data from Memory to Flash. + * 4. Copy generated ECC data from Register to Spare Area. + * 5. X'fer 16 byets of Spare area from Memory to Flash. + * Read Operation Sequence for Small Block NAND + * ---------------------------------------------------------- + * 1. X'fer 256 bytes of data from Flash to Memory. + * 2. Copy generated ECC data from Register to ECC calc Buffer. + * 3. X'fer next 256 bytes of data from Flash to Memory. + * 4. Copy generated ECC data from Register to ECC calc Buffer. + * 5. X'fer 16 bytes of Spare area from Flash to Memory. + * Write Operation Sequence for Large Block NAND + * ---------------------------------------------------------- + * 1. Steps(1-4) of Write Operations repeate for four times + * which generates 16 DMA descriptors to X'fer 2048 bytes of + * data & 32 bytes of ECC data. + * 2. X'fer 64 bytes of Spare area from Memory to Flash. + * Read Operation Sequence for Large Block NAND + * ---------------------------------------------------------- + * 1. Steps(1-4) of Read Operations repeate for four times + * which generates 16 DMA descriptors to X'fer 2048 bytes of + * data & 32 bytes of ECC data. + * 2. X'fer 64 bytes of Spare area from Flash to Memory. + */ + + for (i = 0; i < size/256; i++) { + dmalist[i*2].dma_src = (read ? (dmasrc) : (dmasrc + (i*256))); + dmalist[i*2].dma_dest = (read ? (dmadst + (i*256)) : dmadst); + dmalist[i*2].next_lli = (uint32_t)&dmalist[(i*2)+1]; + dmalist[i*2].next_ctrl = ctrl; + + dmalist[(i*2) + 1].dma_src = + (uint32_t)(base + offsetof(struct lpc32xx_nand_slc_regs, + ecc)); + dmalist[(i*2) + 1].dma_dest = (uint32_t)&ecc_gen[i]; + dmalist[(i*2) + 1].next_lli = (uint32_t)&dmalist[(i*2)+2]; + dmalist[(i*2) + 1].next_ctrl = ecc_ctrl; + } + + if (i) { /* Data only transfer */ + dmalist[(i*2) - 1].next_lli = 0; + dmalist[(i*2) - 1].next_ctrl |= DMAC_CHAN_INT_TC_EN; + return; + } + + /* OOB only transfer */ + if (read) { + dmasrc = (uint32_t)(base + + offsetof(struct lpc32xx_nand_slc_regs, + dma_data)); + dmadst = (uint32_t)(buffer); + oob_ctrl |= DMAC_CHAN_DEST_AUTOINC; + } else { + dmadst = (uint32_t)(base + + offsetof(struct lpc32xx_nand_slc_regs, + dma_data)); + dmasrc = (uint32_t)(buffer); + oob_ctrl |= DMAC_CHAN_SRC_AUTOINC; + } + + /* Read/ Write Spare Area Data To/From Flash */ + dmalist[i*2].dma_src = dmasrc; + dmalist[i*2].dma_dest = dmadst; + dmalist[i*2].next_lli = 0; + dmalist[i*2].next_ctrl = (oob_ctrl | DMAC_CHAN_INT_TC_EN); +} + +static void lpc32xx_nand_xfer(struct mtd_info *mtd, const u_char *buf, + int len, int read) +{ + struct nand_chip *chip = mtd->priv; + uint32_t config; + + /* DMA Channel Configuration */ + config = (read ? DMAC_CHAN_FLOW_D_P2M : DMAC_CHAN_FLOW_D_M2P) | + (read ? DMAC_DEST_PERIP(0) : DMAC_DEST_PERIP(DMA_PERID_NAND1)) | + (read ? DMAC_SRC_PERIP(DMA_PERID_NAND1) : DMAC_SRC_PERIP(0)) | + DMAC_CHAN_ENABLE; + + /* Prepare DMA descriptors */ + lpc32xx_nand_dma_configure(chip, buf, len, read); + + /* Setup SLC controller and start transfer */ + if (read) + setbits_le32(&lpc32xx_nand_slc_regs->cfg, SLCCFG_DMA_DIR); + else /* NAND_ECC_WRITE */ + clrbits_le32(&lpc32xx_nand_slc_regs->cfg, SLCCFG_DMA_DIR); + setbits_le32(&lpc32xx_nand_slc_regs->cfg, SLCCFG_DMA_BURST); + + /* Write length for new transfers */ + if (!((readl(&lpc32xx_nand_slc_regs->stat) & SLCSTAT_DMA_FIFO) | + readl(&lpc32xx_nand_slc_regs->tc))) { + int tmp = (len != mtd->oobsize) ? mtd->oobsize : 0; + writel(len + tmp, &lpc32xx_nand_slc_regs->tc); + } + + setbits_le32(&lpc32xx_nand_slc_regs->ctrl, SLCCTRL_DMA_START); + + /* Start DMA transfers */ + lpc32xx_dma_start_xfer(dmachan, dmalist, config); + + /* Wait for NAND to be ready */ + while (!lpc32xx_nand_dev_ready(mtd)) + ; + + /* Wait till DMA transfer is DONE */ + if (lpc32xx_dma_wait_status(dmachan)) + pr_err("NAND DMA transfer error!\r\n"); + + /* Stop DMA & HW ECC */ + clrbits_le32(&lpc32xx_nand_slc_regs->ctrl, SLCCTRL_DMA_START); + clrbits_le32(&lpc32xx_nand_slc_regs->cfg, + SLCCFG_DMA_DIR | SLCCFG_DMA_BURST | + SLCCFG_ECC_EN | SLCCFG_DMA_ECC); +} + +static uint32_t slc_ecc_copy_to_buffer(uint8_t *spare, const uint32_t *ecc, + int count) +{ + int i; + for (i = 0; i < (count * 3); i += 3) { + uint32_t ce = ecc[i/3]; + ce = ~(ce << 2) & 0xFFFFFF; + spare[i+2] = (uint8_t)(ce & 0xFF); ce >>= 8; + spare[i+1] = (uint8_t)(ce & 0xFF); ce >>= 8; + spare[i] = (uint8_t)(ce & 0xFF); + } + return 0; +} + +static int lpc32xx_ecc_calculate(struct mtd_info *mtd, const uint8_t *dat, + uint8_t *ecc_code) +{ + return slc_ecc_copy_to_buffer(ecc_code, ecc_buffer, + CONFIG_SYS_NAND_ECCSIZE + == NAND_LARGE_BLOCK_PAGE_SIZE ? 8 : 2); +} + +/* Enables and prepares SLC NAND controller + * for doing data transfers with H/W ECC enabled. + */ +static void lpc32xx_hwecc_enable(struct mtd_info *mtd, int mode) +{ + /* Clear ECC */ + writel(SLCCTRL_ECC_CLEAR, &lpc32xx_nand_slc_regs->ctrl); + + /* Setup SLC controller for H/W ECC operations */ + setbits_le32(&lpc32xx_nand_slc_regs->cfg, + SLCCFG_ECC_EN | SLCCFG_DMA_ECC); +} + +/** + * lpc32xx_correct_data - [NAND Interface] Detect and correct bit error(s) + * mtd: MTD block structure + * dat: raw data read from the chip + * read_ecc: ECC from the chip + * calc_ecc: the ECC calculated from raw data + * + * Detect and correct a 1 bit error for 256 byte block + * + */ +int lpc32xx_correct_data(struct mtd_info *mtd, u_char *dat, + u_char *read_ecc, u_char *calc_ecc) +{ + uint8_t i, nb_ecc256; + int ret1, ret2 = 0; + u_char *r = read_ecc; + u_char *c = calc_ecc; + uint16_t data_offset = 0; + + nb_ecc256 = (CONFIG_SYS_NAND_ECCSIZE == NAND_LARGE_BLOCK_PAGE_SIZE + ? 8 : 2); + + for (i = 0 ; i < nb_ecc256 ; i++ , r += 3, c += 3, data_offset += 256) { + ret1 = nand_correct_data(mtd, dat + data_offset, r, c); + + if (ret1 < 0) + return -EBADMSG; + else + ret2 += ret1; + } + + return ret2; +} +#endif + static void lpc32xx_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) { +#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_SPL_BUILD) + lpc32xx_nand_xfer(mtd, buf, len, 1); +#else while (len-- > 0) *buf++ = readl(&lpc32xx_nand_slc_regs->data); +#endif } static uint8_t lpc32xx_read_byte(struct mtd_info *mtd) @@ -121,8 +429,12 @@ static uint8_t lpc32xx_read_byte(struct mtd_info *mtd) static void lpc32xx_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) { +#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_SPL_BUILD) + lpc32xx_nand_xfer(mtd, buf, len, 0); +#else while (len-- > 0) writel(*buf++, &lpc32xx_nand_slc_regs->data); +#endif } static void lpc32xx_write_byte(struct mtd_info *mtd, uint8_t byte) @@ -137,15 +449,30 @@ static void lpc32xx_write_byte(struct mtd_info *mtd, uint8_t byte) */ int board_nand_init(struct nand_chip *lpc32xx_chip) { +#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_SPL_BUILD) + /* Acquire a channel for our use */ + dmachan = lpc32xx_dma_get_channel(); + if (unlikely(dmachan < 0)) { + pr_info("Unable to get free DMA channel for NAND transfers\n"); + return -1; + } +#endif + lpc32xx_chip->cmd_ctrl = lpc32xx_nand_cmd_ctrl; lpc32xx_chip->dev_ready = lpc32xx_nand_dev_ready; +#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_SPL_BUILD) + /* Hardware ECC calculation is supported when + * DMA driver is selected. */ + lpc32xx_chip->ecc.mode = NAND_ECC_HW; +#else /* * Hardware ECC calculation is not supported by the driver, * because it requires DMA support, see LPC32x0 User Manual, * note after SLC_ECC register description (UM10326, p.198) */ lpc32xx_chip->ecc.mode = NAND_ECC_SOFT; +#endif /* * The implementation of these functions is quite common, but @@ -157,12 +484,22 @@ int board_nand_init(struct nand_chip *lpc32xx_chip) lpc32xx_chip->write_buf = lpc32xx_write_buf; lpc32xx_chip->write_byte = lpc32xx_write_byte; +#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_SPL_BUILD) + lpc32xx_chip->ecc.calculate = lpc32xx_ecc_calculate; + lpc32xx_chip->ecc.correct = lpc32xx_correct_data; + lpc32xx_chip->ecc.hwctl = lpc32xx_hwecc_enable; + lpc32xx_chip->chip_delay = 2000; + + lpc32xx_chip->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES; + lpc32xx_chip->ecc.size = CONFIG_SYS_NAND_ECCSIZE; +#else /* * Use default ECC layout, but these values are predefined * for both small and large page NAND flash devices. */ lpc32xx_chip->ecc.size = 256; lpc32xx_chip->ecc.bytes = 3; +#endif lpc32xx_chip->ecc.strength = 1; #if defined(CONFIG_SYS_NAND_USE_FLASH_BBT) -- 1.8.3.1

4 3

[U-Boot] [PATCH v2 1/4] dma: lpc32xx: add DMA driver
by slemieux.tyco＠gmail.com 29 Jul '15

29 Jul '15

From: Sylvain Lemieux <slemieux(a)tycoint.com> Incorporate DMA driver from legacy LPCLinux NXP BSP. The files taken from the legacy patch are: - lpc32xx DMA driver - lpc3250 header file DMA registers definition. The legacy driver was updated to integrate with the latest u-boot. Signed-off-by: Sylvain Lemieux <slemieux(a)tycoint.com> --- Changes from v1 to v2: * Moved the DMA patch as the first patch of the series. * The NAND SLC patch (link below) is applied before this patch: https://patchwork.ozlabs.org/patch/497308/ Update to the legacy driver to integrate with the latest u-boot: 1) Fixed checkpatch script output in legacy code. 2) Use LPC32xx definition from "cpu.h" and "clk.h". 3) Incorporate DMA specific register definition from "lpc3250.h" header file from legacy BSP patch from LPCLinux. 4) Use u-boot API for register access to remove the volatile in register definition taken from "lpc3250.h" header file. 5) Add DMA interface to "dma.h". 6) Add dma clock control register bits (clk.h). 7) Add functions to initialize the DMA clock. The legacy BSP patch (u-boot-2009.03_lpc32x0-v1.07.patch.tar.bz2) was downloaded from the LPCLinux Web site. arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 6 + arch/arm/include/asm/arch-lpc32xx/clk.h | 3 + arch/arm/include/asm/arch-lpc32xx/dma.h | 33 ++++++ arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 1 + drivers/dma/Makefile | 1 + drivers/dma/lpc32xx_dma.c | 153 ++++++++++++++++++++++++++ 6 files changed, 197 insertions(+) create mode 100644 arch/arm/include/asm/arch-lpc32xx/dma.h create mode 100644 drivers/dma/lpc32xx_dma.c diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c index c0c9c6c..0d2ef7a 100644 --- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c +++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c @@ -65,6 +65,12 @@ void lpc32xx_slc_nand_init(void) writel(CLK_NAND_SLC | CLK_NAND_SLC_SELECT, &clk->flashclk_ctrl); } +void lpc32xx_dma_init(void) +{ + /* Enable DMA interface */ + setbits_le32(&clk->dmaclk_ctrl, DMA_CLK_ENABLE); +} + void lpc32xx_i2c_init(unsigned int devnum) { /* Enable I2C interface */ diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h b/arch/arm/include/asm/arch-lpc32xx/clk.h index 010211a..663f6bc 100644 --- a/arch/arm/include/asm/arch-lpc32xx/clk.h +++ b/arch/arm/include/asm/arch-lpc32xx/clk.h @@ -158,6 +158,9 @@ struct clk_pm_regs { #define CLK_NAND_SLC_SELECT (1 << 2) #define CLK_NAND_MLC_INT (1 << 5) +/* DMA Clock Control Register bits */ +#define DMA_CLK_ENABLE (1 << 0) + /* SSP Clock Control Register bits */ #define CLK_SSP0_ENABLE_CLOCK (1 << 0) diff --git a/arch/arm/include/asm/arch-lpc32xx/dma.h b/arch/arm/include/asm/arch-lpc32xx/dma.h new file mode 100644 index 0000000..7b467a2 --- /dev/null +++ b/arch/arm/include/asm/arch-lpc32xx/dma.h @@ -0,0 +1,33 @@ +/* + * LPC32xx DMA Controller Interface + * + * Copyright (C) 2008-2015 by NXP Semiconductors + * All rights reserved. + * + * @Author: Kevin Wells + * @Descr: Definitions for LPC3250 chip + * @References: NXP LPC3250 User's Guide + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _LPC32XX_DMA_H +#define _LPC32XX_DMA_H + +#include <common.h> + +/* DMA linked list structure used with a channel's LLI register */ +typedef struct +{ + volatile uint32_t dma_src; + volatile uint32_t dma_dest; + volatile uint32_t next_lli; + volatile uint32_t next_ctrl; +} dmac_ll_t; + +int lpc32xx_dma_get_channel(void); +int lpc32xx_dma_start_xfer(int channel, const dmac_ll_t *desc, uint32_t config); +int lpc32xx_dma_wait_status(int channel); +void lpc32xx_dma_put_channel(int channel); + +#endif /* _LPC32XX_DMA_H */ diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h index 0845f83..7f997d9 100644 --- a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h +++ b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h @@ -13,6 +13,7 @@ void lpc32xx_uart_init(unsigned int uart_id); void lpc32xx_mac_init(void); void lpc32xx_mlc_nand_init(void); void lpc32xx_slc_nand_init(void); +void lpc32xx_dma_init(void); void lpc32xx_i2c_init(unsigned int devnum); void lpc32xx_ssp_init(void); #if defined(CONFIG_SPL_BUILD) diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index 4c8fcc2..f95fe70 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -10,3 +10,4 @@ obj-$(CONFIG_APBH_DMA) += apbh_dma.o obj-$(CONFIG_FSL_DMA) += fsl_dma.o obj-$(CONFIG_TI_KSNAV) += keystone_nav.o keystone_nav_cfg.o obj-$(CONFIG_TI_EDMA3) += ti-edma3.o +obj-$(CONFIG_DMA_LPC32XX) += lpc32xx_dma.o diff --git a/drivers/dma/lpc32xx_dma.c b/drivers/dma/lpc32xx_dma.c new file mode 100644 index 0000000..feb16ce --- /dev/null +++ b/drivers/dma/lpc32xx_dma.c @@ -0,0 +1,153 @@ +/* + * Copyright (C) 2008-2015 by NXP Semiconductors + * All rights reserved. + * + * @Author: Kevin Wells + * @Descr: LPC3250 DMA controller interface support functions + * + * See file CREDITS for list of people who contributed to this + * project. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/dma.h> +#include <asm/arch/cpu.h> +#include <asm/arch/clk.h> +#include <asm/arch/sys_proto.h> +#include <asm/io.h> + +/* Some optimization stuff */ +#ifndef unlikely +#define likely(x) __builtin_expect(!!(x), 1) +#define unlikely(x) __builtin_expect(!!(x), 0) +#endif + +/* bit position macro */ +#define _BIT(n) (0x1 << (n)) + +/* DMA controller channel register structure */ +struct dmac_chan_reg { + uint32_t src_addr; + uint32_t dest_addr; + uint32_t lli; + uint32_t control; + uint32_t config_ch; + uint32_t reserved[3]; +}; + +/* DMA controller register structures */ +struct dma_reg { + uint32_t int_stat; + uint32_t int_tc_stat; + uint32_t int_tc_clear; + uint32_t int_err_stat; + uint32_t int_err_clear; + uint32_t raw_tc_stat; + uint32_t raw_err_stat; + uint32_t chan_enable; + uint32_t sw_burst_req; + uint32_t sw_single_req; + uint32_t sw_last_burst_req; + uint32_t sw_last_single_req; + uint32_t config; + uint32_t sync; + uint32_t reserved[50]; + struct dmac_chan_reg dma_chan[8]; +}; + +/* Macro pointing to DMA registers */ +#define DMA_NO_OF_CHANNELS 8 + +/* config register definitions */ +#define DMAC_CTRL_ENABLE (1 << 0) /* For enabling the DMA controller */ + +static uint32_t alloc_ch; + +static struct dma_reg *dma = (struct dma_reg *)DMA_BASE; + +int lpc32xx_dma_get_channel(void) +{ + int i; + uint32_t status = 0; + + if (!alloc_ch) { /* First time caller */ + /* DMA clock are enable by "lpc32xx_dma_init()" and should + * be call by board "board_early_init_f()" function. */ + + /* Make sure DMA controller and all channels are disabled. + * Controller is in little-endian mode. Disable sync signals */ + writel(0, &dma->config); + writel(0, &dma->sync); + + /* Clear interrupt and error statuses */ + writel(0xFF, &dma->int_tc_clear); + writel(0xFF, &dma->raw_tc_stat); + writel(0xFF, &dma->int_err_clear); + writel(0xFF, &dma->raw_err_stat); + + /* Enable DMA controller */ + writel(DMAC_CTRL_ENABLE, &dma->config); + } + + for (i = 0; i < DMA_NO_OF_CHANNELS && (status & _BIT(i)); i++) + ; + + /* Check if all the available channles are busy */ + if (unlikely(i == DMA_NO_OF_CHANNELS)) + return -1; + alloc_ch |= _BIT(i); + return i; +} + +int lpc32xx_dma_start_xfer(int channel, const dmac_ll_t *desc, uint32_t config) +{ + if (unlikely((_BIT(channel) & alloc_ch) == 0)) { + printf("ERR: Request for xfer on unallocated channel %d\r\n", + channel); + BUG(); + } + writel(_BIT(channel), &dma->int_tc_clear); + writel(_BIT(channel), &dma->int_err_clear); + writel(desc->dma_src, &dma->dma_chan[channel].src_addr); + writel(desc->dma_dest, &dma->dma_chan[channel].dest_addr); + writel(desc->next_lli, &dma->dma_chan[channel].lli); + writel(desc->next_ctrl, &dma->dma_chan[channel].control); + writel(config, &dma->dma_chan[channel].config_ch); + + return 0; +} + +int lpc32xx_dma_wait_status(int channel) +{ + while (((readl(&dma->raw_tc_stat) | readl(dma->raw_err_stat)) + & _BIT(channel)) == 0) + ; + + if (unlikely(readl(&dma->raw_err_stat) & _BIT(channel))) { + setbits_le32(&dma->int_err_clear, _BIT(channel)); + setbits_le32(&dma->raw_err_stat, _BIT(channel)); + return -1; + } + setbits_le32(&dma->int_tc_clear, _BIT(channel)); + setbits_le32(&dma->raw_tc_stat, _BIT(channel)); + return 0; +} + +void lpc32xx_dma_put_channel(int channel) +{ + /* Check if given channel no is valid */ + if (channel >= DMA_NO_OF_CHANNELS || channel < 0) + return; + alloc_ch &= ~_BIT(channel); + + /* Shut down channel */ + writel(0, &dma->dma_chan[channel].control); + writel(0, &dma->dma_chan[channel].config_ch); + clrbits_le32(&dma->sync, _BIT(channel)); + + if (!alloc_ch) + /* Disable DMA controller */ + clrbits_le32(&dma->config, DMAC_CTRL_ENABLE); +} -- 1.8.3.1

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[U-Boot] [PATCH] mpc85xx/T104xRDB: Remove vbank check redundant code
by Priyanka Jain 29 Jul '15

29 Jul '15

sw variable in checkboard function is storing vbank value which can only take 4-bit value. So check of sw value for if greater than 7 is redundant. Signed-off-by: Priyanka Jain <Priyanka.Jain(a)freescale.com> --- board/freescale/t104xrdb/t104xrdb.c | 5 +---- 1 files changed, 1 insertions(+), 4 deletions(-) diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c index 9cd5e15..c34eea6 100644 --- a/board/freescale/t104xrdb/t104xrdb.c +++ b/board/freescale/t104xrdb/t104xrdb.c @@ -35,10 +35,7 @@ int checkboard(void) sw = CPLD_READ(flash_ctl_status); sw = ((sw & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT); - if (sw <= 7) - printf("vBank: %d\n", sw); - else - printf("Unsupported Bank=%x\n", sw); + printf("vBank: %d\n", sw); return 0; } -- 1.7.4.1

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[U-Boot] [PATCH v2 3/4] nand: lpc32xx: add ECC layout for small page NAND
by slemieux.tyco＠gmail.com 29 Jul '15

29 Jul '15

From: Sylvain Lemieux <slemieux(a)tycoint.com> Incorporate ECC layout for small page NAND from legacy LPCLinux NXP BSP. The code taken from the legacy patch is: - lpc32xx SLC NAND driver (ECC layout for small page) This layout is matching the lpc32xx NAND SLC Kernel driver: https://git.kernel.org/cgit/linux/kernel/git/stable/linux-stable.git/tree/d… Signed-off-by: Sylvain Lemieux <slemieux(a)tycoint.com> --- Changes from v1 to v2: * Move ECC layout for small page NAND into a separate patch. The legacy BSP patch (u-boot-2009.03_lpc32x0-v1.07.patch.tar.bz2) was downloaded from the LPCLinux Web site. drivers/mtd/nand/lpc32xx_nand_slc.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/mtd/nand/lpc32xx_nand_slc.c b/drivers/mtd/nand/lpc32xx_nand_slc.c index b8b33e3..14f66dd 100644 --- a/drivers/mtd/nand/lpc32xx_nand_slc.c +++ b/drivers/mtd/nand/lpc32xx_nand_slc.c @@ -108,6 +108,19 @@ struct lpc32xx_nand_slc_regs { #define NAND_LARGE_BLOCK_PAGE_SIZE 2048 #define NAND_SMALL_BLOCK_PAGE_SIZE 512 +/* NAND ECC Layout for small page NAND devices + * Note: For large page devices, the default layouts are used. */ +static struct nand_ecclayout lpc32xx_nand_oob_16 = { + .eccbytes = 6, + .eccpos = {10, 11, 12, 13, 14, 15}, + .oobfree = { + {.offset = 0, + . length = 4}, + {.offset = 6, + . length = 4} + } +}; + #if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_SPL_BUILD) /* DMA Descriptors * For Large Block: 17 descriptors = ((16 Data and ECC Read) + 1 Spare Area) @@ -502,6 +515,9 @@ int board_nand_init(struct nand_chip *lpc32xx_chip) #endif lpc32xx_chip->ecc.strength = 1; + if (CONFIG_SYS_NAND_ECCSIZE != NAND_LARGE_BLOCK_PAGE_SIZE) + lpc32xx_chip->ecc.layout = &lpc32xx_nand_oob_16; + #if defined(CONFIG_SYS_NAND_USE_FLASH_BBT) lpc32xx_chip->bbt_options |= NAND_BBT_USE_FLASH; #endif -- 1.8.3.1

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[U-Boot] [PATCH v2 0/4] lpc32xx: add legacy NXP BSP drivers
by slemieux.tyco＠gmail.com 29 Jul '15

29 Jul '15

From: Sylvain Lemieux <slemieux(a)tycoint.com> This series of patches bring the legacy NXP LPC32xx BSP drivers SLC NAND (hardware ECC), DMA & USB into the latest u-boot. Refer to each individual patches for details on the change done to integrate the driver into the latest u-boot. The legacy BSP patch (u-boot-2009.03_lpc32x0-v1.07.patch.tar.bz2) was downloaded from the LPCLinux Web site. The patch adding the LPC32xx MAC and SMSC RMII phy support should be applied first: - http://patchwork.ozlabs.org/patch/489100/ - http://patchwork.ozlabs.org/patch/489190/ - http://patchwork.ozlabs.org/patch/491419/ - http://patchwork.ozlabs.org/patch/491420/ The SLC NAND patch should be applied after: - https://patchwork.ozlabs.org/patch/497308/ The patch modifying the I2C to use the HCLK get API function should be applied after the SLC NAND patch: - https://patchwork.ozlabs.org/patch/500511/ The NAND driver was only tested for large page NAND. Potential test opportunity for small page NAND: - Since the equivalent of the legacy NXP BSP drivers are available (NAND SLC / DMA / Ethernet / USB), it will be nice if somebody using the PHY3250 development board can test small pafe NAND. - The remaining porting work to the latest u-boot include the migration of the board & configuration files. Changes from v1 to v2: * Moved the DMA patch as the first patch of the series and the NAND SLC patch as thesecond one. * As per discussion on mailing list with Vladimir, incorporate NAND SLC hardware ECC support into the following NAND SLC patch: https://patchwork.ozlabs.org/patch/497308/ * As per discussion on mailing list with Vladimir & Albert, add conditional compile option to build the original NAND SLC code using software ECC for SPL build. * Moved ECC layout for small page NAND in a separate patch. * Addressed Marek's comments on LPC32xx USB driver: - use "get_timer()" to handle timeout. - Split USB and I2C driver. * Updated LPC32xx I2C driver to support the I2C that is part of the USB module. * Removed ISP1301 USB transceiver I2C registers definition that are not used. * For the USB driver, use "cpu" initialization & stop functions API instead of the "board" API. Note: I am sending the patches using <slemieux.tyco(a)gmail.com>, until I can submit patch using my regular e-mail <slemieux(a)tycoint.com>. Sylvain Lemieux (4): dma: lpc32xx: add DMA driver nand: lpc32xx: add hardware ECC support nand: lpc32xx: add ECC layout for small page NAND usb: lpc32xx: add host USB driver arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 6 + arch/arm/include/asm/arch-lpc32xx/clk.h | 15 ++ arch/arm/include/asm/arch-lpc32xx/dma.h | 33 +++ arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 1 + drivers/dma/Makefile | 1 + drivers/dma/lpc32xx_dma.c | 153 +++++++++++ drivers/i2c/lpc32xx_i2c.c | 21 +- drivers/mtd/nand/lpc32xx_nand_slc.c | 351 ++++++++++++++++++++++++++ drivers/usb/host/Makefile | 1 + drivers/usb/host/ohci-lpc32xx.c | 245 ++++++++++++++++++ 10 files changed, 823 insertions(+), 4 deletions(-) create mode 100644 arch/arm/include/asm/arch-lpc32xx/dma.h create mode 100644 drivers/dma/lpc32xx_dma.c create mode 100644 drivers/usb/host/ohci-lpc32xx.c -- 1.8.3.1

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[U-Boot] Please pull u-boot-x86
by Simon Glass 29 Jul '15

29 Jul '15

Hi Tom, Here are some more PCI driver model improvements and better interrupt support on x86. The following changes since commit 66d10c18bf2c34698362b6fe1891bcc6e8755243: Merge branch 'zynq' of git://www.denx.de/git/u-boot-microblaze (2015-07-28 11:31:21 -0400) are available in the git repository at: git://git.denx.de/u-boot-x86.git for you to fetch changes up to 488d19cbcace0b87a2d08881eab7356088198903: patman: add distutils based installer (2015-07-28 10:36:25 -0600) ---------------------------------------------------------------- Bin Meng (20): x86: Display correct CS/EIP/EFLAGS when there is an error code x86: Simplify architecture defined exception handling in irq_llsr() x86: Change pci option rom area MTRR setting to cacheable x86: Enable DM RTC support for all x86 boards x86: pci: Assign pci irqs to all functions x86: pci: Do not assign irq 0 to pci device buildman: Correct '--fetch-arch' command documentation Fix incorrect comments in linker_lists.h dm: pci: Correct primary/secondary/subordinate bus number assignment dm: pci: Use complete bdf in all pci config read/write routines dm: pci: Pass only device/function to pci_bus_find_devfn() dm: pci: Support bridge device configuration correctly x86: Convert to use driver model pci on queensbay/crownbay x86: mpspec: Allow platform to determine how PIRQ is connected to I/O APIC x86: mpspec: Move writing ISA interrupt entry after PCI x86: qemu: Enable I/O APIC chip select on PIIX3 x86: Allow cpu-x86 driver to be probed for UP x86: qemu: Enable writing MP table x86: qemu: Turn on PCIe ECAM address range decoding on Q35 x86: Reserve PCIe ECAM address range in the E820 table Chris Packham (1): patman: add distutils based installer arch/x86/Kconfig | 10 ++++ arch/x86/cpu/cpu.c | 36 ++++++++++++--- arch/x86/cpu/interrupts.c | 180 ++++++++++++++++++++++++++++++------------------------------------------ arch/x86/cpu/ivybridge/lpc.c | 1 - arch/x86/cpu/ivybridge/sdram.c | 32 +++++++++---- arch/x86/cpu/pci.c | 29 ++++++++---- arch/x86/cpu/qemu/pci.c | 45 ++++++++++++++++-- arch/x86/cpu/queensbay/Makefile | 1 - arch/x86/cpu/queensbay/tnc.c | 5 -- arch/x86/cpu/queensbay/tnc_pci.c | 46 ------------------- arch/x86/dts/chromebook_link.dts | 1 + arch/x86/dts/chromebox_panther.dts | 1 + arch/x86/dts/crownbay.dts | 6 ++- arch/x86/dts/galileo.dts | 1 + arch/x86/dts/minnowmax.dts | 1 + arch/x86/dts/qemu-x86_i440fx.dts | 13 ++++++ arch/x86/dts/qemu-x86_q35.dts | 13 ++++++ arch/x86/dts/rtc.dtsi | 1 + arch/x86/include/asm/arch-qemu/qemu.h | 10 +++- arch/x86/include/asm/interrupt.h | 24 ++++++++++ arch/x86/include/asm/mpspec.h | 17 +++++++ arch/x86/include/asm/mtrr.h | 2 + arch/x86/include/asm/pci.h | 3 +- arch/x86/include/asm/ptrace.h | 16 +++++-- arch/x86/lib/fsp/fsp_dram.c | 6 +++ arch/x86/lib/mpspec.c | 50 +++++++++++++++----- arch/x86/lib/pirq_routing.c | 3 +- arch/x86/lib/zimage.c | 5 +- configs/chromebook_link_defconfig | 1 + configs/chromebox_panther_defconfig | 1 + configs/crownbay_defconfig | 1 + configs/galileo_defconfig | 1 + configs/minnowmax_defconfig | 1 + configs/qemu-x86_defconfig | 4 ++ drivers/pci/pci-uclass.c | 62 ++++++++++++------------- drivers/pci/pci_auto.c | 75 +++++++++++++++++++++++++----- drivers/pci/pci_common.c | 7 ++- include/linker_lists.h | 20 ++++---- tools/buildman/README | 4 +- tools/patman/README | 11 +++++ tools/patman/__init__.py | 3 ++ tools/patman/patman.py | 20 ++++---- tools/patman/setup.py | 13 ++++++ 43 files changed, 506 insertions(+), 276 deletions(-) delete mode 100644 arch/x86/cpu/queensbay/tnc_pci.c create mode 100644 tools/patman/__init__.py create mode 100644 tools/patman/setup.py Regards, Simon

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[U-Boot] [PATCH v2] x86: baytrail: Configure FSP UPD from device tree
by andrew＠bradfordembedded.com 29 Jul '15

29 Jul '15

From: Andrew Bradford <andrew.bradford(a)kodakalaris.com> Allow for configuration of FSP UPD from the device tree which will override any settings which the FSP was built with itself if the device tree settings exist, otherwise simply trust the FSP's defaults. Modifies the MinnowMax board to transfer the FSP UPD hard-coded settings to the MinnowMax dts. Signed-off-by: Andrew Bradford <andrew.bradford(a)kodakalaris.com> --- Changes from v1: - Use "-" rather than "_" in dt property names. - Use "Bay Trail" for the formal name of the Intel product family. - Use an "fsp," prefix for dt property names for clarity. - Fix minor code indentation issues. - Create a dt subnode for the memory-down-params. - Clarify documentation that dt overrides the FSP's config, so we don't use booleans. arch/x86/cpu/baytrail/fsp_configs.c | 188 +++++++++++++++++---- arch/x86/dts/minnowmax.dts | 30 ++++ .../misc/intel,baytrail-fsp.txt | 119 +++++++++++++ include/fdtdec.h | 2 + lib/fdtdec.c | 2 + 5 files changed, 311 insertions(+), 30 deletions(-) create mode 100644 doc/device-tree-bindings/misc/intel,baytrail-fsp.txt diff --git a/arch/x86/cpu/baytrail/fsp_configs.c b/arch/x86/cpu/baytrail/fsp_configs.c index 86b6926..fce76e6 100644 --- a/arch/x86/cpu/baytrail/fsp_configs.c +++ b/arch/x86/cpu/baytrail/fsp_configs.c @@ -1,14 +1,18 @@ /* * Copyright (C) 2013, Intel Corporation * Copyright (C) 2014, Bin Meng <bmeng.cn(a)gmail.com> + * Copyright (C) 2015, Kodak Alaris, Inc * * SPDX-License-Identifier: Intel */ #include <common.h> +#include <fdtdec.h> #include <asm/arch/fsp/azalia.h> #include <asm/fsp/fsp_support.h> +DECLARE_GLOBAL_DATA_PTR; + /* ALC262 Verb Table - 10EC0262 */ static const uint32_t verb_table_data13[] = { /* Pin Complex (NID 0x11) */ @@ -116,41 +120,165 @@ const struct pch_azalia_config azalia_config = { .reset_wait_timer_us = 300 }; +/** + * Update the FSP's UPD. The FSP itself can be configured for defaults to + * store in UPD through Intel's GUI configurator but likely a specific board + * will want to update these from u-boot, so allow for that via device tree. + * If the device tree does not specify a setting, trust the FSP's default. + */ void update_fsp_upd(struct upd_region *fsp_upd) { struct memory_down_data *mem; + const void *blob = gd->fdt_blob; + int node; - /* - * Configure everything here to avoid the poor hard-pressed user - * needing to run Intel's binary configuration tool. It may also allow - * us to support the 1GB single core variant easily. - * - * TODO(sjg(a)chromium.org): Move to device tree - */ - fsp_upd->mrc_init_tseg_size = 8; - fsp_upd->mrc_init_mmio_size = 0x800; - fsp_upd->emmc_boot_mode = 0xff; - fsp_upd->enable_sdio = 1; - fsp_upd->enable_sdcard = 1; - fsp_upd->enable_hsuart0 = 1; fsp_upd->azalia_config_ptr = (uint32_t)&azalia_config; - fsp_upd->enable_i2_c0 = 0; - fsp_upd->enable_i2_c2 = 0; - fsp_upd->enable_i2_c3 = 0; - fsp_upd->enable_i2_c4 = 0; - fsp_upd->enable_xhci = 0; - fsp_upd->igd_render_standby = 1; + + node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_BAYTRAIL_FSP); + if (node < 0) { + debug("%s: Cannot find FSP node\n", __func__); + return; + } + + fsp_upd->mrc_init_tseg_size = fdtdec_get_int(blob, node, + "fsp,mrc-int-tseg-size", + fsp_upd->mrc_init_tseg_size); + fsp_upd->mrc_init_mmio_size = fdtdec_get_int(blob, node, + "fsp,mrc-init-mmio-size", + fsp_upd->mrc_init_mmio_size); + fsp_upd->mrc_init_spd_addr1 = fdtdec_get_int(blob, node, + "fsp,mrc-init-spd-addr1", + fsp_upd->mrc_init_spd_addr1); + fsp_upd->mrc_init_spd_addr2 = fdtdec_get_int(blob, node, + "fsp,mrc-init-spd-addr2", + fsp_upd->mrc_init_spd_addr2); + fsp_upd->emmc_boot_mode = fdtdec_get_int(blob, node, "fsp,emmc-boot-mode", + fsp_upd->emmc_boot_mode); + fsp_upd->enable_sdio = fdtdec_get_int(blob, node, "fsp,enable-sdio", + fsp_upd->enable_sdio); + fsp_upd->enable_sdcard = fdtdec_get_int(blob, node, "fsp,enable-sdcard", + fsp_upd->enable_sdcard); + fsp_upd->enable_hsuart0 = fdtdec_get_int(blob, node, "fsp,enable-hsuart0", + fsp_upd->enable_hsuart0); + fsp_upd->enable_hsuart1 = fdtdec_get_int(blob, node, "fsp,enable-hsuart1", + fsp_upd->enable_hsuart1); + fsp_upd->enable_spi = fdtdec_get_int(blob, node, "fsp,enable-spi", + fsp_upd->enable_spi); + fsp_upd->enable_sata = fdtdec_get_int(blob, node, "fsp,enable-sata", + fsp_upd->enable_sata); + fsp_upd->enable_azalia = fdtdec_get_int(blob, node, "fsp,enable-azalia", + fsp_upd->enable_azalia); + fsp_upd->enable_xhci = fdtdec_get_int(blob, node, "fsp,enable-xhci", + fsp_upd->enable_xhci); + fsp_upd->enable_lpe = fdtdec_get_int(blob, node, "fsp,enable-lpe", + fsp_upd->enable_lpe); + fsp_upd->lpss_sio_enable_pci_mode = fdtdec_get_int(blob, node, + "fsp,lpss-sio-enable-pci-mode", + fsp_upd->lpss_sio_enable_pci_mode); + fsp_upd->enable_dma0 = fdtdec_get_int(blob, node, "fsp,enable-dma0", + fsp_upd->enable_dma0); + fsp_upd->enable_dma1 = fdtdec_get_int(blob, node, "fsp,enable-dma1", + fsp_upd->enable_dma1); + fsp_upd->enable_i2_c0 = fdtdec_get_int(blob, node, "fsp,enable-i2-c0", + fsp_upd->enable_i2_c0); + fsp_upd->enable_i2_c1 = fdtdec_get_int(blob, node, "fsp,enable-i2-c1", + fsp_upd->enable_i2_c1); + fsp_upd->enable_i2_c2 = fdtdec_get_int(blob, node, "fsp,enable-i2-c2", + fsp_upd->enable_i2_c2); + fsp_upd->enable_i2_c3 = fdtdec_get_int(blob, node, "fsp,enable-i2-c3", + fsp_upd->enable_i2_c3); + fsp_upd->enable_i2_c4 = fdtdec_get_int(blob, node, "fsp,enable-i2-c4", + fsp_upd->enable_i2_c4); + fsp_upd->enable_i2_c5 = fdtdec_get_int(blob, node, "fsp,enable-i2-c5", + fsp_upd->enable_i2_c5); + fsp_upd->enable_i2_c6 = fdtdec_get_int(blob, node, "fsp,enable-i2-c6", + fsp_upd->enable_i2_c6); + fsp_upd->enable_pwm0 = fdtdec_get_int(blob, node, "fsp,enable-pwm0", + fsp_upd->enable_pwm0); + fsp_upd->enable_pwm1 = fdtdec_get_int(blob, node, "fsp,enable-pwm1", + fsp_upd->enable_pwm1); + fsp_upd->enable_hsi = fdtdec_get_int(blob, node, "fsp,enable-hsi", + fsp_upd->enable_hsi); + fsp_upd->igd_dvmt50_pre_alloc = fdtdec_get_int(blob, node, + "fsp,igd-dvmt50-pre-alloc", + fsp_upd->igd_dvmt50_pre_alloc); + fsp_upd->aperture_size = fdtdec_get_int(blob, node, "fsp,aperture-size", + fsp_upd->aperture_size); + fsp_upd->gtt_size = fdtdec_get_int(blob, node, "fsp,gtt-size", + fsp_upd->gtt_size); + fsp_upd->serial_debug_port_address = fdtdec_get_int(blob, node, + "fsp,serial-debug-port-address", + fsp_upd->serial_debug_port_address); + fsp_upd->serial_debug_port_type = fdtdec_get_int(blob, node, + "fsp,serial-debug-port-type", + fsp_upd->serial_debug_port_type); + fsp_upd->mrc_debug_msg = fdtdec_get_int(blob, node, "fsp,mrc-debug-msg", + fsp_upd->mrc_debug_msg); + fsp_upd->isp_enable = fdtdec_get_int(blob, node, "fsp,isp-enable", + fsp_upd->isp_enable); + fsp_upd->scc_enable_pci_mode = fdtdec_get_int(blob, node, + "fsp,scc-enable-pci-mode", + fsp_upd->scc_enable_pci_mode); + fsp_upd->igd_render_standby = fdtdec_get_int(blob, node, + "fsp,igd-render-standby", + fsp_upd->igd_render_standby); + fsp_upd->txe_uma_enable = fdtdec_get_int(blob, node, "fsp,txe-uma-enable", + fsp_upd->txe_uma_enable); + fsp_upd->os_selection = fdtdec_get_int(blob, node, "fsp,os-selection", + fsp_upd->os_selection); + fsp_upd->emmc45_ddr50_enabled = fdtdec_get_int(blob, node, + "fsp,emmc45-ddr50-enabled", + fsp_upd->emmc45_ddr50_enabled); + fsp_upd->emmc45_hs200_enabled = fdtdec_get_int(blob, node, + "fsp,emmc45-hs200-enabled", + fsp_upd->emmc45_hs200_enabled); + fsp_upd->emmc45_retune_timer_value = fdtdec_get_int(blob, node, + "fsp,emmc45-retune-timer-value", + fsp_upd->emmc45_retune_timer_value); + fsp_upd->igd_render_standby = fdtdec_get_int(blob, node, + "fsp,igd-render-standby", + fsp_upd->igd_render_standby); mem = &fsp_upd->memory_params; - mem->enable_memory_down = 1; - mem->dram_speed = 1; - mem->dimm_width = 1; - mem->dimm_density = 2; - mem->dimm_tcl = 0xb; - mem->dimm_trpt_rcd = 0xb; - mem->dimm_twr = 0xc; - mem->dimm_twtr = 6; - mem->dimm_trrd = 6; - mem->dimm_trtp = 6; - mem->dimm_tfaw = 0x14; + mem->enable_memory_down = fdtdec_get_int(blob, node, + "fsp,enable-memory-down", + mem->enable_memory_down); + node = fdtdec_next_compatible(blob, node, + COMPAT_INTEL_BAYTRAIL_FSP_MDP); + if (node < 0) { + debug("%s: Cannot find FSP memory-down-params node\n", __func__); + } else { + mem->dram_speed = fdtdec_get_int(blob, node, "fsp,dram-speed", + mem->dram_speed); + mem->dram_type = fdtdec_get_int(blob, node, "fsp,dram-type", + mem->dram_type); + mem->dimm_0_enable = fdtdec_get_int(blob, node, "fsp,dimm-0-enable", + mem->dimm_0_enable); + mem->dimm_1_enable = fdtdec_get_int(blob, node, "fsp,dimm-1-enable", + mem->dimm_1_enable); + mem->dimm_width = fdtdec_get_int(blob, node, "fsp,dimm-width", + mem->dimm_width); + mem->dimm_density = fdtdec_get_int(blob, node, + "fsp,dimm-density", + mem->dimm_density); + mem->dimm_bus_width = fdtdec_get_int(blob, node, + "fsp,dimm-bus-width", + mem->dimm_bus_width); + mem->dimm_sides = fdtdec_get_int(blob, node, "fsp,dimm-sides", + mem->dimm_sides); + mem->dimm_tcl = fdtdec_get_int(blob, node, "fsp,dimm-tcl", + mem->dimm_tcl); + mem->dimm_trpt_rcd = fdtdec_get_int(blob, node, "fsp,dimm-trpt-rcd", + mem->dimm_trpt_rcd); + mem->dimm_twr = fdtdec_get_int(blob, node, "fsp,dimm-twr", + mem->dimm_twr); + mem->dimm_twtr = fdtdec_get_int(blob, node, "fsp,dimm-twtr", + mem->dimm_twtr); + mem->dimm_trrd = fdtdec_get_int(blob, node, "fsp,dimm-trrd", + mem->dimm_trrd); + mem->dimm_trtp = fdtdec_get_int(blob, node, "fsp,dimm-trtp", + mem->dimm_trtp); + mem->dimm_tfaw = fdtdec_get_int(blob, node, "fsp,dimm-tfaw", + mem->dimm_tfaw); + } } diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts index 0e59b18..279d08d 100644 --- a/arch/x86/dts/minnowmax.dts +++ b/arch/x86/dts/minnowmax.dts @@ -121,6 +121,36 @@ 0x01000000 0x0 0x2000 0x2000 0 0xe000>; }; + fsp { + compatible = "intel,baytrail-fsp"; + fsp,mrc-init-tseg-size = <8>; + fsp,mrc-init-mmio-size = <0x800>; + fsp,emmc-boot-mode = <0xff>; + fsp,enable-sdio = <1>; + fsp,enable-sdcard = <1>; + fsp,enable-hsuart0 = <1>; + fsp,enable-i2-c0 = <0>; + fsp,enable-i2-c2 = <0>; + fsp,enable-i2-c3 = <0>; + fsp,enable-i2-c4 = <0>; + fsp,enable-xhci = <0>; + fsp,igd-render-standby = <1>; + fsp,enable-memory-down = <1>; + fsp,memory-down-params { + compatible = "intel,baytrail-fsp-mdp"; + fsp,dram-speed = <1>; + fsp,dimm-width = <1>; + fsp,dimm-density = <2>; + fsp,dimm-tcl = <0xb>; + fsp,dimm-trpt-rcd = <0xb>; + fsp,dimm-twr = <0xc>; + fsp,dimm-twtr = <6>; + fsp,dimm-trrd = <6>; + fsp,dimm-trtp = <6>; + fsp,dimm-tfaw = <0x14>; + }; + }; + spi { #address-cells = <1>; #size-cells = <0>; diff --git a/doc/device-tree-bindings/misc/intel,baytrail-fsp.txt b/doc/device-tree-bindings/misc/intel,baytrail-fsp.txt new file mode 100644 index 0000000..979d646 --- /dev/null +++ b/doc/device-tree-bindings/misc/intel,baytrail-fsp.txt @@ -0,0 +1,119 @@ +Intel Bay Trail FSP UPD Binding +============================== + +The device tree node which describes the overriding of the Intel Bay Trail FSP +UPD data for configuring the SoC. + +All properties are optional, if a property is unspecified then the FSP's +preconfigured choices will be used. For this reason, using normal boolean +properties is not desired as the lack of a boolean property would disable a +given property and force the user to include all properties they wish to enable. + +All properties can be found within the `upd-region` struct in +arch/x86/include/asm/arch-baytrail/fsp/fsp-vpd.h, under the same names, and in +Intel's FSP Binary Configuration Tool for Bay Trail. + +Optional properties: + +- fsp,mrc-init-tseg-size +- fsp,mrc-init-mmio-size +- fsp,mrc-init-spd-addr1 +- fsp,mrc-init-spd-addr2 +- fsp,emmc-boot-mode +- fsp,enable-sdio +- fsp,enable-sdcard +- fsp,enable-hsuart0 +- fsp,enable-hsuart1 +- fsp,enable-spi +- fsp,enable-sata +- fsp,sata-mode +- fsp,enable-azalia +- fsp,enable-xhci +- fsp,enable-lpe +- fsp,lpss-sio-enable-pci-mode +- fsp,enable-dma0 +- fsp,enable-dma1 +- fsp,enable-i2-c0 +- fsp,enable-i2-c1 +- fsp,enable-i2-c2 +- fsp,enable-i2-c3 +- fsp,enable-i2-c4 +- fsp,enable-i2-c5 +- fsp,enable-i2-c6 +- fsp,enable-pwm0 +- fsp,enable-pwm1 +- fsp,enable-hsi +- fsp,igd-dvmt50-pre-alloc +- fsp,aperture-size +- fsp,gtt-size +- fsp,serial-debug-port-address +- fsp,serial-debug-port-type +- fsp,mrc-debug-msg +- fsp,isp-enable +- fsp,scc-enable-pci-mode +- fsp,igd-render-standby +- fsp,txe-uma-enable +- fsp,os-selection +- fsp,emmc45-ddr50-enabled +- fsp,emmc45-hs200-enabled +- fsp,emmc45-retune-timer-value +- fsp,enable-memory-down + +- fsp,memory-down-params { + + The following are only used if enable-memory-down is set, otherwise + the FSP will use the DIMM's SPD information to configure the memory: + - fsp,dram-speed + - fsp,dram-type + - fsp,dimm-0-enable + - fsp,dimm-1-enable + - fsp,dimm-width + - fsp,dimm-density + - fsp,dimm-bus-width + - fsp,dimm-sides + - fsp,dimm-tcl + - fsp,dimm-trpt-rcd + - fsp,dimm-twr + - fsp,dimm-twtr + - fsp,dimm-trrd + - fsp,dimm-trtp + - fsp,dimm-tfaw +}; + +Example (from MinnowMax Dual Core): +----------------------------------- + +/ { + ... + + fsp { + compatible = "intel,baytrail-fsp"; + fsp,mrc-init-tseg-size = <8>; + fsp,mrc-init-mmio-size = <0x800>; + fsp,emmc-boot-mode = <0xff>; + fsp,enable-sdio = <1>; + fsp,enable-sdcard = <1>; + fsp,enable-hsuart0 = <1>; + fsp,enable-i2-c0 = <0>; + fsp,enable-i2-c2 = <0>; + fsp,enable-i2-c3 = <0>; + fsp,enable-i2-c4 = <0>; + fsp,enable-xhci = <0>; + fsp,igd-render-standby = <1>; + fsp,memory-down-params { + compatible = "intel,baytrail-fsp-mdp"; + fsp,dram-speed = <1>; + fsp,dimm-width = <1>; + fsp,dimm-density = <2>; + fsp,dimm-tcl = <0xb>; + fsp,dimm-trpt-rcd = <0xb>; + fsp,dimm-twr = <0xc>; + fsp,dimm-twtr = <6>; + fsp,dimm-trrd = <6>; + fsp,dimm-trtp = <6>; + fsp,dimm-tfaw = <0x14>; + }; + }; + + ... +}; diff --git a/include/fdtdec.h b/include/fdtdec.h index 2323603..76d07eb 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -183,6 +183,8 @@ enum fdt_compat_id { COMPAT_SOCIONEXT_XHCI, /* Socionext UniPhier xHCI */ COMPAT_INTEL_PCH, /* Intel PCH */ COMPAT_INTEL_IRQ_ROUTER, /* Intel Interrupt Router */ + COMPAT_INTEL_BAYTRAIL_FSP, /* Intel Bay Trail FSP */ + COMPAT_INTEL_BAYTRAIL_FSP_MDP, /* Intel Bay Trail FSP memory-down params */ COMPAT_COUNT, }; diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 9877849..1e48b82 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -76,6 +76,8 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(SOCIONEXT_XHCI, "socionext,uniphier-xhci"), COMPAT(COMPAT_INTEL_PCH, "intel,bd82x6x"), COMPAT(COMPAT_INTEL_IRQ_ROUTER, "intel,irq-router"), + COMPAT(COMPAT_INTEL_BAYTRAIL_FSP, "intel,baytrail-fsp"), + COMPAT(COMPAT_INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"), }; const char *fdtdec_get_compatible(enum fdt_compat_id id) -- 2.4.5

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[U-Boot] Driver for SD card in Odroid-X2
by Humberto López León 29 Jul '15

29 Jul '15

Hi community, my team and I are working on the implementation of a driver for SD cards in the ODROID-X2 (exynos4412). This driver we want to incorporate into the framework GenodeOS, but we have some doubts in implementation. Below I list a few: 1- We are implementing the controller DWMMC. This is the right controller to handle the SD card in the exynos4412? The SDHCI controller is most appropriate? 2- What exynos4412 SoC base address should be used for handling the SD card? 3- What is the IRQ associated with handling SD tajetas with DWMMC controller? 4- To use the DWMMC controller you need to configure GPIO ports? 5- What clocks should be initialized to handle SD cards? Anybody know any document that describes the initialization process of an SD card? We have been reviewing the implementation of the driver for the SD card in the U-Boot and Linux kernel, but have not resolved the questions above. Thank you for your help !!

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[U-Boot] [PATCH 0/4] Add UniPhier GPIO driver support
by Masahiro Yamada 29 Jul '15

29 Jul '15

Masahiro Yamada (4): gpio: UniPhier: add driver for UniPhier GPIO controller gpio: do not include <asm/arch/gpio.h> for UniPhier ARM: UniPhier: enable UniPhier GPIO driver ARM: dts: UniPhier: add GPIO controller nodes arch/arm/Kconfig | 1 + arch/arm/dts/uniphier-ph1-ld4.dtsi | 8 ++ arch/arm/dts/uniphier-ph1-pro4.dtsi | 8 ++ arch/arm/dts/uniphier-ph1-sld3.dtsi | 8 ++ arch/arm/dts/uniphier-ph1-sld8.dtsi | 8 ++ arch/arm/include/asm/gpio.h | 2 + configs/ph1_ld4_defconfig | 1 + configs/ph1_pro4_defconfig | 1 + configs/ph1_sld8_defconfig | 1 + drivers/gpio/Kconfig | 6 ++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-uniphier.c | 186 ++++++++++++++++++++++++++++++++++++ 12 files changed, 231 insertions(+) create mode 100644 drivers/gpio/gpio-uniphier.c -- 1.9.1

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