May 2015 - U-Boot

[U-Boot] [PATCH] ARM: cpu: Add ARMv7 barrier operations support
by Vladimir Barinov 20 Aug '15

20 Aug '15

From: Valentine Barshak <valentine.barshak(a)cogentembedded.com> This enables ARMv7 barrier operations support when march=armv7-a is enabled. Using CP15 barriers causes U-Boot bootm command crash when transferring control to the loaded image on Renesas R8A7794 Cortex A7 CPU. Using ARMv7 barrier operations instead of the deprecated CP15 barriers helps to avoid these issues. Signed-off-by: Valentine Barshak <valentine.barshak+renesas(a)cogentembedded.com> Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas(a)cogentembedded.com> Reviewed-by: Tom Rini <trini(a)konsulko.com> --- arch/arm/cpu/armv7/cache_v7.c | 14 +++++++------- arch/arm/include/asm/armv7.h | 10 ++++++++++ 2 files changed, 17 insertions(+), 7 deletions(-) diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c index 0f9d837..e8ee875 100644 --- a/arch/arm/cpu/armv7/cache_v7.c +++ b/arch/arm/cpu/armv7/cache_v7.c @@ -68,7 +68,7 @@ static void v7_inval_dcache_level_setway(u32 level, u32 num_sets, } } /* DSB to make sure the operation is complete */ - CP15DSB; + DSB; } static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets, @@ -96,7 +96,7 @@ static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets, } } /* DSB to make sure the operation is complete */ - CP15DSB; + DSB; } static void v7_maint_dcache_level_setway(u32 level, u32 operation) @@ -215,7 +215,7 @@ static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op) } /* DSB to make sure the operation is complete */ - CP15DSB; + DSB; } /* Invalidate TLB */ @@ -228,9 +228,9 @@ static void v7_inval_tlb(void) /* Invalidate entire instruction TLB */ asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0)); /* Full system DSB - make sure that the invalidation is complete */ - CP15DSB; + DSB; /* Full system ISB - make sure the instruction stream sees it */ - CP15ISB; + ISB; } void invalidate_dcache_all(void) @@ -343,10 +343,10 @@ void invalidate_icache_all(void) asm volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0)); /* Full system DSB - make sure that the invalidation is complete */ - CP15DSB; + DSB; /* ISB - make sure the instruction stream sees it */ - CP15ISB; + ISB; } #else void invalidate_icache_all(void) diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h index a13da23..189f3f0 100644 --- a/arch/arm/include/asm/armv7.h +++ b/arch/arm/include/asm/armv7.h @@ -70,6 +70,16 @@ #define CP15DSB asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)) #define CP15DMB asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0)) +#ifdef __ARM_ARCH_7A__ +#define ISB asm volatile ("isb" : : : "memory") +#define DSB asm volatile ("dsb" : : : "memory") +#define DMB asm volatile ("dmb" : : : "memory") +#else +#define ISB CP15ISB +#define DSB CP15DSB +#define DMB CP15DMB +#endif + /* * Workaround for ARM errata # 798870 * Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been -- 1.9.3

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[U-Boot] [PATCH] ARM: atmel: switch to usb ehci for sama5d3 boards
by Josh Wu 19 Aug '15

19 Aug '15

From: Bo Shen <voice.shen(a)atmel.com> As the cache coherence issue in OHCI HCD, when enable I/D cache for sama5d3 SoC, the OHCI can not work properly. So, switch to EHCI, then the USB can work well. Signed-off-by: Bo Shen <voice.shen(a)atmel.com> [rebase to mainline] Signed-off-by: Josh Wu <josh.wu(a)atmel.com> --- include/configs/sama5d3_xplained.h | 21 +++------------------ include/configs/sama5d3xek.h | 21 +++------------------ 2 files changed, 6 insertions(+), 36 deletions(-) diff --git a/include/configs/sama5d3_xplained.h b/include/configs/sama5d3_xplained.h index bfd8aa7..0dab15d 100644 --- a/include/configs/sama5d3_xplained.h +++ b/include/configs/sama5d3_xplained.h @@ -20,17 +20,6 @@ #define CONFIG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID ATMEL_ID_DBGU -/* - * This needs to be defined for the OHCI code to work but it is defined as - * ATMEL_ID_UHPHS in the CPU specific header files. - */ -#define ATMEL_ID_UHP ATMEL_ID_UHPHS - -/* - * Specify the clock enable bit in the PMC_SCER register. - */ -#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP - /* SDRAM */ #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS @@ -95,13 +84,9 @@ #define CONFIG_CMD_USB #ifdef CONFIG_CMD_USB -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_UPLL -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "SAMA5D3 Xplained" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_ATMEL +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 #define CONFIG_DOS_PARTITION #define CONFIG_USB_STORAGE #endif diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h index d933a9e..d3ab6e4 100644 --- a/include/configs/sama5d3xek.h +++ b/include/configs/sama5d3xek.h @@ -24,17 +24,6 @@ #define CONFIG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID ATMEL_ID_DBGU -/* - * This needs to be defined for the OHCI code to work but it is defined as - * ATMEL_ID_UHPHS in the CPU specific header files. - */ -#define ATMEL_ID_UHP ATMEL_ID_UHPHS - -/* - * Specify the clock enable bit in the PMC_SCER register. - */ -#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP - /* LCD */ #define CONFIG_LCD #define LCD_BPP LCD_COLOR16 @@ -128,13 +117,9 @@ #define CONFIG_CMD_USB #ifdef CONFIG_CMD_USB -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_UPLL -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "sama5d3" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_ATMEL +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 #define CONFIG_DOS_PARTITION #define CONFIG_USB_STORAGE #endif -- 1.9.1

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[U-Boot] [PATCHv3 00/17] Add SPL support for SoCFPGA
by dinguyen＠opensource.altera.com 13 Aug '15

13 Aug '15

From: Dinh Nguyen <dinguyen(a)opensource.altera.com> Hello, This is v3 of the patchset that adds all the SPL code that is necessary to support the SoCFPGA platform. For v3, here are the changes: - Remove gdata - Remove s_init - Remove socfpga lowlevel_init.S - Use common u-boot-spl.lds - Properly use CONFIG_SPL_TEXT_BASE so we don't have to add an .sram section I have pushed a branch to git://git.rocketboards.org/u-boot-socfpga-next.git socfpga_for_next_spl_v3 for testing and reviewing. Rebased to 2015.04-rc4. Thanks, Dinh Nguyen (17): arm: socfpga: spl: Add main sdram code arm: socfpga: spl: Add CONFIG_SPL_MAX_SIZE to be 64KB arm: socfpga: add functions to bring sdram, timer, and uart out of reset arm: socfpga: spl: enable sdram, timer and uart arm: socfpga: spl: Add call to timer_init arm: socfpga: spl: allow bootrom to enable IOs after warm reset arm: socfpga: spl: add sdram init and calibration arm: socfpga: spl: printout sdram size arm: socfpga: spl: Use common lowlevel_init arm: socfpga: spl: Add s_init stub arm: socfpga: spl: add CONFIG_SPL_STACK to socfpga_common.h arm: socfpga: spl: Adjust the SYS_INIT_RAM_SIZE to have room for the spl malloc arm: socfpga: spl: add board_init_f to SPL arm: socfpga: spl: Add SDRAM check arm: socfpga: spl: update pll_config for dev kit arm: socfpga: remove the need to map sdram in arch_early_init arm: socfpga: fix uart0 pin mux configuration Makefile | 1 + arch/arm/cpu/armv7/Makefile | 2 +- arch/arm/cpu/armv7/socfpga/Makefile | 1 - arch/arm/cpu/armv7/socfpga/lowlevel_init.S | 45 - arch/arm/cpu/armv7/socfpga/misc.c | 3 - arch/arm/cpu/armv7/socfpga/reset_manager.c | 24 + arch/arm/cpu/armv7/socfpga/spl.c | 62 + arch/arm/cpu/armv7/socfpga/system_manager.c | 9 + arch/arm/include/asm/arch-socfpga/reset_manager.h | 6 + arch/arm/include/asm/arch-socfpga/sdram.h | 434 +++ arch/arm/include/asm/arch-socfpga/sdram_config.h | 100 + arch/arm/include/asm/arch-socfpga/system_manager.h | 1 + board/altera/socfpga/pinmux_config.c | 4 +- board/altera/socfpga/pll_config.h | 4 +- board/altera/socfpga/socfpga.c | 2 + drivers/ddr/altera/Makefile | 12 + drivers/ddr/altera/sdram.c | 1307 +++++++ drivers/ddr/altera/sequencer.c | 3970 ++++++++++++++++++++ drivers/ddr/altera/sequencer.h | 359 ++ drivers/ddr/altera/sequencer_auto.h | 216 ++ drivers/ddr/altera/sequencer_auto_ac_init.c | 85 + drivers/ddr/altera/sequencer_auto_inst_init.c | 270 ++ drivers/ddr/altera/sequencer_defines.h | 121 + include/configs/socfpga_common.h | 8 +- include/configs/socfpga_cyclone5.h | 1 + scripts/Makefile.spl | 1 + 26 files changed, 6993 insertions(+), 55 deletions(-) delete mode 100644 arch/arm/cpu/armv7/socfpga/lowlevel_init.S create mode 100644 arch/arm/include/asm/arch-socfpga/sdram.h create mode 100644 arch/arm/include/asm/arch-socfpga/sdram_config.h create mode 100644 drivers/ddr/altera/Makefile create mode 100644 drivers/ddr/altera/sdram.c create mode 100644 drivers/ddr/altera/sequencer.c create mode 100644 drivers/ddr/altera/sequencer.h create mode 100644 drivers/ddr/altera/sequencer_auto.h create mode 100644 drivers/ddr/altera/sequencer_auto_ac_init.c create mode 100644 drivers/ddr/altera/sequencer_auto_inst_init.c create mode 100644 drivers/ddr/altera/sequencer_defines.h -- 2.2.1

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[U-Boot] [PATCH 0/3] e1000: fix semaphore sync issues
by Tim Harvey 12 Aug '15

12 Aug '15

The following patchset resolves semaphore sync issues I've encountered on a board with an i210 (programmed, copper mode) using the internal phy. The first patch adds releasing of the semaphore once they are no longer needed, and the other two patches revert logic that I believe was working around the fact that they were previsouly not released. This will need testing on the various configurations of e1000 so I've taken care to Cc the maintainers that were listed by boards using CONFIG_E1000 as well as the authors of the patches I'm reverting sections from. Cc: Marcel Ziswiler <marcel(a)ziswiler.com> Cc: Marek Vasut <marex(a)denx.de> Cc: Aneesh Bansal <aneesh.bansal(a)freescale.com> Cc: Naveen Burmi <NaveenBurmi(a)freescale.com> Cc: Po Liu <po.liu(a)freescale.com> Cc: Bin Meng <bmeng.cn(a)gmail.com> Cc: Alison Wang <alison.wang(a)freescale.com> Cc: Reinhard Arlt <reinhard.arlt(a)esd-electronics.com> Cc: Shengzhou Liu <Shengzhou.Liu(a)freescale.com> Cc: York Sun <yorksun(a)freescale.com> Signed-off-by: Tim Harvey <tharvey(a)gateworks.com> Tim Harvey (3): e1000: fix eeprom sync issues by releasing semaphore once no longer needed Revert "e1000: fix sw fw sync on igb i210/i211" e1000: remove unnecessary clearing of SWSM.SWSM_SMBI drivers/net/e1000.c | 32 ++++++++++++++++++++++++-------- drivers/net/e1000.h | 1 - 2 files changed, 24 insertions(+), 9 deletions(-) -- 1.9.1

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[U-Boot] [PATCH] net/phy: set led for rtl8211f phy
by Shengzhou Liu 12 Aug '15

12 Aug '15

Initialize LCR rigister to configure green LED for Link, yellow LED for Active. Signed-off-by: Shengzhou Liu <Shengzhou.Liu(a)freescale.com> --- drivers/net/phy/realtek.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c index 79452a8..bba48da 100644 --- a/drivers/net/phy/realtek.c +++ b/drivers/net/phy/realtek.c @@ -41,6 +41,7 @@ #define MIIM_RTL8211F_PAGE_SELECT 0x1f #define MIIM_RTL8211F_TX_DELAY 0x100 +#define MIIM_RTL8211F_LCR 0x10 /* RealTek RTL8211x */ static int rtl8211x_config(struct phy_device *phydev) @@ -79,6 +80,13 @@ static int rtl8211f_config(struct phy_device *phydev) MIIM_RTL8211F_PAGE_SELECT, 0x0); } + /* Set green LED for Link, yellow LED for Active */ + phy_write(phydev, MDIO_DEVAD_NONE, + MIIM_RTL8211F_PAGE_SELECT, 0xd04); + phy_write(phydev, MDIO_DEVAD_NONE, 0x10, 0x617f); + phy_write(phydev, MDIO_DEVAD_NONE, + MIIM_RTL8211F_PAGE_SELECT, 0x0); + genphy_config_aneg(phydev); return 0; -- 2.1.0.27.g96db324

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[U-Boot] [RESEND PATCH] usb: gadget: f_thor: Allocate request up to THOR_PACKET_SIZE
by Michal Simek 12 Aug '15

12 Aug '15

From: Siva Durga Prasad Paladugu <siva.durga.paladugu(a)xilinx.com> Allocate request up to THOR_PACKET_SIZE not the ep0->maxpacket as the descriptors data depend on the number of descriptors and this 64 bytes were not enough and the buffer might overflow which results in memalign failures later. Signed-off-by: Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- drivers/usb/gadget/f_thor.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/gadget/f_thor.c b/drivers/usb/gadget/f_thor.c index 31eec36be876..5c8f6768519c 100644 --- a/drivers/usb/gadget/f_thor.c +++ b/drivers/usb/gadget/f_thor.c @@ -775,7 +775,7 @@ static int thor_func_bind(struct usb_configuration *c, struct usb_function *f) goto fail; } dev->req->buf = memalign(CONFIG_SYS_CACHELINE_SIZE, - gadget->ep0->maxpacket); + THOR_PACKET_SIZE); if (!dev->req->buf) { status = -ENOMEM; goto fail; -- 2.3.5

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[U-Boot] [PATCH v2] f_thor: Dont perform reset at the end of thor
by Michal Simek 12 Aug '15

12 Aug '15

From: Siva Durga Prasad Paladugu <siva.durga.paladugu(a)xilinx.com> Dont perform reset at the end of thor download if configured to do reset off. Reset may not be required in all cases and hence provided an option to do so. The case would be to download the images to DDR instead of flash device. Signed-off-by: Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- Changes in v2: - Update commit message with additional description drivers/usb/gadget/f_thor.c | 7 +++++++ drivers/usb/gadget/f_thor.h | 3 +++ 2 files changed, 10 insertions(+) diff --git a/drivers/usb/gadget/f_thor.c b/drivers/usb/gadget/f_thor.c index e9a690eff5f1..5c8f6768519c 100644 --- a/drivers/usb/gadget/f_thor.c +++ b/drivers/usb/gadget/f_thor.c @@ -123,6 +123,9 @@ static int process_rqt_cmd(const struct rqt_box *rqt) send_rsp(rsp); g_dnl_unregister(); dfu_free_entities(); +#ifdef CONFIG_THOR_RESET_OFF + return RESET_DONE; +#endif run_command("reset", 0); break; case RQT_CMD_POWEROFF: @@ -728,6 +731,10 @@ int thor_handle(void) if (ret > 0) { ret = process_data(); +#ifdef CONFIG_THOR_RESET_OFF + if (ret == RESET_DONE) + break; +#endif if (ret < 0) return ret; } else { diff --git a/drivers/usb/gadget/f_thor.h b/drivers/usb/gadget/f_thor.h index 833a9d24ae7e..83412851dd17 100644 --- a/drivers/usb/gadget/f_thor.h +++ b/drivers/usb/gadget/f_thor.h @@ -121,4 +121,7 @@ struct f_thor { #define F_NAME_BUF_SIZE 32 #define THOR_PACKET_SIZE SZ_1M /* 1 MiB */ #define THOR_STORE_UNIT_SIZE SZ_32M /* 32 MiB */ +#ifdef CONFIG_THOR_RESET_OFF +#define RESET_DONE 0xFFFFFFFF +#endif #endif /* _USB_THOR_H_ */ -- 2.3.5

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[U-Boot] [PATCH] net/fm: Update FMan Compatibels
by Igal.Liberman 12 Aug '15

12 Aug '15

From: Igal Liberman <igal.liberman(a)freescale.com> During FMan upstreaming, the FMan Port and MAC compatibles changed. This patch aligns the FMan Port and MAC compatibles to the FMan device tree binding document. The FMan device tree binding document can be found in the Linux kernel: ./Documentation/devicetree/bindings/powerpc/fsl/fman.txt Signed-off-by: Igal Liberman <igal.liberman(a)freescale.com> --- arch/powerpc/include/asm/fsl_liodn.h | 20 ++++++++++++++++---- drivers/net/fm/init.c | 4 ++-- 2 files changed, 18 insertions(+), 6 deletions(-) diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h index 811f034..d493f8c 100644 --- a/arch/powerpc/include/asm/fsl_liodn.h +++ b/arch/powerpc/include/asm/fsl_liodn.h @@ -133,15 +133,27 @@ extern void fdt_fixup_liodn(void *blob); CONFIG_SYS_FSL_FM##fmNum##_OFFSET + \ offsetof(struct ccsr_fman, fm_bmi_common.fmbm_ppid[portID - 1]) -/* enetNum is 0, 1, 2... so we + 8 for 1g to get to HW Port ID */ +#ifdef CONFIG_SYS_FMAN_V3 +#define SET_FMAN_RX_1G_LIODN(fmNum, enetNum, liodn) \ + _SET_FMAN_RX_1G_LIODN("fsl,fman-v3-port-rx", fmNum, enetNum, liodn) +#define SET_FMAN_RX_10G_LIODN(fmNum, enetNum, liodn) \ + _SET_FMAN_RX_10G_LION("fsl,fman-v3-port-rx", fmNum, enetNum, liodn) +#else #define SET_FMAN_RX_1G_LIODN(fmNum, enetNum, liodn) \ - SET_LIODN_ENTRY_1("fsl,fman-port-1g-rx", liodn, \ + _SET_FMAN_RX_1G_LIODN("fsl,fman-v2-port-rx", fmNum, enetNum, liodn) +#define SET_FMAN_RX_10G_LIODN(fmNum, enetNum, liodn) \ + _SET_FMAN_RX_10G_LIODN("fsl,fman-v2-port-rx", fmNum, enetNum, liodn) +#endif + +/* enetNum is 0, 1, 2... so we + 8 for 1g to get to HW Port ID */ +#define _SET_FMAN_RX_1G_LIODN(compatible, fmNum, enetNum, liodn) \ + SET_LIODN_ENTRY_1(compatible, liodn, \ FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \ CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET) \ /* enetNum is 0, 1, 2... so we + 16 for 10g to get to HW Port ID */ -#define SET_FMAN_RX_10G_LIODN(fmNum, enetNum, liodn) \ - SET_LIODN_ENTRY_1("fsl,fman-port-10g-rx", liodn, \ +#define _SET_FMAN_RX_10G_LIODN(compatible, fmNum, enetNum, liodn) \ + SET_LIODN_ENTRY_1(compatible, liodn, \ FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 16), \ CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET) \ diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c index 9a8a007..4e43cca 100644 --- a/drivers/net/fm/init.c +++ b/drivers/net/fm/init.c @@ -306,9 +306,9 @@ void fdt_fixup_fman_ethernet(void *blob) #else for (i = 0; i < ARRAY_SIZE(fm_info); i++) { if (fm_info[i].type == FM_ETH_1G_E) - ft_fixup_port(blob, &fm_info[i], "fsl,fman-1g-mac"); + ft_fixup_port(blob, &fm_info[i], "fsl,fman-dtsec"); else - ft_fixup_port(blob, &fm_info[i], "fsl,fman-10g-mac"); + ft_fixup_port(blob, &fm_info[i], "fsl,fman-xgec"); } #endif } -- 1.7.9.5

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[U-Boot] [PATCH 0/3] DM9000 support for multiple interfaces
by Andrew Ruder 11 Aug '15

11 Aug '15

This is a rework of the DM9000 driver to support registering interfaces dynamically (i.e. determine how many ethernet chips we have at boot and register 0, 1, 2, or more). It was tested on a yet-to-be-submitted board which is based on the PXA270 + 0, 1, or 2 DM9000 chips. To maintain backwards compatibility with older board files, we add a new initialize function taking the io address, data address, and availability of a SROM chip. The old initialize function is now a shim around this new initialize function but provides the parameters based on the old DM9000 preprocessor symbols. I have compile-tested this on all the arm-based boards. Cc: Joe Hershberger <joe.hershberger(a)gmail.com> Andrew Ruder (3): dm9000: mark dump_regs() function as unused dm9000: Add struct eth_device * to SROM functions dm9000: rework dm9000 to support multiple devices board/trizepsiv/eeprom.c | 5 +- drivers/net/dm9000x.c | 382 +++++++++++++++++++++++++++-------------------- include/dm9000.h | 8 +- include/netdev.h | 1 + 4 files changed, 224 insertions(+), 172 deletions(-) -- 2.1.1

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[U-Boot] [PATCH v1 0/3] sparc: Add support for Gaisler GR712RC-BOARD Development Kit
by Francois Retief 11 Aug '15

11 Aug '15

This patch series add support for the Aeroflex Gaisler GR712RC-BOARD Development Kit. It builds on top of the previous SPARC architecture update series. Francois Retief (3): sparc: Make LEON serial drivers use readl/writel macros sparc: Add MDIO support to GRETH driver sparc: Add support for gr712rc-board arch/sparc/Kconfig | 8 + arch/sparc/cpu/leon2/serial.c | 121 +++++----- arch/sparc/cpu/leon3/serial.c | 93 ++++---- arch/sparc/include/asm/io.h | 43 ++-- board/gaisler/gr712rc_board/Kconfig | 9 + board/gaisler/gr712rc_board/MAINTAINERS | 6 + board/gaisler/gr712rc_board/Makefile | 8 + board/gaisler/gr712rc_board/README | 24 ++ board/gaisler/gr712rc_board/gr712rc_board.c | 68 ++++++ common/cmd_bdinfo.c | 4 + configs/gr712rc_board_defconfig | 3 + drivers/net/greth.c | 57 +++++ include/configs/gr712rc_board.h | 333 ++++++++++++++++++++++++++++ include/configs/gr_cpci_ax2000.h | 4 - include/configs/gr_ep2s60.h | 4 - include/configs/gr_xc3s_1500.h | 4 - include/configs/grsim.h | 3 - 17 files changed, 650 insertions(+), 142 deletions(-) create mode 100644 board/gaisler/gr712rc_board/Kconfig create mode 100644 board/gaisler/gr712rc_board/MAINTAINERS create mode 100644 board/gaisler/gr712rc_board/Makefile create mode 100644 board/gaisler/gr712rc_board/README create mode 100644 board/gaisler/gr712rc_board/gr712rc_board.c create mode 100644 configs/gr712rc_board_defconfig create mode 100644 include/configs/gr712rc_board.h -- 1.9.3 ________________________________ Disclaimer and confidentiality note – refer to our website for further details: www.spaceteq.co.za <http://www.spaceteq.co.za/home/emaildisclaimer/>

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