April 2015 - U-Boot

[U-Boot] [PATCH 1/4] sunxi: Removed dram files cleanup in MAINTAINERS
by Paul Kocialkowski 15 Apr '15

15 Apr '15

A few dram files were still listed as maintained even though they were removed some time ago Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr> --- board/sunxi/MAINTAINERS | 3 --- 1 file changed, 3 deletions(-) diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index f368d6f..458d4e5 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -42,13 +42,11 @@ F: configs/Ippo_q8h_v1_2_defconfig A20-OLINUXINO-LIME BOARD M: FUKAUMI Naoki <naobsd(a)gmail.com> S: Maintained -F: board/sunxi/dram_a20_olinuxino_l.c F: configs/A20-OLinuXino-Lime_defconfig A20-OLINUXINO-LIME2 BOARD M: Iain Paton <ipaton0(a)gmail.com> S: Maintained -F: board/sunxi/dram_a20_olinuxino_l2.c F: configs/A20-OLinuXino-Lime2_defconfig AINOL AW1 BOARD @@ -92,7 +90,6 @@ F: configs/Hummingbird_A31_defconfig INET-86VS BOARD M: Michal Suchanek <hramrach(a)gmail.com> S: Maintained -F: board/sunxi/dram_inet_86vs.c F: configs/Inet_86VS_defconfig IPPO-Q8H-V5 BOARD -- 1.9.1

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[U-Boot] [PATCH] net: gem: Use correct type for casting
by Michal Simek 15 Apr '15

15 Apr '15

Use phys_addr_t which is used in function prototype in system.h. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- drivers/net/zynq_gem.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 430e22821c7d..897cf0154b83 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -513,7 +513,8 @@ int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr, /* Align bd_space to 1MB */ bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE); - mmu_set_region_dcache_behaviour((u32)bd_space, BD_SPACE, DCACHE_OFF); + mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, + BD_SPACE, DCACHE_OFF); /* Initialize the bd spaces for tx and rx bd's */ priv->tx_bd = (struct emac_bd *)bd_space; -- 2.3.5

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[U-Boot] [PATCH] net: Use u32 instead of ulong for transaction ID in bootp
by Michal Simek 15 Apr '15

15 Apr '15

From: Siva Durga Prasad Paladugu <siva.durga.paladugu(a)xilinx.com> Based on rfc951 transaction ID has 4 bytes which is not the case when ulong type is used on ARM64. Use u32 type which is well defined for all archs. BOOTP_VENDOR_MAGIC is also 4 bytes. Based on RFC1048 Time Offset (code 2) is also 4bytes long and IP Address Lease Time also. The patch converts NetCopyLong to netcopy32 and NetReadLong to netread32 to follow u-boot coding style. Signed-off-by: Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- include/net.h | 14 +++++++------- net/bootp.c | 18 +++++++++--------- net/bootp.h | 2 +- 3 files changed, 17 insertions(+), 17 deletions(-) diff --git a/include/net.h b/include/net.h index 237c932be334..9b5f8249ddbb 100644 --- a/include/net.h +++ b/include/net.h @@ -607,12 +607,12 @@ static inline IPaddr_t NetReadIP(void *from) return ip; } -/* return ulong *in network byteorder* */ -static inline ulong NetReadLong(ulong *from) +/* return u32 *in network byteorder* */ +static inline u32 netread32(void *from) { - ulong l; + u32 l; - memcpy((void *)&l, (void *)from, sizeof(l)); + memcpy((void *)&l, from, sizeof(u32)); return l; } @@ -628,10 +628,10 @@ static inline void NetCopyIP(void *to, void *from) memcpy((void *)to, from, sizeof(IPaddr_t)); } -/* copy ulong */ -static inline void NetCopyLong(ulong *to, ulong *from) +/* copy u32 */ +static inline void netcopy32(void *to, void *from) { - memcpy((void *)to, (void *)from, sizeof(ulong)); + memcpy(to, from, sizeof(u32)); } /** diff --git a/net/bootp.c b/net/bootp.c index 81066015f1c2..de0d587228df 100644 --- a/net/bootp.c +++ b/net/bootp.c @@ -125,7 +125,7 @@ static int BootpCheckPkt(uchar *pkt, unsigned dest, unsigned src, unsigned len) retval = -4; else if (bp->bp_hlen != HWL_ETHER) retval = -5; - else if (!bootp_match_id(NetReadLong((ulong *)&bp->bp_id))) + else if (!bootp_match_id(netread32(&bp->bp_id))) retval = -6; debug("Filtering pkt = %d\n", retval); @@ -350,7 +350,7 @@ BootpHandler(uchar *pkt, unsigned dest, IPaddr_t sip, unsigned src, BootpCopyNetParams(bp); /* Store net parameters from reply */ /* Retrieve extended information (we must parse the vendor area) */ - if (NetReadLong((ulong *)&bp->bp_vend[0]) == htonl(BOOTP_VENDOR_MAGIC)) + if (netread32(&bp->bp_vend[0]) == htonl(BOOTP_VENDOR_MAGIC)) BootpVendorProcess((uchar *)&bp->bp_vend[4], len); NetSetTimeout(0, (thand_f *)0); @@ -732,7 +732,7 @@ BootpRequest(void) BootpID += get_timer(0); BootpID = htonl(BootpID); bootp_add_id(BootpID); - NetCopyLong(&bp->bp_id, &BootpID); + netcopy32(&bp->bp_id, &BootpID); /* * Calculate proper packet lengths taking into account the @@ -770,7 +770,7 @@ static void DhcpOptionsProcess(uchar *popt, struct Bootp_t *bp) #if defined(CONFIG_CMD_SNTP) && defined(CONFIG_BOOTP_TIMEOFFSET) case 2: /* Time offset */ to_ptr = &NetTimeOffset; - NetCopyLong((ulong *)to_ptr, (ulong *)(popt + 2)); + netcopy32(to_ptr, popt + 2); NetTimeOffset = ntohl(NetTimeOffset); break; #endif @@ -806,7 +806,7 @@ static void DhcpOptionsProcess(uchar *popt, struct Bootp_t *bp) break; #endif case 51: - NetCopyLong(&dhcp_leasetime, (ulong *) (popt + 2)); + netcopy32(&dhcp_leasetime, popt + 2); break; case 53: /* Ignore Message Type Option */ break; @@ -860,7 +860,7 @@ static void DhcpOptionsProcess(uchar *popt, struct Bootp_t *bp) static int DhcpMessageType(unsigned char *popt) { - if (NetReadLong((ulong *)popt) != htonl(BOOTP_VENDOR_MAGIC)) + if (netread32(popt) != htonl(BOOTP_VENDOR_MAGIC)) return -1; popt += 4; @@ -911,7 +911,7 @@ static void DhcpSendRequestPkt(struct Bootp_t *bp_offer) * ID is the id of the OFFER packet */ - NetCopyLong(&bp->bp_id, &bp_offer->bp_id); + netcopy32(&bp->bp_id, &bp_offer->bp_id); /* * Copy options from OFFER packet if present @@ -970,7 +970,7 @@ DhcpHandler(uchar *pkt, unsigned dest, IPaddr_t sip, unsigned src, debug("TRANSITIONING TO REQUESTING STATE\n"); dhcp_state = REQUESTING; - if (NetReadLong((ulong *)&bp->bp_vend[0]) == + if (netread32(&bp->bp_vend[0]) == htonl(BOOTP_VENDOR_MAGIC)) DhcpOptionsProcess((u8 *)&bp->bp_vend[4], bp); @@ -986,7 +986,7 @@ DhcpHandler(uchar *pkt, unsigned dest, IPaddr_t sip, unsigned src, debug("DHCP State: REQUESTING\n"); if (DhcpMessageType((u8 *)bp->bp_vend) == DHCP_ACK) { - if (NetReadLong((ulong *)&bp->bp_vend[0]) == + if (netread32(&bp->bp_vend[0]) == htonl(BOOTP_VENDOR_MAGIC)) DhcpOptionsProcess((u8 *)&bp->bp_vend[4], bp); /* Store net params from reply */ diff --git a/net/bootp.h b/net/bootp.h index 3b95a0a2ded8..cc71b2b56dec 100644 --- a/net/bootp.h +++ b/net/bootp.h @@ -38,7 +38,7 @@ struct Bootp_t { uchar bp_hlen; /* Hardware address length */ # define HWL_ETHER 6 uchar bp_hops; /* Hop count (gateway thing) */ - ulong bp_id; /* Transaction ID */ + u32 bp_id; /* Transaction ID */ ushort bp_secs; /* Seconds since boot */ ushort bp_spare1; /* Alignment */ IPaddr_t bp_ciaddr; /* Client IP address */ -- 2.3.5

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[U-Boot] Uboot Rel v2015.04 status
by Rob Westfall 15 Apr '15

15 Apr '15

Did v2015.04 get released?I didn't see a release announcement on this email list. The information on the web site about it is inconsistent: The ReleaseCycle web page (http://www.denx.de/wiki/view/U-Boot/ReleaseCycle) says this: - U-Boot v2015.04 was released on Mon, 13 Apr 2015. - The Merge Window for the next release (v2015.04) is *open* until Sat, Sat, May 02, 2015 23:59:59 UTC = 16 days remaining. - Release "v2015.07" is scheduled in 88 days — on Jul 13, 2015.\ This is inconsistent - it is "released", but merges for the next release (v2015.04) are still open. There is a tag in GIT for 2015.04, but there is no archive in the ftp directory and the "current" still points to 2015.01. Yes, I realize that I can create an archive from the GIT and work from there, but it would be nice to have an email from the "powers-that-be" saying that work on v2015.04 is completed and that it is released and new development will be in v2015.07. Thanks, Rob Westfall

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[U-Boot] [PATCH v5 0/2] i2c: sunxi: Support every i2c controller on each supported platform
by Paul Kocialkowski 15 Apr '15

15 Apr '15

Changes since v4: * Got rid of Kconfig after all * Only build mvtwsi when at least one controller is enabled on sunxi * Controller 0 doesn't have to be enabled in particular Changes since v3: * Kconfig support for MVTWSI * Only enable twsi0 by default for platforms that always use it for the AXP * Remove enabling other I2C busses by default on boards that expose them on pin headers since those might be used for some other functionalities Changes since v2: * I2C/TWI busses enable for Cubietruck as well Changes since v1: * Kconfig option to enable I2C/TWI controllers 1-4 (when applicable) * Following patch to enable exposed busses on a few community-supported single-board-computers This series adds support for every i2c controller found on sun4i/sun5i/sun6i/sun7i/sun8i platforms and shouldn't break support for Marvell platforms (orion5x, kirkwood, armada xp) the driver was originally written for. Regarding sunxi, I double-checked that this doesn't conflict with VIDEO_LCD_PANEL_I2C. I would be interested in having this tested on sun8i (A23), since I changed TWI0 muxing (to PH2-PH3 instead of PB0-PB1), according to the user manual and what is being done on the upstream Linux kernel. I2C was either not working before, or it was being muxed correctly by the bootrom, probably to communicate with the AXP, which luckily made it work in U-Boot too, since the I/O base address was already correct. My use case here is that I'm writing a slave-side bitbang i2c implementation (with an Arduino) for a school project, using a Cubieboard2 as master and U-Boot as POC. However, only TWI1 was available through the expansion pins, hence the need for this series.

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[U-Boot] [GIT] Pull request: u-boot-dfu
by Lukasz Majewski 15 Apr '15

15 Apr '15

The following changes since commit 7704fdbda3afb3d3bb0749378f444c71f92fb9ca: usb: gadget: thor: Claim EP after allocating it in thor gadget (2015-04-14 05:48:12 +0200) are available in the git repository at: git://git.denx.de/u-boot-dfu.git for you to fetch changes up to a32d27912961040230320268d6cde80e9442dc33: fastboot: Proper download gadget unregister and clear when cable is missing (2015-04-14 10:19:05 +0200) ---------------------------------------------------------------- Alexey Firago (1): fastboot: add support for reboot-bootloader command Fabio Estevam (1): cmd_usb_mass_storage: Use 'USB Mass Storage' in the help text Heiko Schocher (1): dfu: cmd: trigger watchdog before calling usb_gadget_handle_interrupts Michael Scott (1): fastboot: check for alias when looking up partition by name Paul Kocialkowski (1): fastboot: Proper download gadget unregister and clear when cable is missing common/cmd_dfu.c | 2 ++ common/cmd_fastboot.c | 2 ++ common/cmd_usb_mass_storage.c | 2 +- common/fb_mmc.c | 26 ++++++++++++++++++++++++-- doc/README.android-fastboot | 9 +++++++++ drivers/usb/gadget/f_fastboot.c | 13 +++++++++++++ 6 files changed, 51 insertions(+), 3 deletions(-) Tested at: Exynos4210 - Trats board -- Best regards, Lukasz Majewski Samsung R&D Institute Poland (SRPOL) | Linux Platform Group

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[U-Boot] [PATCH] zynqmp: sdhci: Remove the quirk SDHCI_QUIRK_NO_CD
by Michal Simek 15 Apr '15

15 Apr '15

From: Siva Durga Prasad Paladugu <siva.durga.paladugu(a)xilinx.com> Remove the quirk SDHCI_QUIRK_NO_CD as it is not required. Signed-off-by: Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- drivers/mmc/zynq_sdhci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index 7887f11c649b..d4f3882cbd38 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -25,7 +25,7 @@ int zynq_sdhci_init(phys_addr_t regbase) host->name = "zynq_sdhci"; host->ioaddr = (void *)regbase; - host->quirks = SDHCI_QUIRK_NO_CD | SDHCI_QUIRK_WAIT_SEND_CMD | + host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_BROKEN_R1B; host->version = sdhci_readw(host, SDHCI_HOST_VERSION); -- 2.3.5

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[U-Boot] [PATCH] zynqmp: Add support for R5 sw loading
by Michal Simek 15 Apr '15

15 Apr '15

Add support for loading sw for R5 with enabling for zynqmp. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> --- arch/arm/cpu/armv8/zynqmp/Makefile | 1 + arch/arm/cpu/armv8/zynqmp/mp.c | 242 ++++++++++++++++++++++++++++ arch/arm/include/asm/arch-zynqmp/hardware.h | 43 ++++- include/configs/xilinx_zynqmp.h | 2 + 4 files changed, 285 insertions(+), 3 deletions(-) create mode 100644 arch/arm/cpu/armv8/zynqmp/mp.c diff --git a/arch/arm/cpu/armv8/zynqmp/Makefile b/arch/arm/cpu/armv8/zynqmp/Makefile index a997e045bd0a..efab5eabc97b 100644 --- a/arch/arm/cpu/armv8/zynqmp/Makefile +++ b/arch/arm/cpu/armv8/zynqmp/Makefile @@ -7,3 +7,4 @@ obj-y += clk.o obj-y += cpu.o +obj-$(CONFIG_MP) += mp.o diff --git a/arch/arm/cpu/armv8/zynqmp/mp.c b/arch/arm/cpu/armv8/zynqmp/mp.c new file mode 100644 index 000000000000..17e32a7b7ce8 --- /dev/null +++ b/arch/arm/cpu/armv8/zynqmp/mp.c @@ -0,0 +1,242 @@ +/* + * (C) Copyright 2014 - 2015 Xilinx, Inc. + * Michal Simek <michal.simek(a)xilinx.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/hardware.h> +#include <asm/arch/sys_proto.h> +#include <asm/io.h> + +#define LOCK 0 +#define SPLIT 1 + +#define HALT 0 +#define RELEASE 1 + +#define ZYNQMP_BOOTADDR_HIGH_MASK 0xFFFFFFFF +#define ZYNQMP_R5_HIVEC_ADDR 0xFFFF0000 +#define ZYNQMP_R5_LOVEC_ADDR 0x0 +#define ZYNQMP_RPU_CFG_CPU_HALT_MASK 0x01 +#define ZYNQMP_RPU_CFG_HIVEC_MASK 0x04 +#define ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK 0x08 +#define ZYNQMP_RPU_GLBL_CTRL_TCM_COMB_MASK 0x40 +#define ZYNQMP_RPU_GLBL_CTRL_SLCLAMP_MASK 0x10 + +#define ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK 0x04 +#define ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK 0x01 +#define ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK 0x02 +#define ZYNQMP_CRLAPB_CPU_R5_CTRL_CLKACT_MASK 0x1000000 + +#define ZYNQMP_TCM_START_ADDRESS 0xFFE00000 +#define ZYNQMP_TCM_BOTH_SIZE 0x40000 + +#define ZYNQMP_CORE_APU0 0 +#define ZYNQMP_CORE_APU3 3 + +#define ZYNQMP_MAX_CORES 6 + +int is_core_valid(unsigned int core) +{ + if (core < ZYNQMP_MAX_CORES) + return 1; + + return 0; +} + +int cpu_reset(int nr) +{ + puts("Feature is not implemented.\n"); + return 0; +} + +static void set_r5_halt_mode(u8 halt, u8 mode) +{ + u32 tmp; + + tmp = readl(&rpu_base->rpu0_cfg); + if (halt == HALT) + tmp &= ~ZYNQMP_RPU_CFG_CPU_HALT_MASK; + else + tmp |= ZYNQMP_RPU_CFG_CPU_HALT_MASK; + writel(tmp, &rpu_base->rpu0_cfg); + + if (mode == LOCK) { + tmp = readl(&rpu_base->rpu1_cfg); + if (halt == HALT) + tmp &= ~ZYNQMP_RPU_CFG_CPU_HALT_MASK; + else + tmp |= ZYNQMP_RPU_CFG_CPU_HALT_MASK; + writel(tmp, &rpu_base->rpu1_cfg); + } +} + +static void set_r5_tcm_mode(u8 mode) +{ + u32 tmp; + + tmp = readl(&rpu_base->rpu_glbl_ctrl); + if (mode == LOCK) { + tmp &= ~ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK; + tmp |= ZYNQMP_RPU_GLBL_CTRL_TCM_COMB_MASK | + ZYNQMP_RPU_GLBL_CTRL_SLCLAMP_MASK; + } else { + tmp |= ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK; + tmp &= ~(ZYNQMP_RPU_GLBL_CTRL_TCM_COMB_MASK | + ZYNQMP_RPU_GLBL_CTRL_SLCLAMP_MASK); + } + + writel(tmp, &rpu_base->rpu_glbl_ctrl); +} + +static void set_r5_reset(u8 mode) +{ + u32 tmp; + + tmp = readl(&crlapb_base->rst_lpd_top); + tmp |= (ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK | + ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK); + + if (mode == LOCK) + tmp |= ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK; + + writel(tmp, &crlapb_base->rst_lpd_top); +} + +static void release_r5_reset(u8 mode) +{ + u32 tmp; + + tmp = readl(&crlapb_base->rst_lpd_top); + tmp &= ~(ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK | + ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK); + + if (mode == LOCK) + tmp &= ~ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK; + + writel(tmp, &crlapb_base->rst_lpd_top); +} + +static void enable_clock_r5(void) +{ + u32 tmp; + + tmp = readl(&crlapb_base->cpu_r5_ctrl); + tmp |= ZYNQMP_CRLAPB_CPU_R5_CTRL_CLKACT_MASK; + writel(tmp, &crlapb_base->cpu_r5_ctrl); + + /* Give some delay for clock + * to propogate */ + udelay(0x500); +} + +int cpu_disable(int nr) +{ + if (nr >= ZYNQMP_CORE_APU0 && nr <= ZYNQMP_CORE_APU3) { + u32 val = readl(&crfapb_base->rst_fpd_apu); + val |= 1 << nr; + writel(val, &crfapb_base->rst_fpd_apu); + } else { + set_r5_reset(LOCK); + } + + return 0; +} + +int cpu_status(int nr) +{ + if (nr >= ZYNQMP_CORE_APU0 && nr <= ZYNQMP_CORE_APU3) { + u32 addr_low = readl(((u8 *)&apu_base->rvbar_addr0_l) + nr * 8); + u32 addr_high = readl(((u8 *)&apu_base->rvbar_addr0_h) + + nr * 8); + u32 val = readl(&crfapb_base->rst_fpd_apu); + val &= 1 << nr; + printf("APU CPU%d %s - starting address HI: %x, LOW: %x\n", + nr, val ? "OFF" : "ON" , addr_high, addr_low); + } else { + u32 val = readl(&crlapb_base->rst_lpd_top); + val &= 1 << (nr - 4); + printf("RPU CPU%d %s\n", nr - 4, val ? "OFF" : "ON"); + } + + return 0; +} + +static void set_r5_start(u8 high) +{ + u32 tmp; + + tmp = readl(&rpu_base->rpu0_cfg); + if (high) + tmp |= ZYNQMP_RPU_CFG_HIVEC_MASK; + else + tmp &= ~ZYNQMP_RPU_CFG_HIVEC_MASK; + writel(tmp, &rpu_base->rpu0_cfg); + + tmp = readl(&rpu_base->rpu1_cfg); + if (high) + tmp |= ZYNQMP_RPU_CFG_HIVEC_MASK; + else + tmp &= ~ZYNQMP_RPU_CFG_HIVEC_MASK; + writel(tmp, &rpu_base->rpu1_cfg); +} + +int cpu_release(int nr, int argc, char * const argv[]) +{ + if (nr >= ZYNQMP_CORE_APU0 && nr <= ZYNQMP_CORE_APU3) { + u64 boot_addr = simple_strtoull(argv[0], NULL, 16); + /* HIGH */ + writel((u32)(boot_addr >> 32), + ((u8 *)&apu_base->rvbar_addr0_h) + nr * 8); + /* LOW */ + writel((u32)(boot_addr & ZYNQMP_BOOTADDR_HIGH_MASK), + ((u8 *)&apu_base->rvbar_addr0_l) + nr * 8); + + u32 val = readl(&crfapb_base->rst_fpd_apu); + val &= ~(1 << nr); + writel(val, &crfapb_base->rst_fpd_apu); + } else { + if (argc != 2) { + printf("Invalid number of arguments to release.\n"); + printf("<addr> <mode>-Start addr lockstep or split\n"); + return 1; + } + + u32 boot_addr = simple_strtoul(argv[0], NULL, 16); + if (!(boot_addr == ZYNQMP_R5_LOVEC_ADDR || + boot_addr == ZYNQMP_R5_HIVEC_ADDR)) { + printf("Invalid starting address 0x%x\n", boot_addr); + printf("0 or 0xffff0000 are permitted\n"); + return 1; + } + + if (!strncmp(argv[1], "lockstep", 8)) { + printf("R5 lockstep mode\n"); + set_r5_tcm_mode(LOCK); + set_r5_halt_mode(HALT, LOCK); + + if (boot_addr == 0) + set_r5_start(0); + else + set_r5_start(1); + + enable_clock_r5(); + release_r5_reset(LOCK); + set_r5_halt_mode(RELEASE, LOCK); + } else if (!strncmp(argv[1], "split", 5)) { + printf("R5 split mode\n"); + set_r5_tcm_mode(SPLIT); + set_r5_halt_mode(HALT, SPLIT); + enable_clock_r5(); + release_r5_reset(SPLIT); + set_r5_halt_mode(RELEASE, SPLIT); + } else { + printf("Unsupported mode\n"); + return 1; + } + } + + return 0; +} diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h index 37f9a7d0719e..c9dc49d78317 100644 --- a/arch/arm/include/asm/arch-zynqmp/hardware.h +++ b/arch/arm/include/asm/arch-zynqmp/hardware.h @@ -24,11 +24,15 @@ #define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1000000 struct crlapb_regs { - u32 reserved0[74]; + u32 reserved0[36]; + u32 cpu_r5_ctrl; /* 0x90 */ + u32 reserved1[37]; u32 timestamp_ref_ctrl; /* 0x128 */ - u32 reserved0_1[53]; + u32 reserved2[53]; u32 boot_mode; /* 0x200 */ - u32 reserved1[26]; + u32 reserved3[14]; + u32 rst_lpd_top; /* 0x23C */ + u32 reserved4[26]; }; #define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR) @@ -51,6 +55,39 @@ struct iou_scntr { #define EMMC_MODE 0x00000006 #define JTAG_MODE 0x00000000 +#define ZYNQMP_RPU_BASEADDR 0xFF9A0000 + +struct rpu_regs { + u32 rpu_glbl_ctrl; + u32 reserved0[63]; + u32 rpu0_cfg; /* 0x100 */ + u32 reserved1[63]; + u32 rpu1_cfg; /* 0x200 */ +}; + +#define rpu_base ((struct rpu_regs *)ZYNQMP_RPU_BASEADDR) + +#define ZYNQMP_CRF_APB_BASEADDR 0xFD1A0000 + +struct crfapb_regs { + u32 reserved0[65]; + u32 rst_fpd_apu; /* 0x104 */ + u32 reserved1; +}; + +#define crfapb_base ((struct crfapb_regs *)ZYNQMP_CRF_APB_BASEADDR) + +#define ZYNQMP_APU_BASEADDR 0xFD5C0000 + +struct apu_regs { + u32 reserved0[16]; + u32 rvbar_addr0_l; /* 0x40 */ + u32 rvbar_addr0_h; /* 0x44 */ + u32 reserved1[20]; +}; + +#define apu_base ((struct apu_regs *)ZYNQMP_APU_BASEADDR) + /* Board version value */ #define ZYNQMP_CSU_VERSION_SILICON 0x0 #define ZYNQMP_CSU_VERSION_EP108 0x1 diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 4c48f9449f02..6c608abfb9bb 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -71,6 +71,8 @@ #define CONFIG_CMD_FS_GENERIC #define CONFIG_CMD_MEMORY #define CONFIG_DOS_PARTITION +#define CONFIG_CMD_ELF +#define CONFIG_MP /* SPI */ #ifdef CONFIG_ZYNQ_SPI -- 2.3.5

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[U-Boot] [PATCH] zynqmp: caches: Enable dcache for zynqmp
by Michal Simek 15 Apr '15

15 Apr '15

From: Siva Durga Prasad Paladugu <siva.durga.paladugu(a)xilinx.com> Define the mmu table till 2MB granularity enable dcaches for zynqmp. Signed-off-by: Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- arch/arm/cpu/armv8/zynqmp/cpu.c | 164 ++++++++++++++++++++++++++++++++++++++++ include/configs/xilinx_zynqmp.h | 2 +- 2 files changed, 165 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv8/zynqmp/cpu.c b/arch/arm/cpu/armv8/zynqmp/cpu.c index 79e6ff591bb4..60d7d20e17c8 100644 --- a/arch/arm/cpu/armv8/zynqmp/cpu.c +++ b/arch/arm/cpu/armv8/zynqmp/cpu.c @@ -28,3 +28,167 @@ unsigned int zynqmp_get_silicon_version(void) return ZYNQMP_CSU_VERSION_EP108; } + +#ifndef CONFIG_SYS_DCACHE_OFF +#include <asm/armv8/mmu.h> + +#define SECTION_SHIFT_L1 30UL +#define SECTION_SHIFT_L2 21UL +#define BLOCK_SIZE_L0 0x8000000000UL +#define BLOCK_SIZE_L1 (1 << SECTION_SHIFT_L1) +#define BLOCK_SIZE_L2 (1 << SECTION_SHIFT_L2) + +#define TCR_TG1_4K (1 << 31) +#define TCR_EPD1_DISABLE (1 << 23) +#define ZYNQMO_VA_BITS 40 +#define ZYNQMP_TCR TCR_TG1_4K | \ + TCR_EPD1_DISABLE | \ + TCR_SHARED_OUTER | \ + TCR_SHARED_INNER | \ + TCR_IRGN_WBWA | \ + TCR_ORGN_WBWA | \ + TCR_T0SZ(ZYNQMO_VA_BITS) + +#define MEMORY_ATTR PMD_SECT_AF | PMD_SECT_INNER_SHARE | \ + PMD_ATTRINDX(MT_NORMAL) | \ + PMD_TYPE_SECT +#define DEVICE_ATTR PMD_SECT_AF | PMD_SECT_PXN | \ + PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_NGNRNE) | \ + PMD_TYPE_SECT + +/* 4K size is required to place 512 entries in each level */ +#define TLB_TABLE_SIZE 0x1000 + +struct attr_tbl { + u32 num; + u64 attr; +}; + +static struct attr_tbl attr_tbll1t0[4] = { {16, 0x0}, + {8, DEVICE_ATTR}, + {32, MEMORY_ATTR}, + {456, DEVICE_ATTR} + }; +static struct attr_tbl attr_tbll2t3[4] = { {0x180, DEVICE_ATTR}, + {0x40, 0x0}, + {0x3F, DEVICE_ATTR}, + {0x1, MEMORY_ATTR} + }; + +/* + * This mmu table looks as below + * Level 0 table contains two entries to 512GB sizes. One is Level1 Table 0 + * and other Level1 Table1. + * Level1 Table0 contains entries for each 1GB from 0 to 511GB. + * Level1 Table1 contains entries for each 1GB from 512GB to 1TB. + * Level2 Table0, Level2 Table1, Level2 Table2 and Level2 Table3 contains + * entries for each 2MB starting from 0GB, 1GB, 2GB and 3GB respectively. + */ +static void zynqmp_mmu_setup(void) +{ + int el; + u32 index_attr; + u64 i, section_l1t0, section_l1t1; + u64 section_l2t0, section_l2t1, section_l2t2, section_l2t3; + u64 *level0_table = (u64 *)gd->arch.tlb_addr; + u64 *level1_table_0 = (u64 *)(gd->arch.tlb_addr + TLB_TABLE_SIZE); + u64 *level1_table_1 = (u64 *)(gd->arch.tlb_addr + (2 * TLB_TABLE_SIZE)); + u64 *level2_table_0 = (u64 *)(gd->arch.tlb_addr + (3 * TLB_TABLE_SIZE)); + u64 *level2_table_1 = (u64 *)(gd->arch.tlb_addr + (4 * TLB_TABLE_SIZE)); + u64 *level2_table_2 = (u64 *)(gd->arch.tlb_addr + (5 * TLB_TABLE_SIZE)); + u64 *level2_table_3 = (u64 *)(gd->arch.tlb_addr + (6 * TLB_TABLE_SIZE)); + + level0_table[0] = + (u64)level1_table_0 | PMD_TYPE_TABLE; + level0_table[1] = + (u64)level1_table_1 | PMD_TYPE_TABLE; + + /* + * set level 1 table 0, covering 0 to 512GB + * set level 1 table 1, covering 512GB to 1TB + */ + section_l1t0 = 0; + section_l1t1 = BLOCK_SIZE_L0; + + index_attr = 0; + for (i = 0; i < 512; i++) { + level1_table_0[i] = section_l1t0; + level1_table_0[i] |= attr_tbll1t0[index_attr].attr; + attr_tbll1t0[index_attr].num--; + if (attr_tbll1t0[index_attr].num == 0) + index_attr++; + level1_table_1[i] = section_l1t1; + level1_table_1[i] |= DEVICE_ATTR; + section_l1t0 += BLOCK_SIZE_L1; + section_l1t1 += BLOCK_SIZE_L1; + } + + level1_table_0[0] = + (u64)level2_table_0 | PMD_TYPE_TABLE; + level1_table_0[1] = + (u64)level2_table_1 | PMD_TYPE_TABLE; + level1_table_0[2] = + (u64)level2_table_2 | PMD_TYPE_TABLE; + level1_table_0[3] = + (u64)level2_table_3 | PMD_TYPE_TABLE; + + section_l2t0 = 0; + section_l2t1 = section_l2t0 + BLOCK_SIZE_L1; /* 1GB */ + section_l2t2 = section_l2t1 + BLOCK_SIZE_L1; /* 2GB */ + section_l2t3 = section_l2t2 + BLOCK_SIZE_L1; /* 3GB */ + + index_attr = 0; + + for (i = 0; i < 512; i++) { + level2_table_0[i] = section_l2t0 | MEMORY_ATTR; + level2_table_1[i] = section_l2t1 | MEMORY_ATTR; + level2_table_2[i] = section_l2t2 | DEVICE_ATTR; + level2_table_3[i] = section_l2t3 | + attr_tbll2t3[index_attr].attr; + attr_tbll2t3[index_attr].num--; + if (attr_tbll2t3[index_attr].num == 0) + index_attr++; + section_l2t0 += BLOCK_SIZE_L2; + section_l2t1 += BLOCK_SIZE_L2; + section_l2t2 += BLOCK_SIZE_L2; + section_l2t3 += BLOCK_SIZE_L2; + } + + /* flush new MMU table */ + flush_dcache_range(gd->arch.tlb_addr, + gd->arch.tlb_addr + gd->arch.tlb_size); + + /* point TTBR to the new table */ + el = current_el(); + set_ttbr_tcr_mair(el, gd->arch.tlb_addr, + ZYNQMP_TCR, MEMORY_ATTRIBUTES); + + set_sctlr(get_sctlr() | CR_M); +} + +int arch_cpu_init(void) +{ + icache_enable(); + __asm_invalidate_dcache_all(); + __asm_invalidate_tlb_all(); + return 0; +} + +/* + * This function is called from lib/board.c. + * It recreates MMU table in main memory. MMU and d-cache are enabled earlier. + * There is no need to disable d-cache for this operation. + */ +void enable_caches(void) +{ + /* The data cache is not active unless the mmu is enabled */ + if (!(get_sctlr() & CR_M)) { + invalidate_dcache_all(); + __asm_invalidate_tlb_all(); + zynqmp_mmu_setup(); + } + puts("Enabling Caches...\n"); + + set_sctlr(get_sctlr() | CR_C); +} +#endif diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 2f00b417809e..6c608abfb9bb 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -36,7 +36,7 @@ #define CPU_RELEASE_ADDR 0xFFFFFF0 /* Cache Definitions */ -#define CONFIG_SYS_DCACHE_OFF +#define CONFIG_SYS_CACHELINE_SIZE 64 #define CONFIG_IDENT_STRING " Xilinx ZynqMP" -- 2.3.5

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[U-Boot] [RESEND PATCH] f_thor: Dont perform reset at the end of thor
by Michal Simek 15 Apr '15

15 Apr '15

From: Siva Durga Prasad Paladugu <siva.durga.paladugu(a)xilinx.com> Dont perform reset at the end of thor download if configured to do reset off. Reset may not be required in all cases and hence provided an option to do so. Signed-off-by: Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- drivers/usb/gadget/f_thor.c | 7 +++++++ drivers/usb/gadget/f_thor.h | 3 +++ 2 files changed, 10 insertions(+) diff --git a/drivers/usb/gadget/f_thor.c b/drivers/usb/gadget/f_thor.c index e9a690eff5f1..5c8f6768519c 100644 --- a/drivers/usb/gadget/f_thor.c +++ b/drivers/usb/gadget/f_thor.c @@ -123,6 +123,9 @@ static int process_rqt_cmd(const struct rqt_box *rqt) send_rsp(rsp); g_dnl_unregister(); dfu_free_entities(); +#ifdef CONFIG_THOR_RESET_OFF + return RESET_DONE; +#endif run_command("reset", 0); break; case RQT_CMD_POWEROFF: @@ -728,6 +731,10 @@ int thor_handle(void) if (ret > 0) { ret = process_data(); +#ifdef CONFIG_THOR_RESET_OFF + if (ret == RESET_DONE) + break; +#endif if (ret < 0) return ret; } else { diff --git a/drivers/usb/gadget/f_thor.h b/drivers/usb/gadget/f_thor.h index 833a9d24ae7e..83412851dd17 100644 --- a/drivers/usb/gadget/f_thor.h +++ b/drivers/usb/gadget/f_thor.h @@ -121,4 +121,7 @@ struct f_thor { #define F_NAME_BUF_SIZE 32 #define THOR_PACKET_SIZE SZ_1M /* 1 MiB */ #define THOR_STORE_UNIT_SIZE SZ_32M /* 32 MiB */ +#ifdef CONFIG_THOR_RESET_OFF +#define RESET_DONE 0xFFFFFFFF +#endif #endif /* _USB_THOR_H_ */ -- 2.3.5

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