April 2015 - U-Boot

[U-Boot] [PATCH] video, ipu: make ldb clock frequenz overwriteable through board code
by Heiko Schocher 17 Apr '15

17 Apr '15

the ldb clock can be setup in board code (for example set through PLL5). Update the ldb_clock rate also through board code. This should be removed, if a clock framework is availiable. Signed-off-by: Heiko Schocher <hs(a)denx.de> --- drivers/video/ipu.h | 1 + drivers/video/ipu_common.c | 11 +++++++++++ 2 files changed, 12 insertions(+) diff --git a/drivers/video/ipu.h b/drivers/video/ipu.h index 091b58f..f13934f 100644 --- a/drivers/video/ipu.h +++ b/drivers/video/ipu.h @@ -266,4 +266,5 @@ void ipu_dp_uninit(ipu_channel_t channel); void ipu_dp_dc_disable(ipu_channel_t channel, unsigned char swap); ipu_color_space_t format_to_colorspace(uint32_t fmt); +int ipu_set_ldb_clock(int rate); #endif diff --git a/drivers/video/ipu_common.c b/drivers/video/ipu_common.c index 1a209d4..dc054bc 100644 --- a/drivers/video/ipu_common.c +++ b/drivers/video/ipu_common.c @@ -1198,3 +1198,14 @@ ipu_color_space_t format_to_colorspace(uint32_t fmt) } return RGB; } + +/* should removed when clk framework is availiable */ +int ipu_set_ldb_clock(int rate) +{ + if (g_ldb_clk == NULL) + return -ENOENT; + + g_ldb_clk->rate = rate; + + return 0; +} -- 2.1.0

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[U-Boot] Compile minnowboard max error
by li yuqian 17 Apr '15

17 Apr '15

Hi I am trying compiling uboot for the Minnowboard MAX, but always got following error --------------------Output file is too small. (8388608 < -2138725469) Makefile:1037: recipe for target 'u-boot.rom' failed make: *** [u-boot.rom] Error 1-------------------- is this a bug ? i used git master version. Thank you

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[U-Boot] U-Boot
by wehner.junior＠googlemail.com 17 Apr '15

17 Apr '15

Hello, I want to add a fixed phy connection to describe the rgmii interface between a cpu and an ethernet switch. What is the recommended way over the phylib? Kind regards, Mark

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[U-Boot] Commit d3cfcb3 breaks beagle_x15 build
by Albert ARIBAUD 17 Apr '15

17 Apr '15

Hello, Commit d3cfcb3 (ARM: DRA7: Enable clocks for USB OTGSS and USB PHY) breaks beagle_x15 build: Building current source for 1 boards (1 thread, 8 jobs per thread) arm: + beagle_x15 +board/ti/beagle_x15/board.c: In function 'board_usb_init': +board/ti/beagle_x15/board.c:393:1: error: 'const struct prcm_regs' has no member named 'cm_l3init_usb_otg_ss_clkctrl' +make[2]: *** [board/ti/beagle_x15/board.o] Error 1 +make[1]: *** [board/ti/beagle_x15] Error 2 +make: *** [sub-make] Error 2 Cc:ing the committer and author. Kishon, can you look into this? Amicalement, -- Albert.

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[U-Boot] [PATCH] sf: Poll both the read status and flag status
by Siva Durga Prasad Paladugu 17 Apr '15

17 Apr '15

Poll both the Read status and Flag status registers for sucessful erase and program operations for the Micron devices with E_FSR flag set in params table. Signed-off-by: Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> --- drivers/mtd/spi/sf_ops.c | 32 +++++++++++++++++++++++++------- 1 file changed, 25 insertions(+), 7 deletions(-) diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c index 34bc54e..38592f5 100644 --- a/drivers/mtd/spi/sf_ops.c +++ b/drivers/mtd/spi/sf_ops.c @@ -154,21 +154,17 @@ static void spi_flash_dual_flash(struct spi_flash *flash, u32 *addr) } #endif -int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout) +static int spi_flash_poll_status(struct spi_slave *spi, unsigned long timeout, + u8 cmd, u8 poll_bit) { - struct spi_slave *spi = flash->spi; unsigned long timebase; unsigned long flags = SPI_XFER_BEGIN; int ret; u8 status; u8 check_status = 0x0; - u8 poll_bit = STATUS_WIP; - u8 cmd = flash->poll_cmd; - if (cmd == CMD_FLAG_STATUS) { - poll_bit = STATUS_PEC; + if (cmd == CMD_FLAG_STATUS) check_status = poll_bit; - } #ifdef CONFIG_SF_DUAL_FLASH if (spi->flags & SPI_XFER_U_PAGE) @@ -204,6 +200,28 @@ int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout) return -1; } +int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout) +{ + struct spi_slave *spi = flash->spi; + int ret; + u8 poll_bit = STATUS_WIP; + u8 cmd = CMD_READ_STATUS; + + ret = spi_flash_poll_status(spi, timeout, cmd, poll_bit); + if (ret < 0) + return ret; + + if (flash->poll_cmd == CMD_FLAG_STATUS) { + poll_bit = STATUS_PEC; + cmd = CMD_FLAG_STATUS; + ret = spi_flash_poll_status(spi, timeout, cmd, poll_bit); + if (ret < 0) + return ret; + } + + return 0; +} + int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd, size_t cmd_len, const void *buf, size_t buf_len) { -- 2.1.1

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[U-Boot] [PATCH] sf: Correct the macros as per new array fast read command
by Siva Durga Prasad Paladugu 17 Apr '15

17 Apr '15

Correct the macros as per insertion of array fast read command CMD_READ_ARRAY_FAST in spi_read_cmds_array in file sf_probe.c Signed-off-by: Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> --- include/spi.h | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/include/spi.h b/include/spi.h index c58e453..7829063 100644 --- a/include/spi.h +++ b/include/spi.h @@ -38,11 +38,12 @@ /* SPI RX operation modes */ #define SPI_OPM_RX_AS (1 << 0) -#define SPI_OPM_RX_DOUT (1 << 1) -#define SPI_OPM_RX_DIO (1 << 2) -#define SPI_OPM_RX_QOF (1 << 3) -#define SPI_OPM_RX_QIOF (1 << 4) -#define SPI_OPM_RX_EXTN (SPI_OPM_RX_AS | SPI_OPM_RX_DOUT | \ +#define SPI_OPM_RX_AF (1 << 1) +#define SPI_OPM_RX_DOUT (1 << 2) +#define SPI_OPM_RX_DIO (1 << 3) +#define SPI_OPM_RX_QOF (1 << 4) +#define SPI_OPM_RX_QIOF (1 << 5) +#define SPI_OPM_RX_EXTN (SPI_OPM_RX_AS | SPI_OPM_RX_AF | SPI_OPM_RX_DOUT | \ SPI_OPM_RX_DIO | SPI_OPM_RX_QOF | \ SPI_OPM_RX_QIOF) -- 2.1.1

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[U-Boot] [PATCH] zynq: spi: Remove unnecessary error condition
by Michal Simek 17 Apr '15

17 Apr '15

From: Siva Durga Prasad Paladugu <siva.durga.paladugu(a)xilinx.com> Removed the unnecessary error check from spi_xfer as the bitlen zero is possible now to deassert the chip select for which no data is required to be transfered. Signed-off-by: Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- drivers/spi/zynq_spi.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c index 5da87591ceef..e9129da79d99 100644 --- a/drivers/spi/zynq_spi.c +++ b/drivers/spi/zynq_spi.c @@ -227,9 +227,6 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, debug("spi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n", slave->bus, slave->cs, bitlen, len, flags); - if (bitlen == 0) - return -1; - if (bitlen % 8) { debug("spi_xfer: Non byte aligned SPI transfer\n"); return -1; -- 2.3.5

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[U-Boot] [ANN] U-Boot v2015.04 released
by Tom Rini 17 Apr '15

17 Apr '15

Hey all, I've pushed v2015.04 out to the repository and tarballs should exist soon. The Kconfig migration is moving along nicely as is the DM work. This has been a good all-around nice set of updates, bug fixes and new board and feature support. Two last things, to repeat what I said last release. First, really, we're going to deprecate and then remove MAKEALL. If you've got a use-case that's not working with buildman please start yelling now so that we can get it addressed (and note that there's stuff ready to come in once the merge window is open). Second, we really are removing boards that don't support CONFIG_SYS_GENERIC_BOARD. Many have been dropped and some haven't yet only because the patches to do so caused some other people to speak up and maintain similar platforms. And I would encourage custodians to follow-up with anything big I've overlooked. Thanks for the hard work everyone! The merge window is now open and will close on Saturday May 2nd. -- Tom

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[U-Boot] [PATCH v2 4/4] powerpc/t2080qds: enable eSDHC peripheral clock support for kernel
by Yangbo Lu 17 Apr '15

17 Apr '15

Enable eSDHC peripheral clock support for kernel, and linux will use SD clock generated by peripheral clock instead of platform clock. Signed-off-by: Yangbo Lu <yangbo.lu(a)freescale.com> Cc: York Sun <yorksun(a)freescale.com> --- include/configs/T208xQDS.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 8d6918a..ea8f89a 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -757,6 +757,7 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_MMC #define CONFIG_CMD_MMC #define CONFIG_FSL_ESDHC +#define define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 -- 2.1.0.27.g96db324

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[U-Boot] [PATCH v2 3/4] mmc: fsl_esdhc: Add peripheral clock support for kernel
by Yangbo Lu 17 Apr '15

17 Apr '15

The SD clock could be generated by platform clock or peripheral clock for some platforms. This patch adds peripheral clock support for kernel for T1024/T1040/T2080. To enable it, define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK. Signed-off-by: Yangbo Lu <yangbo.lu(a)freescale.com> Cc: York Sun <yorksun(a)freescale.com> --- arch/powerpc/cpu/mpc85xx/speed.c | 49 ++++++++++++++++++++++++++++++- arch/powerpc/include/asm/config_mpc85xx.h | 10 +++++-- drivers/mmc/fsl_esdhc.c | 5 ++++ include/e500.h | 1 + 4 files changed, 62 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 7e69873..79202bb 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -69,7 +69,8 @@ void get_sys_info(sys_info_t *sys_info) [14] = 4, /* CC4 PPL / 4 */ }; uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS]; -#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) +#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) || \ + defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK) uint rcw_tmp; #endif uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS]; @@ -313,6 +314,48 @@ void get_sys_info(sys_info_t *sys_info) #endif #endif +#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK +#if defined(CONFIG_PPC_T2080) +#define ESDHC_CLK_SEL 0x00000007 +#define ESDHC_CLK_SHIFT 0 +#define ESDHC_CLK_RCWSR 15 +#else /* Support T1040 T1024 by now */ +#define ESDHC_CLK_SEL 0xe0000000 +#define ESDHC_CLK_SHIFT 29 +#define ESDHC_CLK_RCWSR 7 +#endif + rcw_tmp = in_be32(&gur->rcwsr[ESDHC_CLK_RCWSR]); + switch ((rcw_tmp & ESDHC_CLK_SEL) >> ESDHC_CLK_SHIFT) { + case 1: + sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK]; + break; + case 2: + sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 2; + break; + case 3: + sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 3; + break; +#if defined(CONFIG_SYS_SDHC_CLK_2_PLL) + case 4: + sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 4; + break; +#if defined(CONFIG_PPC_T2080) + case 5: + sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK]; + break; +#endif + case 6: + sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK] / 2; + break; + case 7: + sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK] / 3; + break; +#endif + default: + sys_info->freq_sdhc = 0; + printf("Error: Unknown SDHC peripheral clock select!\n"); + } +#endif #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) { @@ -520,12 +563,16 @@ int get_clocks (void) gd->arch.i2c2_clk = gd->arch.i2c1_clk; #if defined(CONFIG_FSL_ESDHC) +#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK + gd->arch.sdhc_clk = sys_info.freq_sdhc / 2; +#else #if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\ defined(CONFIG_P1014) gd->arch.sdhc_clk = gd->bus_clk; #else gd->arch.sdhc_clk = gd->bus_clk / 2; #endif +#endif #endif /* defined(CONFIG_FSL_ESDHC) */ #if defined(CONFIG_CPM2) diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 01b0905..24c593b 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -757,7 +757,6 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #endif #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } -#define CONFIG_SYS_SDHC_CLOCK 0 #define CONFIG_SYS_FSL_NUM_LAWS 16 #define CONFIG_SYS_FSL_SRDS_1 #define CONFIG_SYS_FSL_SEC_COMPAT 5 @@ -773,6 +772,9 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define CONFIG_SYS_FMAN_V3 #define CONFIG_FM_PLAT_CLK_DIV 1 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV +#define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1 + per rcw field value */ +#define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */ #define CONFIG_SYS_FM_MURAM_SIZE 0x30000 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK #define CONFIG_SYS_FSL_TBCLK_DIV 16 @@ -805,7 +807,6 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) #endif #define CONFIG_SYS_FSL_NUM_CC_PLL 2 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } -#define CONFIG_SYS_SDHC_CLOCK 0 #define CONFIG_SYS_FSL_NUM_LAWS 16 #define CONFIG_SYS_FSL_SRDS_1 #define CONFIG_SYS_FSL_SEC_COMPAT 5 @@ -818,6 +819,8 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_SYS_FM1_CLK 0 +#define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1 + per rcw field value */ #define CONFIG_QBMAN_CLK_DIV 1 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK @@ -865,6 +868,9 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) #define CONFIG_PME_PLAT_CLK_DIV 1 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV #define CONFIG_SYS_FM1_CLK 0 +#define CONFIG_SYS_SDHC_CLK 1/* Select SDHC CLK begining from PLL2 + per rcw field value */ +#define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */ #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_SYS_FMAN_V3 diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 355cada..8dea365 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -689,8 +689,13 @@ void fdt_fixup_esdhc(void *blob, bd_t *bd) } #endif +#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK + do_fixup_by_compat_u32(blob, compat, "peripheral-frequency", + gd->arch.sdhc_clk, 1); +#else do_fixup_by_compat_u32(blob, compat, "clock-frequency", gd->arch.sdhc_clk, 1); +#endif #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT do_fixup_by_compat_u32(blob, compat, "adapter-type", (u32)(gd->arch.sdhc_adapter), 1); diff --git a/include/e500.h b/include/e500.h index 5884a22..07d0ee8 100644 --- a/include/e500.h +++ b/include/e500.h @@ -15,6 +15,7 @@ typedef struct unsigned long freq_ddrbus; unsigned long freq_localbus; unsigned long freq_qe; + unsigned long freq_sdhc; #ifdef CONFIG_SYS_DPAA_FMAN unsigned long freq_fman[CONFIG_SYS_NUM_FMAN]; #endif -- 2.1.0.27.g96db324

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