April 2015 - U-Boot

[U-Boot] [PATCH v2 0/6] Add support for Colibri Vybrid Modules
by Sanchayan Maity 15 Apr '15

15 Apr '15

Hello, This is the second version of the patchset which adds support for the Toradex Colibri Vybrid VF50 and VF61 modules. Boot up has been tested using the serial loader over UART. First patch in the series refactors the DDR related code for use by both the tower board and colibri modules. It also introduces a DDR3 based JEDEC timing structure. Second third and fourth patch in this series are improvement patches related to RTC, SoC/CPU detection and caches. Fifth patch introduces USB support for Vybrid modules. Much of the code is similar to the ehci-mx6 driver. One open question here would be is there a better way to take care of this similarity and perhaps share the code base among the two drivers? Both host and client modes are working and DFU has also been tested. Currently, we restrict the ports to be in one of host and client mode. Sixth patch adds the actual support for the Colibri modules. Comments and feedback are most welcome. The patchset is based and tested on the latest master branch as of this writing. Discussion on the version 1 of the patchset can be found at the below link: https://www.mail-archive.com/u-boot@lists.denx.de/msg168136.html Changes since v1: - Rework the USB driver to use register offsets using the regular struct {} method - Some cleanups and fixes in the sixth patch for the colibri_vf.h file which takes care of environment variables in uboot - Purge some useless defines in the fifth and sixth patch which were related to USB. - Sanchayan. Sanchayan Maity (4): ARM: vf610: Move DDR3 initialization to imx-common ARM: vf610: Add SoC and CPU type detection usb: host: Add ehci-vf USB driver for ARM Vybrid SoC's ARM: vf610: Initial integration for Colibri VF50/VF61 Stefan Agner (2): ARM: vf610: Enable external 32KHz oscillator ARM: vf610: Enable caches arch/arm/Kconfig | 5 + arch/arm/cpu/armv7/vf610/generic.c | 45 ++- arch/arm/imx-common/Makefile | 3 + arch/arm/imx-common/ddrmc-vf610.c | 278 ++++++++++++++++++ arch/arm/include/asm/arch-vf610/crm_regs.h | 11 + arch/arm/include/asm/arch-vf610/ddrmc-vf610.h | 72 +++++ arch/arm/include/asm/arch-vf610/imx-regs.h | 36 ++- arch/arm/include/asm/arch-vf610/regs-usbphy.h | 31 +++ board/freescale/vf610twr/vf610twr.c | 295 +++++--------------- board/toradex/colibri_vf/Kconfig | 18 ++ board/toradex/colibri_vf/MAINTAINERS | 6 + board/toradex/colibri_vf/Makefile | 7 + board/toradex/colibri_vf/colibri_vf.c | 387 ++++++++++++++++++++++++++ board/toradex/colibri_vf/imximage.cfg | 17 ++ configs/colibri_vf_defconfig | 3 + drivers/usb/host/Makefile | 1 + drivers/usb/host/ehci-vf.c | 196 +++++++++++++ include/configs/colibri_vf.h | 271 ++++++++++++++++++ 18 files changed, 1447 insertions(+), 235 deletions(-) create mode 100644 arch/arm/imx-common/ddrmc-vf610.c create mode 100644 arch/arm/include/asm/arch-vf610/ddrmc-vf610.h create mode 100644 arch/arm/include/asm/arch-vf610/regs-usbphy.h create mode 100644 board/toradex/colibri_vf/Kconfig create mode 100644 board/toradex/colibri_vf/MAINTAINERS create mode 100644 board/toradex/colibri_vf/Makefile create mode 100644 board/toradex/colibri_vf/colibri_vf.c create mode 100644 board/toradex/colibri_vf/imximage.cfg create mode 100644 configs/colibri_vf_defconfig create mode 100644 drivers/usb/host/ehci-vf.c create mode 100644 include/configs/colibri_vf.h -- 2.3.5

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[U-Boot] [PATCH v2 0/4] mtd: nand: mxs: Calculate ECC strength dynamically
by Jörg Krause 15 Apr '15

15 Apr '15

This series of patches are based on the patch of Peng Fan: https://patchwork.ozlabs.org/patch/422756/ Patch 1 is the originally patch from Peng Fan, Patch 2 and 3 add minor changes to 1 and patch 4 adds the ECC strength calculation to tools/mxsboot to be aligned with the changes made in patch 1 to 3. Instead of hard-coding every possible oob size / ECC strength combination calculate the ECC strength dynamically to be aligned with the Linux Kernel MTD NAND driver. Also adds the calculation to tools/mxsboot to be aligned with the U-Boot MTD NAND driver. Obviously, we have some code redundancy here in mxs_nand.c and mxsboot.c. Jörg Krause (3): mtd: nand: mxs: Replace magic number for bits per ECC level with macro mtd: nand: mxs: Add comment for calculating ECC strength tools: mxsboot: Calculate ECC strength dynamically Peng Fan (1): mtd:mxs:nand calculate ecc strength dynamically drivers/mtd/nand/mxs_nand.c | 36 +++++++++++++++--------------------- tools/mxsboot.c | 39 ++++++++++++++++++++++++--------------- 2 files changed, 39 insertions(+), 36 deletions(-) -- 2.3.5

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[U-Boot] Is patchwork down?
by Simon Glass 15 Apr '15

15 Apr '15

Hi, I don't see mailing list patches appearing as normal on patchwork. Regards, Simon

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[U-Boot] [PATCH] net: pch_gbe: Fix pch_gbe device name
by Bin Meng 15 Apr '15

15 Apr '15

The name "pch_gbe.%x" exceeds the limit of the name in the 'struct eth_device'. Rename it as just "pch_gbe". Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- drivers/net/pch_gbe.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/pch_gbe.c b/drivers/net/pch_gbe.c index 976848d..6c7b551 100644 --- a/drivers/net/pch_gbe.c +++ b/drivers/net/pch_gbe.c @@ -446,7 +446,7 @@ int pch_gbe_register(bd_t *bis) dev->iobase = iobase; priv->mac_regs = (struct pch_gbe_regs *)iobase; - sprintf(dev->name, "pch_gbe.%x", iobase); + sprintf(dev->name, "pch_gbe"); /* Read MAC address from SROM and initialize dev->enetaddr with it */ pch_gbe_mac_read(priv->mac_regs, dev->enetaddr); -- 1.8.2.1

1 0

[U-Boot] [PATCH] net: pch_gbe: Fix pch_gbe device name
by Bin Meng 15 Apr '15

15 Apr '15

The name "pch_gbe.%x" exceeds the limit of the name in the 'struct eth_device'. Rename it as just "pch_gbe". Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- drivers/net/pch_gbe.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/pch_gbe.c b/drivers/net/pch_gbe.c index 976848d..6c7b551 100644 --- a/drivers/net/pch_gbe.c +++ b/drivers/net/pch_gbe.c @@ -446,7 +446,7 @@ int pch_gbe_register(bd_t *bis) dev->iobase = iobase; priv->mac_regs = (struct pch_gbe_regs *)iobase; - sprintf(dev->name, "pch_gbe.%x", iobase); + sprintf(dev->name, "pch_gbe"); /* Read MAC address from SROM and initialize dev->enetaddr with it */ pch_gbe_mac_read(priv->mac_regs, dev->enetaddr); -- 1.8.2.1

1 0

[U-Boot] [PATCH] patman: check git format.subjectprefix setting when generate patches prefix
by Josh Wu 15 Apr '15

15 Apr '15

For the local project, we may specified format.subjectprefix setting. Then the patch will be formated as [Project_prefix][PATCH]. But patman will not check this setting. It will remove the format.subjectprefix. So This patch will let patman check this setting and add it as a project prefix. Signed-off-by: Josh Wu <josh.wu(a)atmel.com> --- tools/patman/gitutil.py | 11 +++++++++++ tools/patman/series.py | 8 +++++++- 2 files changed, 18 insertions(+), 1 deletion(-) diff --git a/tools/patman/gitutil.py b/tools/patman/gitutil.py index 4c2c35b..9e739d8 100644 --- a/tools/patman/gitutil.py +++ b/tools/patman/gitutil.py @@ -545,6 +545,17 @@ def GetDefaultUserEmail(): uemail = command.OutputOneLine('git', 'config', '--global', 'user.email') return uemail +def GetDefaultSubjectPrefix(): + """Gets the format.subjectprefix from local .git/config file. + + Returns: + Subject prefix found in local .git/config file, or None if none + """ + sub_prefix = command.OutputOneLine('git', 'config', 'format.subjectprefix', + raise_on_error=False) + + return sub_prefix + def Setup(): """Set up git utils, by reading the alias files.""" # Check for a git alias file also diff --git a/tools/patman/series.py b/tools/patman/series.py index 60ebc76..a17a7d1 100644 --- a/tools/patman/series.py +++ b/tools/patman/series.py @@ -254,6 +254,12 @@ class Series(dict): Return: Patch string, like 'RFC PATCH v5' or just 'PATCH' """ + git_prefix = gitutil.GetDefaultSubjectPrefix() + if git_prefix: + git_prefix = '%s][' % git_prefix + else: + git_prefix = '' + version = '' if self.get('version'): version = ' v%s' % self['version'] @@ -262,4 +268,4 @@ class Series(dict): prefix = '' if self.get('prefix'): prefix = '%s ' % self['prefix'] - return '%sPATCH%s' % (prefix, version) + return '%s%sPATCH%s' % (git_prefix, prefix, version) -- 1.9.1

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[U-Boot] [PATCH V2] ARM: tegra: enable STDIO deregistration
by Stephen Warren 15 Apr '15

15 Apr '15

From: Stephen Warren <swarren(a)nvidia.com> At the very least when USB keyboard support is enabled, we need to enable CONFIG_SYS_STDIO_DEREGISTER, so the "usb reset" is able to re-scan USB ports and find new devices. Enable it everywhere per request from Simon Glass. Signed-off-by: Stephen Warren <swarren(a)nvidia.com> --- v2: Always enable the option, and hence do so in a different file. Since v1 missed the v2015.04 release, here's v2 that implements the "post release" request from Simon right from the get-go. --- include/configs/tegra-common.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 2cf1f68404b1..7ae179235484 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -89,6 +89,9 @@ #define CONFIG_CONSOLE_MUX #define CONFIG_SYS_CONSOLE_IS_IN_ENV +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_STDIO_DEREGISTER +#endif /* * Miscellaneous configurable options -- 1.9.1

2 1

[U-Boot] [PATCH v3 1/3] dm: usb: Move descriptor setup code into its own function
by Simon Glass 14 Apr '15

14 Apr '15

usb_new_device() is far too long and does far too much. As a first step, move the code that does initial setup and reads a descriptor into its own function called usb_setup_descriptor(). For XHCI the init order is different - we set up the device but don't actually read the descriptor until after we set an address. Support this option as a parameter to usb_setup_descriptor(). Avoid changing this torturous code more than necessary to make it easy to review. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- Changes in v3: - Fix polarity of CONFIG_XHCI check (which broke USB keyboards) common/usb.c | 117 ++++++++++++++++++++++++++++++++++------------------------- 1 file changed, 67 insertions(+), 50 deletions(-) diff --git a/common/usb.c b/common/usb.c index 4ab2213..e5df98f 100644 --- a/common/usb.c +++ b/common/usb.c @@ -891,35 +891,12 @@ int usb_legacy_port_reset(struct usb_device *hub, int portnr) return 0; } -/* - * By the time we get here, the device has gotten a new device ID - * and is in the default state. We need to identify the thing and - * get the ball rolling.. - * - * Returns 0 for success, != 0 for error. - */ -int usb_new_device(struct usb_device *dev) +static int usb_setup_descriptor(struct usb_device *dev, bool do_read) { - int addr, err; - int tmp; + __maybe_unused struct usb_device_descriptor *desc; ALLOC_CACHE_ALIGN_BUFFER(unsigned char, tmpbuf, USB_BUFSIZ); /* - * Allocate usb 3.0 device context. - * USB 3.0 (xHCI) protocol tries to allocate device slot - * and related data structures first. This call does that. - * Refer to sec 4.3.2 in xHCI spec rev1.0 - */ - if (usb_alloc_device(dev)) { - printf("Cannot allocate device context to get SLOT_ID\n"); - return -1; - } - - /* We still haven't set the Address yet */ - addr = dev->devnum; - dev->devnum = 0; - - /* * This is a Windows scheme of initialization sequence, with double * reset of the device (Linux uses the same sequence) * Some equipment is said to work only with such init sequence; this @@ -934,40 +911,31 @@ int usb_new_device(struct usb_device *dev) * the maxpacket size is 8 or 16 the device may be waiting to transmit * some more, or keeps on retransmitting the 8 byte header. */ + desc = (struct usb_device_descriptor *)tmpbuf; dev->descriptor.bMaxPacketSize0 = 64; /* Start off at 64 bytes */ /* Default to 64 byte max packet size */ dev->maxpacketsize = PACKET_SIZE_64; dev->epmaxpacketin[0] = 64; dev->epmaxpacketout[0] = 64; - /* - * XHCI needs to issue a Address device command to setup - * proper device context structures, before it can interact - * with the device. So a get_descriptor will fail before any - * of that is done for XHCI unlike EHCI. - */ -#ifndef CONFIG_USB_XHCI - struct usb_device_descriptor *desc; + if (do_read) { + int err; - desc = (struct usb_device_descriptor *)tmpbuf; - err = usb_get_descriptor(dev, USB_DT_DEVICE, 0, desc, 64); - if (err < 0) { - debug("usb_new_device: usb_get_descriptor() failed\n"); - return 1; + err = usb_get_descriptor(dev, USB_DT_DEVICE, 0, desc, 64); + if (err < sizeof(dev->descriptor)) { + if (err < 0) { + printf("unable to get device descriptor (error=%d)\n", + err); + return err; + } else { + printf("USB device descriptor short read (expected %i, got %i)\n", + (int)sizeof(dev->descriptor), err); + return -EIO; + } + } + memcpy(&dev->descriptor, tmpbuf, sizeof(dev->descriptor)); } - dev->descriptor.bMaxPacketSize0 = desc->bMaxPacketSize0; - /* - * Fetch the device class, driver can use this info - * to differentiate between HUB and DEVICE. - */ - dev->descriptor.bDeviceClass = desc->bDeviceClass; -#endif - - err = usb_legacy_port_reset(dev->parent, dev->portnr); - if (err) - return err; - dev->epmaxpacketin[0] = dev->descriptor.bMaxPacketSize0; dev->epmaxpacketout[0] = dev->descriptor.bMaxPacketSize0; switch (dev->descriptor.bMaxPacketSize0) { @@ -984,6 +952,55 @@ int usb_new_device(struct usb_device *dev) dev->maxpacketsize = PACKET_SIZE_64; break; } + + return 0; +} + +/* + * By the time we get here, the device has gotten a new device ID + * and is in the default state. We need to identify the thing and + * get the ball rolling.. + * + * Returns 0 for success, != 0 for error. + */ +int usb_new_device(struct usb_device *dev) +{ + bool do_read = true; + int addr, err; + int tmp; + ALLOC_CACHE_ALIGN_BUFFER(unsigned char, tmpbuf, USB_BUFSIZ); + + /* + * Allocate usb 3.0 device context. + * USB 3.0 (xHCI) protocol tries to allocate device slot + * and related data structures first. This call does that. + * Refer to sec 4.3.2 in xHCI spec rev1.0 + */ + if (usb_alloc_device(dev)) { + printf("Cannot allocate device context to get SLOT_ID\n"); + return -1; + } + + /* We still haven't set the Address yet */ + addr = dev->devnum; + dev->devnum = 0; + + /* + * XHCI needs to issue a Address device command to setup + * proper device context structures, before it can interact + * with the device. So a get_descriptor will fail before any + * of that is done for XHCI unlike EHCI. + */ +#ifdef CONFIG_USB_XHCI + do_read = false; +#endif + err = usb_setup_descriptor(dev, do_read); + if (err) + return err; + err = usb_legacy_port_reset(dev->parent, dev->portnr); + if (err) + return err; + dev->devnum = addr; err = usb_set_address(dev); /* set address */ -- 2.2.0.rc0.207.ga3a616c

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[U-Boot] [PATCH v2 2/2] arm: ls102xa: Enable regulation of outstanding read transactions for slave interface S2
by Alison Wang 14 Apr '15

14 Apr '15

This patch will enable regulation of outstanding read transactions for slave interface S2 for silicon VER1.0. Signed-off-by: Alison Wang <alison.wang(a)freescale.com> --- Changes in v2: - Modify the subject and commit to describe accurately arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 ++ board/freescale/ls1021aqds/ls1021aqds.c | 7 +++++++ board/freescale/ls1021atwr/ls1021atwr.c | 7 +++++++ 3 files changed, 16 insertions(+) diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index a8122c1..1766f88 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -499,6 +499,8 @@ struct ccsr_ddr { #define CCI400_SHAORD_NON_SHAREABLE 0x00000002 #define CCI400_DVM_MESSAGE_REQ_EN 0x00000002 #define CCI400_SNOOP_REQ_EN 0x00000001 +#define CCI400_REGULATION_READ_EN 0x00000008 +#define CCI400_INT_MAX_OUT_TRANS 0x01000000 /* CCI-400 registers */ struct ccsr_cci400 { diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index 69a5671..b7d1c90 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -225,6 +225,13 @@ int board_early_init_f(void) */ out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); + /* + * To fix interleaving issue on VER1.0, regulation of + * outstanding read transactions for slave interface S2 + * is enabled + */ + out_le32(&cci->slave[2].qos_ctrl, CCI400_REGULATION_READ_EN); + out_le32(&cci->slave[2].max_ot, CCI400_INT_MAX_OUT_TRANS); /* Workaround for the issue that DDR could not respond to * barrier transaction which is generated by executing DSB/ISB diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index a9c87f2..bba3073 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -309,6 +309,13 @@ int board_early_init_f(void) */ out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); + /* + * To fix interleaving issue on VER1.0, regulation of + * outstanding read transactions for slave interface S2 + * is enabled + */ + out_le32(&cci->slave[2].qos_ctrl, CCI400_REGULATION_READ_EN); + out_le32(&cci->slave[2].max_ot, CCI400_INT_MAX_OUT_TRANS); } return 0; -- 2.1.0.27.g96db324

2 1

[U-Boot] [PATCH 1/2][v6] powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041
by Aneesh Bansal 14 Apr '15

14 Apr '15

Secure Boot Target is added for NAND for P3041. Changes: In PowerPC, the core begins execution from address 0xFFFFFFFC. In case of secure boot, this default address maps to Boot ROM. The Boot ROM code requires that the bootloader(U-boot) must lie in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF. In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is configured as SRAM. U-Boot binary will be located on this SRAM at location 0xBFF40000 with entry point as 0xBFFFFFFC. Signed-off-by: Ruchika Gupta <ruchika.gupta(a)freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal(a)freescale.com> --- Changes in v6: Changed the version in Patchset. Makefile | 4 ++++ arch/powerpc/cpu/mpc85xx/cpu_init.c | 17 +++++++++++++++++ board/freescale/common/p_corenet/tlb.c | 19 +++++++++++++++++-- board/freescale/corenet_ds/MAINTAINERS | 5 +++++ configs/P3041DS_NAND_SECURE_BOOT_defconfig | 4 ++++ include/configs/corenet_ds.h | 21 +++++++++++++++++++++ 6 files changed, 68 insertions(+), 2 deletions(-) create mode 100644 configs/P3041DS_NAND_SECURE_BOOT_defconfig diff --git a/Makefile b/Makefile index bd4abab..acfaa23 100644 --- a/Makefile +++ b/Makefile @@ -719,8 +719,12 @@ ALL-$(CONFIG_ONENAND_U_BOOT) += u-boot-onenand.bin ifeq ($(CONFIG_SPL_FSL_PBL),y) ALL-$(CONFIG_RAMBOOT_PBL) += u-boot-with-spl-pbl.bin else +ifneq ($(CONFIG_SECURE_BOOT), y) +# For Secure Boot The Image needs to be signed and Header must also +# be included. So The image has to be built explicitly ALL-$(CONFIG_RAMBOOT_PBL) += u-boot.pbl endif +endif ALL-$(CONFIG_SPL) += spl/u-boot-spl.bin ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot.img ALL-$(CONFIG_TPL) += tpl/u-boot-tpl.bin diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 4cf8853..1f520fe 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -843,6 +843,23 @@ int cpu_init_r(void) setup_mp(); #endif +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) && \ + defined(CONFIG_SECURE_BOOT) + /* Disable the TLB Created for L3 and create the TLB required for + * PCIE which was not created earlier. + */ + int tlb_index; + tlb_index = find_tlb_idx((void *)CONFIG_BPTR_VIRT_ADDR, 1); + if (tlb_index != -1) { + disable_tlb(tlb_index); + + set_tlb(1, CONFIG_SECBOOT_TLB_VIRT_ADDR, + CONFIG_SECBOOT_TLB_PHYS_ADDR, + CONFIG_SECBOOT_TLB_PERM, CONFIG_SECBOOT_TLB_ATTR, + 0, tlb_index, CONFIG_SECBOOT_TLB_PAGESZ, 1); + } +#endif + #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13 { if (SVR_MAJ(svr) < 3) { diff --git a/board/freescale/common/p_corenet/tlb.c b/board/freescale/common/p_corenet/tlb.c index 8148e46..dcadba1 100644 --- a/board/freescale/common/p_corenet/tlb.c +++ b/board/freescale/common/p_corenet/tlb.c @@ -42,7 +42,9 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 1 */ /* *I*** - Covers boot page */ -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) + /* In Case of Secure RAM Boot L3 address is defined at 0xbff00000 */ +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) && \ + !defined(CONFIG_SECURE_BOOT) /* * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the * SRAM is at 0xfff00000, it covered the 0xfffff000. @@ -76,11 +78,24 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) && \ + defined(CONFIG_SECURE_BOOT) + /* In case of Secure Boot, L3 is used as 1M SRAM + * and the address of the SRAM is at 0xbff00000. + * The PCIE TLB entry conflicts with the above entry. + * So, the entry for PCIE is not created at this point of time. + * It will be created later on in cpu_init_r() + * when U-Boot has relocated to DDR + */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_1M, 1), +#else /* *I*G* - PCI */ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_1G, 1), - +#endif /* *I*G* - PCI */ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000, CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000, diff --git a/board/freescale/corenet_ds/MAINTAINERS b/board/freescale/corenet_ds/MAINTAINERS index 745847c..6855446 100644 --- a/board/freescale/corenet_ds/MAINTAINERS +++ b/board/freescale/corenet_ds/MAINTAINERS @@ -28,3 +28,8 @@ F: configs/P5040DS_NAND_defconfig F: configs/P5040DS_SDCARD_defconfig F: configs/P5040DS_SPIFLASH_defconfig F: configs/P5040DS_SECURE_BOOT_defconfig + +CORENET_DS_SECURE_BOOT BOARD +M: Aneesh Bansal <aneesh.bansal(a)freescale.com> +S: Maintained +F: configs/P3041DS_NAND_SECURE_BOOT_defconfig diff --git a/configs/P3041DS_NAND_SECURE_BOOT_defconfig b/configs/P3041DS_NAND_SECURE_BOOT_defconfig new file mode 100644 index 0000000..e810b1c --- /dev/null +++ b/configs/P3041DS_NAND_SECURE_BOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xBFF40000" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P3041DS=y diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 225ffdd..4d09133 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -16,6 +16,26 @@ #include "../board/freescale/common/ics307_clk.h" #ifdef CONFIG_RAMBOOT_PBL +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_RESET_VECTOR_ADDRESS 0xbffffffc +#define CONFIG_BPTR_VIRT_ADDR 0xbffff000 + +/* In case of Secure Boot, L3 is used as 1M SRAM + * and the address of the SRAM is at 0xbff00000. + * The PCIE TLB entry conflicts with L3 TLB entry. + * The creation of PCIE TLB entry will be delayed + * till the time L3 entry is not required. + */ +#define CONFIG_SECBOOT_TLB_VIRT_ADDR CONFIG_SYS_PCIE1_MEM_VIRT +#define CONFIG_SECBOOT_TLB_PHYS_ADDR CONFIG_SYS_PCIE1_MEM_PHYS +#define CONFIG_SECBOOT_TLB_PERM MAS3_SW|MAS3_SR +#define CONFIG_SECBOOT_TLB_ATTR MAS2_I|MAS2_G +#define CONFIG_SECBOOT_TLB_PAGESZ BOOKE_PAGESZ_1G +#ifdef CONFIG_NAND +#define CONFIG_RAMBOOT_NAND +#endif +#else #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg @@ -29,6 +49,7 @@ #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg #endif #endif +#endif #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE /* Set 1M boot space */ -- 1.8.1.4

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