April 2015 - U-Boot

[U-Boot] [PATCH 5/5] x86: Kconfig: Remove deprecated CONFIG_SYS_EXTRA_OPTIONS
by Bin Meng 28 Apr '15

28 Apr '15

Currently all x86 boards still use CONFIG_SYS_EXTRA_OPTIONS to define the text base address. Since it is deprecated, just remove it and use CONFIG_SYS_TEXT_BASE directly. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- Kconfig | 2 +- board/coreboot/coreboot/Kconfig | 3 +++ board/google/chromebook_link/Kconfig | 3 +++ board/google/chromebox_panther/Kconfig | 3 +++ board/intel/crownbay/Kconfig | 3 +++ board/intel/galileo/Kconfig | 3 +++ board/intel/minnowmax/Kconfig | 3 +++ configs/chromebook_link_defconfig | 1 - configs/chromebox_panther_defconfig | 1 - configs/coreboot-x86_defconfig | 1 - configs/crownbay_defconfig | 1 - configs/galileo_defconfig | 1 - configs/minnowmax_defconfig | 1 - 13 files changed, 19 insertions(+), 7 deletions(-) diff --git a/Kconfig b/Kconfig index 41d4784..85faff7 100644 --- a/Kconfig +++ b/Kconfig @@ -178,7 +178,7 @@ config SYS_EXTRA_OPTIONS new boards should not use this option. config SYS_TEXT_BASE - depends on SPARC || ARC + depends on SPARC || ARC || X86 hex "Text Base" help TODO: Move CONFIG_SYS_TEXT_BASE for all the architecture diff --git a/board/coreboot/coreboot/Kconfig b/board/coreboot/coreboot/Kconfig index 981de1f..6a04158 100644 --- a/board/coreboot/coreboot/Kconfig +++ b/board/coreboot/coreboot/Kconfig @@ -9,6 +9,9 @@ config SYS_VENDOR config SYS_SOC default "coreboot" +config SYS_TEXT_BASE + default 0x01110000 + comment "coreboot-specific options" config SYS_CONFIG_NAME diff --git a/board/google/chromebook_link/Kconfig b/board/google/chromebook_link/Kconfig index ea45472..9c8d020 100644 --- a/board/google/chromebook_link/Kconfig +++ b/board/google/chromebook_link/Kconfig @@ -12,6 +12,9 @@ config SYS_SOC config SYS_CONFIG_NAME default "chromebook_link" +config SYS_TEXT_BASE + default 0xfff00000 + config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select X86_RESET_VECTOR diff --git a/board/google/chromebox_panther/Kconfig b/board/google/chromebox_panther/Kconfig index 11df55a..e3604eb 100644 --- a/board/google/chromebox_panther/Kconfig +++ b/board/google/chromebox_panther/Kconfig @@ -12,6 +12,9 @@ config SYS_SOC config SYS_CONFIG_NAME default "chromebox_panther" +config SYS_TEXT_BASE + default 0xfff00000 + # Panther actually uses haswell, not ivybridge, so this is just a placeholder config BOARD_SPECIFIC_OPTIONS # dummy def_bool y diff --git a/board/intel/crownbay/Kconfig b/board/intel/crownbay/Kconfig index 762663a..b30701a 100644 --- a/board/intel/crownbay/Kconfig +++ b/board/intel/crownbay/Kconfig @@ -12,6 +12,9 @@ config SYS_SOC config SYS_CONFIG_NAME default "crownbay" +config SYS_TEXT_BASE + default 0xfff00000 + config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select X86_RESET_VECTOR diff --git a/board/intel/galileo/Kconfig b/board/intel/galileo/Kconfig index 85afbbc..6515bac 100644 --- a/board/intel/galileo/Kconfig +++ b/board/intel/galileo/Kconfig @@ -12,6 +12,9 @@ config SYS_SOC config SYS_CONFIG_NAME default "galileo" +config SYS_TEXT_BASE + default 0xfff10000 + config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select X86_RESET_VECTOR diff --git a/board/intel/minnowmax/Kconfig b/board/intel/minnowmax/Kconfig index 43c50a5..f2a0b71 100644 --- a/board/intel/minnowmax/Kconfig +++ b/board/intel/minnowmax/Kconfig @@ -12,6 +12,9 @@ config SYS_SOC config SYS_CONFIG_NAME default "minnowmax" +config SYS_TEXT_BASE + default 0xfff00000 + config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select X86_RESET_VECTOR diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig index 9cfc65b..81222d2 100644 --- a/configs/chromebook_link_defconfig +++ b/configs/chromebook_link_defconfig @@ -1,4 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xfff00000" CONFIG_X86=y CONFIG_VENDOR_GOOGLE=y CONFIG_TARGET_CHROMEBOOK_LINK=y diff --git a/configs/chromebox_panther_defconfig b/configs/chromebox_panther_defconfig index c4db232..91189c9 100644 --- a/configs/chromebox_panther_defconfig +++ b/configs/chromebox_panther_defconfig @@ -1,4 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xfff00000" CONFIG_X86=y CONFIG_VENDOR_GOOGLE=y CONFIG_TARGET_CHROMEBOX_PANTHER=y diff --git a/configs/coreboot-x86_defconfig b/configs/coreboot-x86_defconfig index eb192ae..799853f 100644 --- a/configs/coreboot-x86_defconfig +++ b/configs/coreboot-x86_defconfig @@ -1,4 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x01110000" CONFIG_X86=y CONFIG_VENDOR_COREBOOT=y CONFIG_TARGET_COREBOOT=y diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig index de84650..61d1fcc 100644 --- a/configs/crownbay_defconfig +++ b/configs/crownbay_defconfig @@ -1,4 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xfff00000" CONFIG_X86=y CONFIG_VENDOR_INTEL=y CONFIG_TARGET_CROWNBAY=y diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig index 787e15f..1a54ba5 100644 --- a/configs/galileo_defconfig +++ b/configs/galileo_defconfig @@ -1,4 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xfff10000" CONFIG_X86=y CONFIG_VENDOR_INTEL=y CONFIG_TARGET_GALILEO=y diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig index c4dbfca..c59f4ac 100644 --- a/configs/minnowmax_defconfig +++ b/configs/minnowmax_defconfig @@ -1,4 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xfff00000" CONFIG_X86=y CONFIG_VENDOR_INTEL=y CONFIG_TARGET_MINNOWMAX=y -- 1.8.2.1

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[U-Boot] [PATCH 4/5] x86: Kconfig: Move DM_SPI & DM_SPI_FLASH to arch/Kconfig
by Bin Meng 28 Apr '15

28 Apr '15

Since all x86 boards have been converted to use DM_SPI and DM_SPI_FLASH, move them to arch/Kconfig x86 section. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- arch/Kconfig | 2 ++ arch/x86/Kconfig | 6 ------ 2 files changed, 2 insertions(+), 6 deletions(-) diff --git a/arch/Kconfig b/arch/Kconfig index 1102346..200588a 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -93,6 +93,8 @@ config X86 select DM select DM_SERIAL select DM_GPIO + select DM_SPI + select DM_SPI_FLASH endchoice diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 2387fb7..f3a600e 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -39,12 +39,6 @@ source "arch/x86/cpu/queensbay/Kconfig" # architecture-specific options below -config DM_SPI - default y - -config DM_SPI_FLASH - default y - config SYS_MALLOC_F_LEN default 0x800 -- 1.8.2.1

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[U-Boot] [PATCH 3/5] x86: Kconfig: MARK_GRAPHICS_MEM_WRCOMB cosmetics
by Bin Meng 28 Apr '15

28 Apr '15

Remove the ending period of the MARK_GRAPHICS_MEM_WRCOMB option. Also fix the indention of its help text. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- arch/x86/Kconfig | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 43062cd..2387fb7 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -181,12 +181,12 @@ config X86_RAMTEST detecting obvious failures. config MARK_GRAPHICS_MEM_WRCOMB - bool "Mark graphics memory as write-combining." + bool "Mark graphics memory as write-combining" default n help - The graphics performance may increase if the graphics - memory is set as write-combining cache type. This option - enables marking the graphics memory as write-combining. + The graphics performance may increase if the graphics + memory is set as write-combining cache type. This option + enables marking the graphics memory as write-combining. menu "Display" -- 1.8.2.1

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[U-Boot] [PATCH 2/5] x86: Kconfig: Move platform options forward
by Bin Meng 28 Apr '15

28 Apr '15

Move platform-specific options under in arch/x86/Kconfig forward right after the board-specific options but before any architecture-specific options. When it comes to the same Kconfig option, board-specific one takes take the highest precedence, then platform-specific one, and finally architecture-specific one. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- arch/x86/Kconfig | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index c3cc144..43062cd 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -30,6 +30,15 @@ source "board/coreboot/Kconfig" source "board/google/Kconfig" source "board/intel/Kconfig" +# platform-specific options below +source "arch/x86/cpu/baytrail/Kconfig" +source "arch/x86/cpu/coreboot/Kconfig" +source "arch/x86/cpu/ivybridge/Kconfig" +source "arch/x86/cpu/quark/Kconfig" +source "arch/x86/cpu/queensbay/Kconfig" + +# architecture-specific options below + config DM_SPI default y @@ -358,16 +367,6 @@ config FSP_TEMP_RAM_ADDR Stack top address which is used in FspInit after DRAM is ready and CAR is disabled. -source "arch/x86/cpu/baytrail/Kconfig" - -source "arch/x86/cpu/coreboot/Kconfig" - -source "arch/x86/cpu/ivybridge/Kconfig" - -source "arch/x86/cpu/quark/Kconfig" - -source "arch/x86/cpu/queensbay/Kconfig" - config TSC_CALIBRATION_BYPASS bool "Bypass Time-Stamp Counter (TSC) calibration" default n -- 1.8.2.1

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[U-Boot] [PATCH 1/5] x86: Kconfig: Divide the target selection to vendor/model
by Bin Meng 28 Apr '15

28 Apr '15

Let arch/x86/Kconfig prompt board vendor first, then select the board model under that vendor. This way arch/x86/Kconfig only needs concern board vendor and leave the supported target list to board/<vendor>/Kconfig. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- arch/x86/Kconfig | 92 ++++++------------------------------- board/coreboot/Kconfig | 26 +++++++++++ board/google/Kconfig | 43 +++++++++++++++++ board/intel/Kconfig | 51 ++++++++++++++++++++ configs/chromebook_link_defconfig | 1 + configs/chromebox_panther_defconfig | 1 + configs/coreboot-x86_defconfig | 1 + configs/crownbay_defconfig | 1 + configs/galileo_defconfig | 1 + configs/minnowmax_defconfig | 1 + 10 files changed, 139 insertions(+), 79 deletions(-) create mode 100644 board/coreboot/Kconfig create mode 100644 board/google/Kconfig create mode 100644 board/intel/Kconfig diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index aaceaef..c3cc144 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -11,79 +11,25 @@ config SYS_VSNPRINTF default y choice - prompt "Target select" + prompt "Mainboard vendor" + default VENDOR_COREBOOT -config TARGET_COREBOOT - bool "Support coreboot" - help - This target is used for running U-Boot on top of Coreboot. In - this case Coreboot does the early inititalisation, and U-Boot - takes over once the RAM, video and CPU are fully running. - U-Boot is loaded as a fallback payload from Coreboot, in - Coreboot terminology. This method was used for the Chromebook - Pixel when launched. - -config TARGET_CHROMEBOOK_LINK - bool "Support Chromebook link" - help - This is the Chromebook Pixel released in 2013. It uses an Intel - i5 Ivybridge which is a die-shrink of Sandybridge, with 4GB of - SDRAM. It has a Panther Point platform controller hub, PCIe - WiFi and Bluetooth. It also includes a 720p webcam, USB SD - reader, microphone and speakers, display port and 32GB SATA - solid state drive. There is a Chrome OS EC connected on LPC, - and it provides a 2560x1700 high resolution touch-enabled LCD - display. - -config TARGET_CHROMEBOX_PANTHER - bool "Support Chromebox panther (not available)" - select n - help - Note: At present this must be used with Coreboot. See README.x86 - for instructions. - - This is the Asus Chromebox CN60 released in 2014. It uses an Intel - Haswell Celeron 2955U Dual Core CPU with 2GB of SDRAM. It has a - Lynx Point platform controller hub, PCIe WiFi and Bluetooth. It also - includes a USB SD reader, four USB3 ports, display port and HDMI - video output and a 16GB SATA solid state drive. There is no Chrome - OS EC on this model. - -config TARGET_CROWNBAY - bool "Support Intel Crown Bay CRB" - help - This is the Intel Crown Bay Customer Reference Board. It contains - the Intel Atom Processor E6xx populated on the COM Express module - with 1GB DDR2 soldered down memory and a carrier board with the - Intel Platform Controller Hub EG20T, other system components and - peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS. - -config TARGET_MINNOWMAX - bool "Support Intel Minnowboard MAX" - help - This is the Intel Minnowboard MAX. It contains an Atom E3800 - processor in a small form factor with Ethernet, micro-SD, USB 2, - USB 3, SATA, serial console, some GPIOs and HDMI 1.3 video out. - It requires some binary blobs - see README.x86 for details. +config VENDOR_COREBOOT + bool "coreboot" - Note that PCIE_ECAM_BASE is set up by the FSP so the value used - by U-Boot matches that value. +config VENDOR_GOOGLE + bool "Google" -config TARGET_GALILEO - bool "Support Intel Galileo" - help - This is the Intel Galileo board, which is the first in a family of - Arduino-certified development and prototyping boards based on Intel - architecture. It includes an Intel Quark SoC X1000 processor, a 32-bit - single-core, single-thread, Intel Pentium processor instrunction set - architecture (ISA) compatible, operating at speeds up to 400Mhz, - along with 256MB DDR3 memory. It supports a wide range of industry - standard I/O interfaces, including a full-sized mini-PCIe slot, - one 100Mb Ethernet port, a microSD card slot, a USB host port and - a USB client port. +config VENDOR_INTEL + bool "Intel" endchoice +# board-specific options below +source "board/coreboot/Kconfig" +source "board/google/Kconfig" +source "board/intel/Kconfig" + config DM_SPI default y @@ -473,18 +419,6 @@ config IRQ_SLOT_COUNT should be enough for most boards. If this does not fit your board, change it according to your needs. -source "board/coreboot/coreboot/Kconfig" - -source "board/google/chromebook_link/Kconfig" - -source "board/google/chromebox_panther/Kconfig" - -source "board/intel/crownbay/Kconfig" - -source "board/intel/minnowmax/Kconfig" - -source "board/intel/galileo/Kconfig" - config PCIE_ECAM_BASE hex default 0xe0000000 diff --git a/board/coreboot/Kconfig b/board/coreboot/Kconfig new file mode 100644 index 0000000..dc9b70f --- /dev/null +++ b/board/coreboot/Kconfig @@ -0,0 +1,26 @@ +# +# Copyright (C) 2015, Bin Meng <bmeng.cn(a)gmail.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +if VENDOR_COREBOOT + +choice + prompt "Mainboard model" + +config TARGET_COREBOOT + bool "coreboot" + help + This target is used for running U-Boot on top of coreboot. In + this case coreboot does the early inititalisation, and U-Boot + takes over once the RAM, video and CPU are fully running. + U-Boot is loaded as a fallback payload from coreboot, in + coreboot terminology. This method was used for the Chromebook + Pixel when launched. + +endchoice + +source "board/coreboot/coreboot/Kconfig" + +endif diff --git a/board/google/Kconfig b/board/google/Kconfig new file mode 100644 index 0000000..302f68e --- /dev/null +++ b/board/google/Kconfig @@ -0,0 +1,43 @@ +# +# Copyright (C) 2015, Bin Meng <bmeng.cn(a)gmail.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +if VENDOR_GOOGLE + +choice + prompt "Mainboard model" + +config TARGET_CHROMEBOOK_LINK + bool "Chromebook link" + help + This is the Chromebook Pixel released in 2013. It uses an Intel + i5 Ivybridge which is a die-shrink of Sandybridge, with 4GB of + SDRAM. It has a Panther Point platform controller hub, PCIe + WiFi and Bluetooth. It also includes a 720p webcam, USB SD + reader, microphone and speakers, display port and 32GB SATA + solid state drive. There is a Chrome OS EC connected on LPC, + and it provides a 2560x1700 high resolution touch-enabled LCD + display. + +config TARGET_CHROMEBOX_PANTHER + bool "Chromebox panther (not available)" + select n + help + Note: At present this must be used with coreboot. See README.x86 + for instructions. + + This is the Asus Chromebox CN60 released in 2014. It uses an Intel + Haswell Celeron 2955U Dual Core CPU with 2GB of SDRAM. It has a + Lynx Point platform controller hub, PCIe WiFi and Bluetooth. It also + includes a USB SD reader, four USB3 ports, display port and HDMI + video output and a 16GB SATA solid state drive. There is no Chrome + OS EC on this model. + +endchoice + +source "board/google/chromebook_link/Kconfig" +source "board/google/chromebox_panther/Kconfig" + +endif diff --git a/board/intel/Kconfig b/board/intel/Kconfig new file mode 100644 index 0000000..7fe21b9 --- /dev/null +++ b/board/intel/Kconfig @@ -0,0 +1,51 @@ +# +# Copyright (C) 2015, Bin Meng <bmeng.cn(a)gmail.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +if VENDOR_INTEL + +choice + prompt "Mainboard model" + +config TARGET_CROWNBAY + bool "Crown Bay" + help + This is the Intel Crown Bay Customer Reference Board. It contains + the Intel Atom Processor E6xx populated on the COM Express module + with 1GB DDR2 soldered down memory and a carrier board with the + Intel Platform Controller Hub EG20T, other system components and + peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS. + +config TARGET_GALILEO + bool "Galileo" + help + This is the Intel Galileo board, which is the first in a family of + Arduino-certified development and prototyping boards based on Intel + architecture. It includes an Intel Quark SoC X1000 processor, a 32-bit + single-core, single-thread, Intel Pentium processor instrunction set + architecture (ISA) compatible, operating at speeds up to 400Mhz, + along with 256MB DDR3 memory. It supports a wide range of industry + standard I/O interfaces, including a full-sized mini-PCIe slot, + one 100Mb Ethernet port, a microSD card slot, a USB host port and + a USB client port. + +config TARGET_MINNOWMAX + bool "Minnowboard MAX" + help + This is the Intel Minnowboard MAX. It contains an Atom E3800 + processor in a small form factor with Ethernet, micro-SD, USB 2, + USB 3, SATA, serial console, some GPIOs and HDMI 1.3 video out. + It requires some binary blobs - see README.x86 for details. + + Note that PCIE_ECAM_BASE is set up by the FSP so the value used + by U-Boot matches that value. + +endchoice + +source "board/intel/crownbay/Kconfig" +source "board/intel/galileo/Kconfig" +source "board/intel/minnowmax/Kconfig" + +endif diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig index fe2610a..9cfc65b 100644 --- a/configs/chromebook_link_defconfig +++ b/configs/chromebook_link_defconfig @@ -1,5 +1,6 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xfff00000" CONFIG_X86=y +CONFIG_VENDOR_GOOGLE=y CONFIG_TARGET_CHROMEBOOK_LINK=y CONFIG_OF_CONTROL=y CONFIG_OF_SEPARATE=y diff --git a/configs/chromebox_panther_defconfig b/configs/chromebox_panther_defconfig index 0613cd6..c4db232 100644 --- a/configs/chromebox_panther_defconfig +++ b/configs/chromebox_panther_defconfig @@ -1,5 +1,6 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xfff00000" CONFIG_X86=y +CONFIG_VENDOR_GOOGLE=y CONFIG_TARGET_CHROMEBOX_PANTHER=y CONFIG_OF_CONTROL=y CONFIG_OF_SEPARATE=y diff --git a/configs/coreboot-x86_defconfig b/configs/coreboot-x86_defconfig index 0249172..eb192ae 100644 --- a/configs/coreboot-x86_defconfig +++ b/configs/coreboot-x86_defconfig @@ -1,5 +1,6 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x01110000" CONFIG_X86=y +CONFIG_VENDOR_COREBOOT=y CONFIG_TARGET_COREBOOT=y CONFIG_OF_CONTROL=y CONFIG_DM_PCI=y diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig index 47763f9..de84650 100644 --- a/configs/crownbay_defconfig +++ b/configs/crownbay_defconfig @@ -1,5 +1,6 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xfff00000" CONFIG_X86=y +CONFIG_VENDOR_INTEL=y CONFIG_TARGET_CROWNBAY=y CONFIG_OF_CONTROL=y CONFIG_OF_SEPARATE=y diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig index 9b0f969..787e15f 100644 --- a/configs/galileo_defconfig +++ b/configs/galileo_defconfig @@ -1,5 +1,6 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xfff10000" CONFIG_X86=y +CONFIG_VENDOR_INTEL=y CONFIG_TARGET_GALILEO=y CONFIG_OF_CONTROL=y CONFIG_OF_SEPARATE=y diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig index d1add19..c4dbfca 100644 --- a/configs/minnowmax_defconfig +++ b/configs/minnowmax_defconfig @@ -1,5 +1,6 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xfff00000" CONFIG_X86=y +CONFIG_VENDOR_INTEL=y CONFIG_TARGET_MINNOWMAX=y CONFIG_OF_CONTROL=y CONFIG_OF_SEPARATE=y -- 1.8.2.1

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[U-Boot] [PATCH 2/3] x86: quark: Turn on legacy segments decode
by Bin Meng 28 Apr '15

28 Apr '15

By default the legacy segments (A0000h-B0000h, E0000h-F0000h) do not decode to system RAM. Turn on the decode so that we can write configuration tables in the F segment. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- arch/x86/cpu/quark/quark.c | 12 ++++++++++++ arch/x86/include/asm/arch-quark/quark.h | 7 +++++++ 2 files changed, 19 insertions(+) diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c index e4b19c2..4ffa437 100644 --- a/arch/x86/cpu/quark/quark.c +++ b/arch/x86/cpu/quark/quark.c @@ -72,6 +72,15 @@ static void quark_setup_bars(void) CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN); } +static void quark_enable_legacy_seg(void) +{ + u32 hmisc2; + + hmisc2 = msg_port_read(MSG_PORT_HOST_BRIDGE, HMISC2); + hmisc2 |= (HMISC2_SEGE | HMISC2_SEGF | HMISC2_SEGAB); + msg_port_write(MSG_PORT_HOST_BRIDGE, HMISC2, hmisc2); +} + int arch_cpu_init(void) { struct pci_controller *hose; @@ -96,6 +105,9 @@ int arch_cpu_init(void) */ quark_setup_bars(); + /* Turn on legacy segments (A/B/E/F) decode to system RAM */ + quark_enable_legacy_seg(); + unprotect_spi_flash(); return 0; diff --git a/arch/x86/include/asm/arch-quark/quark.h b/arch/x86/include/asm/arch-quark/quark.h index ceb583e..6dd02fd 100644 --- a/arch/x86/include/asm/arch-quark/quark.h +++ b/arch/x86/include/asm/arch-quark/quark.h @@ -21,6 +21,13 @@ /* Port 0x03: Host Bridge Message Port Registers */ +/* Host Miscellaneous Controls 2 */ +#define HMISC2 0x03 + +#define HMISC2_SEGE 0x00000002 +#define HMISC2_SEGF 0x00000004 +#define HMISC2_SEGAB 0x00000010 + /* Host Memory I/O Boundary */ #define HM_BOUND 0x08 -- 1.8.2.1

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[U-Boot] [PATCH 1/3] x86: Check PIRQ routing table sanity in the F segment
by Bin Meng 28 Apr '15

28 Apr '15

Previously the PIRQ routing table sanity check was performed against the original table provided by the platform codes. Now we switch to check its sanity on the final table in the F segment as this one is the one seen by the OS. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- arch/x86/lib/pirq_routing.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/arch/x86/lib/pirq_routing.c b/arch/x86/lib/pirq_routing.c index 5a2591a..7a34dcf 100644 --- a/arch/x86/lib/pirq_routing.c +++ b/arch/x86/lib/pirq_routing.c @@ -110,11 +110,7 @@ void pirq_route_irqs(struct irq_info *irq, int num) u32 copy_pirq_routing_table(u32 addr, struct irq_routing_table *rt) { - if (rt->signature != PIRQ_SIGNATURE || rt->version != PIRQ_VERSION || - rt->size % 16) { - debug("Interrupt Routing Table not valid\n"); - return addr; - } + struct irq_routing_table *rom_rt; /* Fix up the table checksum */ rt->checksum = table_compute_checksum(rt, rt->size); @@ -125,5 +121,17 @@ u32 copy_pirq_routing_table(u32 addr, struct irq_routing_table *rt) debug("Copying Interrupt Routing Table to 0x%x\n", addr); memcpy((void *)addr, rt, rt->size); + /* + * We do the sanity check here against the copied table after memcpy, + * as something might go wrong after the memcpy, which is normally + * due to the F segment decode is not turned on to systeam RAM. + */ + rom_rt = (struct irq_routing_table *)addr; + if (rom_rt->signature != PIRQ_SIGNATURE || + rom_rt->version != PIRQ_VERSION || rom_rt->size % 16) { + printf("Interrupt Routing Table not valid\n"); + return addr; + } + return addr + rt->size; } -- 1.8.2.1

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[U-Boot] [PATCH] x86: minnowmax: use the correct NOR in the configuration
by Gabriel Huau 28 Apr '15

28 Apr '15

The SPI NOR on the minnowboard max is a MICRON N25Q064A Signed-off-by: Gabriel Huau <contact(a)huau-gabriel.fr> --- include/configs/minnowmax.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h index 3c7b266..72393fa 100644 --- a/include/configs/minnowmax.h +++ b/include/configs/minnowmax.h @@ -43,7 +43,7 @@ #define CONFIG_SCSI_DEV_LIST \ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA} -#define CONFIG_SPI_FLASH_SST +#define CONFIG_SPI_FLASH_STMICRO #define CONFIG_MMC #define CONFIG_SDHCI -- 2.1.4

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[U-Boot] Pull request: u-boot-spi/master
by Jagannadha Sutradharudu Teki 28 Apr '15

28 Apr '15

Hi Tom, Please pick this PR. thanks! Jagan. The following changes since commit d77447fdb122dab290fb1ad184a62456011e6e06: serial: pl01x: fix PL010 regression (2015-04-21 10:05:42 -0400) are available in the git repository at: git://git.denx.de/u-boot-spi.git master for you to fetch changes up to c650ca7b4c160193791dc7a52381c71c6a29e871: sf: Fix to compute proper sector_size (2015-04-28 13:31:36 +0530) ---------------------------------------------------------------- Bin Meng (2): dm: sf: Save flash flags to struct spi_flash dm: sf: Make SST flash write op work again David Dueck (1): spi: omap3: Fix timeout handling Jagannadha Sutradharudu Teki (2): Revert "spi: add config option to enable the WP pin function on st micron flashes" sf: Fix to compute proper sector_size Pavel Machek (1): spi flash: fix trivial problems Peng Fan (1): mtd: spi: check return value of spi_setup_slave Simon Glass (1): dm: spi: Correct SPI claim/release_bus() methods Siva Durga Prasad Paladugu (3): sf: Correct the macros as per new array fast read command sf: Poll both the read status and flag status zynq: spi: Remove unnecessary error condition Stefan Roese (1): cmd_sf: Fix problem with "sf update" and unaligned length README | 11 ---------- common/cmd_sf.c | 16 +++++++------- drivers/mtd/spi/sf_internal.h | 7 ++----- drivers/mtd/spi/sf_ops.c | 32 +++++++++++++++++++++------- drivers/mtd/spi/sf_probe.c | 49 +++++++++++++++++-------------------------- drivers/spi/exynos_spi.c | 6 ++++-- drivers/spi/omap3_spi.c | 20 +++++++++++------- drivers/spi/spi-uclass.c | 4 ++-- drivers/spi/tegra114_spi.c | 3 ++- drivers/spi/tegra20_sflash.c | 3 ++- drivers/spi/tegra20_slink.c | 3 ++- drivers/spi/zynq_spi.c | 3 --- include/spi.h | 21 ++++++++++--------- include/spi_flash.h | 9 ++++---- 14 files changed, 93 insertions(+), 94 deletions(-)

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[U-Boot] Please pull u-boot-fdt
by Simon Glass 28 Apr '15

28 Apr '15

Hi Tom, The following changes since commit d8c1d5d5fb6eafbc532982125f006e49f2c40e71: Merge branch 'buildman' of git://git.denx.de/u-boot-x86 (2015-04-23 14:56:47 -0400) are available in the git repository at: http://git.denx.de/u-boot-fdt.git for you to fetch changes up to 77d7fff8cec2652be8c2494b6b66d14a398ec860: fdt: Fix handling of paths with options in them (2015-04-23 22:54:32 -0600) ---------------------------------------------------------------- Hans de Goede (1): fdt: Fix handling of paths with options in them lib/libfdt/fdt_ro.c | 25 ++++++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) Regards, Simon

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