April 2015 - U-Boot

[U-Boot] [PATCH] x86: Correct Minnowboard instructions to use the right descriptor
by Simon Glass 29 Apr '15

29 Apr '15

The descriptor provided with the FSP does not seem to work. Update the instructions to use the descriptor from the original Intel firmware. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- doc/README.x86 | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/doc/README.x86 b/doc/README.x86 index 0355d1c..fe31f3d 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -127,15 +127,32 @@ board/intel/minnowmax/fsp.bin Obtain the VGA RAM (Vga.dat at the time of writing) and put it into the same directory: board/intel/minnowmax/vga.bin -You still need two more binary blobs. These come from the sample SPI image -provided in the FSP (SPI.bin at the time of writing). +You still need two more binary blobs. The first comes from the original +firmware image available from: + +http://firmware.intel.com/sites/default/files/2014-WW42.4-MinnowBoardMax.73-64-bit.bin_Release.zip + +Unzip it: + + $ unzip 2014-WW42.4-MinnowBoardMax.73-64-bit.bin_Release.zip Use ifdtool in the U-Boot tools directory to extract the images from that file, for example: + $ ./tools/ifdtool -x MNW2MAX1.X64.0073.R02.1409160934.bin + +This will provide the descriptor file - copy this into the correct place: + + $ cp flashregion_0_flashdescriptor.bin board/intel/minnowmax/descriptor.bin + +Then do the same with the sample SPI image provided in the FSP (SPI.bin at +the time of writing) to obtain the last image. Note that this will also +produce a flash descriptor file, but it does not seem to work, probably +because it is not designed for the Minnowmax. That is why you need to get +the flash descriptor from the original firmware as above. + $ ./tools/ifdtool -x BayleyBay/SPI.bin $ cp flashregion_2_intel_me.bin board/intel/minnowmax/me.bin - $ cp flashregion_0_flashdescriptor.bin board/intel/minnowmax/descriptor.bin Now you can build U-Boot and obtain u-boot.rom -- 2.2.0.rc0.207.ga3a616c

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[U-Boot] [PATCH] x86: link: Add PCH driver to support SPI Flash
by Simon Glass 29 Apr '15

29 Apr '15

U-Boot on coreboot does not have a driver for the PCH so cannot see the SPI peripheral now that it has moved inside the PCH. Add a simple driver so that SPI flash works again. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- arch/x86/cpu/coreboot/pci.c | 11 +++++++++++ arch/x86/dts/chromebook_link.dts | 2 +- 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/x86/cpu/coreboot/pci.c b/arch/x86/cpu/coreboot/pci.c index fa415dd..67eb14c 100644 --- a/arch/x86/cpu/coreboot/pci.c +++ b/arch/x86/cpu/coreboot/pci.c @@ -34,3 +34,14 @@ U_BOOT_DRIVER(pci_x86_drv) = { .of_match = pci_x86_ids, .ops = &pci_x86_ops, }; + +static const struct udevice_id generic_pch_ids[] = { + { .compatible = "intel,pch" }, + { } +}; + +U_BOOT_DRIVER(generic_pch_drv) = { + .name = "pch", + .id = UCLASS_PCH, + .of_match = generic_pch_ids, +}; diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts index b450c3c..7c7034c 100644 --- a/arch/x86/dts/chromebook_link.dts +++ b/arch/x86/dts/chromebook_link.dts @@ -181,7 +181,7 @@ pch { reg = <0x0000f800 0 0 0 0>; - compatible = "intel,bd82x6x"; + compatible = "intel,bd82x6x", "intel,pch"; u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; -- 2.2.0.rc0.207.ga3a616c

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[U-Boot] [PATCH 1/2] x86: Correct Minnowboard instructions to use the right descriptor
by Simon Glass 29 Apr '15

29 Apr '15

The descriptor provided with the FSP does not seem to work. Update the instructions to use the descriptor from the original Intel firmware. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- doc/README.x86 | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/doc/README.x86 b/doc/README.x86 index 0355d1c..fe31f3d 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -127,15 +127,32 @@ board/intel/minnowmax/fsp.bin Obtain the VGA RAM (Vga.dat at the time of writing) and put it into the same directory: board/intel/minnowmax/vga.bin -You still need two more binary blobs. These come from the sample SPI image -provided in the FSP (SPI.bin at the time of writing). +You still need two more binary blobs. The first comes from the original +firmware image available from: + +http://firmware.intel.com/sites/default/files/2014-WW42.4-MinnowBoardMax.73-64-bit.bin_Release.zip + +Unzip it: + + $ unzip 2014-WW42.4-MinnowBoardMax.73-64-bit.bin_Release.zip Use ifdtool in the U-Boot tools directory to extract the images from that file, for example: + $ ./tools/ifdtool -x MNW2MAX1.X64.0073.R02.1409160934.bin + +This will provide the descriptor file - copy this into the correct place: + + $ cp flashregion_0_flashdescriptor.bin board/intel/minnowmax/descriptor.bin + +Then do the same with the sample SPI image provided in the FSP (SPI.bin at +the time of writing) to obtain the last image. Note that this will also +produce a flash descriptor file, but it does not seem to work, probably +because it is not designed for the Minnowmax. That is why you need to get +the flash descriptor from the original firmware as above. + $ ./tools/ifdtool -x BayleyBay/SPI.bin $ cp flashregion_2_intel_me.bin board/intel/minnowmax/me.bin - $ cp flashregion_0_flashdescriptor.bin board/intel/minnowmax/descriptor.bin Now you can build U-Boot and obtain u-boot.rom -- 2.2.0.rc0.207.ga3a616c

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[U-Boot] [RFC PATCH v2] arm: mx6: Clamp MMDC and DDR3 clocks for timing calculations
by Nikolay Dimitrov 28 Apr '15

28 Apr '15

This is proposal for clamping the MMDC/DDR3 clocks to the maximum supported frequencies as per imx6 SOC models, and for dynamically calculating valid clock value based on mem_speed. Currently the code uses impossible values for mem_speed (1333, 1600 MT/s) for calculating the DDR timings, and uses fixed clock (528 or 400 MHz) which doesn't take into account DDR3 memory limitations. Signed-off-by: Nikolay Dimitrov <picmaster(a)mail.bg> Cc: Fabio Estevam <festevam(a)gmail.com> Cc: Stefano Babic <sbabic(a)denx.de> Cc: Tim Harvey <tharvey(a)gateworks.com> Cc: Eric Nelson <eric.nelson(a)boundarydevices.com> --- Changes v1 -> v2: - fixed mistake of accessing a struct const member arch/arm/cpu/armv7/mx6/ddr.c | 30 +++++++++++++++++++++++------- 1 file changed, 23 insertions(+), 7 deletions(-) diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c index fef2231..a0a7082 100644 --- a/arch/arm/cpu/armv7/mx6/ddr.c +++ b/arch/arm/cpu/armv7/mx6/ddr.c @@ -265,24 +265,40 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo, u16 tdllk = 0x1ff; /* DLL locking time: 512 cycles (JEDEC DDR3) */ u8 coladdr; int clkper; /* clock period in picoseconds */ - int clock; /* clock freq in mHz */ + int clock; /* clock freq in MHz */ int cs; + u16 mem_speed = ddr3_cfg->mem_speed; mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR; #ifndef CONFIG_MX6SX mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR; #endif - /* MX6D/MX6Q: 1066 MHz memory clock, clkper = 1.894ns = 1894ps */ + /* Limit mem_speed for MX6D/MX6Q */ if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) { - clock = 528; + if (mem_speed > 1066) + mem_speed = 1066; /* 1066 MT/s */ + tcwl = 4; } - /* MX6S/MX6DL: 800 MHz memory clock, clkper = 2.5ns = 2500ps */ + /* Limit mem_speed for MX6S/MX6DL */ else { - clock = 400; + if (mem_speed > 800) + mem_speed = 800; /* 800 MT/s */ + tcwl = 3; } + + clock = mem_speed / 2; + /* + * Data rate of 1066 MT/s requires 533 MHz DDR3 clock, but MX6D/Q supports + * up to 528 MHz, so reduce the clock to fit chip specs + */ + if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) { + if (clock > 528) + clock = 528; /* 528 MHz */ + } + clkper = (1000 * 1000) / clock; /* pico seconds */ todtlon = tcwl; taxpd = tcwl; @@ -313,7 +329,7 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo, } txpr = txs; - switch (ddr3_cfg->mem_speed) { + switch (mem_speed) { case 800: txp = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1; tcke = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1; @@ -382,7 +398,7 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo, debug("density:%d Gb (%d Gb per chip)\n", sysinfo->cs_density, ddr3_cfg->density); debug("clock: %dMHz (%d ps)\n", clock, clkper); - debug("memspd:%d\n", ddr3_cfg->mem_speed); + debug("memspd:%d\n", mem_speed); debug("tcke=%d\n", tcke); debug("tcksrx=%d\n", tcksrx); debug("tcksre=%d\n", tcksre); -- 1.7.10.4

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[U-Boot] [PATCH] mpc85xx: gpio related compiler error fix when build common/cmd_gpio.c
by Oleksandr G Zhadan 28 Apr '15

28 Apr '15

1. Include asm/mpc85xx_gpio.h into asm/gpio.h 2. Fix Incompatibility in functions gpio_free() and gpio_set_value() definitions between <asm/mpc85xx_gpio.h> and <asm-generic/gpio.h> Signed-off-by: Michael Durrant <mdurrant(a)arcturusnetworks.com> Signed-off-by: Oleksandr G Zhadan <oleks(a)arcturusnetworks.com> --- arch/powerpc/include/asm/arch-mpc85xx/gpio.h | 2 ++ arch/powerpc/include/asm/mpc85xx_gpio.h | 6 ++++-- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/include/asm/arch-mpc85xx/gpio.h b/arch/powerpc/include/asm/arch-mpc85xx/gpio.h index 8beed30..71794a8 100644 --- a/arch/powerpc/include/asm/arch-mpc85xx/gpio.h +++ b/arch/powerpc/include/asm/arch-mpc85xx/gpio.h @@ -12,4 +12,6 @@ #ifndef __ASM_ARCH_MX85XX_GPIO_H #define __ASM_ARCH_MX85XX_GPIO_H +#include <asm/mpc85xx_gpio.h> + #endif diff --git a/arch/powerpc/include/asm/mpc85xx_gpio.h b/arch/powerpc/include/asm/mpc85xx_gpio.h index 87bb4a0..1d0dad4 100644 --- a/arch/powerpc/include/asm/mpc85xx_gpio.h +++ b/arch/powerpc/include/asm/mpc85xx_gpio.h @@ -72,9 +72,10 @@ static inline int gpio_request(unsigned gpio, const char *label) return 0; } -static inline void gpio_free(unsigned gpio) +static inline int gpio_free(unsigned gpio) { /* Compatibility shim */ + return 0; } static inline int gpio_direction_input(unsigned gpio) @@ -97,12 +98,13 @@ static inline int gpio_get_value(unsigned gpio) return !!mpc85xx_gpio_get(1U << gpio); } -static inline void gpio_set_value(unsigned gpio, int value) +static inline int gpio_set_value(unsigned gpio, int value) { if (value) mpc85xx_gpio_set_high(1U << gpio); else mpc85xx_gpio_set_low(1U << gpio); + return 0; } static inline int gpio_is_valid(int gpio) -- 2.1.4

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[U-Boot] [PATCH] New QorIQ p1020 based board support from Arcturus Networks Inc.
by Oleksandr G Zhadan 28 Apr '15

28 Apr '15

New QorIQ p1020 based board support from Arcturus Networks Inc. http://www.arcturusnetworks.com/products/ucp1020/ Signed-off-by: Michael Durrant <mdurrant(a)arcturusnetworks.com> Signed-off-by: Oleksandr G Zhadan <oleks(a)arcturusnetworks.com> --- arch/powerpc/cpu/mpc85xx/Kconfig | 4 + board/Arcturus/ucp1020/Kconfig | 44 ++ board/Arcturus/ucp1020/MAINTAINERS | 7 + board/Arcturus/ucp1020/Makefile | 33 ++ board/Arcturus/ucp1020/README | 54 ++ board/Arcturus/ucp1020/cmd_arc.c | 215 +++++++ board/Arcturus/ucp1020/ddr.c | 161 ++++++ board/Arcturus/ucp1020/law.c | 25 + board/Arcturus/ucp1020/spl.c | 126 ++++ board/Arcturus/ucp1020/spl_minimal.c | 67 +++ board/Arcturus/ucp1020/tlb.c | 101 ++++ board/Arcturus/ucp1020/ucp1020.c | 383 ++++++++++++ configs/UCP1020_SPIFLASH_defconfig | 6 + configs/UCP1020_defconfig | 5 + include/configs/UCP1020.h | 1058 ++++++++++++++++++++++++++++++++++ 15 files changed, 2289 insertions(+) create mode 100644 board/Arcturus/ucp1020/Kconfig create mode 100644 board/Arcturus/ucp1020/MAINTAINERS create mode 100644 board/Arcturus/ucp1020/Makefile create mode 100644 board/Arcturus/ucp1020/README create mode 100644 board/Arcturus/ucp1020/cmd_arc.c create mode 100644 board/Arcturus/ucp1020/ddr.c create mode 100644 board/Arcturus/ucp1020/law.c create mode 100644 board/Arcturus/ucp1020/spl.c create mode 100644 board/Arcturus/ucp1020/spl_minimal.c create mode 100644 board/Arcturus/ucp1020/tlb.c create mode 100644 board/Arcturus/ucp1020/ucp1020.c create mode 100644 configs/UCP1020_SPIFLASH_defconfig create mode 100644 configs/UCP1020_defconfig create mode 100644 include/configs/UCP1020.h diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index adb5bd3..e481ab4 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -153,6 +153,9 @@ config TARGET_XPEDITE537X config TARGET_XPEDITE550X bool "Support xpedite550x" +config TARGET_UCP1020 + bool "Support uCP1020" + endchoice source "board/freescale/b4860qds/Kconfig" @@ -194,5 +197,6 @@ source "board/stx/stxssa/Kconfig" source "board/xes/xpedite520x/Kconfig" source "board/xes/xpedite537x/Kconfig" source "board/xes/xpedite550x/Kconfig" +source "board/Arcturus/ucp1020/Kconfig" endmenu diff --git a/board/Arcturus/ucp1020/Kconfig b/board/Arcturus/ucp1020/Kconfig new file mode 100644 index 0000000..feca03a --- /dev/null +++ b/board/Arcturus/ucp1020/Kconfig @@ -0,0 +1,44 @@ +if TARGET_UCP1020 + +config SYS_BOARD + string + default "ucp1020" + +config SYS_VENDOR + string + default "Arcturus" + +config SYS_CONFIG_NAME + string + default "UCP1020" + +config SPI_FLASH + bool + default y + +config SPI_PCI + bool + default y + +choice + prompt "Target image select" + +config TARGET_UCP1020_NOR + bool "NOR flash u-boot image" + +config TARGET_UCP1020_SPIFLASH + bool "SPI flash u-boot image" + +endchoice + +if TARGET_UCP1020_SPIFLASH +config UCBOOT + bool + default y + +config SPIFLASH + bool + default y +endif + +endif diff --git a/board/Arcturus/ucp1020/MAINTAINERS b/board/Arcturus/ucp1020/MAINTAINERS new file mode 100644 index 0000000..e4a4718 --- /dev/null +++ b/board/Arcturus/ucp1020/MAINTAINERS @@ -0,0 +1,7 @@ +UCP1020 BOARD +M: Oleksandr Zhadan and Michael Durrant <arcsupport(a)arcturusnetworks.com> +S: Maintained +F: board/Arcturus/ucp1020/ +F: include/configs/UCP1020.h +F: configs/UCP1020_defconfig +F: configs/UCP1020_SPIFLASH_defconfig diff --git a/board/Arcturus/ucp1020/Makefile b/board/Arcturus/ucp1020/Makefile new file mode 100644 index 0000000..35c88b9 --- /dev/null +++ b/board/Arcturus/ucp1020/Makefile @@ -0,0 +1,33 @@ +# +# Copyright 2013-2015 Arcturus Networks, Inc. +# based on board/freescale/p1_p2_rdb_pc/Makefile +# original copyright follows: +# Copyright 2010-2011 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +MINIMAL= + +ifdef CONFIG_SPL_BUILD +ifdef CONFIG_SPL_INIT_MINIMAL +MINIMAL=y +endif +endif + +ifdef MINIMAL + +obj-y += spl_minimal.o tlb.o law.o + +else +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +endif + +obj-y += ucp1020.o +obj-y += ddr.o +obj-y += law.o +obj-y += tlb.o +obj-y += cmd_arc.o + +endif diff --git a/board/Arcturus/ucp1020/README b/board/Arcturus/ucp1020/README new file mode 100644 index 0000000..555c4ef --- /dev/null +++ b/board/Arcturus/ucp1020/README @@ -0,0 +1,54 @@ +The uCP1020 product family (ucp1020) is an Arcturus Networks Inc. System on Modules +product featuring a Freescale P1020 CPU, optionally populated with 1, 2 or 3 Gig-Ethernet PHYs, +DDR3, NOR Flash, eMMC NAND Flash and/or SPI Flash. + +Information on the generic product family can be found here: + http://www.arcturusnetworks.com/products/ucp1020 + +The UCP1020 several configurable options +======================================== + +- the selection of populated phy(s): + KSZ9031 (current default for eTSEC 1 and 3) + +- the selection of boot location: + SPI Flash or NOR flash + +The UCP1020 includes 2 default configurations +============================================= +NOR boot image: + configs/UCP1020_defconfig +SPI boot image: + configs/UCP1020_SPIFLASH_defconfig + +The UCP1020 adds an additional command in cmd_arc.c to access and program +SPI resident factory defaults for serial number, and 1, 2 or 3 Ethernet +HW Addresses. + + +Build example +============= + +make distclean +make UCP1020_defconfig +make + +Default Scripts +=============== +A default upgrade scripts is included in the default environment variable example: + +B$ run tftpflash + +Dual Environment +================ + +This build enables dual / failover environment environment. + +NOR Flash Partition declarations and scripts +============================================ +Several scripts are available to allow TFTP of images and programming directly +into defined NOR flash partitions. Examples: + +B$ run program0 +B$ run program1 +B$ run program2 diff --git a/board/Arcturus/ucp1020/cmd_arc.c b/board/Arcturus/ucp1020/cmd_arc.c new file mode 100644 index 0000000..bfd91ae --- /dev/null +++ b/board/Arcturus/ucp1020/cmd_arc.c @@ -0,0 +1,215 @@ +/* + * Command for accessing Arcturus factory environment. + * + * Copyright 2013-2015 Arcturus Networks Inc. + * http://www.arcturusnetworks.com/products/ucp1020/ + * by Oleksandr G Zhadan et al. + * + * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause + * + */ + +#include <common.h> +#include <div64.h> +#include <malloc.h> +#include <spi_flash.h> + +#include <asm/io.h> + +#ifndef CONFIG_SF_DEFAULT_SPEED +# define CONFIG_SF_DEFAULT_SPEED 1000000 +#endif +#ifndef CONFIG_SF_DEFAULT_MODE +# define CONFIG_SF_DEFAULT_MODE SPI_MODE0 +#endif +#ifndef CONFIG_SF_DEFAULT_CS +# define CONFIG_SF_DEFAULT_CS 0 +#endif +#ifndef CONFIG_SF_DEFAULT_BUS +# define CONFIG_SF_DEFAULT_BUS 0 +#endif + +#define MAX_SERIAL_SIZE 15 +#define MAX_HWADDR_SIZE 17 + +static struct spi_flash *flash; +char smac[4][18]; + +static int ishwaddr(char *hwaddr) +{ + if (strlen(hwaddr) == MAX_HWADDR_SIZE) + if (hwaddr[2] == ':' && + hwaddr[5] == ':' && + hwaddr[8] == ':' && + hwaddr[11] == ':' && + hwaddr[14] == ':') + return 0; + return -1; +} + +static int set_arc_product(int argc, char *const argv[]) +{ + int err = 0; + char mystrerr[] = "ERROR: Failed to save factory info in spi locations"; + + if (argc != 5) + return -1; + + /* Check serial number */ + if (strlen(argv[1]) != MAX_SERIAL_SIZE) + return -1; + + /* Check HWaddrs */ + if (ishwaddr(argv[2]) || ishwaddr(argv[3]) || ishwaddr(argv[4])) + return -1; + + strcpy(smac[3], argv[1]); + strcpy(smac[2], argv[2]); + strcpy(smac[1], argv[3]); + strcpy(smac[0], argv[4]); + + flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS, + CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE); + + /* + * Save factory defaults + */ + if (spi_flash_write(flash, (0x200 - sizeof(smac)), sizeof(smac), smac)) { + printf("%s: %s [1]\n", __func__, mystrerr); + err++; + } + if (spi_flash_write(flash, (0x400 - sizeof(smac)), sizeof(smac), smac)) { + printf("%s: %s [2]\n", __func__, mystrerr); + err++; + } + + if (spi_flash_write(flash, (CONFIG_ENV_SECT_SIZE + 0x200 - sizeof(smac)), sizeof(smac), smac)) { + printf("%s: %s [3]\n", __func__, mystrerr); + err++; + } + + if (spi_flash_write(flash, (CONFIG_ENV_SECT_SIZE + 0x400 - sizeof(smac)), sizeof(smac), smac)) { + printf("%s: %s [4]\n", __func__, mystrerr); + err++; + } + + if (err == 4) { + printf("%s: %s [ALL]\n", __func__, mystrerr); + return -2; + } + + return 0; +} + +int get_arc_info(void) +{ + int location = 1; + + flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS, + CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE); + + if (spi_flash_read(flash, (0x200 - sizeof(smac)), sizeof(smac), smac)) { + location++; + if (spi_flash_read(flash, (0x400 - sizeof(smac)), sizeof(smac), smac)) { + location++; + if (spi_flash_read(flash, (CONFIG_ENV_SECT_SIZE + 0x200 - sizeof(smac)), sizeof(smac), smac)) { + location++; + if (spi_flash_read(flash, (CONFIG_ENV_SECT_SIZE + 0x400 - sizeof(smac)), sizeof(smac), smac)) { + printf("%s: ERROR: Failed to read all %d factory info spi locations\n", __func__, location); + return -2; + } + } + } + } + if (smac[3][0] != 0) { + if (location > 1) + printf("Using region %d\n", location); + printf("SERIAL: "); + if (smac[3][0] == 0xFF) { + printf("\t<not found>\n"); + } else { + printf("\t%s\n", smac[3]); + setenv("SERIAL", smac[3]); + } + } + if (strcmp(smac[2], "00:00:00:00:00:00") != 0) { + printf("HWADDR0:"); + if (smac[2][0] == 0xFF) { + printf("\t<not found>\n"); + } else { + char *ret = getenv("ethaddr"); + + if (strcmp(ret, __stringify(CONFIG_ETHADDR)) == 0) { + setenv("ethaddr", smac[2]); + printf("\t%s (factory)\n", smac[2]); + } else { + printf("\t%s\n", ret); + } + } + if (strcmp(smac[1], "00:00:00:00:00:00") != 0) { + printf("HWADDR1:"); + if (smac[1][0] == 0xFF) { + printf("\t<not found>\n"); + } else { + char *ret = getenv("eth1addr"); + + if (strcmp(ret, __stringify(CONFIG_ETH1ADDR)) == 0) { + setenv("eth1addr", smac[1]); + printf("\t%s (factory)\n", smac[1]); + } else { + printf("\t%s\n", ret); + } + } + if (strcmp(smac[0], "00:00:00:00:00:00") != 0) { + printf("HWADDR2:"); + if (smac[0][0] == 0xFF) { + printf("\t<not found>\n"); + } else { + char *ret = getenv("eth2addr"); + + if (strcmp(ret, __stringify(CONFIG_ETH2ADDR)) == 0) { + setenv("eth2addr", smac[0]); + printf("\t%s (factory)\n", smac[0]); + } else { + printf("\t%s\n", ret); + } + } + } else { + setenv("eth2addr", smac[1]); + } + } else { + setenv("eth1addr", smac[2]); + setenv("eth2addr", smac[2]); + } + } + return 0; +} + +static int do_arc_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + const char *cmd; + int ret = -1; + + cmd = argv[1]; + --argc; + ++argv; + + if (strcmp(cmd, "product") == 0) { + ret = set_arc_product(argc, argv); + goto done; + } + if (strcmp(cmd, "info") == 0) { + ret = get_arc_info(); + goto done; + } +done: + if (ret == -1) + return CMD_RET_USAGE; + + return ret; +} + +U_BOOT_CMD(arc, 6, 1, do_arc_cmd, + "Arcturus product command sub-system", + "product serial hwaddr0 hwaddr1 hwaddr2 - save Arcturus factory env\n" + "info - show Arcturus factory env\n\n"); diff --git a/board/Arcturus/ucp1020/ddr.c b/board/Arcturus/ucp1020/ddr.c new file mode 100644 index 0000000..42fbae0 --- /dev/null +++ b/board/Arcturus/ucp1020/ddr.c @@ -0,0 +1,161 @@ +/* + * Copyright 2013-2015 Arcturus Networks, Inc. + * http://www.arcturusnetworks.com/products/ucp1020/ + * based on board/freescale/p1_p2_rdb_pc/spl.c + * original copyright follows: + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/mmu.h> +#include <asm/immap_85xx.h> +#include <asm/processor.h> +#include <fsl_ddr_sdram.h> +#include <fsl_ddr_dimm_params.h> +#include <asm/io.h> +#include <asm/fsl_law.h> + +#ifdef CONFIG_SYS_DDR_RAW_TIMING +#if defined(CONFIG_UCP1020) || defined(CONFIG_UCP1020T1) +/* + * Micron MT41J128M16HA-15E + * */ +dimm_params_t ddr_raw_timing = { + .n_ranks = 1, + .rank_density = 536870912u, + .capacity = 536870912u, + .primary_sdram_width = 32, + .ec_sdram_width = 8, + .registered_dimm = 0, + .mirrored_dimm = 0, + .n_row_addr = 14, + .n_col_addr = 10, + .n_banks_per_sdram_device = 8, + .edc_config = 2, + .burst_lengths_bitmask = 0x0c, + + .tckmin_x_ps = 1650, + .caslat_x = 0x7e << 4, /* 5,6,7,8,9,10 */ + .taa_ps = 14050, + .twr_ps = 15000, + .trcd_ps = 13500, + .trrd_ps = 75000, + .trp_ps = 13500, + .tras_ps = 40000, + .trc_ps = 49500, + .trfc_ps = 160000, + .twtr_ps = 75000, + .trtp_ps = 75000, + .refresh_rate_ps = 7800000, + .tfaw_ps = 30000, +}; + +#else +#error Missing raw timing data for this board +#endif + +int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, + unsigned int controller_number, + unsigned int dimm_number) +{ + const char dimm_model[] = "Fixed DDR on board"; + + if ((controller_number == 0) && (dimm_number == 0)) { + memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); + memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); + memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); + } + + return 0; +} +#endif /* CONFIG_SYS_DDR_RAW_TIMING */ + +#ifdef CONFIG_SYS_DDR_CS0_BNDS +/* Fixed sdram init -- doesn't use serial presence detect. */ +phys_size_t fixed_sdram(void) +{ + sys_info_t sysinfo; + char buf[32]; + size_t ddr_size; + fsl_ddr_cfg_regs_t ddr_cfg_regs = { + .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, + .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, +#if CONFIG_CHIP_SELECTS_PER_CTRL > 1 + .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, + .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, + .cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2, +#endif + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3, + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0, + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1, + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2, + .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1, + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2, + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL, + .ddr_data_init = CONFIG_SYS_DDR_DATA_INIT, + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL, + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL, + .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 + }; + + get_sys_info(&sysinfo); + printf("Configuring DDR for %s MT/s data rate\n", + strmhz(buf, sysinfo.freq_ddrbus)); + + ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; + + fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0); + + if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, + ddr_size, LAW_TRGT_IF_DDR_1) < 0) { + printf("ERROR setting Local Access Windows for DDR\n"); + return 0; + }; + + return ddr_size; +} +#endif + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + int i; + + popts->clk_adjust = 6; + popts->cpo_override = 0x1f; + popts->write_data_delay = 2; + popts->half_strength_driver_enable = 1; + /* Write leveling override */ + popts->wrlvl_en = 1; + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + popts->wrlvl_start = 0x8; + popts->trwt_override = 1; + popts->trwt = 0; + + if (pdimm->primary_sdram_width == 64) + popts->data_bus_width = 0; + else if (pdimm->primary_sdram_width == 32) + popts->data_bus_width = 1; + else + printf("Error in DDR bus width configuration!\n"); + + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER; + popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS; + } +} diff --git a/board/Arcturus/ucp1020/law.c b/board/Arcturus/ucp1020/law.c new file mode 100644 index 0000000..7d40905 --- /dev/null +++ b/board/Arcturus/ucp1020/law.c @@ -0,0 +1,25 @@ +/* + * Copyright 2013-2015 Arcturus Networks, Inc. + * http://www.arcturusnetworks.com/products/ucp1020/ + * based on board/freescale/p1_p2_rdb_pc/spl.c + * original copyright follows: + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/fsl_law.h> +#include <asm/mmu.h> + +struct law_entry law_table[] = { +#ifdef CONFIG_VSC7385_ENET + SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), +#endif + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC), +#ifdef CONFIG_SYS_NAND_BASE_PHYS + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC), +#endif +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/Arcturus/ucp1020/spl.c b/board/Arcturus/ucp1020/spl.c new file mode 100644 index 0000000..236b0d0 --- /dev/null +++ b/board/Arcturus/ucp1020/spl.c @@ -0,0 +1,126 @@ +/* + * Copyright 2013-2015 Arcturus Networks, Inc. + * http://www.arcturusnetworks.com/products/ucp1020/ + * based on board/freescale/p1_p2_rdb_pc/spl.c + * original copyright follows: + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <ns16550.h> +#include <malloc.h> +#include <mmc.h> +#include <nand.h> +#include <i2c.h> +#include <fsl_esdhc.h> +#include <spi_flash.h> + +DECLARE_GLOBAL_DATA_PTR; + +static const u32 sysclk_tbl[] = { + 66666000, 7499900, 83332500, 8999900, + 99999000, 11111000, 12499800, 13333200 +}; + +phys_size_t get_effective_memsize(void) +{ + return CONFIG_SYS_L2_SIZE; +} + +void board_init_f(ulong bootflag) +{ + u32 plat_ratio, bus_clk; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + + console_init_f(); + + /* Set pmuxcr to allow both i2c1 and i2c2 */ + setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000); + setbits_be32(&gur->pmuxcr, + in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA); + + /* Read back the register to synchronize the write. */ + in_be32(&gur->pmuxcr); + +#ifdef CONFIG_SPL_SPI_BOOT + clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA); +#endif + + /* initialize selected port with appropriate baud rate */ + plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; + plat_ratio >>= 1; + bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; + gd->bus_clk = bus_clk; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + bus_clk / 16 / CONFIG_BAUDRATE); +#ifdef CONFIG_SPL_MMC_BOOT + puts("\nSD boot...\n"); +#elif defined(CONFIG_SPL_SPI_BOOT) + puts("\nSPI Flash boot...\n"); +#endif + + /* copy code to RAM and jump to it - this should not return */ + /* NOTE - code has to be copied out of NAND buffer before + * other blocks can be read. + */ + relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + /* Pointer is writable since we allocated a register for it */ + gd = (gd_t *)CONFIG_SPL_GD_ADDR; + bd_t *bd; + + memset(gd, 0, sizeof(gd_t)); + bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t)); + memset(bd, 0, sizeof(bd_t)); + gd->bd = bd; + bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR; + bd->bi_memsize = CONFIG_SYS_L2_SIZE; + + probecpu(); + get_clocks(); + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, + CONFIG_SPL_RELOC_MALLOC_SIZE); + +#ifndef CONFIG_SPL_NAND_BOOT + env_init(); +#endif +#ifdef CONFIG_SPL_MMC_BOOT + mmc_initialize(bd); +#endif + /* relocate environment function pointers etc. */ +#ifdef CONFIG_SPL_NAND_BOOT + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); + gd->env_addr = (ulong)(CONFIG_ENV_ADDR); + gd->env_valid = 1; +#else + env_relocate(); +#endif + +#ifdef CONFIG_SYS_I2C + i2c_init_all(); +#else + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +#endif + + gd->ram_size = initdram(0); +#ifdef CONFIG_SPL_NAND_BOOT + puts("Tertiary program loader running in sram..."); +#else + puts("Second program loader running in sram...\n"); +#endif + +#ifdef CONFIG_SPL_MMC_BOOT + mmc_boot(); +#elif defined(CONFIG_SPL_SPI_BOOT) + spi_boot(); +#elif defined(CONFIG_SPL_NAND_BOOT) + nand_boot(); +#endif +} diff --git a/board/Arcturus/ucp1020/spl_minimal.c b/board/Arcturus/ucp1020/spl_minimal.c new file mode 100644 index 0000000..5bdefb8 --- /dev/null +++ b/board/Arcturus/ucp1020/spl_minimal.c @@ -0,0 +1,67 @@ +/* + * Copyright 2013-2015 Arcturus Networks, Inc. + * http://www.arcturusnetworks.com/products/ucp1020/ + * based on board/freescale/p1_p2_rdb_pc/spl_minimal.c + * original copyright follows: + * Copyright 2011 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <ns16550.h> +#include <asm/io.h> +#include <nand.h> +#include <linux/compiler.h> +#include <asm/fsl_law.h> +#include <fsl_ddr_sdram.h> +#include <asm/global_data.h> + +DECLARE_GLOBAL_DATA_PTR; + +void board_init_f(ulong bootflag) +{ + u32 plat_ratio; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + +#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM) + set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM); + set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM); +#endif + + /* initialize selected port with appropriate baud rate */ + plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; + plat_ratio >>= 1; + gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + gd->bus_clk / 16 / CONFIG_BAUDRATE); + + puts("\nNAND boot... "); + + /* copy code to RAM and jump to it - this should not return */ + /* NOTE - code has to be copied out of NAND buffer before + * other blocks can be read. + */ + relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + puts("\nSecond program loader running in sram..."); + nand_boot(); +} + +void putc(char c) +{ + if (c == '\n') + NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r'); + + NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c); +} + +void puts(const char *str) +{ + while (*str) + putc(*str++); +} diff --git a/board/Arcturus/ucp1020/tlb.c b/board/Arcturus/ucp1020/tlb.c new file mode 100644 index 0000000..fd7134f --- /dev/null +++ b/board/Arcturus/ucp1020/tlb.c @@ -0,0 +1,101 @@ +/* + * Copyright 2013-2015 Arcturus Networks, Inc + * http://www.arcturusnetworks.com/products/ucp1020/ + * based on board/freescale/p1_p2_rdb_pc/tlb.c + * original copyright follows: + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, + CONFIG_SYS_INIT_RAM_ADDR_PHYS, + MAS3_SX | MAS3_SW | MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + MAS3_SX | MAS3_SW | MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + MAS3_SX | MAS3_SW | MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + MAS3_SX | MAS3_SW | MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I, + 0, 0, BOOKE_PAGESZ_4K, 1), + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 1, BOOKE_PAGESZ_1M, 1), + +#ifndef CONFIG_SPL_BUILD + /* W**G* - Flash/promjet, localbus */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX | MAS3_SR, MAS2_W | MAS2_G, + 0, 2, BOOKE_PAGESZ_64M, 1), + +#ifdef CONFIG_PCI + /* *I*G* - PCI memory 1.5G */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 3, BOOKE_PAGESZ_1G, 1), + + /* *I*G* - PCI I/O effective: 192K */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 4, BOOKE_PAGESZ_256K, 1), +#endif + +#ifdef CONFIG_VSC7385_ENET + /* *I*G - VSC7385 Switch */ + SET_TLB_ENTRY(1, CONFIG_SYS_VSC7385_BASE, CONFIG_SYS_VSC7385_BASE_PHYS, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 5, BOOKE_PAGESZ_1M, 1), +#endif +#endif /* not SPL */ + +#ifdef CONFIG_SYS_NAND_BASE + /* *I*G - NAND */ + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 7, BOOKE_PAGESZ_1M, 1), +#endif + +#if defined(CONFIG_SYS_RAMBOOT) || \ + (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR)) + /* *I*G - eSDHC/eSPI/NAND boot */ + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX | MAS3_SW | MAS3_SR, 0, + 0, 8, BOOKE_PAGESZ_1G, 1), + +#endif /* RAMBOOT/SPL */ + +#ifdef CONFIG_SYS_INIT_L2_ADDR + /* *I*G - L2SRAM */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_G, + 0, 11, BOOKE_PAGESZ_256K, 1), +#if CONFIG_SYS_L2_SIZE >= (256 << 10) + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000, + CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 12, BOOKE_PAGESZ_256K, 1) +#endif +#endif +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/Arcturus/ucp1020/ucp1020.c b/board/Arcturus/ucp1020/ucp1020.c new file mode 100644 index 0000000..daba4c7 --- /dev/null +++ b/board/Arcturus/ucp1020/ucp1020.c @@ -0,0 +1,383 @@ +/* + * Copyright 2013-2015 Arcturus Networks, Inc. + * http://www.arcturusnetworks.com/products/ucp1020/ + * by Oleksandr G Zhadan et al. + * based on board/freescale/p1_p2_rdb_pc/spl.c + * original copyright follows: + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <hwconfig.h> +#include <pci.h> +#include <i2c.h> +#include <miiphy.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <fsl_mdio.h> +#include <tsec.h> +#include <ioports.h> +#include <netdev.h> +#include <micrel.h> +#include <spi_flash.h> +#include <mmc.h> +#include <linux/ctype.h> +#include <asm/fsl_serdes.h> +#include <asm/gpio.h> +#include <asm/processor.h> +#include <asm/mmu.h> +#include <asm/cache.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_pci.h> +#include <fsl_ddr_sdram.h> +#include <asm/io.h> +#include <asm/fsl_law.h> +#include <asm/fsl_lbc.h> +#include <asm/mp.h> + +#define GPIO0 31 +#define GPIO1 30 +#define GPIO2 29 +#define GPIO3 28 +#define GPIO4 27 +#define GPIO5 26 +#define GPIO6 25 +#define GPIO7 24 +#define GPIO8 23 +#define GPIO9 22 +#define GPIO10 21 +#define GPIO11 20 +#define GPIO12 19 +#define GPIO13 18 +#define GPIO14 17 +#define GPIO15 16 +#define GPIO_MAX_NUM 16 + +#define GPIO_SDHC_CD GPIO8 +#define GPIO_SDHC_WP GPIO9 +#define GPIO_USB_PCTL0 GPIO10 +#define GPIO_PCIE1_EN GPIO11 +#define GPIO_PCIE2_EN GPIO10 +#define GPIO_USB_PCTL1 GPIO11 + +#define GPIO_WD GPIO15 + +int get_arc_info(void); + +void spi_set_speed(struct spi_slave *slave, uint hz) +{ + /* TO DO: It's actially have to be in spi/ */ +} + +/* + * To be compatible with cmd_gpio + */ +int name_to_gpio(const char *name) +{ + int gpio = 31 - simple_strtoul(name, NULL, 10); + + if (gpio < 16) + gpio = -1; + + return gpio; +} + +void board_gpio_init(void) +{ + int i; + char envname[8], *val; + + for (i = 0; i < GPIO_MAX_NUM; i++) { + sprintf(envname, "GPIO%d", i); + val = getenv(envname); + if (val) { + char direction = toupper(val[0]); + char level = toupper(val[1]); + + if (direction == 'I') { + gpio_direction_input(i); + } else { + if (direction == 'O') { + if (level == '1') + gpio_direction_output(i, 1); + else + gpio_direction_output(i, 0); + } + } + } + } + + val = getenv("PCIE_OFF"); + if (val) { + gpio_direction_input(GPIO_PCIE1_EN); + gpio_direction_input(GPIO_PCIE2_EN); + } else { + gpio_direction_output(GPIO_PCIE1_EN, 1); + gpio_direction_output(GPIO_PCIE2_EN, 1); + } + + val = getenv("SDHC_CDWP_OFF"); + if (!val) { + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + setbits_be32(&gur->pmuxcr, (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP)); + } +} + +int board_early_init_f(void) +{ + return 0; /* Just in case. Could be disable in config file */ +} + +int checkboard(void) +{ + printf("Board: %s\n", CONFIG_BOARDNAME_LOCAL); + board_gpio_init(); + printf("SD/MMC: 4-bit Mode\n"); + + return 0; +} + +#ifdef CONFIG_PCI +void pci_init_board(void) +{ + fsl_pcie_init_board(0); +} +#endif + +int board_early_init_r(void) +{ + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + + /* + * Remap Boot flash region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + /* invalidate existing TLB entry for flash */ + disable_tlb(flash_esel); + + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, /* perms, wimge */ + 0, flash_esel, BOOKE_PAGESZ_64M, 1); /* ts, esel, tsize, iprot */ + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ +#if defined(CONFIG_PHY_MICREL_KSZ9021) + int regval; + static int cnt; + + if (cnt++ == 0) + printf("PHYs address ["); + + if (phydev->addr == TSEC1_PHY_ADDR || phydev->addr == TSEC3_PHY_ADDR) { + regval = ksz9021_phy_extended_read(phydev, MII_KSZ9021_EXT_STRAP_STATUS); + /* + * min rx data delay + */ + ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x6666); + /* + * max rx/tx clock delay, min rx/tx control + */ + ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf6f6); + printf("0x%x", (regval & 0x1f)); + } else { + printf("0x%x", (TSEC2_PHY_ADDR & 0x1f)); + } + if (cnt == 3) + printf("] "); + else + printf(","); +#endif + +#if defined(CONFIG_PHY_MICREL_KSZ9031_DEBUG) + regval = ksz9031_phy_extended_read(phydev, 2, 0x01, 0x4000); + if (regval >= 0) + printf(" (ADDR 0x%x) ", regval & 0x1f); +#endif + + return 0; +} + +int last_stage_init(void) +{ + static char newkernelargs[256]; + static u8 id1[16]; + static u8 id2; + struct mmc *mmc; + char *sval, *kval; + + if (i2c_read(CONFIG_SYS_I2C_IDT6V49205B, 7, 1, &id1[0], 2) < 0) { + printf("Error reading i2c IDT6V49205B information!\n"); + } else { + printf("IDT6V49205B(0x%02x): ready\n", id1[1]); + i2c_read(CONFIG_SYS_I2C_IDT6V49205B, 4, 1, &id1[0], 2); + if (!(id1[1] & 0x02)) { + id1[1] |= 0x02; + i2c_write(CONFIG_SYS_I2C_IDT6V49205B, 4, 1, &id1[0], 2); + asm("nop; nop"); + } + } + + if (i2c_read(CONFIG_SYS_I2C_NCT72_ADDR, 0xFE, 1, &id2, 1) < 0) + printf("Error reading i2c NCT72 information!\n"); + else + printf("NCT72(0x%x): ready\n", id2); + + kval = getenv("kernelargs"); + + mmc = find_mmc_device(0); + if (mmc) + if (!mmc_init(mmc)) { + printf("MMC/SD card detected\n"); + if (kval) { + char *tmp = strstr(kval, "root=/dev/mtdblock1 rootfstype=cramfs ro"); + int n = strlen("root=/dev/mtdblock1 rootfstype=cramfs ro"); + + *tmp = 0; + strcpy(newkernelargs, kval); + strcat(newkernelargs, " root=/dev/mmcblk0p1 rootwait rw "); + strcat(newkernelargs, &tmp[n]); + setenv("kernelargs", newkernelargs); + } else { + setenv("kernelargs", "root=/dev/mmcblk0p1 rootwait rw"); + } + } + get_arc_info(); + + if (kval) { + sval = getenv("SERIAL"); + if (sval) { + strcpy(newkernelargs, "SN="); + strcat(newkernelargs, sval); + strcat(newkernelargs, " "); + strcat(newkernelargs, kval); + setenv("kernelargs", newkernelargs); + } + } else { + printf("Error reading kernelargs env variable!\n"); + } + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + struct fsl_pq_mdio_info mdio_info; + struct tsec_info_struct tsec_info[4]; +#ifdef CONFIG_TSEC2 + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); +#endif + int num = 0; + +#ifdef CONFIG_TSEC1 + SET_STD_TSEC_INFO(tsec_info[num], 1); + num++; +#endif +#ifdef CONFIG_TSEC2 + SET_STD_TSEC_INFO(tsec_info[num], 2); + if (is_serdes_configured(SGMII_TSEC2)) { + if ((in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_SGMII2_DIS) == 0) { + puts("eTSEC2 is in sgmii mode.\n"); + tsec_info[num].flags |= TSEC_SGMII; + tsec_info[num].phyaddr = TSEC2_PHY_ADDR_SGMII; + } + } + num++; +#endif +#ifdef CONFIG_TSEC3 + SET_STD_TSEC_INFO(tsec_info[num], 3); + num++; +#endif + + if (!num) { + printf("No TSECs initialized\n"); + return 0; + } + + mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; + mdio_info.name = DEFAULT_MII_NAME; + + fsl_pq_mdio_init(bis, &mdio_info); + + tsec_eth_init(bis, tsec_info, num); + + return pci_eth_init(bis); +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + const char *soc_usb_compat = "fsl-usb2-dr"; + int err, usb1_off, usb2_off; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + + FT_FSL_PCI_SETUP; + +#if defined(CONFIG_HAS_FSL_DR_USB) + fdt_fixup_dr_usb(blob, bd); +#endif + +#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) + /* Delete eLBC node as it is muxed with USB2 controller */ + if (hwconfig("usb2")) { + const char *soc_elbc_compat = "fsl,p1020-elbc"; + int off = fdt_node_offset_by_compatible(blob, -1, + soc_elbc_compat); + if (off < 0) { + printf("WARNING: could not find compatible node %s: %s.\n", + soc_elbc_compat, + fdt_strerror(off)); + return off; + } + err = fdt_del_node(blob, off); + if (err < 0) { + printf("WARNING: could not remove %s: %s.\n", + soc_elbc_compat, fdt_strerror(err)); + } + return err; + } +#endif + +/* Delete USB2 node as it is muxed with eLBC */ + usb1_off = fdt_node_offset_by_compatible(blob, -1, soc_usb_compat); + if (usb1_off < 0) { + printf("WARNING: could not find compatible node %s: %s.\n", + soc_usb_compat, + fdt_strerror(usb1_off)); + return usb1_off; + } + usb2_off = fdt_node_offset_by_compatible(blob, usb1_off, soc_usb_compat); + if (usb2_off < 0) { + printf("WARNING: could not find compatible node %s: %s.\n", + soc_usb_compat, + fdt_strerror(usb2_off)); + return usb2_off; + } + err = fdt_del_node(blob, usb2_off); + if (err < 0) { + printf("WARNING: could not remove %s: %s.\n", + soc_usb_compat, fdt_strerror(err)); + } + return 0; +} +#endif diff --git a/configs/UCP1020_SPIFLASH_defconfig b/configs/UCP1020_SPIFLASH_defconfig new file mode 100644 index 0000000..2ffb8da --- /dev/null +++ b/configs/UCP1020_SPIFLASH_defconfig @@ -0,0 +1,6 @@ +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_UCP1020=y +CONFIG_TARGET_UCP1020_SPIFLASH=y +CONFIG_SPI_FLASH=y +CONFIG_UCP1020=y diff --git a/configs/UCP1020_defconfig b/configs/UCP1020_defconfig new file mode 100644 index 0000000..61de360 --- /dev/null +++ b/configs/UCP1020_defconfig @@ -0,0 +1,5 @@ +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_UCP1020=y +CONFIG_SPI_FLASH=y +CONFIG_UCP1020=y diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h new file mode 100644 index 0000000..2bbd4ae --- /dev/null +++ b/include/configs/UCP1020.h @@ -0,0 +1,1058 @@ +/* + * Copyright 2013-2015 Arcturus Networks, Inc. + * http://www.arcturusnetworks.com/products/ucp1020/ + * based on include/configs/p1_p2_rdb_pc.h + * original copyright follows: + * Copyright 2009-2011 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * QorIQ uCP1020-xx boards configuration file + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_FSL_ELBC +#define CONFIG_PCI +#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ +#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ +#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ + +#if defined(CONFIG_TARTGET_UCP1020T1) + +#define CONFIG_UCP1020_REV_1_3 + +#define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1" +#define CONFIG_P1020 + +#define CONFIG_TSEC_ENET +#define CONFIG_TSEC1 +#define CONFIG_TSEC3 +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#define CONFIG_ETHADDR 00:19:D3:FF:FF:FF +#define CONFIG_ETH1ADDR 00:19:D3:FF:FF:FE +#define CONFIG_ETH2ADDR 00:19:D3:FF:FF:FD +#define CONFIG_IPADDR 10.80.41.229 +#define CONFIG_SERVERIP 10.80.41.227 +#define CONFIG_NETMASK 255.255.252.0 +#define CONFIG_ETHPRIME "eTSEC3" + +#ifndef CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH y +#endif +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT + +#define CONFIG_MMC +#define CONFIG_SYS_L2_SIZE (256 << 10) +#define CONFIG_ENV_FIT_UCBOOT_TODO + +#define CONFIG_LAST_STAGE_INIT + +#if !defined(CONFIG_DONGLE) +#define CONFIG_SILENT_CONSOLE +#endif + +#endif + +#if defined(CONFIG_TARGET_UCP1020) + +#define CONFIG_UCP1020 +#define CONFIG_UCP1020_REV_1_3 + +#define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR" +#define CONFIG_P1020 + +#define CONFIG_TSEC_ENET +#define CONFIG_TSEC1 +#define CONFIG_TSEC2 +#define CONFIG_TSEC3 +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#define CONFIG_HAS_ETH2 +#define CONFIG_ETHADDR 00:06:3B:FF:FF:FF +#define CONFIG_ETH1ADDR 00:06:3B:FF:FF:FE +#define CONFIG_ETH2ADDR 00:06:3B:FF:FF:FD +#define CONFIG_IPADDR 192.168.1.81 +#define CONFIG_IPADDR1 192.168.1.82 +#define CONFIG_IPADDR2 192.168.1.83 +#define CONFIG_SERVERIP 192.168.1.80 +#define CONFIG_GATEWAYIP 102.168.1.1 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_ETHPRIME "eTSEC1" + +#ifndef CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH y +#endif +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT + +#define CONFIG_MMC +#define CONFIG_SYS_L2_SIZE (256 << 10) +#define CONFIG_ENV_FIT_UCBOOT_TODO + +#define CONFIG_LAST_STAGE_INIT + +#endif + +#if defined(CONFIG_TARGET_UCP2020) +#define CONFIG_BOARDNAME "uCP2020-A" +#define CONFIG_NAND_FSL_ELBC +#define CONFIG_P2020 + +#define CONFIG_TSEC_ENET +#define CONFIG_TSEC1 +#define CONFIG_TSEC2 +#define CONFIG_TSEC3 + +#define CONFIG_SPI_FLASH +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT + +#define CONFIG_VSC7385_ENET +#define __SW_BOOT_MASK 0x03 +#define __SW_BOOT_NOR 0xc8 +#define __SW_BOOT_SPI 0x28 +#define __SW_BOOT_SD 0x68 /* or 0x18 */ +#define __SW_BOOT_NAND 0xe8 +#define __SW_BOOT_PCIE 0xa8 +#define CONFIG_SYS_L2_SIZE (512 << 10) +#define CONFIG_ENV_FIT_UCBOOT_TODO +#endif + +#if CONFIG_SYS_L2_SIZE >= (512 << 10) +/* must be 32-bit */ +#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR +#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#endif + +#ifdef CONFIG_SDCARD +#define CONFIG_RAMBOOT_SDCARD +#define CONFIG_SYS_RAMBOOT +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_SYS_TEXT_BASE 0x11000000 +#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#endif + +#ifdef CONFIG_SPIFLASH +#define CONFIG_RAMBOOT_SPIFLASH +#define CONFIG_SYS_RAMBOOT +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_SYS_TEXT_BASE 0x11000000 +#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#endif + +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#endif +#define CONFIG_SYS_TEXT_BASE_NOR 0xeff80000 + +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif + +#ifndef CONFIG_SYS_MONITOR_BASE +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif + +/* High Level Configuration Options */ +#define CONFIG_BOOKE +#define CONFIG_E500 +/* #define CONFIG_MPC85xx */ + +#define CONFIG_MP + +#define CONFIG_FSL_LAW + +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_CMD_SATA +#define CONFIG_SATA_SIL +#define CONFIG_SYS_SATA_MAX_DEVICE 2 +#define CONFIG_LIBATA +#define CONFIG_LBA48 + +#if defined(CONFIG_UCP2020) +#define CONFIG_SYS_CLK_FREQ 100000000 +#else +#define CONFIG_SYS_CLK_FREQ 66666666 +#endif +#define CONFIG_DDR_CLK_FREQ 66666666 + +#define CONFIG_HWCONFIG + +#define CONFIG_DTT_ADM1021 1 /* ADM1021 temp sensor support */ +#define CONFIG_SYS_DTT_BUS_NUM 1 /* The I2C bus for DTT */ +#define CONFIG_DTT_SENSORS { 0, 1 } /* Sensor index */ +/* + * ADM1021/NCT72 temp sensor configuration (see dtt/adm1021.c for details). + * there will be one entry in this array for each two (dummy) sensors in + * CONFIG_DTT_SENSORS. + * + * For uCP1020 module: + * - only one ADM1021/NCT72 + * - i2c addr 0x41 + * - conversion rate 0x02 = 0.25 conversions/second + * - ALERT output disabled + * - local temp sensor enabled, min set to 0 deg, max set to 85 deg + * - remote temp sensor enabled, min set to 0 deg, max set to 85 deg + */ +#define CONFIG_SYS_DTT_ADM1021 { { CONFIG_SYS_I2C_NCT72_ADDR, 0x02, 0, 1, 0, 85, 1, 0, 85} } + +#define CONFIG_CMD_DTT + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE +#define CONFIG_BTB + +#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ + +#define CONFIG_ENABLE_36BIT_PHYS + +#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x1fffffff +#define CONFIG_PANIC_HANG /* do not reset board on panic */ + +#define CONFIG_SYS_CCSRBAR 0xffe00000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR + +/* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k + SPL code*/ +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE +#endif + +/* DDR Setup */ +#define CONFIG_DDR_ECC_ENABLE +#define CONFIG_SYS_FSL_DDR3 +#ifndef CONFIG_DDR_ECC_ENABLE +#define CONFIG_SYS_DDR_RAW_TIMING +#define CONFIG_DDR_SPD +#endif +#define CONFIG_SYS_SPD_BUS_NUM 1 +#undef CONFIG_FSL_DDR_INTERACTIVE + +#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M +#define CONFIG_CHIP_SELECTS_PER_CTRL 1 +#define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 + +/* Default settings for DDR3 */ +#ifndef CONFIG_UCP2020 +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f +#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 +#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 +#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f +#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 +#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 + +#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef +#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 +#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 +#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 + +#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 +#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608 +#define CONFIG_SYS_DDR_SR_CNTR 0x00000000 +#define CONFIG_SYS_DDR_RCW_1 0x00000000 +#define CONFIG_SYS_DDR_RCW_2 0x00000000 +#ifdef CONFIG_DDR_ECC_ENABLE +#define CONFIG_SYS_DDR_CONTROL 0xE70C0000 /* Type = DDR3 & ECC */ +#else +#define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ +#endif +#define CONFIG_SYS_DDR_CONTROL_2 0x04401050 +#define CONFIG_SYS_DDR_TIMING_4 0x00220001 +#define CONFIG_SYS_DDR_TIMING_5 0x03402400 + +#define CONFIG_SYS_DDR_TIMING_3 0x00020000 +#define CONFIG_SYS_DDR_TIMING_0 0x00330004 +#define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846 +#define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF +#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 +#define CONFIG_SYS_DDR_MODE_1 0x40461520 +#define CONFIG_SYS_DDR_MODE_2 0x8000c000 +#define CONFIG_SYS_DDR_INTERVAL 0x0C300000 +#endif + +#undef CONFIG_CLOCKS_IN_MHZ + +/* + * Memory map + * + * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable + * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) + * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1 + * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable + * (early boot only) + * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable + * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable + * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable + */ + +/* + * Local Bus Definitions + */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ +#define CONFIG_SYS_FLASH_BASE 0xec000000 + +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE + +#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ + | BR_PS_16 | BR_V) + +#define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 + +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ + +#undef CONFIG_SYS_FLASH_CHECKSUM +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE + +#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ + +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ +/* Initial L1 address */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS +/* Size of used area in RAM */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ + +#define CONFIG_SYS_PMC_BASE 0xff980000 +#define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE +#define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \ + BR_PS_8 | BR_V) +#define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ + OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \ + OR_GPCM_EAD) + +#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ +#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ +#ifdef CONFIG_NAND_FSL_ELBC +#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ +#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ +#endif + +/* Serial Port - controlled on board with jumper J8 + * open - index 2 + * shorted - index 1 + */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) +#define CONFIG_NS16550_MIN_FUNCTIONS +#endif + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER + +/* + * Pass open firmware flat tree + */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS + +/* new uImage format support */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 400000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } +#define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ + +#define CONFIG_RTC_DS1337 +#define CONFIG_SYS_RTC_DS1337_NOOSC +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 +#define CONFIG_SYS_I2C_NCT72_ADDR 0x4C +#define CONFIG_SYS_I2C_IDT6V49205B 0x69 + +/* + * eSPI - Enhanced SPI + */ +#define CONFIG_HARD_SPI +#define CONFIG_FSL_ESPI + +#define CONFIG_SPI_FLASH_SST 1 +#define CONFIG_SPI_FLASH_STMICRO 1 +#define CONFIG_SPI_FLASH_WINBOND 1 +#define CONFIG_CMD_SF 1 +#define CONFIG_CMD_SPI 1 +#define CONFIG_SF_DEFAULT_SPEED 10000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 + +#if defined(CONFIG_PCI) +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ + +/* controller 2, direct to uli, tgtid 2, Base address 9000 */ +#define CONFIG_SYS_PCIE2_NAME "PCIe SLOT CON9" +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ + +/* controller 1, Slot 2, tgtid 1, Base address a000 */ +#define CONFIG_SYS_PCIE1_NAME "PCIe SLOT CON10" +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ + +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_E1000 /* Defind e1000 pci Ethernet card*/ +#define CONFIG_CMD_PCI +#define CONFIG_CMD_NET + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_DOS_PARTITION +#endif /* CONFIG_PCI */ + +/* + * Environment + */ +#ifdef CONFIG_ENV_FIT_UCBOOT + +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x20000) +#define CONFIG_ENV_SIZE 0x20000 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ + +#else + +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 10000000 +#define CONFIG_ENV_SPI_MODE 0 + +#ifdef CONFIG_RAMBOOT_SPIFLASH + +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SIZE 0x3000 /* 12KB */ +#define CONFIG_ENV_OFFSET 0x2000 /* 8KB */ +#define CONFIG_ENV_SECT_SIZE 0x1000 + +#if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT) +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE +#endif + +#elif defined(CONFIG_RAMBOOT_SDCARD) +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_FSL_FIXED_MMC_LOCATION +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#elif defined(CONFIG_SYS_RAMBOOT) +#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) +#define CONFIG_ENV_SIZE 0x2000 + +#else +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_BASE (CONFIG_SYS_FLASH_BASE) +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#define CONFIG_ENV_ADDR (CONFIG_ENV_BASE + 0xC0000) +#if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT) +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE +#endif + +#endif + +#endif /* CONFIG_ENV_FIT_UCBOOT */ + +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_PING +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_DATE +#define CONFIG_CMD_ELF +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_ERRATA +#define CONFIG_CMD_CRAMFS +#define CONFIG_CRAMFS_CMDLINE + +/* + * USB + */ +#define CONFIG_HAS_FSL_DR_USB + +#if defined(CONFIG_HAS_FSL_DR_USB) +#define CONFIG_USB_EHCI + +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 + +#ifdef CONFIG_USB_EHCI +#define CONFIG_CMD_USB +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_EHCI_FSL +#define CONFIG_USB_STORAGE +#endif +#endif + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#ifdef CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CONFIG_CMD_MMC +#define CONFIG_MMC_SPI +#define CONFIG_CMD_MMC_SPI +#define CONFIG_GENERIC_MMC +#endif + +#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) || defined(CONFIG_FSL_SATA) +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +/* Misc Extra Settings */ +#define CONFIG_CMD_GPIO 1 +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "B$ " /* Monitor Command Prompt */ +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ + +#if defined(CONFIG_TSEC_ENET) + +#if defined(CONFIG_UCP1020_REV_1_2) +#define CONFIG_PHY_MICREL_KSZ9021 +#elif defined(CONFIG_UCP1020_REV_1_3) +#define CONFIG_PHY_MICREL_KSZ9031 +#else +#error "UCP1020 module revision is not defined !!!" +#endif + +#define CONFIG_CMD_DHCP +#define CONFIG_BOOTP_SERVERIP + +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_TSEC1_NAME "eTSEC1" +#define CONFIG_TSEC2_NAME "eTSEC2" +#define CONFIG_TSEC3_NAME "eTSEC3" + +#define TSEC1_PHY_ADDR 4 +#define TSEC2_PHY_ADDR 0 +#define TSEC2_PHY_ADDR_SGMII 0x00 +#define TSEC3_PHY_ADDR 6 + +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) + +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC3_PHYIDX 0 + +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ + +#endif + +#define CONFIG_HOSTNAME UCP1020 +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 + +/* + * Autobooting + */ +#define CONFIG_AUTOBOOT_KEYED +#define CONFIG_AUTOBOOT_STOP_STR "\x1b" +#define DEBUG_BOOTKEYS 0 +#undef CONFIG_AUTOBOOT_DELAY_STR +#undef CONFIG_BOOTARGS +#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, " \ + "press \"<Esc>\" to stop\n", bootdelay + +#define CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define CONFIG_BAUDRATE 115200 + +#if defined(CONFIG_DONGLE) + +#define CONFIG_BOOTDELAY 1 /* autoboot after 1 seconds */ +#define CONFIG_EXTRA_ENV_SETTINGS \ +"bootcmd=run prog_spi_mbrbootcramfs\0" \ +"bootfile=uImage\0" \ +"consoledev=ttyS0\0" \ +"cramfsfile=image.cramfs\0" \ +"dtbaddr=0x00c00000\0" \ +"dtbfile=image.dtb\0" \ +"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ +"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \ +"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \ +"fileaddr=0x01000000\0" \ +"filesize=0x00080000\0" \ +"flashmbr=sf probe 0; " \ + "tftp $loadaddr $mbr; " \ + "sf erase $mbr_offset +$filesize; " \ + "sf write $loadaddr $mbr_offset $filesize\0" \ +"flashrecovery=tftp $recoveryaddr $cramfsfile; " \ + "protect off $nor_recoveryaddr +$filesize; " \ + "erase $nor_recoveryaddr +$filesize; " \ + "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \ + "protect on $nor_recoveryaddr +$filesize\0 " \ +"flashuboot=tftp $ubootaddr $ubootfile; " \ + "protect off $nor_ubootaddr +$filesize; " \ + "erase $nor_ubootaddr +$filesize; " \ + "cp.b $ubootaddr $nor_ubootaddr $filesize; " \ + "protect on $nor_ubootaddr +$filesize\0 " \ +"flashworking=tftp $workingaddr $cramfsfile; " \ + "protect off $nor_workingaddr +$filesize; " \ + "erase $nor_workingaddr +$filesize; " \ + "cp.b $workingaddr $nor_workingaddr $filesize; " \ + "protect on $nor_workingaddr +$filesize\0 " \ +"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \ +"kerneladdr=0x01100000\0" \ +"kernelfile=uImage\0" \ +"loadaddr=0x01000000\0" \ +"mbr=uCP1020d.mbr\0" \ +"mbr_offset=0x00000000\0" \ +"mmbr=uCP1020Quiet.mbr\0" \ +"mmcpart=0:2\0" \ +"mmc__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \ + "mmc erase 1 1; " \ + "mmc write $loadaddr 1 1\0" \ +"mmc__uboot=fatload mmc $mmcpart $loadaddr $ubootfile; " \ + "mmc erase 0x40 0x400; " \ + "mmc write $loadaddr 0x40 0x400\0" \ +"netdev=eth0\0" \ +"nor_recoveryaddr=0xEC0A0000\0" \ +"nor_ubootaddr=0xEFF80000\0" \ +"nor_workingaddr=0xECFA0000\0" \ +"norbootrecovery=setenv bootargs $recoverybootargs console=$consoledev,$baudrate $othbootargs; " \ + "run norloadrecovery; " \ + "bootm $kerneladdr - $dtbaddr\0" \ +"norbootworking=setenv bootargs $workingbootargs console=$consoledev,$baudrate $othbootargs; " \ + "run norloadworking; " \ + "bootm $kerneladdr - $dtbaddr\0" \ +"norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \ + "setenv cramfsaddr $nor_recoveryaddr; " \ + "cramfsload $dtbaddr $dtbfile; " \ + "cramfsload $kerneladdr $kernelfile\0" \ +"norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \ + "setenv cramfsaddr $nor_workingaddr; " \ + "cramfsload $dtbaddr $dtbfile; " \ + "cramfsload $kerneladdr $kernelfile\0" \ +"prog_spi_mbr=run spi__mbr\0" \ +"prog_spi_mbrboot=run spi__mbr; run spi__boot1; run spi__boot2\0" \ +"prog_spi_mbrbootcramfs=run spi__mbr; run spi__boot1; run spi__boot2; " \ + "run spi__cramfs\0" \ +"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro console=$consoledev,$baudrate $othbootargs; " \ + "tftp $rootfsaddr $rootfsfile; " \ + "tftp $loadaddr $kernelfile; " \ + "tftp $dtbaddr $dtbfile; " \ + "bootm $loadaddr $rootfsaddr $dtbaddr\0" \ +"ramdisk_size=120000\0" \ +"ramdiskfile=rootfs.ext2.gz.uboot\0" \ +"recoveryaddr=0x02F00000\0" \ +"recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \ +"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \ + "mw.l 0xffe0f008 0x00400000\0" \ +"rootfsaddr=0x02F00000\0" \ +"rootfsfile=rootfs.ext2.gz.uboot\0" \ +"rootpath=/opt/nfsroot\0" \ +"spi__boot1=fatload mmc $mmcpart $loadaddr u-boot.bin; " \ + "protect off 0xeC000000 +$filesize; " \ + "erase 0xEC000000 +$filesize; " \ + "cp.b $loadaddr 0xEC000000 $filesize; " \ + "cmp.b $loadaddr 0xEC000000 $filesize; " \ + "protect on 0xeC000000 +$filesize\0" \ +"spi__boot2=fatload mmc $mmcpart $loadaddr u-boot.bin; " \ + "protect off 0xeFF80000 +$filesize; " \ + "erase 0xEFF80000 +$filesize; " \ + "cp.b $loadaddr 0xEFF80000 $filesize; " \ + "cmp.b $loadaddr 0xEFF80000 $filesize; " \ + "protect on 0xeFF80000 +$filesize\0" \ +"spi__bootd=fatload mmc $mmcpart $loadaddr $ubootd; " \ + "sf probe 0; sf erase 0x8000 +$filesize; " \ + "sf write $loadaddr 0x8000 $filesize\0" \ +"spi__cramfs=fatload mmc $mmcpart $loadaddr image.cramfs; " \ + "protect off 0xec0a0000 +$filesize; " \ + "erase 0xeC0A0000 +$filesize; " \ + "cp.b $loadaddr 0xeC0A0000 $filesize; " \ + "protect on 0xec0a0000 +$filesize\0" \ +"spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \ + "sf probe 1; sf erase 0 +$filesize; " \ + "sf write $loadaddr 0 $filesize\0" \ +"spi__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \ + "sf probe 0; sf erase 0 +$filesize; " \ + "sf write $loadaddr 0 $filesize\0" \ +"tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ + "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ + "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \ + "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ + "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0" \ +"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \ +"ubootaddr=0x01000000\0" \ +"ubootfile=u-boot.bin\0" \ +"ubootd=u-boot4dongle.bin\0" \ +"upgrade=run flashworking\0" \ +"usb_phy_type=ulpi\0 " \ +"workingaddr=0x02F00000\0" \ +"workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" + +#else + +#if defined(CONFIG_UCP1020T1) + +#define CONFIG_BOOTDELAY 2 /* autoboot after 2 sec, -1 disables auto-boot */ +#define CONFIG_EXTRA_ENV_SETTINGS \ +"bootcmd=run releasefpga; run norbootworking || run norbootrecovery\0" \ +"bootfile=uImage\0" \ +"consoledev=ttyS0\0" \ +"cramfsfile=image.cramfs\0" \ +"dtbaddr=0x00c00000\0" \ +"dtbfile=image.dtb\0" \ +"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ +"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \ +"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \ +"fileaddr=0x01000000\0" \ +"filesize=0x00080000\0" \ +"flashmbr=sf probe 0; " \ + "tftp $loadaddr $mbr; " \ + "sf erase $mbr_offset +$filesize; " \ + "sf write $loadaddr $mbr_offset $filesize\0" \ +"flashrecovery=tftp $recoveryaddr $cramfsfile; " \ + "protect off $nor_recoveryaddr +$filesize; " \ + "erase $nor_recoveryaddr +$filesize; " \ + "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \ + "protect on $nor_recoveryaddr +$filesize\0 " \ +"flashuboot=tftp $ubootaddr $ubootfile; " \ + "protect off $nor_ubootaddr +$filesize; " \ + "erase $nor_ubootaddr +$filesize; " \ + "cp.b $ubootaddr $nor_ubootaddr $filesize; " \ + "protect on $nor_ubootaddr +$filesize\0 " \ +"flashworking=tftp $workingaddr $cramfsfile; " \ + "protect off $nor_workingaddr +$filesize; " \ + "erase $nor_workingaddr +$filesize; " \ + "cp.b $workingaddr $nor_workingaddr $filesize; " \ + "protect on $nor_workingaddr +$filesize\0 " \ +"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \ +"kerneladdr=0x01100000\0" \ +"kernelfile=uImage\0" \ +"loadaddr=0x01000000\0" \ +"mbr=uCP1020.mbr\0" \ +"mbr_offset=0x00000000\0" \ +"netdev=eth0\0" \ +"nor_recoveryaddr=0xEC0A0000\0" \ +"nor_ubootaddr=0xEFF80000\0" \ +"nor_workingaddr=0xECFA0000\0" \ +"norbootrecovery=setenv bootargs $recoverybootargs console=$consoledev,$baudrate $othbootargs; " \ + "run norloadrecovery; " \ + "bootm $kerneladdr - $dtbaddr\0" \ +"norbootworking=setenv bootargs $workingbootargs console=$consoledev,$baudrate $othbootargs; " \ + "run norloadworking; " \ + "bootm $kerneladdr - $dtbaddr\0" \ +"norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \ + "setenv cramfsaddr $nor_recoveryaddr; " \ + "cramfsload $dtbaddr $dtbfile; " \ + "cramfsload $kerneladdr $kernelfile\0" \ +"norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \ + "setenv cramfsaddr $nor_workingaddr; " \ + "cramfsload $dtbaddr $dtbfile; " \ + "cramfsload $kerneladdr $kernelfile\0" \ +"othbootargs=quiet\0" \ +"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro console=$consoledev,$baudrate $othbootargs; " \ + "tftp $rootfsaddr $rootfsfile; " \ + "tftp $loadaddr $kernelfile; " \ + "tftp $dtbaddr $dtbfile; " \ + "bootm $loadaddr $rootfsaddr $dtbaddr\0" \ +"ramdisk_size=120000\0" \ +"ramdiskfile=rootfs.ext2.gz.uboot\0" \ +"recoveryaddr=0x02F00000\0" \ +"recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \ +"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \ + "mw.l 0xffe0f008 0x00400000\0" \ +"rootfsaddr=0x02F00000\0" \ +"rootfsfile=rootfs.ext2.gz.uboot\0" \ +"rootpath=/opt/nfsroot\0" \ +"silent=1\0" \ +"tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ + "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ + "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \ + "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ + "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0" \ +"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \ +"ubootaddr=0x01000000\0" \ +"ubootfile=u-boot.bin\0" \ +"upgrade=run flashworking\0" \ +"workingaddr=0x02F00000\0" \ +"workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" + +#else /* For Arcturus Modules */ + +#define CONFIG_BOOTDELAY 2 /* autoboot after 2 sec, -1 disables auto-boot */ +#define CONFIG_EXTRA_ENV_SETTINGS \ +"bootcmd=run norkernel\0" \ +"bootfile=uImage\0" \ +"consoledev=ttyS0\0" \ +"dtbaddr=0x00c00000\0" \ +"dtbfile=image.dtb\0" \ +"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ +"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \ +"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \ +"fileaddr=0x01000000\0" \ +"filesize=0x00080000\0" \ +"flashmbr=sf probe 0; " \ + "tftp $loadaddr $mbr; " \ + "sf erase $mbr_offset +$filesize; " \ + "sf write $loadaddr $mbr_offset $filesize\0" \ +"flashuboot=tftp $loadaddr $ubootfile; " \ + "protect off $nor_ubootaddr0 +$filesize; " \ + "erase $nor_ubootaddr0 +$filesize; " \ + "cp.b $loadaddr $nor_ubootaddr0 $filesize; " \ + "protect on $nor_ubootaddr0 +$filesize; " \ + "protect off $nor_ubootaddr1 +$filesize; " \ + "erase $nor_ubootaddr1 +$filesize; " \ + "cp.b $loadaddr $nor_ubootaddr1 $filesize; " \ + "protect on $nor_ubootaddr1 +$filesize\0 " \ +"format0=protect off $part0base +$part0size; " \ + "erase $part0base +$part0size\0" \ +"format1=protect off $part1base +$part1size; " \ + "erase $part1base +$part1size\0" \ +"format2=protect off $part2base +$part2size; " \ + "erase $part2base +$part2size\0" \ +"format3=protect off $part3base +$part3size; " \ + "erase $part3base +$part3size\0" \ +"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \ +"kerneladdr=0x01100000\0" \ +"kernelargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" \ +"kernelfile=uImage\0" \ +"loadaddr=0x01000000\0" \ +"mbr=uCP1020.mbr\0" \ +"mbr_offset=0x00000000\0" \ +"netdev=eth0\0" \ +"nor_ubootaddr0=0xEC000000\0" \ +"nor_ubootaddr1=0xEFF80000\0" \ +"norkernel=setenv bootargs $kernelargs console=$consoledev,$baudrate; " \ + "run norkernelload; " \ + "bootm $kerneladdr - $dtbaddr\0" \ +"norkernelload=mw.l $kerneladdr 0x0 0x00a00000; " \ + "setenv cramfsaddr $part0base; " \ + "cramfsload $dtbaddr $dtbfile; " \ + "cramfsload $kerneladdr $kernelfile\0" \ +"part0base=0xEC100000\0" \ +"part0size=0x00700000\0" \ +"part1base=0xEC800000\0" \ +"part1size=0x02000000\0" \ +"part2base=0xEE800000\0" \ +"part2size=0x00800000\0" \ +"part3base=0xEF000000\0" \ +"part3size=0x00F80000\0" \ +"partENVbase=0xEC080000\0" \ +"partENVsize=0x00080000\0" \ +"program0=tftp part0-000000.bin; " \ + "protect off $part0base +$filesize; " \ + "erase $part0base +$filesize; " \ + "cp.b $loadaddr $part0base $filesize; " \ + "echo Verifying...; " \ + "cmp.b $loadaddr $part0base $filesize\0" \ +"program1=tftp part1-000000.bin; " \ + "protect off $part1base +$filesize; " \ + "erase $part1base +$filesize; " \ + "cp.b $loadaddr $part1base $filesize; " \ + "echo Verifying...; " \ + "cmp.b $loadaddr $part1base $filesize\0" \ +"program2=tftp part2-000000.bin; " \ + "protect off $part2base +$filesize; " \ + "erase $part2base +$filesize; " \ + "cp.b $loadaddr $part2base $filesize; " \ + "echo Verifying...; " \ + "cmp.b $loadaddr $part2base $filesize\0" \ +"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro console=$consoledev,$baudrate $othbootargs; " \ + "tftp $rootfsaddr $rootfsfile; " \ + "tftp $loadaddr $kernelfile; " \ + "tftp $dtbaddr $dtbfile; " \ + "bootm $loadaddr $rootfsaddr $dtbaddr\0" \ +"ramdisk_size=120000\0" \ +"ramdiskfile=rootfs.ext2.gz.uboot\0" \ +"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \ + "mw.l 0xffe0f008 0x00400000\0" \ +"rootfsaddr=0x02F00000\0" \ +"rootfsfile=rootfs.ext2.gz.uboot\0" \ +"rootpath=/opt/nfsroot\0" \ +"spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \ + "sf probe 0; sf erase 0 +$filesize; " \ + "sf write $loadaddr 0 $filesize\0" \ +"spi__boot=fatload mmc $mmcpart $loadaddr u-boot.bin; " \ + "protect off 0xeC000000 +$filesize; " \ + "erase 0xEC000000 +$filesize; " \ + "cp.b $loadaddr 0xEC000000 $filesize; " \ + "cmp.b $loadaddr 0xEC000000 $filesize; " \ + "protect on 0xeC000000 +$filesize\0" \ +"tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ + "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ + "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \ + "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ + "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0" \ +"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \ +"ubootfile=u-boot.bin\0" \ +"upgrade=run flashuboot\0" \ +"usb_phy_type=ulpi\0 " \ +"boot_nfs= " \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr\0" \ +"boot_hd = " \ + "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "usb start;" \ + "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ + "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ + "bootm $loadaddr - $fdtaddr\0" \ +"boot_usb_fat = " \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs " \ + "ramdisk_size=$ramdisk_size;" \ + "usb start;" \ + "fatload usb 0:2 $loadaddr $bootfile;" \ + "fatload usb 0:2 $fdtaddr $fdtfile;" \ + "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \ +"boot_usb_ext2 = " \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs " \ + "ramdisk_size=$ramdisk_size;" \ + "usb start;" \ + "ext2load usb 0:4 $loadaddr $bootfile;" \ + "ext2load usb 0:4 $fdtaddr $fdtfile;" \ + "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \ +"boot_nor = " \ + "setenv bootargs root=/dev/$jffs2nor rw " \ + "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ + "bootm $norbootaddr - $norfdtaddr\0 " \ +"boot_ram = " \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs " \ + "ramdisk_size=$ramdisk_size;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr\0" + +#endif +#endif + +#endif /* __CONFIG_H */ -- 2.1.4

2 1

[U-Boot] Fat filesystem format support in u-boot
by S Durga Prasad Paladugu 28 Apr '15

28 Apr '15

Hi All, I want to know whether we have FAT file system formatting support in u-boot? I would like to format my SD card from u-boot. Regards, Siva

2 1

[U-Boot] Hi, guys.
by Wandy Lau 28 Apr '15

28 Apr '15

I am new to this project. But I am so interested with it and I want to dive into it. Where should I start ? -- This is my life,but world of us~~

2 1

[U-Boot] [PATCH] mpc85xx/T104xD4RDB: Add T104xD4RDB boards support
by Vijay Rai 28 Apr '15

28 Apr '15

T1040D4RDB is a Freescale reference board that hosts the T1040 SoC. T1040D4RDB is re-designed T1040RDB board with following changes : - Support of DDR4 memory - Support of 0x66 serdes protocol which can support following interfaces - 2 RGMII's on DTSEC4, DTSEC5 - 1 SGMII on DTSEC3 - Support of QE-TDM Similarily T1042D4RDB is a Freescale reference board that hosts the T1040 SoC. T1042D4RDB is re-designed T1042RDB board with following changes : - Support of DDR4 memory - Support for 0x86 serdes protocol which can support following interfaces - 2 RGMII's on DTSEC4, DTSEC5 - 3 SGMII on DTSEC1, DTSEC2 & DTSEC3 - Support of DIU Signed-off-by: Vijay Rai <vijay.rai(a)freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain(a)freescale.com> --- changes from v2: - adds SGMII suport using CPLD - removes extra endif changes from v3: - removes checkpatch error changes from v4: - wrong use of defined MACRO in eth.c file, adds macro properly changes from v5: - updates README files, t1040d4_rcw.cfg and t1042d4_rcw.cfg - update DDR settings board/freescale/t104xrdb/MAINTAINERS | 8 ++++ board/freescale/t104xrdb/README | 75 ++++++++++++++++++++++++++++-- board/freescale/t104xrdb/cpld.h | 2 + board/freescale/t104xrdb/ddr.c | 6 +++ board/freescale/t104xrdb/ddr.h | 9 +++- board/freescale/t104xrdb/eth.c | 20 +++++++- board/freescale/t104xrdb/t1040d4_rcw.cfg | 7 +++ board/freescale/t104xrdb/t1042d4_rcw.cfg | 7 +++ board/freescale/t104xrdb/t104xrdb.c | 21 +++++++++ configs/T1040D4RDB_NAND_defconfig | 5 ++ configs/T1040D4RDB_SDCARD_defconfig | 5 ++ configs/T1040D4RDB_SPIFLASH_defconfig | 5 ++ configs/T1040D4RDB_defconfig | 4 ++ configs/T1042D4RDB_NAND_defconfig | 5 ++ configs/T1042D4RDB_SDCARD_defconfig | 5 ++ configs/T1042D4RDB_SPIFLASH_defconfig | 5 ++ configs/T1042D4RDB_defconfig | 4 ++ include/configs/T104xRDB.h | 42 +++++++++++++---- 18 files changed, 220 insertions(+), 15 deletions(-) create mode 100644 board/freescale/t104xrdb/t1040d4_rcw.cfg create mode 100644 board/freescale/t104xrdb/t1042d4_rcw.cfg create mode 100644 configs/T1040D4RDB_NAND_defconfig create mode 100644 configs/T1040D4RDB_SDCARD_defconfig create mode 100644 configs/T1040D4RDB_SPIFLASH_defconfig create mode 100644 configs/T1040D4RDB_defconfig create mode 100644 configs/T1042D4RDB_NAND_defconfig create mode 100644 configs/T1042D4RDB_SDCARD_defconfig create mode 100644 configs/T1042D4RDB_SPIFLASH_defconfig create mode 100644 configs/T1042D4RDB_defconfig diff --git a/board/freescale/t104xrdb/MAINTAINERS b/board/freescale/t104xrdb/MAINTAINERS index 13d9be9..32e044f 100644 --- a/board/freescale/t104xrdb/MAINTAINERS +++ b/board/freescale/t104xrdb/MAINTAINERS @@ -6,7 +6,13 @@ F: include/configs/T104xRDB.h F: configs/T1040RDB_defconfig F: configs/T1040RDB_NAND_defconfig F: configs/T1040RDB_SPIFLASH_defconfig +F: configs/T1040D4RDB_defconfig +F: configs/T1040D4RDB_NAND_defconfig +F: configs/T1040D4RDB_SPIFLASH_defconfig F: configs/T1042RDB_defconfig +F: configs/T1042D4RDB_defconfig +F: configs/T1042D4RDB_NAND_defconfig +F: configs/T1042D4RDB_SPIFLASH_defconfig F: configs/T1042RDB_PI_defconfig F: configs/T1042RDB_PI_NAND_defconfig F: configs/T1042RDB_PI_SPIFLASH_defconfig @@ -15,6 +21,8 @@ T1040RDB_SDCARD BOARD #M: - S: Maintained F: configs/T1040RDB_SDCARD_defconfig +F: configs/T1040D4RDB_SDCARD_defconfig +F: configs/T1042D4RDB_SDCARD_defconfig F: configs/T1042RDB_PI_SDCARD_defconfig T1040RDB_SECURE_BOOT BOARD diff --git a/board/freescale/t104xrdb/README b/board/freescale/t104xrdb/README index ac95b5e..66538e2 100644 --- a/board/freescale/t104xrdb/README +++ b/board/freescale/t104xrdb/README @@ -12,6 +12,17 @@ The T1042RDB_PI is a Freescale reference board that hosts the T1042 SoC. (a personality of T1040 SoC). The board is similar to T1040RDB but is designed specially with low power features targeted for Printing Image Market. +The T1040D4RDB is a Freescale reference board that hosts the T1040 SoC. +The board is re-designed T1040RDB board with following changes : + - Support of DDR4 memory and some enhancements + +The T1042D4RDB is a Freescale reference board that hosts the T1042 SoC. +The board is re-designed T1040RDB board with following changes : + - Support of DDR4 memory + - Support for 0x86 serdes protocol which can support following interfaces + - 2 RGMII's on DTSEC4, DTSEC5 + - 3 SGMII on DTSEC1, DTSEC2 & DTSEC3 + Basic difference's among T1040RDB, T1042RDB_PI, T1042RDB ------------------------------------------------------------------------- Board Si Protocol Targeted Market @@ -19,6 +30,8 @@ Board Si Protocol Targeted Market T1040RDB T1040 0x66 Networking T1040RDB T1042 0x86 Networking T1042RDB_PI T1042 0x06 Printing & Imaging +T1040D4RDB T1040 0x66 Networking +T1042D4RDB T1042 0x86 Networking T1040 SoC Overview @@ -70,7 +83,6 @@ The T1040/T1042 SoC includes the following function and features: T1040 SoC Personalities ------------------------- - T1022 Personality: T1022 is a reduced personality of T1040 with less core/clusters. @@ -268,8 +280,13 @@ SPI Flash memory Map on T104xRDB Please note QE Firmware is only valid for T1040RDB -Switch Settings: (ON is 0, OFF is 1) -=============== +Switch Settings for T104xRDB boards: (ON is 0, OFF is 1) +========================================================== +NOR boot SW setting: +SW1: 00010011 +SW2: 10111011 +SW3: 11100001 + NAND boot SW setting: SW1: 10001000 SW2: 00111011 @@ -284,3 +301,55 @@ SD boot SW setting: SW1: 00100000 SW2: 00111011 SW3: 11100001 + +Switch Settings for T104xD4RDB boards: (ON is 0, OFF is 1) +============================================================= +NOR boot SW setting: +SW1: 00010011 +SW2: 10111001 +SW3: 11100001 + +NAND boot SW setting: +SW1: 10001000 +SW2: 00111001 +SW3: 11110001 + +SPI boot SW setting: +SW1: 00100010 +SW2: 10111001 +SW3: 11100001 + +SD boot SW setting: +SW1: 00100000 +SW2: 00111001 +SW3: 11100001 + +By default PBI_SRC=14 (which is for IFC-NAND/NOR), which needs to be changed for SPI and SD. + +For SD-boot +============== +1. Set RCW[192:195], PBI_SRC bits as 6 in RCW file (t1040d4_rcw.cfg type files) + +example: + RCW file: board/freescale/t104xrdb/t1040d4_rcw.cfg + +Change +66000002 40000002 ec027000 01000000 +to +66000002 40000002 6c027000 01000000 + +For SPI-boot +============== +1. Set RCW[192:195], PBI_SRC bits as 5 in RCW file (t1040d4_rcw.cfg type files) + +example: + RCW file: board/freescale/t104xrdb/t1040d4_rcw.cfg + +Change +66000002 40000002 ec027000 01000000 +to +66000002 40000002 5c027000 01000000 + +2. SPI does not support flush so remove flush from pbl, make changes in + tools/pblimage.c file, Update value of pbl_end_cmd[0] = 0x09138000 + with 0x091380c0 diff --git a/board/freescale/t104xrdb/cpld.h b/board/freescale/t104xrdb/cpld.h index 0da9a01..543ab53 100644 --- a/board/freescale/t104xrdb/cpld.h +++ b/board/freescale/t104xrdb/cpld.h @@ -38,3 +38,5 @@ void cpld_write(unsigned int reg, u8 value); #define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) #define CPLD_WRITE(reg, value)\ cpld_write(offsetof(struct cpld_data, reg), value) +#define MISC_CTL_SG_SEL 0x80 +#define MISC_CTL_AURORA_SEL 0x02 diff --git a/board/freescale/t104xrdb/ddr.c b/board/freescale/t104xrdb/ddr.c index e1148e5..3c4eabf 100644 --- a/board/freescale/t104xrdb/ddr.c +++ b/board/freescale/t104xrdb/ddr.c @@ -91,8 +91,14 @@ found: popts->zq_en = 1; /* DHC_EN =1, ODT = 75 Ohm */ +#ifdef CONFIG_SYS_FSL_DDR4 + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | + DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ +#else popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); +#endif } #if defined(CONFIG_DEEP_SLEEP) diff --git a/board/freescale/t104xrdb/ddr.h b/board/freescale/t104xrdb/ddr.h index ab1c32d..58b7349 100644 --- a/board/freescale/t104xrdb/ddr.h +++ b/board/freescale/t104xrdb/ddr.h @@ -28,6 +28,9 @@ static const struct board_specific_parameters udimm0[] = { * num| hi| rank| clk| wrlvl | wrlvl * ranks| mhz| GB |adjst| start | ctl2 */ +#ifdef CONFIG_SYS_FSL_DDR4 + {2, 1600, 4, 4, 6, 0x07090A0d, 0x0D0f100a}, +#elif defined(CONFIG_SYS_FSL_DDR3) {2, 833, 4, 4, 6, 0x06060607, 0x08080807}, {2, 833, 0, 4, 6, 0x06060607, 0x08080807}, {2, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09}, @@ -40,10 +43,14 @@ static const struct board_specific_parameters udimm0[] = { {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09}, {1, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A}, {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A}, +#else +#error DDR type not defined +#endif {} }; +#endif + static const struct board_specific_parameters *udimms[] = { udimm0, }; -#endif diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c index 7581a4cd..71d0457 100644 --- a/board/freescale/t104xrdb/eth.c +++ b/board/freescale/t104xrdb/eth.c @@ -43,9 +43,11 @@ int board_eth_init(bd_t *bis) int idx = i - FM1_DTSEC1; switch (fm_info_get_enet_if(i)) { -#ifdef CONFIG_T1040RDB +#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1040D4RDB) case PHY_INTERFACE_MODE_SGMII: - /* T1040RDB only supports SGMII on DTSEC3 */ + /* T1040RDB & T1040D4RDB only supports SGMII on + * DTSEC3 + */ fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_SGMII1_PHY_ADDR); break; @@ -60,6 +62,20 @@ int board_eth_init(bd_t *bis) CONFIG_SYS_SGMII1_PHY_ADDR); break; #endif +#ifdef CONFIG_T1042D4RDB + case PHY_INTERFACE_MODE_SGMII: + /* T1042D4RDB supports SGMII on DTSEC1, DTSEC2 + * & DTSEC3 + */ + if (FM1_DTSEC1 == i) + phy_addr = CONFIG_SYS_SGMII1_PHY_ADDR; + if (FM1_DTSEC2 == i) + phy_addr = CONFIG_SYS_SGMII2_PHY_ADDR; + if (FM1_DTSEC3 == i) + phy_addr = CONFIG_SYS_SGMII3_PHY_ADDR; + fm_info_set_phy_address(i, phy_addr); + break; +#endif case PHY_INTERFACE_MODE_RGMII: if (FM1_DTSEC4 == i) phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR; diff --git a/board/freescale/t104xrdb/t1040d4_rcw.cfg b/board/freescale/t104xrdb/t1040d4_rcw.cfg new file mode 100644 index 0000000..c1034b3 --- /dev/null +++ b/board/freescale/t104xrdb/t1040d4_rcw.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 +# serdes protocol 0x66 +0c18000e 0e000000 00000000 00000000 +66000002 40000002 ec027000 01000000 +00000000 00000000 00000000 00030810 +00000000 0342580f 00000000 00000000 diff --git a/board/freescale/t104xrdb/t1042d4_rcw.cfg b/board/freescale/t104xrdb/t1042d4_rcw.cfg new file mode 100644 index 0000000..9e0ee27 --- /dev/null +++ b/board/freescale/t104xrdb/t1042d4_rcw.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 +# serdes protocol 0x86 +0c18000e 0e000000 00000000 00000000 +86000002 40000002 ec027000 01000000 +00000000 00000000 00000000 00030810 +00000000 0342500f 00000000 00000000 diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c index 9cd5e15..963cae4 100644 --- a/board/freescale/t104xrdb/t104xrdb.c +++ b/board/freescale/t104xrdb/t104xrdb.c @@ -28,7 +28,11 @@ int checkboard(void) struct cpu_type *cpu = gd->arch.cpu; u8 sw; +#ifdef CONFIG_T104XD4RDB + printf("Board: %sD4RDB\n", cpu->name); +#else printf("Board: %sRDB\n", cpu->name); +#endif printf("Board rev: 0x%02x CPLD ver: 0x%02x, ", CPLD_READ(hw_ver), CPLD_READ(sw_ver)); @@ -91,6 +95,23 @@ int board_early_init_r(void) int misc_init_r(void) { + ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 srds_s1; + + srds_s1 = in_be32(&gur->rcwsr[4]) >> 24; + + printf("SERDES Reference : 0x%X\n", srds_s1); + + /* select SGMII*/ + if (srds_s1 == 0x86) + CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) | + MISC_CTL_SG_SEL); + + /* select SGMII and Aurora*/ + if (srds_s1 == 0x8E) + CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) | + MISC_CTL_SG_SEL | MISC_CTL_AURORA_SEL); + return 0; } diff --git a/configs/T1040D4RDB_NAND_defconfig b/configs/T1040D4RDB_NAND_defconfig new file mode 100644 index 0000000..8212b34 --- /dev/null +++ b/configs/T1040D4RDB_NAND_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND,T104XD4RDB,SYS_FSL_DDR4" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_T104XRDB=y diff --git a/configs/T1040D4RDB_SDCARD_defconfig b/configs/T1040D4RDB_SDCARD_defconfig new file mode 100644 index 0000000..d45c60c --- /dev/null +++ b/configs/T1040D4RDB_SDCARD_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD,T104XD4RDB,SYS_FSL_DDR4" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_T104XRDB=y diff --git a/configs/T1040D4RDB_SPIFLASH_defconfig b/configs/T1040D4RDB_SPIFLASH_defconfig new file mode 100644 index 0000000..d7ccacf --- /dev/null +++ b/configs/T1040D4RDB_SPIFLASH_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH,T104XD4RDB,SYS_FSL_DDR4" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_T104XRDB=y diff --git a/configs/T1040D4RDB_defconfig b/configs/T1040D4RDB_defconfig new file mode 100644 index 0000000..f9a23cf --- /dev/null +++ b/configs/T1040D4RDB_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,T104XD4RDB,SYS_FSL_DDR4" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T104XRDB=y diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig new file mode 100644 index 0000000..2ab2b15 --- /dev/null +++ b/configs/T1042D4RDB_NAND_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND,T104XD4RDB,SYS_FSL_DDR4" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_T104XRDB=y diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig new file mode 100644 index 0000000..daba6b7 --- /dev/null +++ b/configs/T1042D4RDB_SDCARD_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD,T104XD4RDB,SYS_FSL_DDR4" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_T104XRDB=y diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig new file mode 100644 index 0000000..0aa5178 --- /dev/null +++ b/configs/T1042D4RDB_SPIFLASH_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH,T104XD4RDB,SYS_FSL_DDR4" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_T104XRDB=y diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig new file mode 100644 index 0000000..3802637 --- /dev/null +++ b/configs/T1042D4RDB_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,T104XD4RDB,SYS_FSL_DDR4" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T104XRDB=y diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 5263318..f11db1d 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -29,6 +29,14 @@ #ifdef CONFIG_T1042RDB #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_rcw.cfg #endif +#ifdef CONFIG_T1040D4RDB +#define CONFIG_SYS_FSL_PBL_RCW \ +$(SRCTREE)/board/freescale/t104xrdb/t1040d4_rcw.cfg +#endif +#ifdef CONFIG_T1042D4RDB +#define CONFIG_SYS_FSL_PBL_RCW \ +$(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg +#endif #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT #define CONFIG_SPL_ENV_SUPPORT @@ -220,7 +228,9 @@ #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) #define CONFIG_DDR_SPD +#ifndef CONFIG_SYS_FSL_DDR4 #define CONFIG_SYS_FSL_DDR3 +#endif #define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x51 @@ -278,7 +288,7 @@ #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */ #define CPLD_LBMAP_RESET 0xFF #define CPLD_LBMAP_SHIFT 0x03 -#ifdef CONFIG_T1042RDB_PI +#if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T104XD4RDB) #define CPLD_DIU_SEL_DFP 0x80 #endif @@ -448,7 +458,7 @@ #define CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#ifdef CONFIG_T1042RDB_PI +#if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T104XD4RDB) /* Video */ #define CONFIG_FSL_DIU_FB @@ -493,11 +503,11 @@ /* I2C bus multiplexer */ #define I2C_MUX_PCA_ADDR 0x70 -#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB) +#if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB) #define I2C_MUX_CH_DEFAULT 0x8 #endif -#ifdef CONFIG_T1042RDB_PI +#if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T104XD4RDB) /* LDI/DVI Encoder for display */ #define CONFIG_SYS_I2C_LDI_ADDR 0x38 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 @@ -666,7 +676,7 @@ #define CONFIG_SYS_DPAA_FMAN #define CONFIG_SYS_DPAA_PME -#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB) +#if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB) #define CONFIG_QE #define CONFIG_U_QE #endif @@ -695,7 +705,7 @@ #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 #endif -#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB) +#if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB) #if defined(CONFIG_SPIFLASH) #define CONFIG_SYS_QE_FW_ADDR 0x130000 #elif defined(CONFIG_SDCARD) @@ -720,10 +730,20 @@ #ifdef CONFIG_FMAN_ENET #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB) -#define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 +#define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 +#elif defined(CONFIG_T1040D4RDB) || defined(CONFIG_T1042D4RDB) +#define CONFIG_SYS_SGMII1_PHY_ADDR 0x02 +#define CONFIG_SYS_SGMII2_PHY_ADDR 0x03 +#define CONFIG_SYS_SGMII3_PHY_ADDR 0x01 +#endif + +#ifdef CONFIG_T104XD4RDB +#define CONFIG_SYS_RGMII1_PHY_ADDR 0x04 +#define CONFIG_SYS_RGMII2_PHY_ADDR 0x05 +#else +#define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 +#define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 #endif -#define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 -#define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 /* Enable VSC9953 L2 Switch driver on T1040 SoC */ #ifdef CONFIG_T1040RDB @@ -842,6 +862,10 @@ #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb" #elif defined(CONFIG_T1042RDB) #define FDTFILE "t1042rdb/t1042rdb.dtb" +#elif defined(CONFIG_T1040D4RDB) +#define FDTFILE "t1042rdb/t1040d4rdb.dtb" +#elif defined(CONFIG_T1042D4RDB) +#define FDTFILE "t1042rdb/t1042d4rdb.dtb" #endif #ifdef CONFIG_FSL_DIU_FB -- 1.7.9.5

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[U-Boot] [PATCH] x86: Correct the typo in write_tables()
by Bin Meng 28 Apr '15

28 Apr '15

It should be #ifdef instead of #if. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- arch/x86/lib/tables.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/lib/tables.c b/arch/x86/lib/tables.c index b390a4b..0836e1e 100644 --- a/arch/x86/lib/tables.c +++ b/arch/x86/lib/tables.c @@ -23,7 +23,7 @@ void write_tables(void) { u32 __maybe_unused rom_table_end = ROM_TABLE_ADDR; -#if CONFIG_GENERATE_PIRQ_TABLE +#ifdef CONFIG_GENERATE_PIRQ_TABLE rom_table_end = write_pirq_routing_table(rom_table_end); rom_table_end = ALIGN(rom_table_end, 1024); #endif -- 1.8.2.1

2 2