March 2015 - U-Boot

[U-Boot] [PATCH] Vexpress64: Fix the compiling error when CONFIG_ARMV8_MULTIENTRY defined
by fenghua＠phytium.com.cn 24 Mar '15

24 Mar '15

From: David Feng <fenghua(a)phytium.com.cn> CPU_RELEASE_ADDR should be defined when CONFIG_ARMV8_MULTIENTRY is used. Signed-off-by: David Feng <fenghua(a)phytium.com.cn> --- board/armltd/vexpress64/vexpress64.c | 8 ++++++++ include/configs/vexpress_aemv8a.h | 9 +++++++++ 2 files changed, 17 insertions(+) diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c index de62864..bb6b5f6 100644 --- a/board/armltd/vexpress64/vexpress64.c +++ b/board/armltd/vexpress64/vexpress64.c @@ -22,6 +22,14 @@ int board_init(void) int dram_init(void) { +#ifdef CONFIG_ARMV8_MULTIENTRY + /* + * Clear spin table so that secondary processors + * observe the correct value after waken up from wfe. + */ + *(unsigned long *)CPU_RELEASE_ADDR = 0; +#endif + gd->ram_size = PHYS_SDRAM_1_SIZE; return 0; } diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h index 810eef1..6fa651a 100644 --- a/include/configs/vexpress_aemv8a.h +++ b/include/configs/vexpress_aemv8a.h @@ -54,6 +54,15 @@ /* Flat Device Tree Definitions */ #define CONFIG_OF_LIBFDT +#ifdef CONFIG_ARMV8_MULTIENTRY +/* SMP Spin Table Definitions */ +#ifdef CONFIG_BASE_FVP +#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000) +#else +#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) +#endif +#endif + /* CS register bases for the original memory map. */ #define V2M_PA_CS0 0x00000000 #define V2M_PA_CS1 0x14000000 -- 1.7.9.5

5 6

[U-Boot] [PATCH] arm: mx5: Add support for USB armory board
by andrej＠inversepath.com 24 Mar '15

24 Mar '15

From: Andrej Rosano <andrej(a)inversepath.com> Add support for Inverse Path USB armory board, an open source flash-drive sized computer based on Freescale i.MX53 SoC. http://inversepath.com/usbarmory Signed-off-by: Andrej Rosano <andrej(a)inversepath.com> --- arch/arm/Kconfig | 5 + board/inversepath/usbarmory/Kconfig | 15 + board/inversepath/usbarmory/MAINTAINERS | 6 + board/inversepath/usbarmory/Makefile | 10 + board/inversepath/usbarmory/imximage.cfg | 82 ++++++ board/inversepath/usbarmory/usbarmory.c | 440 ++++++++++++++++++++++++++++++ configs/usbarmory_defconfig | 3 + include/configs/usbarmory.h | 115 ++++++++ 8 files changed, 676 insertions(+) create mode 100644 board/inversepath/usbarmory/Kconfig create mode 100644 board/inversepath/usbarmory/MAINTAINERS create mode 100644 board/inversepath/usbarmory/Makefile create mode 100644 board/inversepath/usbarmory/imximage.cfg create mode 100644 board/inversepath/usbarmory/usbarmory.c create mode 100644 configs/usbarmory_defconfig create mode 100644 include/configs/usbarmory.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 820ba1c..11f0e8b 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -473,6 +473,10 @@ config TARGET_MX53SMD bool "Support mx53smd" select CPU_V7 +config TARGET_USBARMORY + bool "Support USB armory" + select CPU_V7 + config TARGET_MX51_EFIKAMX bool "Support mx51_efikamx" select CPU_V7 @@ -818,6 +822,7 @@ source "board/h2200/Kconfig" source "board/hale/tt01/Kconfig" source "board/icpdas/lp8x4x/Kconfig" source "board/imx31_phycore/Kconfig" +source "board/inversepath/usbarmory/Kconfig" source "board/isee/igep0033/Kconfig" source "board/jornada/Kconfig" source "board/karo/tx25/Kconfig" diff --git a/board/inversepath/usbarmory/Kconfig b/board/inversepath/usbarmory/Kconfig new file mode 100644 index 0000000..254b6c9 --- /dev/null +++ b/board/inversepath/usbarmory/Kconfig @@ -0,0 +1,15 @@ +if TARGET_USBARMORY + +config SYS_BOARD + default "usbarmory" + +config SYS_VENDOR + default "inversepath" + +config SYS_SOC + default "mx5" + +config SYS_CONFIG_NAME + default "usbarmory" + +endif diff --git a/board/inversepath/usbarmory/MAINTAINERS b/board/inversepath/usbarmory/MAINTAINERS new file mode 100644 index 0000000..71a3dd4 --- /dev/null +++ b/board/inversepath/usbarmory/MAINTAINERS @@ -0,0 +1,6 @@ +USBARMORY BOARD +M: Andrej Rosano <andrej(a)inversepath.com> +S: Maintained +F: board/inversepath/usbarmory/ +F: include/configs/usbarmory.h +F: configs/usbarmory_defconfig diff --git a/board/inversepath/usbarmory/Makefile b/board/inversepath/usbarmory/Makefile new file mode 100644 index 0000000..9b8bd80 --- /dev/null +++ b/board/inversepath/usbarmory/Makefile @@ -0,0 +1,10 @@ +# +# USB armory MkI board Makefile +# http://inversepath.com/usbarmory +# +# Copyright (C) 2015, Inverse Path +# Andrej Rosano <andrej(a)inversepath.com> +# +# SPDX-License-Identifier:|____GPL-2.0+ + +obj-y := usbarmory.o diff --git a/board/inversepath/usbarmory/imximage.cfg b/board/inversepath/usbarmory/imximage.cfg new file mode 100644 index 0000000..392d2f9 --- /dev/null +++ b/board/inversepath/usbarmory/imximage.cfg @@ -0,0 +1,82 @@ +/* + * USB armory MkI board imximage configuration + * http://inversepath.com/usbarmory + * + * Copyright (C) 2015, Inverse Path + * Andrej Rosano <andrej(a)inversepath.com> + * + * SPDX-License-Identifier:|____GPL-2.0+ + */ + +IMAGE_VERSION 2 +BOOT_FROM sd + + +/* IOMUX */ + +DATA 4 0x53fa86f4 0x00000000 /* GRP_DDRMODE_CTL */ +DATA 4 0x53fa8714 0x00000000 /* GRP_DDRMODE */ +DATA 4 0x53fa86fc 0x00000000 /* GRP_DDRPKE */ +DATA 4 0x53fa8724 0x04000000 /* GRP_DDR_TYPE */ + +DATA 4 0x53fa872c 0x00300000 /* GRP_B3DS */ +DATA 4 0x53fa8554 0x00300000 /* DRAM_DQM3 */ +DATA 4 0x53fa8558 0x00300040 /* DRAM_SDQS3 */ + +DATA 4 0x53fa8728 0x00300000 /* GRP_B2DS */ +DATA 4 0x53fa8560 0x00300000 /* DRAM_DQM2 */ +DATA 4 0x53fa8568 0x00300040 /* DRAM_SDQS2 */ + +DATA 4 0x53fa871c 0x00300000 /* GRP_B1DS */ +DATA 4 0x53fa8594 0x00300000 /* DRAM_DQM1 */ +DATA 4 0x53fa8590 0x00300040 /* DRAM_SDQS1 */ + +DATA 4 0x53fa8718 0x00300000 /* GRP_B0DS */ +DATA 4 0x53fa8584 0x00300000 /* DRAM_DQM0 */ +DATA 4 0x53fa857c 0x00300040 /* DRAM_SDQS0 */ + +DATA 4 0x53fa8578 0x00300000 /* DRAM_SDCLK0 */ +DATA 4 0x53fa8570 0x00300000 /* DRAM_SDCLK1 */ + +DATA 4 0x53fa8574 0x00300000 /* DRAM_CAS */ +DATA 4 0x53fa8588 0x00300000 /* DRAM_RAS */ +DATA 4 0x53fa86f0 0x00300000 /* GRP_ADDS */ +DATA 4 0x53fa8720 0x00300000 /* GRP_CTLDS */ + +DATA 4 0x53fa8564 0x00300040 /* DRAM_SDODT1 */ +DATA 4 0x53fa8580 0x00300040 /* DRAM_SDODT0 */ + + +/* ESDCTL */ + +DATA 4 0x63fd9000 0x84180000 /* ESDCTL_ESDCTL */ + +DATA 4 0x63fd9004 0x0002002d /* ESDCTL_ESDPTC */ +DATA 4 0x63fd9008 0x12273030 /* ESDCTL_ESDOTC */ +DATA 4 0x63fd900c 0x9f5152e3 /* ESDCTL_ESDCFG0 */ +DATA 4 0x63fd9010 0xb68e8a63 /* ESDCTL_ESDCFG1 */ +DATA 4 0x63fd9014 0x01ff00db /* ESDCTL_ESDCFG2 */ +DATA 4 0x63fd9018 0x00011740 /* ESDCTL_ESDMISC */ + +DATA 4 0x63fd901c 0x00008032 /* ESDCTL_ESDSCR */ +DATA 4 0x63fd901c 0x00008033 +DATA 4 0x63fd901c 0x00028031 +DATA 4 0x63fd901c 0x052080b0 +DATA 4 0x63fd901c 0x04008040 +DATA 4 0x63fd901c 0x0000803a +DATA 4 0x63fd901c 0x0000803b +DATA 4 0x63fd901c 0x00028039 +DATA 4 0x63fd901c 0x05208138 +DATA 4 0x63fd901c 0x04008048 +DATA 4 0x63fd901c 0x00000000 + +DATA 4 0x63fd9020 0x00005800 /* ESDCTL_ESDREF */ +DATA 4 0x63fd902c 0x000026d2 /* ESDCTL_ESDEWD */ +DATA 4 0x63fd9030 0x009f0e21 /* ESDCTL_ESDOR */ +DATA 4 0x63fd9040 0x05380003 /* ESDCTL_ZQHWCTRL */ +DATA 4 0x63fd9058 0x00022227 /* ESDCTL_ODTCTRL */ + +DATA 4 0x63fd907c 0x01370138 /* ESDCTL_DGCTRL0 */ +DATA 4 0x63fd9080 0x013b013c /* ESDCTL_DGCTRL1 */ +DATA 4 0x63fd9088 0x35343535 /* ESDCTL_RDDLCTL */ +DATA 4 0x63fd9090 0x4d444c44 /* ESDCTL_WRDLCTL */ diff --git a/board/inversepath/usbarmory/usbarmory.c b/board/inversepath/usbarmory/usbarmory.c new file mode 100644 index 0000000..2ebd697 --- /dev/null +++ b/board/inversepath/usbarmory/usbarmory.c @@ -0,0 +1,440 @@ +/* + * USB armory MkI board initialization + * http://inversepath.com/usbarmory + * + * Copyright (C) 2015, Inverse Path + * Andrej Rosano <andrej(a)inversepath.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/clock.h> +#include <asm/arch/iomux-mx53.h> +#include <asm/errno.h> +#include <i2c.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <asm/gpio.h> + +DECLARE_GLOBAL_DATA_PTR; + +u32 get_board_rev(void) +{ + struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; + struct fuse_bank *bank = &iim->bank[0]; + struct fuse_bank0_regs *fuse = + (struct fuse_bank0_regs *)bank->fuse_regs; + + int rev = readl(&fuse->gp[6]); + + return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; +} + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg esdhc_cfg[1] = { + {MMC_SDHC1_BASE_ADDR} +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + /* CD not present */ + return 1; +} + +int board_mmc_init(bd_t *bis) +{ + int ret = 0; + + esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]); + + return ret; +} +#endif + +#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ + PAD_CTL_PUS_100K_UP) +#define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_ODE) +#define PAD_CTRL_UP PAD_CTL_PUS_100K_UP +#define PAD_CTRL_GND PAD_CTL_PUS_100K_DOWN + +static void setup_iomux_sd(void) +{ + static const iomux_v3_cfg_t pads[] = { + NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, MX53_SDHC_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, + MX53_SDHC_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, + MX53_SDHC_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, + MX53_SDHC_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, + MX53_SDHC_PAD_CTRL), + MX53_PAD_EIM_DA13__GPIO3_13, + }; + + imx_iomux_v3_setup_multiple_pads(pads, ARRAY_SIZE(pads)); +} + +static void setup_iomux_led(void) +{ + static const iomux_v3_cfg_t pads[] = { + NEW_PAD_CTRL(MX53_PAD_DISP0_DAT6__GPIO4_27, + PAD_CTL_PUS_100K_DOWN), + }; + + imx_iomux_v3_setup_multiple_pads(pads, ARRAY_SIZE(pads)); +} + +static void setup_iomux_i2c(void) +{ + static const iomux_v3_cfg_t pads[] = { + NEW_PAD_CTRL(MX53_PAD_EIM_D28__I2C1_SDA, I2C_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_EIM_D21__I2C1_SCL, I2C_PAD_CTRL), + }; + + imx_iomux_v3_setup_multiple_pads(pads, ARRAY_SIZE(pads)); +} + +static void setup_iomux_pinheader(void) +{ + static const iomux_v3_cfg_t pads[] = { + NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__GPIO5_26, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__GPIO5_27, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, + MX53_UART_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, + MX53_UART_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_CSI0_DAT12__GPIO5_30, PAD_CTRL_UP), + }; + + imx_iomux_v3_setup_multiple_pads(pads, ARRAY_SIZE(pads)); +} + +static void setup_iomux_unused_boot(void) +{ + static const iomux_v3_cfg_t pads[] = { + + /* Pulled-up pads */ + NEW_PAD_CTRL(MX53_PAD_EIM_A21__GPIO2_17, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_EIM_DA0__GPIO3_0, PAD_CTRL_UP), + + /* Grounded pads */ + NEW_PAD_CTRL(MX53_PAD_EIM_LBA__GPIO2_27, PAD_CTRL_GND), + NEW_PAD_CTRL(MX53_PAD_EIM_EB0__GPIO2_28, PAD_CTRL_GND), + NEW_PAD_CTRL(MX53_PAD_EIM_EB1__GPIO2_29, PAD_CTRL_GND), + NEW_PAD_CTRL(MX53_PAD_EIM_A16__GPIO2_22, PAD_CTRL_GND), + NEW_PAD_CTRL(MX53_PAD_EIM_A17__GPIO2_21, PAD_CTRL_GND), + NEW_PAD_CTRL(MX53_PAD_EIM_A18__GPIO2_20, PAD_CTRL_GND), + NEW_PAD_CTRL(MX53_PAD_EIM_A19__GPIO2_19, PAD_CTRL_GND), + NEW_PAD_CTRL(MX53_PAD_EIM_A20__GPIO2_18, PAD_CTRL_GND), + NEW_PAD_CTRL(MX53_PAD_EIM_A22__GPIO2_16, PAD_CTRL_GND), + NEW_PAD_CTRL(MX53_PAD_EIM_DA1__GPIO3_1, PAD_CTRL_GND), + NEW_PAD_CTRL(MX53_PAD_EIM_DA2__GPIO3_2, PAD_CTRL_GND), + NEW_PAD_CTRL(MX53_PAD_EIM_DA3__GPIO3_3, PAD_CTRL_GND), + NEW_PAD_CTRL(MX53_PAD_EIM_DA4__GPIO3_4, PAD_CTRL_GND), + NEW_PAD_CTRL(MX53_PAD_EIM_DA5__GPIO3_5, PAD_CTRL_GND), + NEW_PAD_CTRL(MX53_PAD_EIM_DA6__GPIO3_6, PAD_CTRL_GND), + NEW_PAD_CTRL(MX53_PAD_EIM_DA7__GPIO3_7, PAD_CTRL_GND), + NEW_PAD_CTRL(MX53_PAD_EIM_DA8__GPIO3_8, PAD_CTRL_GND), + NEW_PAD_CTRL(MX53_PAD_EIM_DA9__GPIO3_9, PAD_CTRL_GND), + NEW_PAD_CTRL(MX53_PAD_EIM_DA10__GPIO3_10, PAD_CTRL_GND), + }; + + imx_iomux_v3_setup_multiple_pads(pads, ARRAY_SIZE(pads)); +} + +static void setup_iomux_unused_nc(void) +{ + /* Out of reset values define the pin values before the + ROM is executed so we force all the not connected pins + to a known state */ + static const iomux_v3_cfg_t pads[] = { + + /* CONTROL PINS block */ + NEW_PAD_CTRL(MX53_PAD_GPIO_0__GPIO1_0, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_GPIO_1__GPIO1_1, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_GPIO_2__GPIO1_2, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_GPIO_3__GPIO1_3, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_GPIO_4__GPIO1_4, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_GPIO_5__GPIO1_5, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_GPIO_6__GPIO1_6, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_GPIO_7__GPIO1_7, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_GPIO_8__GPIO1_8, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_GPIO_9__GPIO1_9, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_GPIO_10__GPIO4_0, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_GPIO_11__GPIO4_1, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_GPIO_12__GPIO4_2, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_GPIO_13__GPIO4_3, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_GPIO_14__GPIO4_4, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_GPIO_16__GPIO7_11, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_GPIO_17__GPIO7_12, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_GPIO_18__GPIO7_13, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_GPIO_19__GPIO4_5, PAD_CTRL_UP), + + /* EIM block */ + NEW_PAD_CTRL(MX53_PAD_EIM_OE__GPIO2_25, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_EIM_WAIT__GPIO5_0, PAD_CTRL_UP), + /* EIM_LBA: setup_iomux_unused_boot() */ + NEW_PAD_CTRL(MX53_PAD_EIM_RW__GPIO2_26, PAD_CTRL_UP), + /* EIM_EB0: setup_iomux_unused_boot() */ + /* EIM_EB1: setup_iomux_unused_boot() */ + NEW_PAD_CTRL(MX53_PAD_EIM_EB2__GPIO2_30, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_EIM_EB3__GPIO2_31, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_EIM_CS0__GPIO2_23, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_EIM_CS1__GPIO2_24, PAD_CTRL_UP), + /* EIM_A16: setup_iomux_unused_boot() */ + /* EIM_A17: setup_iomux_unused_boot() */ + /* EIM_A18: setup_iomux_unused_boot() */ + /* EIM_A19: setup_iomux_unused_boot() */ + /* EIM_A20: setup_iomux_unused_boot() */ + /* EIM_A21: setup_iomux_unused_boot() */ + /* EIM_A22: setup_iomux_unused_boot() */ + NEW_PAD_CTRL(MX53_PAD_EIM_A23__GPIO6_6, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_EIM_A24__GPIO5_4, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_EIM_A25__GPIO5_2, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_EIM_D16__GPIO3_16, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_EIM_D17__GPIO3_17, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_EIM_D18__GPIO3_18, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_EIM_D19__GPIO3_19, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_EIM_D20__GPIO3_20, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_EIM_D21__GPIO3_21, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_EIM_D22__GPIO3_22, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_EIM_D23__GPIO3_23, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_EIM_D24__GPIO3_24, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_EIM_D25__GPIO3_25, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_EIM_D26__GPIO3_26, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_EIM_D27__GPIO3_27, PAD_CTRL_UP), + /* EIM_D28: setup_iomux_unused_boot() */ + /* EIM_D29: setup_iomux_unused_boot() */ + NEW_PAD_CTRL(MX53_PAD_EIM_D30__GPIO3_30, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_EIM_D31__GPIO3_31, PAD_CTRL_UP), + /* EIM_DA0: setup_iomux_unused_boot() */ + /* EIM_DA1: setup_iomux_unused_boot() */ + /* EIM_DA2: setup_iomux_unused_boot() */ + /* EIM_DA3: setup_iomux_unused_boot() */ + /* EIM_DA4: setup_iomux_unused_boot() */ + /* EIM_DA5: setup_iomux_unused_boot() */ + /* EIM_DA6: setup_iomux_unused_boot() */ + /* EIM_DA7: setup_iomux_unused_boot() */ + /* EIM_DA8: setup_iomux_unused_boot() */ + /* EIM_DA9: setup_iomux_unused_boot() */ + /* EIM_DA10: setup_iomux_unused_boot() */ + NEW_PAD_CTRL(MX53_PAD_EIM_DA11__GPIO3_11, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_EIM_DA12__GPIO3_12, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_EIM_DA13__GPIO3_13, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_EIM_DA14__GPIO3_14, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_EIM_DA15__GPIO3_15, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__GPIO6_12, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__GPIO6_13, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__GPIO6_8, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__GPIO6_7, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__GPIO6_9, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__GPIO6_10, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__GPIO6_11, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_NANDF_CS1__GPIO6_14, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_NANDF_CS2__GPIO6_15, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_NANDF_CS3__GPIO6_16, PAD_CTRL_UP), + + /* MISC block */ + NEW_PAD_CTRL(MX53_PAD_FEC_MDC__GPIO1_31, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__GPIO1_22, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__GPIO1_25, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__GPIO1_23, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__GPIO1_24, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__GPIO1_28, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__GPIO1_27, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__GPIO1_26, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__GPIO1_30, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__GPIO1_29, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_KEY_COL0__GPIO4_6, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_KEY_ROW0__GPIO4_7, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_KEY_COL1__GPIO4_8, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__GPIO4_9, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_KEY_COL2__GPIO4_10, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__GPIO4_11, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_KEY_COL3__GPIO4_12, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_KEY_ROW3__GPIO4_13, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_KEY_COL4__GPIO4_14, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_KEY_ROW4__GPIO4_15, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_SD2_CMD__GPIO1_11, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_SD2_CLK__GPIO1_10, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_SD2_DATA0__GPIO1_15, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_SD2_DATA1__GPIO1_14, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_SD2_DATA2__GPIO1_13, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_SD2_DATA3__GPIO1_12, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_PATA_BUFFER_EN__GPIO7_1, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_PATA_CS_0__GPIO7_9, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_PATA_CS_1__GPIO7_10, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_PATA_DA_0__GPIO7_6, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_PATA_DA_1__GPIO7_7, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_PATA_DA_2__GPIO7_8, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__GPIO2_0, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__GPIO2_1, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__GPIO2_2, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__GPIO2_3, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA4__GPIO2_4, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA5__GPIO2_5, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA6__GPIO2_6, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA7__GPIO2_7, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__GPIO2_8, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__GPIO2_9, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__GPIO2_10, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__GPIO2_11, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA12__GPIO2_12, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA13__GPIO2_13, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA14__GPIO2_14, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA15__GPIO2_15, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_PATA_DIOR__GPIO7_3, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_PATA_DIOW__GPIO6_17, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_PATA_DMACK__GPIO6_18, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_PATA_DMARQ__GPIO7_0, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_PATA_INTRQ__GPIO7_2, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__GPIO7_5, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__GPIO7_4, PAD_CTRL_UP), + + /* IPU block */ + NEW_PAD_CTRL(MX53_PAD_CSI0_DAT4__GPIO5_22, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_CSI0_DAT5__GPIO5_23, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_CSI0_DAT6__GPIO5_24, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_CSI0_DAT7__GPIO5_25, PAD_CTRL_UP), + /* CSI0_DAT8: setup_iomux_pinheader() */ + /* CSI0_DAT9: setup_iomux_pinheader() */ + /* CSI0_DAT10: setup_iomux_pinheader() */ + /* CSI0_DAT11: setup_iomux_pinheader() */ + /* CSI0_DAT12: setup_iomux_pinheader() */ + NEW_PAD_CTRL(MX53_PAD_CSI0_DAT13__GPIO5_31, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_CSI0_DAT14__GPIO6_0, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_CSI0_DAT15__GPIO6_1, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_CSI0_DAT16__GPIO6_2, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_CSI0_DAT17__GPIO6_3, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_CSI0_DAT18__GPIO6_4, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_CSI0_DAT19__GPIO6_5, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_CSI0_VSYNC__GPIO5_21, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_CSI0_PIXCLK__GPIO5_18, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_CSI0_MCLK__GPIO5_19, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_CSI0_DATA_EN__GPIO5_20, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_DI0_PIN2__GPIO4_18, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_DI0_PIN3__GPIO4_19, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_DI0_PIN4__GPIO4_20, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_DI0_PIN15__GPIO4_17, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_DISP0_DAT0__GPIO4_21, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_DISP0_DAT1__GPIO4_22, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_DISP0_DAT2__GPIO4_23, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_DISP0_DAT3__GPIO4_24, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_DISP0_DAT4__GPIO4_25, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_DISP0_DAT5__GPIO4_26, PAD_CTRL_UP), + /* DISP0_DAT6: setup_iomux_led() */ + NEW_PAD_CTRL(MX53_PAD_DISP0_DAT7__GPIO4_28, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_DISP0_DAT8__GPIO4_29, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_DISP0_DAT9__GPIO4_30, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_DISP0_DAT10__GPIO4_31, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_DISP0_DAT11__GPIO5_5, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_DISP0_DAT12__GPIO5_6, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_DISP0_DAT13__GPIO5_7, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_DISP0_DAT14__GPIO5_8, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_DISP0_DAT15__GPIO5_9, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_DISP0_DAT16__GPIO5_10, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_DISP0_DAT17__GPIO5_11, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_DISP0_DAT18__GPIO5_12, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_DISP0_DAT19__GPIO5_13, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_DISP0_DAT20__GPIO5_14, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_DISP0_DAT21__GPIO5_15, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_DISP0_DAT22__GPIO5_16, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_DISP0_DAT23__GPIO5_17, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_DI0_DISP_CLK__GPIO4_16, PAD_CTRL_UP), + + /* LVDS block */ + NEW_PAD_CTRL(MX53_PAD_LVDS0_TX0_P__GPIO7_30, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_LVDS0_TX1_P__GPIO7_28, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_LVDS0_TX2_P__GPIO7_26, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_LVDS0_TX3_P__GPIO7_22, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_LVDS1_TX0_P__GPIO6_30, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_LVDS1_TX1_P__GPIO6_28, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_LVDS1_TX2_P__GPIO6_24, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_LVDS1_TX3_P__GPIO6_22, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_LVDS0_CLK_P__GPIO7_24, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_LVDS1_CLK_P__GPIO6_26, PAD_CTRL_UP), + }; + + imx_iomux_v3_setup_multiple_pads(pads, ARRAY_SIZE(pads)); +} + +static void setup_gpio(void) +{ + int i, j; + + /* set all GPIO ports as input */ + for (i = 0; i < 8; i++) { + for (j = 0; j < 32; j++) + gpio_direction_input(IMX_GPIO_NR(i, j)); + } +} + +#define CPU_CLOCK 800 + +static void set_clock(void) +{ + u32 ref_clk = MXC_HCLK; + const uint32_t cpuclk = CPU_CLOCK; + const uint32_t dramclk = 400; + int ret; + + ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK); + if (ret) + printf("CPU: Switch CPU clock to %dMHZ failed\n", cpuclk); + + ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK); + if (ret) + printf("CPU: Switch peripheral clock to %dMHz failed\n", + dramclk); + + ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK); + if (ret) + printf("CPU: Switch DDR clock to %dMHz failed\n", dramclk); +} + +int board_early_init_f(void) +{ + setup_iomux_unused_nc(); + setup_iomux_unused_boot(); + setup_iomux_sd(); + setup_iomux_led(); + setup_iomux_pinheader(); + setup_gpio(); + + set_clock(); + return 0; +} + +int board_init(void) +{ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + setup_iomux_i2c(); + return 0; +} + +int board_late_init(void) +{ + print_cpuinfo(); + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 1 << 30); + return 0; +} + +int checkboard(void) +{ + puts("Board: Inverse Path USB armory MkI\n"); + return 0; +} diff --git a/configs/usbarmory_defconfig b/configs/usbarmory_defconfig new file mode 100644 index 0000000..994d2c7 --- /dev/null +++ b/configs/usbarmory_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/inversepath/usbarmory/imximage.cfg" +CONFIG_ARM=y +CONFIG_TARGET_USBARMORY=y diff --git a/include/configs/usbarmory.h b/include/configs/usbarmory.h new file mode 100644 index 0000000..e00ec7b --- /dev/null +++ b/include/configs/usbarmory.h @@ -0,0 +1,115 @@ +/* + * USB armory MkI board configuration settings + * http://inversepath.com/usbarmory + * + * Copyright (C) 2015, Inverse Path + * Andrej Rosano <andrej(a)inversepath.com> + * + * SPDX-License-Identifier:|____GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_MX53 +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_OF_LIBFDT +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_MXC_GPIO + +#include <asm/arch/imx-regs.h> +#include <config_cmd_default.h> + +/* U-Boot commands */ +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_FAT +#define CONFIG_CMD_MEMTEST +#define CONFIG_CMD_EXT2 +#undef CONFIG_CMD_IMLS + +/* U-Boot environment */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_SYS_NO_FLASH +#define CONFIG_ENV_OFFSET (6 * 64 * 1024) +#define CONFIG_ENV_SIZE (8 * 1024) +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 + +/* U-Boot general configurations */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 512 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_CMDLINE_EDITING + +/* UART */ +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +/* SD/MMC */ +#define CONFIG_CMD_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_ESDHC_NUM 2 +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_DOS_PARTITION + +/* USB */ +#define CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX5 +#define CONFIG_USB_STORAGE +#define CONFIG_MXC_USB_PORT 1 +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 + +/* I2C */ +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC + +/* Fuse */ +#define CONFIG_CMD_FUSE +#define CONFIG_FSL_IIM + +/* Linux boot */ +#define CONFIG_BOOTDELAY 1 +#define CONFIG_LOADADDR 0x72000000 +#define CONFIG_SYS_TEXT_BASE 0x77800000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_HOSTNAME usbarmory +#define CONFIG_BOOTARGS \ + "console=ttymxc0,115200 root=/dev/mmcblk0p1 rootwait rw" +#define CONFIG_BOOTCOMMAND \ + "ext2load mmc 0:1 0x70800000 /boot/uImage; ext2load mmc 0:1" \ + "0x71000000 /boot/imx53-usbarmory.dtb; bootm 0x70800000 - 0x71000000" + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM CSD0_BASE_ADDR +#define PHYS_SDRAM_SIZE (gd->ram_size) + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_SYS_MEMTEST_START 0x70000000 +#define CONFIG_SYS_MEMTEST_END 0x90000000 + +#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) + +#endif /* __CONFIG_H */ -- 1.7.10.4

8 14

[U-Boot] sunxi A10s HDMI output problem
by Michal Suchanek 24 Mar '15

24 Mar '15

Hello, I tried to connect the A10s olinuxino to a screen with dual DVI input and while the display mostly works I get red console background instead of black. Sending get-edid output from PC connected to the other DVI connector obtained using a VBE call. If you need more information please specify how to obtain it. Thanks Michal

1 0

[U-Boot] 64Bit device tree compilation
by Hanna Hawa 24 Mar '15

24 Mar '15

Hi Simon, My name is Hanna, I'm working in Software team in Marvell with Yehuda. I'm trying to run U-Boot with FDT in 64Bit. I've issue when I'm trying to load the image on my board, I got abort (**Synchronous Abort**) Exactly when the U-boot run fdt_addr_to_cpu(*cell) under lib/fdtdec.c The issue is the format of the FDT is 32Bit, and Big Endian mode. After some debug, I changed the typedef of fdt_size, and fdt_addr to be u32. Also fdt_addr_to_cpu, and fdt_size_to_cpu to use u32 swap, it works. My question is: Is that correct to change the typedef to use u32Bit? Thanks, Hanna

5 4

[U-Boot] Rework the network stack
by Jörg Krause 24 Mar '15

24 Mar '15

Hi all, there is an issue with the current network stack using netconsole. It's impossible to use network commands as TFTP inside netconsole, because they try to run as atomic network commands. The issue was already reported by Stefano Babic in 2010: [U-Boot] NetConsole and network API http://lists.denx.de/pipermail/u-boot/2010-August/075535.html I run into the same problem: [U-Boot] netconsole: USB Ethernet connection dropping with ping or tftpboot http://lists.denx.de/pipermail/u-boot/2015-February/203838.html I have looked at the current network stack. The stack is based on the concept of atomic network commands. The implementation for netconsole looks very confusing. Sascha Hauer has reimplemented the network stack for Barebox: http://www.spinics.net/lists/u-boot-v2/msg00914.html Looking at the current implementation of net.c looks very clean and well-designed. What do you think about porting this to U-Boot? Best regards Jörg Krause

3 6

[U-Boot] [PATCH] dm: ls1021a: Bring in ls1021a dts files from linux kernel
by Haikun Wang 24 Mar '15

24 Mar '15

From: haikun <haikun.wang(a)freescale.com> Bring in device tree files for ls1021a from linux V3.19. In order to use it in u-boot, make some changes: 1. remove 'gic' node and interrupt related properties in every node. 2. remove 'clockgen' node and clock related properties in every node. 3. change address-cells and size-cells of root node and 'soc' node from 2 to 1. 4. Add quadspi node. Signed-off-by: Haikun Wang <Haikun.Wang(a)freescale.com> --- arch/arm/dts/Makefile | 3 + arch/arm/dts/ls1021a-qds.dts | 47 ++++++++ arch/arm/dts/ls1021a-twr.dts | 31 +++++ arch/arm/dts/ls1021a.dtsi | 265 +++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 346 insertions(+) create mode 100644 arch/arm/dts/ls1021a-qds.dts create mode 100644 arch/arm/dts/ls1021a-twr.dts create mode 100644 arch/arm/dts/ls1021a.dtsi diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index cbe5b86..67b821a 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -54,6 +54,9 @@ dtb-$(CONFIG_SOCFPGA) += \ socfpga_cyclone5_socdk.dtb \ socfpga_cyclone5_socrates.dtb +dtb-$(CONFIG_TARGET_LS1021AQDS) += ls1021a-qds.dtb +dtb-$(CONFIG_TARGET_LS1021ATWR) += ls1021a-twr.dtb + targets += $(dtb-y) DTC_FLAGS += -R 4 -p 0x1000 diff --git a/arch/arm/dts/ls1021a-qds.dts b/arch/arm/dts/ls1021a-qds.dts new file mode 100644 index 0000000..9a06695 --- /dev/null +++ b/arch/arm/dts/ls1021a-qds.dts @@ -0,0 +1,47 @@ +/* + * Freescale ls1021a QDS board device tree source + * + * Copyright 2013-2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include "ls1021a.dtsi" + +/ { + model = "LS1021A QDS Board"; + + aliases { + spi0 = &qspi; + spi1 = &dspi0; + }; +}; + +&dspi0 { + bus-num = <0>; + status = "okay"; + + dspiflash: at45db021d@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <16000000>; + spi-cpol; + spi-cpha; + reg = <0>; + }; +}; + +&qspi { + bus-num = <0>; + status = "okay"; + + qflash0: s25fl128s@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; diff --git a/arch/arm/dts/ls1021a-twr.dts b/arch/arm/dts/ls1021a-twr.dts new file mode 100644 index 0000000..db528f9 --- /dev/null +++ b/arch/arm/dts/ls1021a-twr.dts @@ -0,0 +1,31 @@ +/* + * Freescale ls1021a TWR board device tree source + * + * Copyright 2013-2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include "ls1021a.dtsi" + +/ { + model = "LS1021A TWR Board"; + + aliases { + spi0 = &qspi; + }; +}; + +&qspi { + bus-num = <0>; + status = "okay"; + + qflash0: n25q128a13@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi new file mode 100644 index 0000000..e160a5d --- /dev/null +++ b/arch/arm/dts/ls1021a.dtsi @@ -0,0 +1,265 @@ +/* + * Freescale ls1021a SOC common device tree source + * + * Copyright 2013-2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "skeleton.dtsi" + +/ { + compatible = "fsl,ls1021a"; + + aliases { + serial0 = &lpuart0; + serial1 = &lpuart1; + serial2 = &lpuart2; + serial3 = &lpuart3; + serial4 = &lpuart4; + serial5 = &lpuart5; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@f00 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0xf00>; + }; + + cpu@f01 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0xf01>; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + }; + + pmu { + compatible = "arm,cortex-a7-pmu"; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + ranges; + + + ifc: ifc@1530000 { + compatible = "fsl,ifc", "simple-bus"; + reg = <0x1530000 0x10000>; + }; + + dcfg: dcfg@1ee0000 { + compatible = "fsl,ls1021a-dcfg", "syscon"; + reg = <0x1ee0000 0x10000>; + big-endian; + }; + + esdhc: esdhc@1560000 { + compatible = "fsl,esdhc"; + reg = <0x1560000 0x10000>; + clock-frequency = <0>; + voltage-ranges = <1800 1800 3300 3300>; + sdhci,auto-cmd12; + big-endian; + bus-width = <4>; + status = "disabled"; + }; + + scfg: scfg@1570000 { + compatible = "fsl,ls1021a-scfg", "syscon"; + reg = <0x1570000 0x10000>; + big-endian; + }; + + + dspi0: dspi@2100000 { + compatible = "fsl,vf610-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2100000 0x10000>; + num-cs = <6>; + big-endian; + status = "disabled"; + }; + + dspi1: dspi@2110000 { + compatible = "fsl,vf610-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2110000 0x10000>; + num-cs = <6>; + big-endian; + status = "disabled"; + }; + + qspi: quadspi@1550000 { + compatible = "fsl,vf610-qspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x1550000 0x0 0x10000>, + <0x0 0x40000000 0x0 0x4000000>; + num-cs = <2>; + big-endian; + status = "disabled"; + }; + + i2c0: i2c@2180000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2180000 0x10000>; + status = "disabled"; + }; + + i2c1: i2c@2190000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2190000 0x10000>; + status = "disabled"; + }; + + i2c2: i2c@21a0000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x21a0000 0x10000>; + status = "disabled"; + }; + + uart0: serial@21c0500 { + compatible = "fsl,16550-FIFO64", "ns16550a"; + reg = <0x21c0500 0x100>; + clock-frequency = <0>; + fifo-size = <15>; + status = "disabled"; + }; + + uart1: serial@21c0600 { + compatible = "fsl,16550-FIFO64", "ns16550a"; + reg = <0x21c0600 0x100>; + clock-frequency = <0>; + fifo-size = <15>; + status = "disabled"; + }; + + uart2: serial@21d0500 { + compatible = "fsl,16550-FIFO64", "ns16550a"; + reg = <0x21d0500 0x100>; + clock-frequency = <0>; + fifo-size = <15>; + status = "disabled"; + }; + + uart3: serial@21d0600 { + compatible = "fsl,16550-FIFO64", "ns16550a"; + reg = <0x21d0600 0x100>; + clock-frequency = <0>; + fifo-size = <15>; + status = "disabled"; + }; + + lpuart0: serial@2950000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x2950000 0x1000>; + status = "disabled"; + }; + + lpuart1: serial@2960000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x2960000 0x1000>; + status = "disabled"; + }; + + lpuart2: serial@2970000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x2970000 0x1000>; + status = "disabled"; + }; + + lpuart3: serial@2980000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x2980000 0x1000>; + status = "disabled"; + }; + + lpuart4: serial@2990000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x2990000 0x1000>; + status = "disabled"; + }; + + lpuart5: serial@29a0000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x29a0000 0x1000>; + status = "disabled"; + }; + + wdog0: watchdog@2ad0000 { + compatible = "fsl,imx21-wdt"; + reg = <0x2ad0000 0x10000>; + big-endian; + }; + + sai1: sai@2b50000 { + compatible = "fsl,vf610-sai"; + reg = <0x2b50000 0x10000>; + dma-names = "tx", "rx"; + dmas = <&edma0 1 47>, + <&edma0 1 46>; + big-endian; + status = "disabled"; + }; + + sai2: sai@2b60000 { + compatible = "fsl,vf610-sai"; + reg = <0x2b60000 0x10000>; + dma-names = "tx", "rx"; + dmas = <&edma0 1 45>, + <&edma0 1 44>; + big-endian; + status = "disabled"; + }; + + edma0: edma@2c00000 { + #dma-cells = <2>; + compatible = "fsl,vf610-edma"; + reg = <0x2c00000 0x10000>, + <0x2c10000 0x10000>, + <0x2c20000 0x10000>; + dma-channels = <32>; + big-endian; + }; + + mdio0: mdio@2d24000 { + compatible = "gianfar"; + device_type = "mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2d24000 0x4000>; + }; + + usb@8600000 { + compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr"; + reg = <0x8600000 0x1000>; + dr_mode = "host"; + phy_type = "ulpi"; + }; + + usb3@3100000 { + compatible = "snps,dwc3"; + reg = <0x3100000 0x10000>; + dr_mode = "host"; + }; + }; +}; -- 2.1.0.27.g96db324

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[U-Boot] multi-image uImage with fitImage
by fat loser 24 Mar '15

24 Mar '15

Hi all, I am currently attempting to port my combined uImage and ramdisk image + dtb over to the fitImage format. I am creating a linux kernel + ramdisk with buildroot and dt blob with buildroot. The .its I am using to create a fitImage is below: /dts-v1/; / { description = "Linux kernel"; #address-cells = <1>; images { kernel@1 { description = "Linux kernel"; data = /incbin/("/tftpboot/uImage"); arch = "arm"; os = "linux"; type = "multi"; compression = "none"; load = <0x89008000>; entry = <0x89008000>; }; fdt@1 { description = "Flattened Device Tree blob"; data = /incbin/("/tftpboot/arm.dtb"); type = "flat_dt"; arch = "arm"; compression = "none"; }; }; configurations { default = "conf@1"; conf@1 { description = "Boot Linux kernel"; kernel = "kernel@1"; fdt = "fdt@1"; }; }; }; After tftp'ing the .itb over to address 0x89000000 and running bootm, I get: # bootm ## Loading kernel from FIT Image at 89000000 ... Using 'conf@1' configuration Trying 'kernel@1' kernel subimage Description: Linux kernel Type: Multi-File Image Compression: uncompressed Data Start: 0x890000d0 Data Size: 28604352 Bytes = 27.3 MiB Verifying Hash Integrity ... OK No Linux ARM Kernel Image Image ERROR: can't get kernel image! The images work perfectly before I try to combine them into a fitImage. Is there a special configuration option for multi-file (combined ramdisk-kernel) images in fitImage? Regards, George.

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[U-Boot] [PATCH 1/2] console: Support board-specific early console
by Thierry Reding 24 Mar '15

24 Mar '15

From: Thierry Reding <treding(a)nvidia.com> This is mostly useful for debugging the early boot process. Often boards can provide some low-level code that outputs a character on some debug port prior to passing the early setup code. Allow boards to implement an early_putc() function that will be used to redirect printf() and friends to this debug port until the proper console becomes ready. Cc: Simon Glass <sjg(a)chromium.org> Cc: Tom Rini <trini(a)konsulko.com> Signed-off-by: Thierry Reding <treding(a)nvidia.com> --- README | 17 +++++++++++++++++ common/console.c | 21 +++++++++++++++++++-- 2 files changed, 36 insertions(+), 2 deletions(-) diff --git a/README b/README index b0124d6022e1..a7cb3d86d2d2 100644 --- a/README +++ b/README @@ -5014,6 +5014,23 @@ Low Level (hardware related) configuration options: driver that uses this: drivers/mtd/nand/davinci_nand.c +- CONFIG_EARLY_CONSOLE + Enables support for an early console. Output from puts() and + printf() will be redirected to this early console. A primary + use-case for this is early board bring up, where U-Boot does + not boot to the proper console yet, but it can also be quite + handy to help debug U-Boot's early boot phases. + + Boards that specify this option in their configuration must + provide an implementation of the early_putc() function: + + void early_putc(char ch); + + This function should output a single character on a device + that is available during early boot. Often this will be a + debug UART that has been preconfigured by a bootloader or + ROM before executing U-Boot. + Freescale QE/FMAN Firmware Support: ----------------------------------- diff --git a/common/console.c b/common/console.c index 3f25e76fe79e..d552dff4ee0f 100644 --- a/common/console.c +++ b/common/console.c @@ -479,6 +479,16 @@ void putc(const char c) } } +#ifdef CONFIG_EARLY_CONSOLE +extern void early_putc(char ch); + +static void early_puts(const char *s) +{ + while (*s) + early_putc(*s++); +} +#endif + void puts(const char *s) { #ifdef CONFIG_SANDBOX @@ -498,6 +508,11 @@ void puts(const char *s) return; #endif +#ifdef CONFIG_EARLY_CONSOLE + if (!gd->have_console) + early_puts(s); +#endif + if (!gd->have_console) return pre_console_puts(s); @@ -517,7 +532,8 @@ int printf(const char *fmt, ...) uint i; char printbuffer[CONFIG_SYS_PBSIZE]; -#if !defined(CONFIG_SANDBOX) && !defined(CONFIG_PRE_CONSOLE_BUFFER) +#if !defined(CONFIG_SANDBOX) && !defined(CONFIG_PRE_CONSOLE_BUFFER) && \ + !defined(CONFIG_EARLY_CONSOLE) if (!gd->have_console) return 0; #endif @@ -540,7 +556,8 @@ int vprintf(const char *fmt, va_list args) uint i; char printbuffer[CONFIG_SYS_PBSIZE]; -#if defined(CONFIG_PRE_CONSOLE_BUFFER) && !defined(CONFIG_SANDBOX) +#if !defined(CONFIG_SANDBOX) && !defined(CONFIG_PRE_CONSOLE_BUFFER) && \ + !defined(CONFIG_EARLY_CONSOLE) if (!gd->have_console) return 0; #endif -- 2.3.2

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[U-Boot] [PATCH] buildman: Keep more outputs with the --keep-outputs flag
by Tom Rini 24 Mar '15

24 Mar '15

When told to keep outputs, be much more liberal in what files we keep. In addition to adding 'MLO', keep anything that matches u-boot-spl.* (so that we keep the map file as well) and anything we generate about 'u-boot itself. A large number of bootable formats now match this and thus it's easier to build many targets and then boot them afterwards using buildman. Cc: Simon Glass <sjg(a)chromium.org> Signed-off-by: Tom Rini <trini(a)konsulko.com> --- tools/buildman/builderthread.py | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/tools/buildman/builderthread.py b/tools/buildman/builderthread.py index efb62f1..0550d26 100644 --- a/tools/buildman/builderthread.py +++ b/tools/buildman/builderthread.py @@ -333,9 +333,8 @@ class BuilderThread(threading.Thread): # Now write the actual build output if keep_outputs: - patterns = ['u-boot', '*.bin', 'u-boot.dtb', '*.map', '*.img', - 'include/autoconf.mk', 'spl/u-boot-spl', - 'spl/u-boot-spl.bin'] + patterns = ['u-boot*', '*.bin', '*.map', '*.img', 'MLO', + 'include/autoconf.mk', 'spl/u-boot-spl*' ] for pattern in patterns: file_list = glob.glob(os.path.join(result.out_dir, pattern)) for fname in file_list: -- 1.7.9.5

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[U-Boot] [PATCH 1/3] fdt: Export fdtdec_get_number()
by Thierry Reding 24 Mar '15

24 Mar '15

From: Thierry Reding <treding(a)nvidia.com> Drivers that need to parse addresses from the device tree will want to reuse this function rather than duplicating it. Cc: Simon Glass <sjg(a)chromium.org> Signed-off-by: Thierry Reding <treding(a)nvidia.com> --- include/fdtdec.h | 8 ++++++++ lib/fdtdec.c | 2 +- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/include/fdtdec.h b/include/fdtdec.h index 5ac515d87d2d..5530ee407311 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -723,6 +723,14 @@ int fdtdec_read_fmap_entry(const void *blob, int node, const char *name, struct fmap_entry *entry); /** + * Read a number from a device property. + * @param ptr pointer to the cells to read + * @param cells number of cells to consume + * @return The number contained in @cells cells at @ptr, in host byte order. + */ +u64 fdtdec_get_number(const fdt32_t *ptr, unsigned int cells); + +/** * Obtain an indexed resource from a device property. * * @param fdt FDT blob diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 0776c3004cbd..613cc8494a74 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -918,7 +918,7 @@ int fdtdec_read_fmap_entry(const void *blob, int node, const char *name, return 0; } -static u64 fdtdec_get_number(const fdt32_t *ptr, unsigned int cells) +u64 fdtdec_get_number(const fdt32_t *ptr, unsigned int cells) { u64 number = 0; -- 2.3.2

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