March 2015 - U-Boot

[U-Boot] [PATCH v2 1/3] sunxi: sun4i: improve cpu clock selection method
by Iain Paton 30 Mar '15

30 Mar '15

clock_set_pll1 would pick the next highest available cpu clock speed if a value not in the pre defined table was selected. this potentially results in overclocking the soc. reverse the selection method so that we select the next lowest speed and add the missing 912Mhz setting that's requested by sun7i which also uses the sun4i clock code. Signed-off-by: Iain Paton <ipaton0(a)gmail.com> --- arch/arm/cpu/armv7/sunxi/clock_sun4i.c | 35 ++++++++++++++++++---------------- 1 file changed, 19 insertions(+), 16 deletions(-) diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c index 49f4032..c3e04af 100644 --- a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c +++ b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c @@ -100,22 +100,23 @@ static struct { unsigned int freq; } pll1_para[] = { /* This array must be ordered by frequency. */ - { PLL1_CFG(16, 0, 0, 0), 384000000 }, - { PLL1_CFG(16, 1, 0, 0), 768000000 }, - { PLL1_CFG(20, 1, 0, 0), 960000000 }, - { PLL1_CFG(21, 1, 0, 0), 1008000000}, - { PLL1_CFG(22, 1, 0, 0), 1056000000}, - { PLL1_CFG(23, 1, 0, 0), 1104000000}, - { PLL1_CFG(24, 1, 0, 0), 1152000000}, - { PLL1_CFG(25, 1, 0, 0), 1200000000}, - { PLL1_CFG(26, 1, 0, 0), 1248000000}, - { PLL1_CFG(27, 1, 0, 0), 1296000000}, - { PLL1_CFG(28, 1, 0, 0), 1344000000}, - { PLL1_CFG(29, 1, 0, 0), 1392000000}, - { PLL1_CFG(30, 1, 0, 0), 1440000000}, { PLL1_CFG(31, 1, 0, 0), 1488000000}, - /* Final catchall entry */ - { PLL1_CFG(31, 1, 0, 0), ~0}, + { PLL1_CFG(30, 1, 0, 0), 1440000000}, + { PLL1_CFG(29, 1, 0, 0), 1392000000}, + { PLL1_CFG(28, 1, 0, 0), 1344000000}, + { PLL1_CFG(27, 1, 0, 0), 1296000000}, + { PLL1_CFG(26, 1, 0, 0), 1248000000}, + { PLL1_CFG(25, 1, 0, 0), 1200000000}, + { PLL1_CFG(24, 1, 0, 0), 1152000000}, + { PLL1_CFG(23, 1, 0, 0), 1104000000}, + { PLL1_CFG(22, 1, 0, 0), 1056000000}, + { PLL1_CFG(21, 1, 0, 0), 1008000000}, + { PLL1_CFG(20, 1, 0, 0), 960000000 }, + { PLL1_CFG(19, 1, 0, 0), 912000000 }, + { PLL1_CFG(16, 1, 0, 0), 768000000 }, + /* Final catchall entry 384MHz*/ + { PLL1_CFG(16, 0, 0, 0), 0 }, + }; void clock_set_pll1(unsigned int hz) @@ -126,10 +127,12 @@ void clock_set_pll1(unsigned int hz) (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; /* Find target frequency */ - while (pll1_para[i].freq < hz) + while (pll1_para[i].freq > hz) i++; hz = pll1_para[i].freq; + if (! hz) + hz = 384000000; /* Calculate system clock divisors */ axi = DIV_ROUND_UP(hz, 432000000); /* Max 450MHz */ -- 2.1.3

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[U-Boot] [PATCH 0/6] ARM: at91: SAMA5: extract the common sama5 chip configurations to a common header
by Josh Wu 30 Mar '15

30 Mar '15

This patch series reorganized the configurations for SAMA5 chips. Make the common part into one file. That way we don't need to have many copy of the same configurations. Josh Wu (6): ARM: at91: sama5d3_xplained: spl: enable PMECC header generation ARM: at91: sama5: move the common part of configurations to at91-sama5_common.h ARM: at91: sama5d3_xplained: set ENV_FAT_DEVICE_AND_PART intead of using number ARM: at91: sama5d3: mmc: save enviroment as a fat file (uboot.env) ARM: at91: sama5: move the bootcmd definition to the common header ARM: at91: at91sam9x5: mmc: save environment as a file in FAT partition. include/configs/at91-sama5_common.h | 126 ++++++++++++++++++++++++++++++++++++ include/configs/at91sam9x5ek.h | 12 ++-- include/configs/sama5d3_xplained.h | 100 ++-------------------------- include/configs/sama5d3xek.h | 114 ++------------------------------ include/configs/sama5d4_xplained.h | 116 ++------------------------------- include/configs/sama5d4ek.h | 116 ++------------------------------- 6 files changed, 153 insertions(+), 431 deletions(-) create mode 100644 include/configs/at91-sama5_common.h -- 1.9.1

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[U-Boot] [PATCH v6 0/8] Extend LPC32xx functionality and add LPC32xx-based work_92015 board
by Albert ARIBAUD (3ADEV) 30 Mar '15

30 Mar '15

This series extends functionality for the LPC32xx platform and introduces the WORK Microwave work_92105 board which makes use of the extended functionality. NOTES: A - I2C driver remains non-DM During v2 review, it was suggested to move to DM for I2C. However, this caused issues with the 'date', 'dtt' and 'eeprom' commands which are configured in this board. Therefore the I2C move to DM was not done. B - Some checkpatch diagnostics are not fixed The following warnings checkpatch warnings and checks were not fixed: 1. "warning: arch/arm/Kconfig,135: please write a paragraph that describes the config symbol fully" Other symbols in the same file have no description either. For consistency, I did not add the requested description. 1. "check: include/configs/work_92105.h,187: spaces required around that ':' (ctx:VxV) (5 occurrences on the same line) This is due to the value of CONFIG_ETHADDR not being in quotes. As it never is in any other definition of CONFIG_ETHADDR, I left it unchanged. Changes in v6: - added some missing readl() wraps - moved descriptors and buffers to SRAM - rewrite timeout loops - fix bad block skipping in SPL chainload loop - remove '+S:' prefixes from defconfig - use custom LPC32XX linker script - reset peripherals at startup - support 128MB boards Changes in v5: - switch to CONFIG_SYS_NAND_SELF_INIT - switched board NAND config to CONFIG_SYS_NAND_SELF_INIT Changes in v4: - remove two debugging statements - add __iomem to regs struct - remove useless 'else return;' - take BB marker out of free OOB area - replace magic numbers in OOB reads/writes - add timeouts in NAND loops - use DIV_ROUND_UP where applicable - fix erroneous comment - skip bad blocks in SPL chainload loop Changes in v3: - move DM dependency constraint into Kconfig - move regs pointer and function cache into private struct - discourage readers from using functions implementation as an example - move regs and functions in private struct - remove script/Makefile.spl change - use writel() in DRAM initialization code - remove useless conditionals in dram.c - fix and complete the board README - remove redundant CONFIG_CMD_DM from config header file - add a note re the hard-coded MAC address - add 'single flashable file' make target Changes in v2: - move from legacy to Driver Model support - added MUX setting for SSP0 - cosmetic: added a blank line before copyright - move boot image generation to mkimage framework Albert ARIBAUD (3ADEV) (8): lpc32xx: add Ethernet support lpc32xx: mtd: nand: add MLC NAND controller lpc32xx: i2c: add LPC32xx I2C interface support lpc32xx: add GPIO support lpc32xx: add LPC32xx SSP support (SPI mode) dtt: add ds620 support lpc32xx: add lpc32xx-spl.bin boot image target lpc32xx: add support for board work_92105 Makefile | 20 + arch/arm/Kconfig | 6 + arch/arm/cpu/arm926ejs/lpc32xx/Makefile | 2 + arch/arm/cpu/arm926ejs/lpc32xx/clk.c | 34 + arch/arm/cpu/arm926ejs/lpc32xx/cpu.c | 13 + arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 43 ++ arch/arm/cpu/arm926ejs/lpc32xx/dram.c | 79 +++ arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S | 45 ++ arch/arm/cpu/arm926ejs/lpc32xx/u-boot.lds | 161 +++++ arch/arm/include/asm/arch-lpc32xx/clk.h | 16 + arch/arm/include/asm/arch-lpc32xx/config.h | 3 + arch/arm/include/asm/arch-lpc32xx/cpu.h | 3 + arch/arm/include/asm/arch-lpc32xx/gpio.h | 43 ++ arch/arm/include/asm/arch-lpc32xx/mux.h | 18 + arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 8 +- board/work-microwave/work_92105/Kconfig | 15 + board/work-microwave/work_92105/MAINTAINERS | 6 + board/work-microwave/work_92105/Makefile | 10 + board/work-microwave/work_92105/README | 91 +++ board/work-microwave/work_92105/work_92105.c | 77 +++ .../work-microwave/work_92105/work_92105_display.c | 349 ++++++++++ .../work-microwave/work_92105/work_92105_display.h | 14 + board/work-microwave/work_92105/work_92105_spl.c | 33 + common/image.c | 1 + configs/work_92105_defconfig | 6 + drivers/gpio/Kconfig | 7 + drivers/gpio/Makefile | 1 + drivers/gpio/lpc32xx_gpio.c | 293 +++++++++ drivers/hwmon/Makefile | 1 + drivers/hwmon/ds620.c | 65 ++ drivers/i2c/Makefile | 1 + drivers/i2c/lpc32xx_i2c.c | 249 +++++++ drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/lpc32xx_nand_mlc.c | 718 +++++++++++++++++++++ drivers/net/Makefile | 1 + drivers/net/lpc32xx_eth.c | 639 ++++++++++++++++++ drivers/spi/Makefile | 1 + drivers/spi/lpc32xx_ssp.c | 144 +++++ include/configs/work_92105.h | 268 ++++++++ include/dtt.h | 15 +- include/image.h | 1 + include/netdev.h | 1 + tools/Makefile | 1 + tools/lpc32xximage.c | 178 +++++ 44 files changed, 3673 insertions(+), 8 deletions(-) create mode 100644 arch/arm/cpu/arm926ejs/lpc32xx/dram.c create mode 100644 arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S create mode 100644 arch/arm/cpu/arm926ejs/lpc32xx/u-boot.lds create mode 100644 arch/arm/include/asm/arch-lpc32xx/gpio.h create mode 100644 arch/arm/include/asm/arch-lpc32xx/mux.h create mode 100644 board/work-microwave/work_92105/Kconfig create mode 100644 board/work-microwave/work_92105/MAINTAINERS create mode 100644 board/work-microwave/work_92105/Makefile create mode 100644 board/work-microwave/work_92105/README create mode 100644 board/work-microwave/work_92105/work_92105.c create mode 100644 board/work-microwave/work_92105/work_92105_display.c create mode 100644 board/work-microwave/work_92105/work_92105_display.h create mode 100644 board/work-microwave/work_92105/work_92105_spl.c create mode 100644 configs/work_92105_defconfig create mode 100644 drivers/gpio/lpc32xx_gpio.c create mode 100644 drivers/hwmon/ds620.c create mode 100644 drivers/i2c/lpc32xx_i2c.c create mode 100644 drivers/mtd/nand/lpc32xx_nand_mlc.c create mode 100644 drivers/net/lpc32xx_eth.c create mode 100644 drivers/spi/lpc32xx_ssp.c create mode 100644 include/configs/work_92105.h create mode 100644 tools/lpc32xximage.c -- 2.1.0

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[U-Boot] NAND Flash with Internal Hardware ECC
by Rajiv Dave 30 Mar '15

30 Mar '15

Hi, We are using an Atmel AT91SAM9263 processor which supports 1 Bit ECC flash devices that have Block 0 Valid with no ECC. These devices are now obsolete. We have fitted a board with a MT29F2G08ABAEWP-E-E, which has an internal Hardware ECC engine. Would you know how provide support for this device within U-Boot? The following output is generated by a board fitted with the NAND Flash with Internal Hardware ECC RomBOOT > U-Boot 1.3.4 (Sep 19 2013 - 15:10:38) DRAM: 64 MB NAND: 256 MiB No Valid Environment Area Found In: serial Out: serial Err: serial Net: macb0 macb0: Starting autonegotiation... macb0: Autonegotiation timed out (status=0x7849) macb0: link down (status: 0x7849) Hit any key to stop autoboot: 3 2 1 0 NAND read: device 0 offset 0x200000, size 0x17e16c 1565036 bytes read: ERROR ## Booting kernel from Legacy Image at 22200000 ... Image Name: Linux-2.6.30 Image Type: ARM Linux Kernel Image (uncompressed) Data Size: 1564972 Bytes = 1.5 MB Load Address: 20008000 Entry Point: 20008000 Verifying Checksum ... Bad Data CRC ERROR: can't get kernel image! U-Boot> Regards Rajiv Dave Disign Consultants t: +44 (0) 207 544 8486 w: www.disignconsultants.com This message and any attachment are confidential and may be privileged or otherwise protected from disclosure. If you are not the intended recipient, please telephone or email the sender and delete this message and any attachment from your system. If you are not the intended recipient you must not copy this message or attachment or disclose the contents to any other person.

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[U-Boot] [PATCHv2 00/20] Add SPL support for SoCFPGA
by dinguyen＠opensource.altera.com 30 Mar '15

30 Mar '15

From: Dinh Nguyen <dinguyen(a)opensource.altera.com> Hello, This is v2 of the patchset that adds all the SPL code that is necessary to support the SoCFPGA platform. For v2, here are the changes: - SDRAM - further clean and addressing all comments. Simplified to only support DDR3, FULLRATE, and Hard PHY. - SDRAM - Moved to drivers/ddr/altera - Move extra code that maps SDRAM to 0x0 in board_init_f I have pushed a branch to git://git.rocketboards.org/u-boot-socfpga-next.git socfpga_for_next_spl_v2 for testing and reviewing. Rebased to 2015.04-rc2. Thanks, Dinh Nguyen (20): arm: socfpga: spl: Add main sdram code arm: socfpga: spl: Add SRAM section arm: socfpga: spl: put SPL in sram arm: socfpga: add functions to bring sdram, timer, and uart out of reset arm: socfpga: spl: enable sdram, timer and uart arm: socfpga: spl: Add call to timer_init arm: socfpga: spl: allow bootrom to enable IOs after warm reset arm: socfpga: spl: add sdram init and calibration arm: socfpga: spl: printout sdram size arm: socfpga: spl: Use common lowlevel_init arm: socfpga: spl: Add s_init arm: socfpga: spl: add the stack in OCRAM arm: socfpga: spl: add CONFIG_SPL_STACK to socfpga_common.h arm: socfpga: add sdram stack to SPL arm: socfpga: spl: adjust SPL_MALLOC_SIZE to 256 arm: socfpga: spl: add a malloc section in sram arm: socfpga: spl: Add SDRAM check arm: socfpga: spl: add board_init_f to SPL arm: socfpga: spl: update pll_config for dev kit arm: socfpga: remove the need to map sdram in arch_early_init Makefile | 1 + arch/arm/cpu/armv7/Makefile | 2 +- arch/arm/cpu/armv7/socfpga/Makefile | 4 +- arch/arm/cpu/armv7/socfpga/lowlevel_init.S | 4 - arch/arm/cpu/armv7/socfpga/misc.c | 3 - arch/arm/cpu/armv7/socfpga/reset_manager.c | 24 + arch/arm/cpu/armv7/socfpga/s_init.c | 37 + arch/arm/cpu/armv7/socfpga/spl.c | 47 + arch/arm/cpu/armv7/socfpga/system_manager.c | 9 + arch/arm/cpu/armv7/socfpga/u-boot-spl.lds | 29 +- arch/arm/include/asm/arch-socfpga/reset_manager.h | 6 + arch/arm/include/asm/arch-socfpga/sdram.h | 434 +++ arch/arm/include/asm/arch-socfpga/sdram_config.h | 100 + arch/arm/include/asm/arch-socfpga/system_manager.h | 1 + board/altera/socfpga/pll_config.h | 8 +- drivers/ddr/altera/Makefile | 12 + drivers/ddr/altera/sdram.c | 1307 +++++++ drivers/ddr/altera/sequencer.c | 3972 ++++++++++++++++++++ drivers/ddr/altera/sequencer.h | 359 ++ drivers/ddr/altera/sequencer_auto.h | 216 ++ drivers/ddr/altera/sequencer_auto_ac_init.c | 85 + drivers/ddr/altera/sequencer_auto_inst_init.c | 270 ++ drivers/ddr/altera/sequencer_defines.h | 121 + include/configs/socfpga_common.h | 11 +- include/configs/socfpga_cyclone5.h | 1 + scripts/Makefile.spl | 1 + 26 files changed, 7046 insertions(+), 18 deletions(-) create mode 100644 arch/arm/cpu/armv7/socfpga/s_init.c create mode 100644 arch/arm/include/asm/arch-socfpga/sdram.h create mode 100644 arch/arm/include/asm/arch-socfpga/sdram_config.h create mode 100644 drivers/ddr/altera/Makefile create mode 100644 drivers/ddr/altera/sdram.c create mode 100644 drivers/ddr/altera/sequencer.c create mode 100644 drivers/ddr/altera/sequencer.h create mode 100644 drivers/ddr/altera/sequencer_auto.h create mode 100644 drivers/ddr/altera/sequencer_auto_ac_init.c create mode 100644 drivers/ddr/altera/sequencer_auto_inst_init.c create mode 100644 drivers/ddr/altera/sequencer_defines.h -- 2.2.1

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[U-Boot] [PATCH] spi: designware_spi: revisit FIFO size detection again
by Axel Lin 29 Mar '15

29 Mar '15

By specification the FIFO size would be in a range 2-256 bytes. From TX Level prospective it means we can set threshold in the range 0-(FIFO size - 1) bytes. Hence there are currently two issues: a) FIFO size 2 bytes is actually skipped since TX Level is 1 bit and could be either 0 or 1 byte; b) FIFO size is incorrectly decreased by 1 which already done by meaning of TX Level register. Fixes: 501943696ea4 (spi: designware_spi: Fix detecting FIFO depth) Signed-off-by: Andy Shevchenko <andriy.shevchenko(a)linux.intel.com> Signed-off-by: Axel Lin <axel.lin(a)ingics.com> --- This fix is from linux-spi tree: http://git.kernel.org/cgit/linux/kernel/git/broonie/spi.git/commit/?h=for-l… drivers/spi/designware_spi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c index 2624844..8f5c0fc 100644 --- a/drivers/spi/designware_spi.c +++ b/drivers/spi/designware_spi.c @@ -164,13 +164,13 @@ static void spi_hw_init(struct dw_spi_priv *priv) if (!priv->fifo_len) { u32 fifo; - for (fifo = 2; fifo <= 256; fifo++) { + for (fifo = 1; fifo < 256; fifo++) { dw_writew(priv, DW_SPI_TXFLTR, fifo); if (fifo != dw_readw(priv, DW_SPI_TXFLTR)) break; } - priv->fifo_len = (fifo == 2) ? 0 : fifo - 1; + priv->fifo_len = (fifo == 1) ? 0 : fifo; dw_writew(priv, DW_SPI_TXFLTR, 0); } debug("%s: fifo_len=%d\n", __func__, priv->fifo_len); -- 1.9.1

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[U-Boot] [PATCH 1/2] spi: cf_spi: Use to_cf_spi_slave to resolve cfslave from slave
by Axel Lin 29 Mar '15

29 Mar '15

Don't assume slave is always the first member of struct cf_spi_slave. Use container_of instead of casting first structure member. Signed-off-by: Axel Lin <axel.lin(a)ingics.com> --- drivers/spi/cf_spi.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/spi/cf_spi.c b/drivers/spi/cf_spi.c index 879a809..7453538 100644 --- a/drivers/spi/cf_spi.c +++ b/drivers/spi/cf_spi.c @@ -46,6 +46,11 @@ DECLARE_GLOBAL_DATA_PTR; #define SPI_MODE_MOD 0x00200000 #define SPI_DBLRATE 0x00100000 +static inline struct cf_spi_slave *to_cf_spi_slave(struct spi_slave *slave) +{ + return container_of(slave, struct cf_spi_slave, slave); +} + void cfspi_init(void) { volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; @@ -105,7 +110,7 @@ u16 cfspi_rx(void) int cfspi_xfer(struct spi_slave *slave, uint bitlen, const void *dout, void *din, ulong flags) { - struct cf_spi_slave *cfslave = (struct cf_spi_slave *)slave; + struct cf_spi_slave *cfslave = to_cf_spi_slave(slave); u16 *spi_rd16 = NULL, *spi_wr16 = NULL; u8 *spi_rd = NULL, *spi_wr = NULL; static u32 ctrl = 0; @@ -326,7 +331,9 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, void spi_free_slave(struct spi_slave *slave) { - free(slave); + struct cf_spi_slave *cfslave = to_cf_spi_slave(slave); + + free(cfslave); } int spi_claim_bus(struct spi_slave *slave) -- 1.9.1

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[U-Boot] Please pull u-boot-sunxi master (v2)
by Hans de Goede 29 Mar '15

29 Mar '15

Hi Tom, This pull-req superceeds my previous pull-req from about 10 minutes ago, as I found that one board was missing a MAINTAINERS entry, so I've included a fix for that in this new pull-req. Please pull u-boot-sunxi/master into master for another round of bugfixes for v2015.04: The following changes since commit 5db752353b6a19c50db4a30692efb7e845fb8a6e: powerpc: ppc4xx: convert AMCC boards to generic board (2015-03-28 12:09:46 -0400) are available in the git repository at: http://git.denx.de/u-boot-sunxi.git master for you to fetch changes up to 662e2acb46250881ec26bc8366fc9eb1856cb7c2: sunxi: UTOO_P66: Add missing MAINTAINERS entry (2015-03-29 14:56:48 +0200) ---------------------------------------------------------------- Hans de Goede (2): sunxi: musb: Fix some lo speed devices not working with musb host sunxi: UTOO_P66: Add missing MAINTAINERS entry Iain Paton (3): sunxi: sun4i: improve cpu clock selection method sunxi: use CONFIG_SYS_CLK_FREQ to set cpu clock sunxi: a10-LIME set the cpu clock at boot to 912MHz Kconfig | 2 +- arch/arm/cpu/armv7/sunxi/clock_sun4i.c | 35 ++++++++++++++++++---------------- arch/arm/cpu/armv7/sunxi/psci.S | 2 +- arch/arm/cpu/armv7/sunxi/usbc.c | 7 +++++++ arch/arm/include/asm/arch-sunxi/usbc.h | 1 + board/sunxi/Kconfig | 4 ++++ board/sunxi/MAINTAINERS | 1 + board/sunxi/board.c | 2 +- configs/A10-OLinuXino-Lime_defconfig | 1 + drivers/usb/musb-new/musb_uboot.c | 14 ++++++++++++++ include/configs/sun4i.h | 1 - include/configs/sun5i.h | 1 - include/configs/sun6i.h | 1 - include/configs/sun7i.h | 4 +--- include/configs/sun8i.h | 1 - 15 files changed, 51 insertions(+), 26 deletions(-) Regards, Hans

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[U-Boot] [PATCH 1/7] sunxi: TZX-Q8-713B7 mmc0 card-detect pin
by Paul Kocialkowski 29 Mar '15

29 Mar '15

Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr> --- configs/TZX-Q8-713B7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/TZX-Q8-713B7_defconfig b/configs/TZX-Q8-713B7_defconfig index 4ff4542..0953554 100644 --- a/configs/TZX-Q8-713B7_defconfig +++ b/configs/TZX-Q8-713B7_defconfig @@ -1,6 +1,7 @@ CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,AXP209_POWER" CONFIG_FDTFILE="sun5i-a13-tzx-q8-713b7.dtb" +CONFIG_MMC0_CD_PIN="PG0" CONFIG_USB_MUSB_SUNXI=y CONFIG_USB0_VBUS_PIN="PG12" CONFIG_USB0_VBUS_DET="PG1" -- 1.9.1

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[U-Boot] [PATCH v4 1/2] sunxi: Serial number support, obtained from SID bits
by Paul Kocialkowski 29 Mar '15

29 Mar '15

Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr> --- board/sunxi/board.c | 33 ++++++++++++++++++++++----------- 1 file changed, 22 insertions(+), 11 deletions(-) diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 01b654e..79516bf 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -372,20 +372,31 @@ int g_dnl_board_usb_cable_connected(void) #ifdef CONFIG_MISC_INIT_R int misc_init_r(void) { + char serial_string[17] = { 0 }; unsigned int sid[4]; + uint8_t mac_addr[6]; + int ret; + + ret = sunxi_get_sid(sid); + if (ret == 0 && sid[0] != 0 && sid[3] != 0) { + if (!getenv("ethaddr")) { + /* Non OUI / registered MAC address */ + mac_addr[0] = 0x02; + mac_addr[1] = (sid[0] >> 0) & 0xff; + mac_addr[2] = (sid[3] >> 24) & 0xff; + mac_addr[3] = (sid[3] >> 16) & 0xff; + mac_addr[4] = (sid[3] >> 8) & 0xff; + mac_addr[5] = (sid[3] >> 0) & 0xff; + + eth_setenv_enetaddr("ethaddr", mac_addr); + } - if (!getenv("ethaddr") && sunxi_get_sid(sid) == 0 && - sid[0] != 0 && sid[3] != 0) { - uint8_t mac_addr[6]; - - mac_addr[0] = 0x02; /* Non OUI / registered MAC address */ - mac_addr[1] = (sid[0] >> 0) & 0xff; - mac_addr[2] = (sid[3] >> 24) & 0xff; - mac_addr[3] = (sid[3] >> 16) & 0xff; - mac_addr[4] = (sid[3] >> 8) & 0xff; - mac_addr[5] = (sid[3] >> 0) & 0xff; + if (!getenv("serial#")) { + snprintf(serial_string, sizeof(serial_string), + "%08x%08x", sid[0], sid[3]); - eth_setenv_enetaddr("ethaddr", mac_addr); + setenv("serial#", serial_string); + } } #if defined(CONFIG_MUSB_HOST) || defined(CONFIG_MUSB_GADGET) -- 1.9.1

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