March 2015 - U-Boot

[U-Boot] [PATCH 2/5 v2] dm: ls1021a: Bring in ls1021a dts files from linux kernel
by Haikun Wang 01 Apr '15

01 Apr '15

From: haikun <haikun.wang(a)freescale.com> Bring in required device tree files for ls1021a from Linux. These are initially unchanged and have a number of pieces not needed by U-Boot. Signed-off-by: Haikun Wang <Haikun.Wang(a)freescale.com> --- Changes in v2: - Use CONFIG_LS102XA in arch/arm/dts/Makefile Changes in v1: None arch/arm/dts/Makefile | 3 + arch/arm/dts/ls1021a-qds.dts | 201 +++++++++++++++++++++++ arch/arm/dts/ls1021a-twr.dts | 88 ++++++++++ arch/arm/dts/ls1021a.dtsi | 370 +++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 662 insertions(+) create mode 100644 arch/arm/dts/ls1021a-qds.dts create mode 100644 arch/arm/dts/ls1021a-twr.dts create mode 100644 arch/arm/dts/ls1021a.dtsi diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index cbe5b86..c326707 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -54,6 +54,9 @@ dtb-$(CONFIG_SOCFPGA) += \ socfpga_cyclone5_socdk.dtb \ socfpga_cyclone5_socrates.dtb +dtb-$(CONFIG_LS102XA) += ls1021a-qds.dtb \ + ls1021a-twr.dtb + targets += $(dtb-y) DTC_FLAGS += -R 4 -p 0x1000 diff --git a/arch/arm/dts/ls1021a-qds.dts b/arch/arm/dts/ls1021a-qds.dts new file mode 100644 index 0000000..c89f85e --- /dev/null +++ b/arch/arm/dts/ls1021a-qds.dts @@ -0,0 +1,201 @@ +/* + * Freescale ls1021a QDS board device tree source + * + * Copyright 2013-2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include "ls1021a.dtsi" + +/ { + model = "LS1021A QDS Board"; + + aliases { + enet0_rgmii_phy = &rgmii_phy1; + enet1_rgmii_phy = &rgmii_phy2; + enet2_rgmii_phy = &rgmii_phy3; + enet0_sgmii_phy = &sgmii_phy1c; + enet1_sgmii_phy = &sgmii_phy1d; + }; +}; + +&dspi0 { + bus-num = <0>; + status = "okay"; + + dspiflash: at45db021d@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,at45db021d", "atmel,at45", "atmel,dataflash"; + spi-max-frequency = <16000000>; + spi-cpol; + spi-cpha; + reg = <0>; + }; +}; + +&i2c0 { + status = "okay"; + + pca9547: mux@77 { + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + + ds3232: rtc@68 { + compatible = "dallas,ds3232"; + reg = <0x68>; + interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + + ina220@40 { + compatible = "ti,ina220"; + reg = <0x40>; + shunt-resistor = <1000>; + }; + + ina220@41 { + compatible = "ti,ina220"; + reg = <0x41>; + shunt-resistor = <1000>; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + + eeprom@56 { + compatible = "atmel,24c512"; + reg = <0x56>; + }; + + eeprom@57 { + compatible = "atmel,24c512"; + reg = <0x57>; + }; + + adt7461a@4c { + compatible = "adi,adt7461a"; + reg = <0x4c>; + }; + }; + }; +}; + +&ifc { + #address-cells = <2>; + #size-cells = <1>; + /* NOR, NAND Flashes and FPGA on board */ + ranges = <0x0 0x0 0x0 0x60000000 0x08000000 + 0x2 0x0 0x0 0x7e800000 0x00010000 + 0x3 0x0 0x0 0x7fb00000 0x00000100>; + status = "okay"; + + nor@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0x0 0x0 0x8000000>; + bank-width = <2>; + device-width = <1>; + }; + + fpga: board-control@3,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + reg = <0x3 0x0 0x0000100>; + bank-width = <1>; + device-width = <1>; + ranges = <0 3 0 0x100>; + + mdio-mux-emi1 { + compatible = "mdio-mux-mmioreg"; + mdio-parent-bus = <&mdio0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x54 1>; /* BRDCFG4 */ + mux-mask = <0xe0>; /* EMI1[2:0] */ + + /* Onboard PHYs */ + ls1021amdio0: mdio@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + rgmii_phy1: ethernet-phy@1 { + reg = <0x1>; + }; + }; + + ls1021amdio1: mdio@20 { + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + rgmii_phy2: ethernet-phy@2 { + reg = <0x2>; + }; + }; + + ls1021amdio2: mdio@40 { + reg = <0x40>; + #address-cells = <1>; + #size-cells = <0>; + rgmii_phy3: ethernet-phy@3 { + reg = <0x3>; + }; + }; + + ls1021amdio3: mdio@60 { + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + sgmii_phy1c: ethernet-phy@1c { + reg = <0x1c>; + }; + }; + + ls1021amdio4: mdio@80 { + reg = <0x80>; + #address-cells = <1>; + #size-cells = <0>; + sgmii_phy1d: ethernet-phy@1d { + reg = <0x1d>; + }; + }; + }; + }; +}; + +&lpuart0 { + status = "okay"; +}; + +&mdio0 { + tbi0: tbi-phy@8 { + reg = <0x8>; + device_type = "tbi-phy"; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; diff --git a/arch/arm/dts/ls1021a-twr.dts b/arch/arm/dts/ls1021a-twr.dts new file mode 100644 index 0000000..34ac82d --- /dev/null +++ b/arch/arm/dts/ls1021a-twr.dts @@ -0,0 +1,88 @@ +/* + * Freescale ls1021a TWR board device tree source + * + * Copyright 2013-2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include "ls1021a.dtsi" + +/ { + model = "LS1021A TWR Board"; + + aliases { + enet2_rgmii_phy = &rgmii_phy1; + enet0_sgmii_phy = &sgmii_phy2; + enet1_sgmii_phy = &sgmii_phy0; + }; +}; + +&dspi1 { + bus-num = <0>; + status = "okay"; + + dspiflash: s25fl064k@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spansion,s25fl064k"; + spi-max-frequency = <16000000>; + spi-cpol; + spi-cpha; + reg = <0>; + }; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&ifc { + #address-cells = <2>; + #size-cells = <1>; + /* NOR Flash on board */ + ranges = <0x0 0x0 0x0 0x60000000 0x08000000>; + status = "okay"; + + nor@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0x0 0x0 0x8000000>; + bank-width = <2>; + device-width = <1>; + }; +}; + +&lpuart0 { + status = "okay"; +}; + +&mdio0 { + sgmii_phy0: ethernet-phy@0 { + reg = <0x0>; + }; + rgmii_phy1: ethernet-phy@1 { + reg = <0x1>; + }; + sgmii_phy2: ethernet-phy@2 { + reg = <0x2>; + }; + tbi1: tbi-phy@1f { + reg = <0x1f>; + device_type = "tbi-phy"; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi new file mode 100644 index 0000000..434b938 --- /dev/null +++ b/arch/arm/dts/ls1021a.dtsi @@ -0,0 +1,370 @@ +/* + * Freescale ls1021a SOC common device tree source + * + * Copyright 2013-2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "skeleton64.dtsi" +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + compatible = "fsl,ls1021a"; + interrupt-parent = <&gic>; + + aliases { + serial0 = &lpuart0; + serial1 = &lpuart1; + serial2 = &lpuart2; + serial3 = &lpuart3; + serial4 = &lpuart4; + serial5 = &lpuart5; + sysclk = &sysclk; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@f00 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0xf00>; + clocks = <&cluster1_clk>; + }; + + cpu@f01 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0xf01>; + clocks = <&cluster1_clk>; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + }; + + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + device_type = "soc"; + interrupt-parent = <&gic>; + ranges; + + gic: interrupt-controller@1400000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x1401000 0x0 0x1000>, + <0x0 0x1402000 0x0 0x1000>, + <0x0 0x1404000 0x0 0x2000>, + <0x0 0x1406000 0x0 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; + + }; + + ifc: ifc@1530000 { + compatible = "fsl,ifc", "simple-bus"; + reg = <0x0 0x1530000 0x0 0x10000>; + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + }; + + dcfg: dcfg@1ee0000 { + compatible = "fsl,ls1021a-dcfg", "syscon"; + reg = <0x0 0x1ee0000 0x0 0x10000>; + big-endian; + }; + + esdhc: esdhc@1560000 { + compatible = "fsl,esdhc"; + reg = <0x0 0x1560000 0x0 0x10000>; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <0>; + voltage-ranges = <1800 1800 3300 3300>; + sdhci,auto-cmd12; + big-endian; + bus-width = <4>; + status = "disabled"; + }; + + scfg: scfg@1570000 { + compatible = "fsl,ls1021a-scfg", "syscon"; + reg = <0x0 0x1570000 0x0 0x10000>; + big-endian; + }; + + clockgen: clocking@1ee1000 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x1ee1000 0x10000>; + + sysclk: sysclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "sysclk"; + }; + + cga_pll1: pll@800 { + compatible = "fsl,qoriq-core-pll-2.0"; + #clock-cells = <1>; + reg = <0x800 0x10>; + clocks = <&sysclk>; + clock-output-names = "cga-pll1", "cga-pll1-div2", + "cga-pll1-div4"; + }; + + platform_clk: pll@c00 { + compatible = "fsl,qoriq-core-pll-2.0"; + #clock-cells = <1>; + reg = <0xc00 0x10>; + clocks = <&sysclk>; + clock-output-names = "platform-clk", "platform-clk-div2"; + }; + + cluster1_clk: clk0c0@0 { + compatible = "fsl,qoriq-core-mux-2.0"; + #clock-cells = <0>; + reg = <0x0 0x10>; + clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4"; + clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>; + clock-output-names = "cluster1-clk"; + }; + }; + + dspi0: dspi@2100000 { + compatible = "fsl,vf610-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2100000 0x0 0x10000>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "dspi"; + clocks = <&platform_clk 1>; + spi-num-chipselects = <5>; + big-endian; + status = "disabled"; + }; + + dspi1: dspi@2110000 { + compatible = "fsl,vf610-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2110000 0x0 0x10000>; + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "dspi"; + clocks = <&platform_clk 1>; + spi-num-chipselects = <5>; + big-endian; + status = "disabled"; + }; + + i2c0: i2c@2180000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2180000 0x0 0x10000>; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "i2c"; + clocks = <&platform_clk 1>; + status = "disabled"; + }; + + i2c1: i2c@2190000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2190000 0x0 0x10000>; + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "i2c"; + clocks = <&platform_clk 1>; + status = "disabled"; + }; + + i2c2: i2c@21a0000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x21a0000 0x0 0x10000>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "i2c"; + clocks = <&platform_clk 1>; + status = "disabled"; + }; + + uart0: serial@21c0500 { + compatible = "fsl,16550-FIFO64", "ns16550a"; + reg = <0x0 0x21c0500 0x0 0x100>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <0>; + fifo-size = <15>; + status = "disabled"; + }; + + uart1: serial@21c0600 { + compatible = "fsl,16550-FIFO64", "ns16550a"; + reg = <0x0 0x21c0600 0x0 0x100>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <0>; + fifo-size = <15>; + status = "disabled"; + }; + + uart2: serial@21d0500 { + compatible = "fsl,16550-FIFO64", "ns16550a"; + reg = <0x0 0x21d0500 0x0 0x100>; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <0>; + fifo-size = <15>; + status = "disabled"; + }; + + uart3: serial@21d0600 { + compatible = "fsl,16550-FIFO64", "ns16550a"; + reg = <0x0 0x21d0600 0x0 0x100>; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <0>; + fifo-size = <15>; + status = "disabled"; + }; + + lpuart0: serial@2950000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2950000 0x0 0x1000>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sysclk>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart1: serial@2960000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2960000 0x0 0x1000>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&platform_clk 1>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart2: serial@2970000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2970000 0x0 0x1000>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&platform_clk 1>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart3: serial@2980000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2980000 0x0 0x1000>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&platform_clk 1>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart4: serial@2990000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2990000 0x0 0x1000>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&platform_clk 1>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart5: serial@29a0000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x29a0000 0x0 0x1000>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&platform_clk 1>; + clock-names = "ipg"; + status = "disabled"; + }; + + wdog0: watchdog@2ad0000 { + compatible = "fsl,imx21-wdt"; + reg = <0x0 0x2ad0000 0x0 0x10000>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&platform_clk 1>; + clock-names = "wdog-en"; + big-endian; + }; + + sai1: sai@2b50000 { + compatible = "fsl,vf610-sai"; + reg = <0x0 0x2b50000 0x0 0x10000>; + interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&platform_clk 1>; + clock-names = "sai"; + dma-names = "tx", "rx"; + dmas = <&edma0 1 47>, + <&edma0 1 46>; + big-endian; + status = "disabled"; + }; + + sai2: sai@2b60000 { + compatible = "fsl,vf610-sai"; + reg = <0x0 0x2b60000 0x0 0x10000>; + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&platform_clk 1>; + clock-names = "sai"; + dma-names = "tx", "rx"; + dmas = <&edma0 1 45>, + <&edma0 1 44>; + big-endian; + status = "disabled"; + }; + + edma0: edma@2c00000 { + #dma-cells = <2>; + compatible = "fsl,vf610-edma"; + reg = <0x0 0x2c00000 0x0 0x10000>, + <0x0 0x2c10000 0x0 0x10000>, + <0x0 0x2c20000 0x0 0x10000>; + interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma-tx", "edma-err"; + dma-channels = <32>; + big-endian; + clock-names = "dmamux0", "dmamux1"; + clocks = <&platform_clk 1>, + <&platform_clk 1>; + }; + + mdio0: mdio@2d24000 { + compatible = "gianfar"; + device_type = "mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2d24000 0x0 0x4000>; + }; + + usb@8600000 { + compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr"; + reg = <0x0 0x8600000 0x0 0x1000>; + interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; + dr_mode = "host"; + phy_type = "ulpi"; + }; + + usb3@3100000 { + compatible = "snps,dwc3"; + reg = <0x0 0x3100000 0x0 0x10000>; + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; + dr_mode = "host"; + }; + }; +}; -- 2.1.0.27.g96db324

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[U-Boot] [PATCH 1/5 v1] dm: arm: Bring in skeleton64 device tree file from Linux
by Haikun Wang 01 Apr '15

01 Apr '15

Backport of kernel commits: 7c14f6c719de092d69c81877786e83ce7ae1a860 35faad2a1563b3d4dc983a82ac41033fe053870c Signed-off-by: Haikun Wang <Haikun.Wang(a)freescale.com> --- arch/arm/dts/skeleton64.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 arch/arm/dts/skeleton64.dtsi diff --git a/arch/arm/dts/skeleton64.dtsi b/arch/arm/dts/skeleton64.dtsi new file mode 100644 index 0000000..b5d7f36 --- /dev/null +++ b/arch/arm/dts/skeleton64.dtsi @@ -0,0 +1,13 @@ +/* + * Skeleton device tree in the 64 bits version; the bare minimum + * needed to boot; just include and add a compatible value. The + * bootloader will typically populate the memory node. + */ + +/ { + #address-cells = <2>; + #size-cells = <2>; + chosen { }; + aliases { }; + memory { device_type = "memory"; reg = <0 0 0 0>; }; +}; -- 2.1.0.27.g96db324

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[U-Boot] [PATCH v2 0/17] dm: x86: Convert x86 to use driver model more fully
by Simon Glass 01 Apr '15

01 Apr '15

At present x86 does not use driver model for SPI or LPC (low-pin-count, a bus used to talk to the EC on Chromebooks). This series: - moves the ICH SPI driver over to driver model - moves the cros_ec LPC driver to driver model - removes non-driver-model cros_ec code (since now I2C, SPI and LPC are converted over) - makes some use of the PCI uclass for x86 init, by no means complete - fixes up the keyboard to work on chromebook_link (previously it would only work when started from coreboot) Changes in v2: - Support pre-driver-model too so we can rebase on dm/next - Adjust snow to move cros_ec from SPI to I2C - Add new patch to move CONFIG_CROS_EC_SANDBOX to Kconfig - Rebase to dm/next Simon Glass (17): dm: sf: Add driver model read/write/erase methods dm: x86: spi: Convert ICH SPI driver to driver model dm: x86: Add a uclass for a Platform Controller Hub dm: x86: Add a uclass for an Low Pin Count (LPC) device x86: chromebook_link: dts: Add PCH and LPC devices dm: cros_ec: Convert cros_ec LPC driver to driver model cros_ec: Reinit the cros_ec device when 'crosec init' is used cros_ec: Drop unused CONFIG_DM_CROS_EC sandbox: cros_ec: Drop unnecessary init x86: cros_ec: Drop unnecessary init exynos: cros_ec: Drop unnecessary init cros_ec: Remove unused cros_ec_board_init() function fdt: cros_ec: Drop compatible string in fdtdec fdt: Drop LPC compatible string in fdtdec cros_ec: exynos: Match up device tree with kernel version sandbox: cros_ec: Add Kconfig for sandbox EC config i8042: Add keyboard enable logic in kbd_reset() arch/arm/dts/exynos5250-snow.dts | 11 +- arch/arm/dts/exynos5420-peach-pit.dts | 5 +- arch/arm/dts/exynos5800-peach-pi.dts | 4 +- arch/sandbox/Kconfig | 3 - arch/sandbox/dts/cros-ec-keyboard.dtsi | 105 +++++ arch/sandbox/dts/sandbox.dts | 115 ++---- arch/x86/Kconfig | 6 + arch/x86/cpu/ivybridge/bd82x6x.c | 9 - arch/x86/cpu/ivybridge/cpu.c | 2 +- arch/x86/cpu/ivybridge/lpc.c | 13 +- arch/x86/cpu/ivybridge/mrccache.c | 7 +- arch/x86/cpu/ivybridge/sdram.c | 17 +- arch/x86/dts/chromebook_link.dts | 70 ++-- arch/x86/include/asm/arch-ivybridge/mrccache.h | 4 +- arch/x86/lib/Makefile | 2 + arch/x86/lib/init_helpers.c | 8 - arch/x86/lib/lpc-uclass.c | 28 ++ arch/x86/lib/pch-uclass.c | 28 ++ board/coreboot/coreboot/coreboot.c | 5 - board/google/chromebook_link/link.c | 3 - board/samsung/common/board.c | 12 - board/samsung/smdk5420/Kconfig | 6 - board/sandbox/sandbox.c | 12 - common/board_r.c | 3 - common/cros_ec.c | 33 -- configs/chromebook_link_defconfig | 1 + configs/sandbox_defconfig | 1 - configs/snow_defconfig | 1 - drivers/input/cros_ec_keyb.c | 2 +- drivers/input/i8042.c | 7 + drivers/misc/Kconfig | 19 +- drivers/misc/cros_ec.c | 250 +----------- drivers/misc/cros_ec_i2c.c | 4 +- drivers/misc/cros_ec_lpc.c | 29 +- drivers/misc/cros_ec_sandbox.c | 77 +--- drivers/misc/cros_ec_spi.c | 4 +- drivers/mtd/spi/sf-uclass.c | 16 + drivers/spi/ich.c | 519 +++++++++++++------------ include/configs/exynos5420-common.h | 2 - include/configs/sandbox.h | 1 - include/configs/smdk5250.h | 1 - include/configs/snow.h | 1 - include/configs/x86-common.h | 1 - include/cros_ec.h | 137 ------- include/dm/uclass-id.h | 1 + include/fdtdec.h | 4 +- include/spi_flash.h | 47 ++- lib/fdtdec.c | 4 +- 48 files changed, 661 insertions(+), 979 deletions(-) create mode 100644 arch/sandbox/dts/cros-ec-keyboard.dtsi create mode 100644 arch/x86/lib/lpc-uclass.c create mode 100644 arch/x86/lib/pch-uclass.c -- 2.2.0.rc0.207.ga3a616c

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[U-Boot] [PATCH v1] dm: spi: Convert Freescale QSPI driver to driver model
by Haikun Wang 01 Apr '15

01 Apr '15

Move the Freescale QSPI driver over to driver model. Signed-off-by: Haikun Wang <Haikun.Wang(a)freescale.com> Signed-off-by: Peng Fan <Peng.Fan(a)freescale.com> --- This patch adds DM support for FSL QSPI driver. Now this driver can support both DM frame and old SPI frame. Driver structure like below: QSPI driver common code #ifndef CONFIG_DM_SPI Old SPI frame interface #else DM SPI frame interface #endif changes in v1: None drivers/spi/fsl_qspi.c | 970 ++++++++++++++++++++++++++++++++----------------- 1 file changed, 645 insertions(+), 325 deletions(-) diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index 5e0b069..1429295 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -11,8 +11,12 @@ #include <spi.h> #include <asm/io.h> #include <linux/sizes.h> +#include <dm.h> +#include <errno.h> #include "fsl_qspi.h" +DECLARE_GLOBAL_DATA_PTR; + #define RX_BUFFER_SIZE 0x80 #ifdef CONFIG_MX6SX #define TX_BUFFER_SIZE 0x200 @@ -63,35 +67,85 @@ #define QSPI_CMD_PP_4B 0x12 /* Page program (up to 256 bytes) */ #define QSPI_CMD_SE_4B 0xdc /* Sector erase (usually 64KiB) */ -#ifdef CONFIG_SYS_FSL_QSPI_LE -#define qspi_read32 in_le32 -#define qspi_write32 out_le32 -#elif defined(CONFIG_SYS_FSL_QSPI_BE) -#define qspi_read32 in_be32 -#define qspi_write32 out_be32 -#endif +/* fsl_qspi_platdata flags */ +#define QSPI_FLAG_REGMAP_ENDIAN_BIG (1 << 0) -static unsigned long spi_bases[] = { - QSPI0_BASE_ADDR, -#ifdef CONFIG_MX6SX - QSPI1_BASE_ADDR, -#endif -}; +/* default SCK frequency, unit: HZ */ +#define FSL_QSPI_DEFAULT_SCK_FREQ 50000000 -static unsigned long amba_bases[] = { - QSPI0_AMBA_BASE, -#ifdef CONFIG_MX6SX - QSPI1_AMBA_BASE, +/* QSPI max chipselect signals number */ +#define FSL_QSPI_MAX_CHIPSELECT_NUM 4 + +#ifdef CONFIG_DM_SPI +/** + * struct fsl_qspi_platdata - platform data for Freescale QSPI + * + * @flags: Flags for QSPI QSPI_FLAG_... + * @speed_hz: Default SCK frequency + * @reg_base: Base address of QSPI registers + * @amba_base: Base address of QSPI memory mapping + * @amba_total_size: size of QSPI memory mapping + * @flash_num: Number of active slave devices + * @num_chipselect: Number of QSPI chipselect signals + */ +struct fsl_qspi_platdata { + u32 flags; + u32 speed_hz; + u32 reg_base; + u32 amba_base; + u32 amba_total_size; + u32 flash_num; + u32 num_chipselect; +}; #endif + +/** + * struct fsl_qspi_priv - private data for Freescale QSPI + * + * @flags: Flags for QSPI QSPI_FLAG_... + * @bus_clk: QSPI input clk frequency + * @speed_hz: Default SCK frequency + * @cur_seqid: current LUT table sequence id + * @sf_addr: flash access offset + * @amba_base: Base address of QSPI memory mapping of every CS + * @amba_total_size: size of QSPI memory mapping + * @cur_amba_base: Base address of QSPI memory mapping of current CS + * @flash_num: Number of active slave devices + * @num_chipselect: Number of QSPI chipselect signals + * @regs: Point to QSPI register structure for I/O access + */ +struct fsl_qspi_priv { + u32 flags; + u32 bus_clk; + u32 speed_hz; + u32 cur_seqid; + u32 sf_addr; + u32 amba_base[FSL_QSPI_MAX_CHIPSELECT_NUM]; + u32 amba_total_size; + u32 cur_amba_base; + u32 flash_num; + u32 num_chipselect; + struct fsl_qspi_regs *regs; }; +#ifndef CONFIG_DM_SPI struct fsl_qspi { struct spi_slave slave; - unsigned long reg_base; - unsigned long amba_base; - u32 sf_addr; - u8 cur_seqid; + struct fsl_qspi_priv priv; }; +#endif + +static u32 qspi_read32(u32 flags, u32 *addr) +{ + return flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ? + in_be32(addr) : in_le32(addr); +} + +static void qspi_write32(u32 flags, u32 *addr, u32 val) +{ + flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ? + out_be32(addr, val) : out_le32(addr, val); +} /* QSPI support swapping the flash read/write data * in hardware for LS102xA, but not for VF610 */ @@ -104,131 +158,135 @@ static inline u32 qspi_endian_xchg(u32 data) #endif } -static inline struct fsl_qspi *to_qspi_spi(struct spi_slave *slave) -{ - return container_of(slave, struct fsl_qspi, slave); -} - -static void qspi_set_lut(struct fsl_qspi *qspi) +static void qspi_set_lut(struct fsl_qspi_priv *priv) { - struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base; + struct fsl_qspi_regs *regs = priv->regs; u32 lut_base; /* Unlock the LUT */ - qspi_write32(&regs->lutkey, LUT_KEY_VALUE); - qspi_write32(&regs->lckcr, QSPI_LCKCR_UNLOCK); + qspi_write32(priv->flags, &regs->lutkey, LUT_KEY_VALUE); + qspi_write32(priv->flags, &regs->lckcr, QSPI_LCKCR_UNLOCK); /* Write Enable */ lut_base = SEQID_WREN * 4; - qspi_write32(&regs->lut[lut_base], OPRND0(QSPI_CMD_WREN) | + qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_WREN) | PAD0(LUT_PAD1) | INSTR0(LUT_CMD)); - qspi_write32(&regs->lut[lut_base + 1], 0); - qspi_write32(&regs->lut[lut_base + 2], 0); - qspi_write32(&regs->lut[lut_base + 3], 0); + qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0); + qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0); + qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0); /* Fast Read */ lut_base = SEQID_FAST_READ * 4; #ifdef CONFIG_SPI_FLASH_BAR - qspi_write32(&regs->lut[lut_base], OPRND0(QSPI_CMD_FAST_READ) | - PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | + qspi_write32(priv->flags, &regs->lut[lut_base], + OPRND0(QSPI_CMD_FAST_READ) | PAD0(LUT_PAD1) | + INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); #else if (FSL_QSPI_FLASH_SIZE <= SZ_16M) - qspi_write32(&regs->lut[lut_base], OPRND0(QSPI_CMD_FAST_READ) | - PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | - PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); + qspi_write32(priv->flags, &regs->lut[lut_base], + OPRND0(QSPI_CMD_FAST_READ) | PAD0(LUT_PAD1) | + INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | + PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); else - qspi_write32(&regs->lut[lut_base], + qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_FAST_READ_4B) | PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) | PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); #endif - qspi_write32(&regs->lut[lut_base + 1], OPRND0(8) | PAD0(LUT_PAD1) | - INSTR0(LUT_DUMMY) | OPRND1(RX_BUFFER_SIZE) | PAD1(LUT_PAD1) | - INSTR1(LUT_READ)); - qspi_write32(&regs->lut[lut_base + 2], 0); - qspi_write32(&regs->lut[lut_base + 3], 0); + qspi_write32(priv->flags, &regs->lut[lut_base + 1], + OPRND0(8) | PAD0(LUT_PAD1) | INSTR0(LUT_DUMMY) | + OPRND1(RX_BUFFER_SIZE) | PAD1(LUT_PAD1) | + INSTR1(LUT_READ)); + qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0); + qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0); /* Read Status */ lut_base = SEQID_RDSR * 4; - qspi_write32(&regs->lut[lut_base], OPRND0(QSPI_CMD_RDSR) | + qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDSR) | PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) | PAD1(LUT_PAD1) | INSTR1(LUT_READ)); - qspi_write32(&regs->lut[lut_base + 1], 0); - qspi_write32(&regs->lut[lut_base + 2], 0); - qspi_write32(&regs->lut[lut_base + 3], 0); + qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0); + qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0); + qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0); /* Erase a sector */ lut_base = SEQID_SE * 4; #ifdef CONFIG_SPI_FLASH_BAR - qspi_write32(&regs->lut[lut_base], OPRND0(QSPI_CMD_SE) | + qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_SE) | PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); #else if (FSL_QSPI_FLASH_SIZE <= SZ_16M) - qspi_write32(&regs->lut[lut_base], OPRND0(QSPI_CMD_SE) | - PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | - PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); + qspi_write32(priv->flags, &regs->lut[lut_base], + OPRND0(QSPI_CMD_SE) | PAD0(LUT_PAD1) | + INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | + PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); else - qspi_write32(&regs->lut[lut_base], OPRND0(QSPI_CMD_SE_4B) | - PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) | - PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); + qspi_write32(priv->flags, &regs->lut[lut_base], + OPRND0(QSPI_CMD_SE_4B) | PAD0(LUT_PAD1) | + INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) | + PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); #endif - qspi_write32(&regs->lut[lut_base + 1], 0); - qspi_write32(&regs->lut[lut_base + 2], 0); - qspi_write32(&regs->lut[lut_base + 3], 0); + qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0); + qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0); + qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0); /* Erase the whole chip */ lut_base = SEQID_CHIP_ERASE * 4; - qspi_write32(&regs->lut[lut_base], OPRND0(QSPI_CMD_CHIP_ERASE) | - PAD0(LUT_PAD1) | INSTR0(LUT_CMD)); - qspi_write32(&regs->lut[lut_base + 1], 0); - qspi_write32(&regs->lut[lut_base + 2], 0); - qspi_write32(&regs->lut[lut_base + 3], 0); + qspi_write32(priv->flags, &regs->lut[lut_base], + OPRND0(QSPI_CMD_CHIP_ERASE) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD)); + qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0); + qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0); + qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0); /* Page Program */ lut_base = SEQID_PP * 4; #ifdef CONFIG_SPI_FLASH_BAR - qspi_write32(&regs->lut[lut_base], OPRND0(QSPI_CMD_PP) | + qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_PP) | PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); #else if (FSL_QSPI_FLASH_SIZE <= SZ_16M) - qspi_write32(&regs->lut[lut_base], OPRND0(QSPI_CMD_PP) | - PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | - PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); + qspi_write32(priv->flags, &regs->lut[lut_base], + OPRND0(QSPI_CMD_PP) | PAD0(LUT_PAD1) | + INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | + PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); else - qspi_write32(&regs->lut[lut_base], OPRND0(QSPI_CMD_PP_4B) | - PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) | - PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); + qspi_write32(priv->flags, &regs->lut[lut_base], + OPRND0(QSPI_CMD_PP_4B) | PAD0(LUT_PAD1) | + INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) | + PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); #endif #ifdef CONFIG_MX6SX /* * To MX6SX, OPRND0(TX_BUFFER_SIZE) can not work correctly. * So, Use IDATSZ in IPCR to determine the size and here set 0. */ - qspi_write32(&regs->lut[lut_base + 1], OPRND0(0) | + qspi_write32(priv->flags, &regs->lut[lut_base + 1], OPRND0(0) | PAD0(LUT_PAD1) | INSTR0(LUT_WRITE)); #else - qspi_write32(&regs->lut[lut_base + 1], OPRND0(TX_BUFFER_SIZE) | - PAD0(LUT_PAD1) | INSTR0(LUT_WRITE)); + qspi_write32(priv->flags, &regs->lut[lut_base + 1], + OPRND0(TX_BUFFER_SIZE) | + PAD0(LUT_PAD1) | INSTR0(LUT_WRITE)); #endif - qspi_write32(&regs->lut[lut_base + 2], 0); - qspi_write32(&regs->lut[lut_base + 3], 0); + qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0); + qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0); /* READ ID */ lut_base = SEQID_RDID * 4; - qspi_write32(&regs->lut[lut_base], OPRND0(QSPI_CMD_RDID) | + qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDID) | PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(8) | PAD1(LUT_PAD1) | INSTR1(LUT_READ)); - qspi_write32(&regs->lut[lut_base + 1], 0); - qspi_write32(&regs->lut[lut_base + 2], 0); - qspi_write32(&regs->lut[lut_base + 3], 0); + qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0); + qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0); + qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0); /* SUB SECTOR 4K ERASE */ lut_base = SEQID_BE_4K * 4; - qspi_write32(&regs->lut[lut_base], OPRND0(QSPI_CMD_BE_4K) | + qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BE_4K) | PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); @@ -239,28 +297,28 @@ static void qspi_set_lut(struct fsl_qspi *qspi) * initialization. */ lut_base = SEQID_BRRD * 4; - qspi_write32(&regs->lut[lut_base], OPRND0(QSPI_CMD_BRRD) | + qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BRRD) | PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) | PAD1(LUT_PAD1) | INSTR1(LUT_READ)); lut_base = SEQID_BRWR * 4; - qspi_write32(&regs->lut[lut_base], OPRND0(QSPI_CMD_BRWR) | + qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BRWR) | PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) | PAD1(LUT_PAD1) | INSTR1(LUT_WRITE)); lut_base = SEQID_RDEAR * 4; - qspi_write32(&regs->lut[lut_base], OPRND0(QSPI_CMD_RDEAR) | + qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDEAR) | PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) | PAD1(LUT_PAD1) | INSTR1(LUT_READ)); lut_base = SEQID_WREAR * 4; - qspi_write32(&regs->lut[lut_base], OPRND0(QSPI_CMD_WREAR) | + qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_WREAR) | PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) | PAD1(LUT_PAD1) | INSTR1(LUT_WRITE)); #endif /* Lock the LUT */ - qspi_write32(&regs->lutkey, LUT_KEY_VALUE); - qspi_write32(&regs->lckcr, QSPI_LCKCR_LOCK); + qspi_write32(priv->flags, &regs->lutkey, LUT_KEY_VALUE); + qspi_write32(priv->flags, &regs->lckcr, QSPI_LCKCR_LOCK); } #if defined(CONFIG_SYS_FSL_QSPI_AHB) @@ -270,14 +328,14 @@ static void qspi_set_lut(struct fsl_qspi *qspi) * the wrong data. The spec tells us reset the AHB domain and Serial Flash * domain at the same time. */ -static inline void qspi_ahb_invalid(struct fsl_qspi *q) +static inline void qspi_ahb_invalid(struct fsl_qspi_priv *priv) { - struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)q->reg_base; + struct fsl_qspi_regs *regs = priv->regs; u32 reg; - reg = qspi_read32(&regs->mcr); + reg = qspi_read32(priv->flags, &regs->mcr); reg |= QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK; - qspi_write32(&regs->mcr, reg); + qspi_write32(priv->flags, &regs->mcr, reg); /* * The minimum delay : 1 AHB + 2 SFCK clocks. @@ -286,46 +344,47 @@ static inline void qspi_ahb_invalid(struct fsl_qspi *q) udelay(1); reg &= ~(QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK); - qspi_write32(&regs->mcr, reg); + qspi_write32(priv->flags, &regs->mcr, reg); } /* Read out the data from the AHB buffer. */ -static inline void qspi_ahb_read(struct fsl_qspi *q, u8 *rxbuf, int len) +static inline void qspi_ahb_read(struct fsl_qspi_priv *priv, u8 *rxbuf, int len) { - struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)q->reg_base; + struct fsl_qspi_regs *regs = priv->regs; u32 mcr_reg; - mcr_reg = qspi_read32(&regs->mcr); + mcr_reg = qspi_read32(priv->flags, &regs->mcr); - qspi_write32(&regs->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | + qspi_write32(priv->flags, &regs->mcr, + QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); /* Read out the data directly from the AHB buffer. */ - memcpy(rxbuf, (u8 *)(q->amba_base + q->sf_addr), len); + memcpy(rxbuf, (u8 *)(priv->cur_amba_base + priv->sf_addr), len); - qspi_write32(&regs->mcr, mcr_reg); + qspi_write32(priv->flags, &regs->mcr, mcr_reg); } static void qspi_enable_ddr_mode(struct fsl_qspi_regs *regs) { u32 reg, reg2; - reg = qspi_read32(&regs->mcr); + reg = qspi_read32(priv->flags, &regs->mcr); /* Disable the module */ - qspi_write32(&regs->mcr, reg | QSPI_MCR_MDIS_MASK); + qspi_write32(priv->flags, &regs->mcr, reg | QSPI_MCR_MDIS_MASK); /* Set the Sampling Register for DDR */ - reg2 = qspi_read32(&regs->smpr); + reg2 = qspi_read32(priv->flags, &regs->smpr); reg2 &= ~QSPI_SMPR_DDRSMP_MASK; reg2 |= (2 << QSPI_SMPR_DDRSMP_SHIFT); - qspi_write32(&regs->smpr, reg2); + qspi_write32(priv->flags, &regs->smpr, reg2); /* Enable the module again (enable the DDR too) */ reg |= QSPI_MCR_DDR_EN_MASK; /* Enable bit 29 for imx6sx */ reg |= (1 << 29); - qspi_write32(&regs->mcr, reg); + qspi_write32(priv->flags, &regs->mcr, reg); } /* @@ -344,22 +403,22 @@ static void qspi_enable_ddr_mode(struct fsl_qspi_regs *regs) static void qspi_init_ahb_read(struct fsl_qspi_regs *regs) { /* AHB configuration for access buffer 0/1/2 .*/ - qspi_write32(&regs->buf0cr, QSPI_BUFXCR_INVALID_MSTRID); - qspi_write32(&regs->buf1cr, QSPI_BUFXCR_INVALID_MSTRID); - qspi_write32(&regs->buf2cr, QSPI_BUFXCR_INVALID_MSTRID); - qspi_write32(&regs->buf3cr, QSPI_BUF3CR_ALLMST_MASK | + qspi_write32(priv->flags, &regs->buf0cr, QSPI_BUFXCR_INVALID_MSTRID); + qspi_write32(priv->flags, &regs->buf1cr, QSPI_BUFXCR_INVALID_MSTRID); + qspi_write32(priv->flags, &regs->buf2cr, QSPI_BUFXCR_INVALID_MSTRID); + qspi_write32(priv->flags, &regs->buf3cr, QSPI_BUF3CR_ALLMST_MASK | (0x80 << QSPI_BUF3CR_ADATSZ_SHIFT)); /* We only use the buffer3 */ - qspi_write32(&regs->buf0ind, 0); - qspi_write32(&regs->buf1ind, 0); - qspi_write32(&regs->buf2ind, 0); + qspi_write32(priv->flags, &regs->buf0ind, 0); + qspi_write32(priv->flags, &regs->buf1ind, 0); + qspi_write32(priv->flags, &regs->buf2ind, 0); /* * Set the default lut sequence for AHB Read. * Parallel mode is disabled. */ - qspi_write32(&regs->bfgencr, + qspi_write32(priv->flags, &regs->bfgencr, SEQID_FAST_READ << QSPI_BFGENCR_SEQID_SHIFT); /*Enable DDR Mode*/ @@ -367,154 +426,75 @@ static void qspi_init_ahb_read(struct fsl_qspi_regs *regs) } #endif -void spi_init() -{ - /* do nothing */ -} - -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) -{ - struct fsl_qspi *qspi; - struct fsl_qspi_regs *regs; - u32 smpr_val; - u32 total_size; - - if (bus >= ARRAY_SIZE(spi_bases)) - return NULL; - - if (cs >= FSL_QSPI_FLASH_NUM) - return NULL; - - qspi = spi_alloc_slave(struct fsl_qspi, bus, cs); - if (!qspi) - return NULL; - - qspi->reg_base = spi_bases[bus]; - /* - * According cs, use different amba_base to choose the - * corresponding flash devices. - * - * If not, only one flash device is used even if passing - * different cs using `sf probe` - */ - qspi->amba_base = amba_bases[bus] + cs * FSL_QSPI_FLASH_SIZE; - - qspi->slave.max_write_size = TX_BUFFER_SIZE; - - regs = (struct fsl_qspi_regs *)qspi->reg_base; - qspi_write32(&regs->mcr, QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK); - - smpr_val = qspi_read32(&regs->smpr); - qspi_write32(&regs->smpr, smpr_val & ~(QSPI_SMPR_FSDLY_MASK | - QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK)); - qspi_write32(&regs->mcr, QSPI_MCR_RESERVED_MASK); - - total_size = FSL_QSPI_FLASH_SIZE * FSL_QSPI_FLASH_NUM; - /* - * Any read access to non-implemented addresses will provide - * undefined results. - * - * In case single die flash devices, TOP_ADDR_MEMA2 and - * TOP_ADDR_MEMB2 should be initialized/programmed to - * TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1 respectively - in effect, - * setting the size of these devices to 0. This would ensure - * that the complete memory map is assigned to only one flash device. - */ - qspi_write32(&regs->sfa1ad, FSL_QSPI_FLASH_SIZE | amba_bases[bus]); - qspi_write32(&regs->sfa2ad, FSL_QSPI_FLASH_SIZE | amba_bases[bus]); - qspi_write32(&regs->sfb1ad, total_size | amba_bases[bus]); - qspi_write32(&regs->sfb2ad, total_size | amba_bases[bus]); - - qspi_set_lut(qspi); - - smpr_val = qspi_read32(&regs->smpr); - smpr_val &= ~QSPI_SMPR_DDRSMP_MASK; - qspi_write32(&regs->smpr, smpr_val); - qspi_write32(&regs->mcr, QSPI_MCR_RESERVED_MASK); - -#ifdef CONFIG_SYS_FSL_QSPI_AHB - qspi_init_ahb_read(regs); -#endif - return &qspi->slave; -} - -void spi_free_slave(struct spi_slave *slave) -{ - struct fsl_qspi *qspi = to_qspi_spi(slave); - - free(qspi); -} - -int spi_claim_bus(struct spi_slave *slave) -{ - return 0; -} - #ifdef CONFIG_SPI_FLASH_BAR /* Bank register read/write, EAR register read/write */ -static void qspi_op_rdbank(struct fsl_qspi *qspi, u8 *rxbuf, u32 len) +static void qspi_op_rdbank(struct fsl_qspi_priv *priv, u8 *rxbuf, u32 len) { - struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base; + struct fsl_qspi_regs *regs = priv->regs; u32 reg, mcr_reg, data, seqid; - mcr_reg = qspi_read32(&regs->mcr); - qspi_write32(&regs->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | + mcr_reg = qspi_read32(priv->flags, &regs->mcr); + qspi_write32(priv->flags, &regs->mcr, + QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); - qspi_write32(&regs->rbct, QSPI_RBCT_RXBRD_USEIPS); + qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS); - qspi_write32(&regs->sfar, qspi->amba_base); + qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base); - if (qspi->cur_seqid == QSPI_CMD_BRRD) + if (priv->cur_seqid == QSPI_CMD_BRRD) seqid = SEQID_BRRD; else seqid = SEQID_RDEAR; - qspi_write32(&regs->ipcr, (seqid << QSPI_IPCR_SEQID_SHIFT) | len); + qspi_write32(priv->flags, &regs->ipcr, + (seqid << QSPI_IPCR_SEQID_SHIFT) | len); /* Wait previous command complete */ - while (qspi_read32(&regs->sr) & QSPI_SR_BUSY_MASK) + while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK) ; while (1) { - reg = qspi_read32(&regs->rbsr); + reg = qspi_read32(priv->flags, &regs->rbsr); if (reg & QSPI_RBSR_RDBFL_MASK) { - data = qspi_read32(&regs->rbdr[0]); + data = qspi_read32(priv->flags, &regs->rbdr[0]); data = qspi_endian_xchg(data); memcpy(rxbuf, &data, len); - qspi_write32(&regs->mcr, qspi_read32(&regs->mcr) | + qspi_write32(priv->flags, &regs->mcr, + qspi_read32(priv->flags, &regs->mcr) | QSPI_MCR_CLR_RXF_MASK); break; } } - qspi_write32(&regs->mcr, mcr_reg); + qspi_write32(priv->flags, &regs->mcr, mcr_reg); } #endif -static void qspi_op_rdid(struct fsl_qspi *qspi, u32 *rxbuf, u32 len) +static void qspi_op_rdid(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len) { - struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base; + struct fsl_qspi_regs *regs = priv->regs; u32 mcr_reg, rbsr_reg, data; int i, size; - mcr_reg = qspi_read32(&regs->mcr); - qspi_write32(&regs->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | - QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); - qspi_write32(&regs->rbct, QSPI_RBCT_RXBRD_USEIPS); + mcr_reg = qspi_read32(priv->flags, &regs->mcr); + qspi_write32(priv->flags, &regs->mcr, + QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | + QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); + qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS); - qspi_write32(&regs->sfar, qspi->amba_base); + qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base); - qspi_write32(&regs->ipcr, (SEQID_RDID << QSPI_IPCR_SEQID_SHIFT) | 0); - while (qspi_read32(&regs->sr) & QSPI_SR_BUSY_MASK) + qspi_write32(priv->flags, &regs->ipcr, + (SEQID_RDID << QSPI_IPCR_SEQID_SHIFT) | 0); + while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK) ; i = 0; size = len; while ((RX_BUFFER_SIZE >= size) && (size > 0)) { - rbsr_reg = qspi_read32(&regs->rbsr); + rbsr_reg = qspi_read32(priv->flags, &regs->rbsr); if (rbsr_reg & QSPI_RBSR_RDBFL_MASK) { - data = qspi_read32(&regs->rbdr[i]); + data = qspi_read32(priv->flags, &regs->rbdr[i]); data = qspi_endian_xchg(data); memcpy(rxbuf, &data, 4); rxbuf++; @@ -523,34 +503,36 @@ static void qspi_op_rdid(struct fsl_qspi *qspi, u32 *rxbuf, u32 len) } } - qspi_write32(&regs->mcr, mcr_reg); + qspi_write32(priv->flags, &regs->mcr, mcr_reg); } #ifndef CONFIG_SYS_FSL_QSPI_AHB /* If not use AHB read, read data from ip interface */ -static void qspi_op_read(struct fsl_qspi *qspi, u32 *rxbuf, u32 len) +static void qspi_op_read(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len) { - struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base; + struct fsl_qspi_regs *regs = priv->regs; u32 mcr_reg, data; int i, size; u32 to_or_from; - mcr_reg = qspi_read32(&regs->mcr); - qspi_write32(&regs->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | - QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); - qspi_write32(&regs->rbct, QSPI_RBCT_RXBRD_USEIPS); + mcr_reg = qspi_read32(priv->flags, &regs->mcr); + qspi_write32(priv->flags, &regs->mcr, + QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | + QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); + qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS); - to_or_from = qspi->sf_addr + qspi->amba_base; + to_or_from = priv->sf_addr + priv->cur_amba_base; while (len > 0) { - qspi_write32(&regs->sfar, to_or_from); + qspi_write32(priv->flags, &regs->sfar, to_or_from); size = (len > RX_BUFFER_SIZE) ? RX_BUFFER_SIZE : len; - qspi_write32(&regs->ipcr, - (SEQID_FAST_READ << QSPI_IPCR_SEQID_SHIFT) | size); - while (qspi_read32(&regs->sr) & QSPI_SR_BUSY_MASK) + qspi_write32(priv->flags, &regs->ipcr, + (SEQID_FAST_READ << QSPI_IPCR_SEQID_SHIFT) | + size); + while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK) ; to_or_from += size; @@ -558,66 +540,69 @@ static void qspi_op_read(struct fsl_qspi *qspi, u32 *rxbuf, u32 len) i = 0; while ((RX_BUFFER_SIZE >= size) && (size > 0)) { - data = qspi_read32(&regs->rbdr[i]); + data = qspi_read32(priv->flags, &regs->rbdr[i]); data = qspi_endian_xchg(data); memcpy(rxbuf, &data, 4); rxbuf++; size -= 4; i++; } - qspi_write32(&regs->mcr, qspi_read32(&regs->mcr) | - QSPI_MCR_CLR_RXF_MASK); + qspi_write32(priv->flags, &regs->mcr, + qspi_read32(priv->flags, &regs->mcr) | + QSPI_MCR_CLR_RXF_MASK); } - qspi_write32(&regs->mcr, mcr_reg); + qspi_write32(priv->flags, &regs->mcr, mcr_reg); } #endif -static void qspi_op_write(struct fsl_qspi *qspi, u8 *txbuf, u32 len) +static void qspi_op_write(struct fsl_qspi_priv *priv, u8 *txbuf, u32 len) { - struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base; + struct fsl_qspi_regs *regs = priv->regs; u32 mcr_reg, data, reg, status_reg, seqid; int i, size, tx_size; u32 to_or_from = 0; - mcr_reg = qspi_read32(&regs->mcr); - qspi_write32(&regs->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | - QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); - qspi_write32(&regs->rbct, QSPI_RBCT_RXBRD_USEIPS); + mcr_reg = qspi_read32(priv->flags, &regs->mcr); + qspi_write32(priv->flags, &regs->mcr, + QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | + QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); + qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS); status_reg = 0; while ((status_reg & FLASH_STATUS_WEL) != FLASH_STATUS_WEL) { - qspi_write32(&regs->ipcr, - (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0); - while (qspi_read32(&regs->sr) & QSPI_SR_BUSY_MASK) + qspi_write32(priv->flags, &regs->ipcr, + (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0); + while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK) ; - qspi_write32(&regs->ipcr, - (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 1); - while (qspi_read32(&regs->sr) & QSPI_SR_BUSY_MASK) + qspi_write32(priv->flags, &regs->ipcr, + (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 1); + while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK) ; - reg = qspi_read32(&regs->rbsr); + reg = qspi_read32(priv->flags, &regs->rbsr); if (reg & QSPI_RBSR_RDBFL_MASK) { - status_reg = qspi_read32(&regs->rbdr[0]); + status_reg = qspi_read32(priv->flags, &regs->rbdr[0]); status_reg = qspi_endian_xchg(status_reg); } - qspi_write32(&regs->mcr, - qspi_read32(&regs->mcr) | QSPI_MCR_CLR_RXF_MASK); + qspi_write32(priv->flags, &regs->mcr, + qspi_read32(priv->flags, &regs->mcr) | + QSPI_MCR_CLR_RXF_MASK); } /* Default is page programming */ seqid = SEQID_PP; #ifdef CONFIG_SPI_FLASH_BAR - if (qspi->cur_seqid == QSPI_CMD_BRWR) + if (priv->cur_seqid == QSPI_CMD_BRWR) seqid = SEQID_BRWR; - else if (qspi->cur_seqid == QSPI_CMD_WREAR) + else if (priv->cur_seqid == QSPI_CMD_WREAR) seqid = SEQID_WREAR; #endif - to_or_from = qspi->sf_addr + qspi->amba_base; + to_or_from = priv->sf_addr + priv->cur_amba_base; - qspi_write32(&regs->sfar, to_or_from); + qspi_write32(priv->flags, &regs->sfar, to_or_from); tx_size = (len > TX_BUFFER_SIZE) ? TX_BUFFER_SIZE : len; @@ -626,7 +611,7 @@ static void qspi_op_write(struct fsl_qspi *qspi, u8 *txbuf, u32 len) for (i = 0; i < size; i++) { memcpy(&data, txbuf, 4); data = qspi_endian_xchg(data); - qspi_write32(&regs->tbdr, data); + qspi_write32(priv->flags, &regs->tbdr, data); txbuf += 4; } @@ -635,150 +620,485 @@ static void qspi_op_write(struct fsl_qspi *qspi, u8 *txbuf, u32 len) data = 0; memcpy(&data, txbuf, size); data = qspi_endian_xchg(data); - qspi_write32(&regs->tbdr, data); + qspi_write32(priv->flags, &regs->tbdr, data); } - qspi_write32(&regs->ipcr, (seqid << QSPI_IPCR_SEQID_SHIFT) | tx_size); - while (qspi_read32(&regs->sr) & QSPI_SR_BUSY_MASK) + qspi_write32(priv->flags, &regs->ipcr, + (seqid << QSPI_IPCR_SEQID_SHIFT) | tx_size); + while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK) ; - qspi_write32(&regs->mcr, mcr_reg); + qspi_write32(priv->flags, &regs->mcr, mcr_reg); } -static void qspi_op_rdsr(struct fsl_qspi *qspi, u32 *rxbuf) +static void qspi_op_rdsr(struct fsl_qspi_priv *priv, u32 *rxbuf) { - struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base; + struct fsl_qspi_regs *regs = priv->regs; u32 mcr_reg, reg, data; - mcr_reg = qspi_read32(&regs->mcr); - qspi_write32(&regs->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | - QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); - qspi_write32(&regs->rbct, QSPI_RBCT_RXBRD_USEIPS); + mcr_reg = qspi_read32(priv->flags, &regs->mcr); + qspi_write32(priv->flags, &regs->mcr, + QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | + QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); + qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS); - qspi_write32(&regs->sfar, qspi->amba_base); + qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base); - qspi_write32(&regs->ipcr, - (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 0); - while (qspi_read32(&regs->sr) & QSPI_SR_BUSY_MASK) + qspi_write32(priv->flags, &regs->ipcr, + (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 0); + while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK) ; while (1) { - reg = qspi_read32(&regs->rbsr); + reg = qspi_read32(priv->flags, &regs->rbsr); if (reg & QSPI_RBSR_RDBFL_MASK) { - data = qspi_read32(&regs->rbdr[0]); + data = qspi_read32(priv->flags, &regs->rbdr[0]); data = qspi_endian_xchg(data); memcpy(rxbuf, &data, 4); - qspi_write32(&regs->mcr, qspi_read32(&regs->mcr) | - QSPI_MCR_CLR_RXF_MASK); + qspi_write32(priv->flags, &regs->mcr, + qspi_read32(priv->flags, &regs->mcr) | + QSPI_MCR_CLR_RXF_MASK); break; } } - qspi_write32(&regs->mcr, mcr_reg); + qspi_write32(priv->flags, &regs->mcr, mcr_reg); } -static void qspi_op_erase(struct fsl_qspi *qspi) +static void qspi_op_erase(struct fsl_qspi_priv *priv) { - struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base; + struct fsl_qspi_regs *regs = priv->regs; u32 mcr_reg; u32 to_or_from = 0; - mcr_reg = qspi_read32(&regs->mcr); - qspi_write32(&regs->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | - QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); - qspi_write32(&regs->rbct, QSPI_RBCT_RXBRD_USEIPS); + mcr_reg = qspi_read32(priv->flags, &regs->mcr); + qspi_write32(priv->flags, &regs->mcr, + QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | + QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); + qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS); - to_or_from = qspi->sf_addr + qspi->amba_base; - qspi_write32(&regs->sfar, to_or_from); + to_or_from = priv->sf_addr + priv->cur_amba_base; + qspi_write32(priv->flags, &regs->sfar, to_or_from); - qspi_write32(&regs->ipcr, - (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0); - while (qspi_read32(&regs->sr) & QSPI_SR_BUSY_MASK) + qspi_write32(priv->flags, &regs->ipcr, + (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0); + while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK) ; - if (qspi->cur_seqid == QSPI_CMD_SE) { - qspi_write32(&regs->ipcr, + if (priv->cur_seqid == QSPI_CMD_SE) { + qspi_write32(priv->flags, &regs->ipcr, (SEQID_SE << QSPI_IPCR_SEQID_SHIFT) | 0); - } else if (qspi->cur_seqid == QSPI_CMD_BE_4K) { - qspi_write32(&regs->ipcr, + } else if (priv->cur_seqid == QSPI_CMD_BE_4K) { + qspi_write32(priv->flags, &regs->ipcr, (SEQID_BE_4K << QSPI_IPCR_SEQID_SHIFT) | 0); } - while (qspi_read32(&regs->sr) & QSPI_SR_BUSY_MASK) + while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK) ; - qspi_write32(&regs->mcr, mcr_reg); + qspi_write32(priv->flags, &regs->mcr, mcr_reg); } -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, +int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen, const void *dout, void *din, unsigned long flags) { - struct fsl_qspi *qspi = to_qspi_spi(slave); u32 bytes = DIV_ROUND_UP(bitlen, 8); static u32 wr_sfaddr; u32 txbuf; if (dout) { if (flags & SPI_XFER_BEGIN) { - qspi->cur_seqid = *(u8 *)dout; + priv->cur_seqid = *(u8 *)dout; memcpy(&txbuf, dout, 4); } if (flags == SPI_XFER_END) { - qspi->sf_addr = wr_sfaddr; - qspi_op_write(qspi, (u8 *)dout, bytes); + priv->sf_addr = wr_sfaddr; + qspi_op_write(priv, (u8 *)dout, bytes); return 0; } - if (qspi->cur_seqid == QSPI_CMD_FAST_READ) { - qspi->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK; - } else if ((qspi->cur_seqid == QSPI_CMD_SE) || - (qspi->cur_seqid == QSPI_CMD_BE_4K)) { - qspi->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK; - qspi_op_erase(qspi); - } else if (qspi->cur_seqid == QSPI_CMD_PP) + if (priv->cur_seqid == QSPI_CMD_FAST_READ) { + priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK; + } else if ((priv->cur_seqid == QSPI_CMD_SE) || + (priv->cur_seqid == QSPI_CMD_BE_4K)) { + priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK; + qspi_op_erase(priv); + } else if (priv->cur_seqid == QSPI_CMD_PP) { wr_sfaddr = swab32(txbuf) & OFFSET_BITS_MASK; + } else if ((priv->cur_seqid == QSPI_CMD_BRWR) || + (priv->cur_seqid == QSPI_CMD_WREAR)) { #ifdef CONFIG_SPI_FLASH_BAR - else if ((qspi->cur_seqid == QSPI_CMD_BRWR) || - (qspi->cur_seqid == QSPI_CMD_WREAR)) { wr_sfaddr = 0; - } #endif + } } if (din) { - if (qspi->cur_seqid == QSPI_CMD_FAST_READ) { + if (priv->cur_seqid == QSPI_CMD_FAST_READ) { #ifdef CONFIG_SYS_FSL_QSPI_AHB - qspi_ahb_read(qspi, din, bytes); + qspi_ahb_read(priv, din, bytes); #else - qspi_op_read(qspi, din, bytes); + qspi_op_read(priv, din, bytes); #endif - } - else if (qspi->cur_seqid == QSPI_CMD_RDID) - qspi_op_rdid(qspi, din, bytes); - else if (qspi->cur_seqid == QSPI_CMD_RDSR) - qspi_op_rdsr(qspi, din); + } else if (priv->cur_seqid == QSPI_CMD_RDID) + qspi_op_rdid(priv, din, bytes); + else if (priv->cur_seqid == QSPI_CMD_RDSR) + qspi_op_rdsr(priv, din); #ifdef CONFIG_SPI_FLASH_BAR - else if ((qspi->cur_seqid == QSPI_CMD_BRRD) || - (qspi->cur_seqid == QSPI_CMD_RDEAR)) { - qspi->sf_addr = 0; - qspi_op_rdbank(qspi, din, bytes); + else if ((priv->cur_seqid == QSPI_CMD_BRRD) || + (priv->cur_seqid == QSPI_CMD_RDEAR)) { + priv->sf_addr = 0; + qspi_op_rdbank(priv, din, bytes); } #endif } #ifdef CONFIG_SYS_FSL_QSPI_AHB - if ((qspi->cur_seqid == QSPI_CMD_SE) || - (qspi->cur_seqid == QSPI_CMD_PP) || - (qspi->cur_seqid == QSPI_CMD_BE_4K) || - (qspi->cur_seqid == QSPI_CMD_WREAR) || - (qspi->cur_seqid == QSPI_CMD_BRWR)) - qspi_ahb_invalid(qspi); + if ((priv->cur_seqid == QSPI_CMD_SE) || + (priv->cur_seqid == QSPI_CMD_PP) || + (priv->cur_seqid == QSPI_CMD_BE_4K) || + (priv->cur_seqid == QSPI_CMD_WREAR) || + (priv->cur_seqid == QSPI_CMD_BRWR)) + qspi_ahb_invalid(priv); #endif return 0; } +void qspi_module_disable(struct fsl_qspi_priv *priv, u8 disable) +{ + u32 mcr_val; + + mcr_val = qspi_read32(priv->flags, &priv->regs->mcr); + if (disable) + mcr_val |= QSPI_MCR_MDIS_MASK; + else + mcr_val &= ~QSPI_MCR_MDIS_MASK; + qspi_write32(priv->flags, &priv->regs->mcr, mcr_val); +} + +void qspi_cfg_smpr(struct fsl_qspi_priv *priv, u32 clear_bits, u32 set_bits) +{ + u32 smpr_val; + + smpr_val = qspi_read32(priv->flags, &priv->regs->smpr); + smpr_val &= ~clear_bits; + smpr_val |= set_bits; + qspi_write32(priv->flags, &priv->regs->smpr, smpr_val); +} +#ifndef CONFIG_DM_SPI +static unsigned long spi_bases[] = { + QSPI0_BASE_ADDR, +#ifdef CONFIG_MX6SX + QSPI1_BASE_ADDR, +#endif +}; + +static unsigned long amba_bases[] = { + QSPI0_AMBA_BASE, +#ifdef CONFIG_MX6SX + QSPI1_AMBA_BASE, +#endif +}; + +static inline struct fsl_qspi *to_qspi_spi(struct spi_slave *slave) +{ + return container_of(slave, struct fsl_qspi, slave); +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct fsl_qspi *qspi; + struct fsl_qspi_regs *regs; + u32 total_size; + + if (bus >= ARRAY_SIZE(spi_bases)) + return NULL; + + if (cs >= FSL_QSPI_FLASH_NUM) + return NULL; + + qspi = spi_alloc_slave(struct fsl_qspi, bus, cs); + if (!qspi) + return NULL; + + regs = (struct fsl_qspi_regs *)spi_bases[bus]; + qspi->priv.regs = regs; + /* + * According cs, use different amba_base to choose the + * corresponding flash devices. + * + * If not, only one flash device is used even if passing + * different cs using `sf probe` + */ + qspi->priv.cur_amba_base = amba_bases[bus] + cs * FSL_QSPI_FLASH_SIZE; + + qspi->slave.max_write_size = TX_BUFFER_SIZE; + + qspi_write32(qspi->priv.flags, &regs->mcr, + QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK); + + qspi_cfg_smpr(&qspi->priv, + ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK | + QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK), 0); + + total_size = FSL_QSPI_FLASH_SIZE * FSL_QSPI_FLASH_NUM; + /* + * Any read access to non-implemented addresses will provide + * undefined results. + * + * In case single die flash devices, TOP_ADDR_MEMA2 and + * TOP_ADDR_MEMB2 should be initialized/programmed to + * TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1 respectively - in effect, + * setting the size of these devices to 0. This would ensure + * that the complete memory map is assigned to only one flash device. + */ + qspi_write32(qspi->priv.flags, &regs->sfa1ad, + FSL_QSPI_FLASH_SIZE | amba_bases[bus]); + qspi_write32(qspi->priv.flags, &regs->sfa2ad, + FSL_QSPI_FLASH_SIZE | amba_bases[bus]); + qspi_write32(qspi->priv.flags, &regs->sfb1ad, + total_size | amba_bases[bus]); + qspi_write32(qspi->priv.flags, &regs->sfb2ad, + total_size | amba_bases[bus]); + + qspi_set_lut(&qspi->priv); + +#ifdef CONFIG_SYS_FSL_QSPI_AHB + qspi_init_ahb_read(regs); +#endif + + qspi_module_disable(&qspi->priv, 0); + + return &qspi->slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + struct fsl_qspi *qspi = to_qspi_spi(slave); + + free(qspi); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + return 0; +} + void spi_release_bus(struct spi_slave *slave) { /* Nothing to do */ } + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct fsl_qspi *qspi = to_qspi_spi(slave); + + return qspi_xfer(&qspi->priv, bitlen, dout, din, flags); +} + +void spi_init(void) +{ + /* Nothing to do */ +} +#else +static int fsl_qspi_child_pre_probe(struct udevice *dev) +{ + struct spi_slave *slave = dev_get_parentdata(dev); + + slave->max_write_size = TX_BUFFER_SIZE; + + return 0; +} + +static int fsl_qspi_probe(struct udevice *bus) +{ + u32 total_size; + struct fsl_qspi_platdata *plat = dev_get_platdata(bus); + struct fsl_qspi_priv *priv = dev_get_priv(bus); + struct dm_spi_bus *dm_spi_bus; + + dm_spi_bus = bus->uclass_priv; + + dm_spi_bus->max_hz = plat->speed_hz; + + priv->regs = (struct fsl_qspi_regs *)plat->reg_base; + priv->flags = plat->flags; + + priv->speed_hz = plat->speed_hz; + priv->amba_base[0] = plat->amba_base; + priv->amba_total_size = plat->amba_total_size; + priv->flash_num = plat->flash_num; + priv->num_chipselect = plat->num_chipselect; + + qspi_write32(priv->flags, &priv->regs->mcr, + QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK); + + qspi_cfg_smpr(priv, ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK | + QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK), 0); + + total_size = FSL_QSPI_FLASH_SIZE * FSL_QSPI_FLASH_NUM; + /* + * Any read access to non-implemented addresses will provide + * undefined results. + * + * In case single die flash devices, TOP_ADDR_MEMA2 and + * TOP_ADDR_MEMB2 should be initialized/programmed to + * TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1 respectively - in effect, + * setting the size of these devices to 0. This would ensure + * that the complete memory map is assigned to only one flash device. + */ + qspi_write32(priv->flags, &priv->regs->sfa1ad, + FSL_QSPI_FLASH_SIZE | priv->amba_base[0]); + qspi_write32(priv->flags, &priv->regs->sfa2ad, + FSL_QSPI_FLASH_SIZE | priv->amba_base[0]); + qspi_write32(priv->flags, &priv->regs->sfb1ad, + total_size | priv->amba_base[0]); + qspi_write32(priv->flags, &priv->regs->sfb2ad, + total_size | priv->amba_base[0]); + + qspi_set_lut(priv); + +#ifdef CONFIG_SYS_FSL_QSPI_AHB + qspi_init_ahb_read(priv->regs); +#endif + + qspi_module_disable(priv, 0); + + return 0; +} + +static int fsl_qspi_ofdata_to_platdata(struct udevice *bus) +{ + struct reg_data { + u32 addr; + u32 size; + } regs_data[2]; + struct fsl_qspi_platdata *plat = bus->platdata; + const void *blob = gd->fdt_blob; + int node = bus->of_offset; + int ret, flash_num = 0, subnode; + + if (fdtdec_get_bool(blob, node, "big-endian")) + plat->flags |= QSPI_FLAG_REGMAP_ENDIAN_BIG; + + ret = fdtdec_get_int_array(blob, node, "reg", (u32 *)regs_data, + sizeof(regs_data)/sizeof(u32)); + if (ret) { + debug("Error: can't get base addresses (ret = %d)!\n", ret); + return -ENOMEM; + } + + /* Count flash numbers */ + fdt_for_each_subnode(blob, subnode, node) + ++flash_num; + + if (flash_num == 0) { + debug("Error: Missing flashes!\n"); + return -ENODEV; + } + + plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency", + FSL_QSPI_DEFAULT_SCK_FREQ); + plat->num_chipselect = fdtdec_get_int(blob, node, "num-cs", + FSL_QSPI_MAX_CHIPSELECT_NUM); + + plat->reg_base = regs_data[0].addr; + plat->amba_base = regs_data[1].addr; + plat->amba_total_size = regs_data[1].size; + plat->flash_num = flash_num; + + debug("%s: regs=<0x%x> <0x%x, 0x%x>, max-frequency=%d, endianess=%s\n", + __func__, + plat->reg_base, + plat->amba_base, + plat->amba_total_size, + plat->speed_hz, + plat->flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le" + ); + + return 0; +} + +static int fsl_qspi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct fsl_qspi_priv *priv; + struct udevice *bus; + + bus = dev->parent; + priv = dev_get_priv(bus); + + return qspi_xfer(priv, bitlen, dout, din, flags); +} + +static int fsl_qspi_claim_bus(struct udevice *dev) +{ + struct fsl_qspi_priv *priv; + struct udevice *bus; + struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); + + bus = dev->parent; + priv = dev_get_priv(bus); + + priv->cur_amba_base = + priv->amba_base[0] + FSL_QSPI_FLASH_SIZE * slave_plat->cs; + + qspi_module_disable(priv, 0); + + return 0; +} + +static int fsl_qspi_release_bus(struct udevice *dev) +{ + struct fsl_qspi_priv *priv; + struct udevice *bus; + + bus = dev->parent; + priv = dev_get_priv(bus); + + qspi_module_disable(priv, 1); + + return 0; +} + +static int fsl_qspi_set_speed(struct udevice *bus, uint speed) +{ + /* Nothing to do */ + return 0; +} + +static int fsl_qspi_set_mode(struct udevice *bus, uint mode) +{ + /* Nothing to do */ + return 0; +} + +static const struct dm_spi_ops fsl_qspi_ops = { + .claim_bus = fsl_qspi_claim_bus, + .release_bus = fsl_qspi_release_bus, + .xfer = fsl_qspi_xfer, + .set_speed = fsl_qspi_set_speed, + .set_mode = fsl_qspi_set_mode, +}; + +static const struct udevice_id fsl_qspi_ids[] = { + { .compatible = "fsl,vf610-qspi" }, + { .compatible = "fsl,imx6sx-qspi" }, + { } +}; + +U_BOOT_DRIVER(fsl_qspi) = { + .name = "fsl_qspi", + .id = UCLASS_SPI, + .of_match = fsl_qspi_ids, + .ops = &fsl_qspi_ops, + .ofdata_to_platdata = fsl_qspi_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct fsl_qspi_platdata), + .priv_auto_alloc_size = sizeof(struct fsl_qspi_priv), + .probe = fsl_qspi_probe, + .child_pre_probe = fsl_qspi_child_pre_probe, +}; +#endif -- 2.1.0.27.g96db324

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[U-Boot] [PATCH 0/6] Allow sandbox to use config_distro_bootcmd
by Sjoerd Simons 01 Apr '15

01 Apr '15

Testing whether images will correctly boot with the standard distro bootcmds can be rather time-consuming as it tends to require flashing the images and booting on a device. Ditto for testing changes to config_distro_bootcmd. Adding support for sandbox to run distro bootcmds makes things a lot more convenient. Sjoerd Simons (6): sandbox: only do sandboxfs for hostfs interface sandbox: Add support for bootz sandbox: Implement host dev [device] config_distro_bootcmd.h: Add shared block definition for the host interface pxe: Ensure all memory access is to mapped memory sandbox: add config_distro_defaults and config_distro_bootcmd arch/sandbox/cpu/cpu.c | 20 +++++++++++ common/cmd_pxe.c | 80 +++++++++++++++++++++++------------------ common/cmd_sandbox.c | 48 +++++++++++++++++++++++++ fs/sandbox/sandboxfs.c | 5 ++- include/config_distro_bootcmd.h | 13 +++++++ include/configs/sandbox.h | 29 +++++++++++++-- 6 files changed, 157 insertions(+), 38 deletions(-) -- 2.1.4

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[U-Boot] [PULL] u-boot-atmel/master -> u-boot/master
by Andreas Bießmann 01 Apr '15

01 Apr '15

Hi Tom, another pull request for 2015.04 release. Atmel stuff should be fine now for this release. The following changes since commit 662e2acb46250881ec26bc8366fc9eb1856cb7c2: sunxi: UTOO_P66: Add missing MAINTAINERS entry (2015-03-29 14:56:48 +0200) are available in the git repository at: git://git.denx.de/u-boot-atmel.git master for you to fetch changes up to b2d387bcebba352ca64b781486507800964d7ffd: ARM: at91: sama5: move the common part of configurations to at91-sama5_common.h (2015-04-01 01:04:32 +0200) ---------------------------------------------------------------- Bo Shen (6): ARM: atmel: arm9: switch to use common timer functions ARM: atmel: armv7: switch to use common timer functions ARM: atmel: arm926ejs: fix clock configuration ARM: atmel: at91sam9m10g45ek: enable spl support ARM: atmel: at91sam9x5ek: enable spl support ARM: atmel: at91sam9n12ek: enable spl support David Dueck (1): ARM: at91: atmel_nand: Support flash based BBT Heiko Schocher (1): arm, at91: corvus: move MACH_TYPE to defconfig Tom Rini (1): spl_atmel.c: Switch s_init to board_init_f Wu, Josh (3): ARM: at91: sama5d4: display the U-Boot version on LCD ARM: at91: at91sam9n12ek: save the environment to a fat file in MMC card ARM: at91: sama5: move the common part of configurations to at91-sama5_common.h arch/arm/mach-at91/Kconfig | 3 + arch/arm/mach-at91/Makefile | 2 + arch/arm/mach-at91/arm926ejs/clock.c | 54 +++++++------- arch/arm/mach-at91/arm926ejs/timer.c | 59 --------------- arch/arm/mach-at91/arm926ejs/u-boot-spl.lds | 48 +++++++++++++ arch/arm/mach-at91/armv7/timer.c | 61 ---------------- arch/arm/mach-at91/include/mach/at91_pmc.h | 6 +- arch/arm/mach-at91/include/mach/at91sam9260.h | 3 + arch/arm/mach-at91/include/mach/at91sam9261.h | 3 + arch/arm/mach-at91/include/mach/at91sam9263.h | 3 + arch/arm/mach-at91/include/mach/at91sam9g45.h | 3 + arch/arm/mach-at91/include/mach/at91sam9rl.h | 3 + arch/arm/mach-at91/include/mach/at91sam9x5.h | 13 ++++ arch/arm/mach-at91/include/mach/sama5d3.h | 3 + arch/arm/mach-at91/include/mach/sama5d4.h | 3 + arch/arm/mach-at91/mpddrc.c | 3 +- arch/arm/mach-at91/spl.c | 2 +- arch/arm/mach-at91/spl_at91.c | 11 ++- arch/arm/mach-at91/spl_atmel.c | 10 +++ board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c | 80 +++++++++++++++++++++ board/atmel/at91sam9n12ek/at91sam9n12ek.c | 73 +++++++++++++++++++ board/atmel/at91sam9x5ek/at91sam9x5ek.c | 74 +++++++++++++++++++ board/atmel/sama5d4_xplained/sama5d4_xplained.c | 2 + board/atmel/sama5d4ek/sama5d4ek.c | 2 + configs/at91sam9m10g45ek_mmc_defconfig | 1 + configs/at91sam9m10g45ek_nandflash_defconfig | 1 + configs/at91sam9n12ek_nandflash_defconfig | 1 + configs/at91sam9n12ek_spiflash_defconfig | 1 + configs/at91sam9x5ek_nandflash_defconfig | 1 + configs/at91sam9x5ek_spiflash_defconfig | 1 + configs/corvus_defconfig | 2 +- drivers/mtd/nand/atmel_nand.c | 6 ++ include/configs/at91-sama5_common.h | 87 +++++++++++++++++++++++ include/configs/at91sam9m10g45ek.h | 58 +++++++++++++++ include/configs/at91sam9n12ek.h | 73 ++++++++++++++++++- include/configs/at91sam9x5ek.h | 57 +++++++++++++++ include/configs/corvus.h | 3 - include/configs/sama5d3_xplained.h | 77 +------------------- include/configs/sama5d3xek.h | 82 ++------------------- include/configs/sama5d4_xplained.h | 76 +------------------- include/configs/sama5d4ek.h | 78 +------------------- 41 files changed, 673 insertions(+), 456 deletions(-) create mode 100644 arch/arm/mach-at91/arm926ejs/u-boot-spl.lds create mode 100644 include/configs/at91-sama5_common.h

2 1

[U-Boot] Pull request: nand flash
by Scott Wood 01 Apr '15

01 Apr '15

[resent with Tom's new e-mail address] The following changes since commit 662e2acb46250881ec26bc8366fc9eb1856cb7c2: sunxi: UTOO_P66: Add missing MAINTAINERS entry (2015-03-29 14:56:48 +0200) are available in the git repository at: git://git.denx.de/u-boot-nand-flash.git for you to fetch changes up to 55765b1842e7dcf22efa8d973c7d1b7498dd99fa: mtd: vf610_nfc: specify transfer size before each transfer (2015-03-30 23:35:27 -0500) ---------------------------------------------------------------- Luca Ellero (2): mtd: nand: mxs: fix PIO_WORDs in mxs_nand_read_buf() mtd: nand: mxs: fix PIO_WORDs in mxs_nand_write_buf() Peter Tyser (7): nand: Remove unused CONFIG_MTD_NAND_ECC_JFFS2 option nand: Remove unused read/write structures nand: Add verification functions cmd_nand: Verify writes to NAND dfu: nand: Verify writes nand: Remove CONFIG_MTD_NAND_VERIFY_WRITE nand: yaffs: Remove the "nand write.yaffs" command Stefan Agner (2): mtd: vf610_nfc: mark page as dirty on block erase mtd: vf610_nfc: specify transfer size before each transfer README | 3 - board/prodrive/alpr/nand.c | 16 ---- board/socrates/nand.c | 25 ------ common/cmd_nand.c | 27 ++----- doc/README.nand | 12 --- drivers/dfu/dfu_nand.c | 2 +- drivers/mtd/nand/davinci_nand.c | 12 --- drivers/mtd/nand/fsl_elbc_nand.c | 38 --------- drivers/mtd/nand/fsl_ifc_nand.c | 38 --------- drivers/mtd/nand/fsl_upm.c | 18 ----- drivers/mtd/nand/mpc5121_nfc.c | 26 ------ drivers/mtd/nand/mxc_nand.c | 33 -------- drivers/mtd/nand/mxs_nand.c | 4 +- drivers/mtd/nand/nand_base.c | 65 --------------- drivers/mtd/nand/nand_util.c | 156 +++++++++++++++++++++++------------- drivers/mtd/nand/ndfc.c | 18 ----- drivers/mtd/nand/vf610_nfc.c | 28 ++++--- include/configs/B4860QDS.h | 1 - include/configs/BSC9131RDB.h | 1 - include/configs/BSC9132QDS.h | 1 - include/configs/C29XPCIE.h | 1 - include/configs/M54418TWR.h | 1 - include/configs/MPC8313ERDB.h | 1 - include/configs/MPC8315ERDB.h | 1 - include/configs/MPC837XEMDS.h | 1 - include/configs/MPC8536DS.h | 1 - include/configs/MPC8569MDS.h | 1 - include/configs/MPC8572DS.h | 1 - include/configs/P1010RDB.h | 1 - include/configs/P1022DS.h | 1 - include/configs/P1023RDB.h | 1 - include/configs/P2041RDB.h | 1 - include/configs/T102xQDS.h | 1 - include/configs/T102xRDB.h | 1 - include/configs/T1040QDS.h | 1 - include/configs/T104xRDB.h | 1 - include/configs/T208xQDS.h | 1 - include/configs/T208xRDB.h | 1 - include/configs/T4240QDS.h | 1 - include/configs/T4240RDB.h | 1 - include/configs/VCMA9.h | 1 - include/configs/corenet_ds.h | 1 - include/configs/ethernut5.h | 1 - include/configs/ids8313.h | 1 - include/configs/km/kmp204x-common.h | 1 - include/configs/ls1021aqds.h | 1 - include/configs/ls2085a_common.h | 1 - include/configs/p1_p2_rdb_pc.h | 1 - include/configs/ve8313.h | 1 - include/configs/xpedite537x.h | 1 - include/configs/xpedite550x.h | 1 - include/linux/mtd/nand.h | 5 -- include/nand.h | 35 ++------ 53 files changed, 133 insertions(+), 462 deletions(-)

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[U-Boot] [PULL] Please pull u-boot-imx
by Stefano Babic 01 Apr '15

01 Apr '15

Hi Tom, please pull from u-boot-imx, thanks ! The following changes since commit 21866c34a1b4098a8868c9250daf01baf84c2397: at91sam9rlek_mmc_defconfig: Add CONFIG_ARCH_AT91=y (2015-03-20 10:47:38 -0400) are available in the git repository at: git://www.denx.de/git/u-boot-imx.git master for you to fetch changes up to 5cab874052614fb130cd9b16fc6a3d27cae0741e: watchdog/imx_watchdog: do not set WCR_WDW (2015-03-25 16:52:16 +0100) ---------------------------------------------------------------- Boris BREZILLON (3): ARM: mx6: move to a standard arch/board approach ARM: iMX: define an IMX_CONFIG Kconfig option board/seco: Add mx6q-uq7 basic board support Peng Fan (2): imx:mx6dlsabresd fix error detecting thermal imx:mx6slevk support reading temperature Sebastian Siewior (1): watchdog/imx_watchdog: do not set WCR_WDW arch/arm/Kconfig | 8 ++ arch/arm/cpu/armv7/mx6/Kconfig | 42 +++++++++ arch/arm/imx-common/Kconfig | 2 + board/seco/Kconfig | 63 ++++++++++++++ board/seco/common/Makefile | 2 + board/seco/common/mx6.c | 138 ++++++++++++++++++++++++++++++ board/seco/common/mx6.h | 9 ++ board/seco/mx6quq7/MAINTAINERS | 6 ++ board/seco/mx6quq7/Makefile | 7 ++ board/seco/mx6quq7/mx6quq7-2g.cfg | 173 ++++++++++++++++++++++++++++++++++++++ board/seco/mx6quq7/mx6quq7.c | 162 +++++++++++++++++++++++++++++++++++ configs/mx6dlsabresd_defconfig | 2 + configs/mx6slevk_defconfig | 4 + configs/mx6slevk_spinor_defconfig | 4 + configs/secomx6quq7_defconfig | 7 ++ drivers/watchdog/imx_watchdog.c | 3 +- include/configs/mx6slevk.h | 7 ++ include/configs/secomx6quq7.h | 166 ++++++++++++++++++++++++++++++++++++ 18 files changed, 803 insertions(+), 2 deletions(-) create mode 100644 arch/arm/cpu/armv7/mx6/Kconfig create mode 100644 arch/arm/imx-common/Kconfig create mode 100644 board/seco/Kconfig create mode 100644 board/seco/common/Makefile create mode 100644 board/seco/common/mx6.c create mode 100644 board/seco/common/mx6.h create mode 100644 board/seco/mx6quq7/MAINTAINERS create mode 100644 board/seco/mx6quq7/Makefile create mode 100644 board/seco/mx6quq7/mx6quq7-2g.cfg create mode 100644 board/seco/mx6quq7/mx6quq7.c create mode 100644 configs/secomx6quq7_defconfig create mode 100644 include/configs/secomx6quq7.h Regards, Stefano -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic(a)denx.de =====================================================================

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[U-Boot] [PATCH 1/2] spl_atmel.c: Switch s_init to board_init_f
by Tom Rini 01 Apr '15

01 Apr '15

To facilitate changing lowlevel_init to become s_init, move the current contents of s_init into board_init_f and add the rest of what board_init_f does here. Cc: Bo Shen <voice.shen(a)atmel.com> Cc: Andreas Bießmann <andreas.devel(a)googlemail.com> Tested-by: Matt Porter <mporter(a)konsulko.com> on sama5d3_xplained Signed-off-by: Tom Rini <trini(a)ti.com> --- arch/arm/cpu/at91-common/spl_atmel.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/at91-common/spl_atmel.c b/arch/arm/cpu/at91-common/spl_atmel.c index 7297530..d815050 100644 --- a/arch/arm/cpu/at91-common/spl_atmel.c +++ b/arch/arm/cpu/at91-common/spl_atmel.c @@ -58,7 +58,7 @@ static void switch_to_main_crystal_osc(void) writel(tmp, &pmc->mor); } -void s_init(void) +void board_init_f(ulong dummy) { switch_to_main_crystal_osc(); @@ -77,4 +77,9 @@ void s_init(void) preloader_console_init(); mem_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + board_init_r(NULL, 0); } -- 1.7.9.5

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[U-Boot] [ PATCH v2] ARM: at91: sama5: move the common part of configurations to at91-sama5_common.h
by Josh Wu 01 Apr '15

01 Apr '15

Create a new configuration file: at91-sama5_common.h. Which includes the configurations that reused by all SAMA5 chips. at91-sama5_common.h includes: - hw macros (clock, text_base and etc.) - default commands. - BOOTARGS - U-Boot common configs. NOTE: NOR flash definition should be put before including the common header. For sama5d3-xplained: - add CMD_SETEXPR For sama5d3xek: - add CMD_SETEXPR - change CONFIG_SYS_MALLOC_LEN to (4*1024*1024) Signed-off-by: Josh Wu <josh.wu(a)atmel.com> --- Changes in v2: - serperate the patch alone and rebase on top of latest u-boot. - add the missing CMD_FLASH for sama5d3_xplained. - remove unrelated changes. - refined format of at91-sama5_common.h. include/configs/at91-sama5_common.h | 87 +++++++++++++++++++++++++++++++++++++ include/configs/sama5d3_xplained.h | 77 ++------------------------------ include/configs/sama5d3xek.h | 82 +++------------------------------- include/configs/sama5d4_xplained.h | 76 ++------------------------------ include/configs/sama5d4ek.h | 78 ++------------------------------- 5 files changed, 102 insertions(+), 298 deletions(-) create mode 100644 include/configs/at91-sama5_common.h diff --git a/include/configs/at91-sama5_common.h b/include/configs/at91-sama5_common.h new file mode 100644 index 0000000..dedb785 --- /dev/null +++ b/include/configs/at91-sama5_common.h @@ -0,0 +1,87 @@ +/* + * Common part of configuration settings for the AT91 SAMA5 board. + * + * Copyright (C) 2015 Atmel Corporation + * Josh Wu <josh.wu(a)atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __AT91_SAMA5_COMMON_H +#define __AT91_SAMA5_COMMON_H + +#include <asm/hardware.h> + +#define CONFIG_SYS_TEXT_BASE 0x26f00000 + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ + +#define CONFIG_ARCH_CPU_INIT + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_DISPLAY_CPUINFO + +#define CONFIG_CMD_BOOTZ +#define CONFIG_OF_LIBFDT /* Device Tree support */ + +#define CONFIG_SYS_GENERIC_BOARD + +/* general purpose I/O */ +#define CONFIG_AT91_GPIO + +#define CONFIG_BOOTDELAY 3 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_LOADS +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_SETEXPR + +#ifdef CONFIG_SYS_USE_MMC +#define CONFIG_BOOTARGS \ + "console=ttyS0,115200 earlyprintk " \ + "root=/dev/mmcblk0p2 rw rootwait" +#else +#define CONFIG_BOOTARGS \ + "console=ttyS0,115200 earlyprintk " \ + "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \ + "256K(env),256k(evn_redundent),256k(spare)," \ + "512k(dtb),6M(kernel)ro,-(rootfs) " \ + "rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs" +#endif + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_SYS_PROMPT "U-Boot> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_HUSH_PARSER + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) + +#endif diff --git a/include/configs/sama5d3_xplained.h b/include/configs/sama5d3_xplained.h index c82728e..bfd8aa7 100644 --- a/include/configs/sama5d3_xplained.h +++ b/include/configs/sama5d3_xplained.h @@ -10,30 +10,10 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include <asm/hardware.h> - -#define CONFIG_SYS_TEXT_BASE 0x26f00000 - -/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ - -#define CONFIG_ARCH_CPU_INIT - -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif - -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_DISPLAY_CPUINFO - -#define CONFIG_CMD_BOOTZ -#define CONFIG_OF_LIBFDT /* Device Tree support */ - -#define CONFIG_SYS_GENERIC_BOARD +/* No NOR flash, this definition should put before common header */ +#define CONFIG_SYS_NO_FLASH -/* general purpose I/O */ -#define CONFIG_AT91_GPIO +#include "at91-sama5_common.h" /* serial console */ #define CONFIG_ATMEL_USART @@ -51,29 +31,6 @@ */ #define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP -#define CONFIG_BOOTDELAY 3 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* No NOR flash */ -#define CONFIG_SYS_NO_FLASH - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_IMI -#undef CONFIG_CMD_LOADS -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP - /* SDRAM */ #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS @@ -181,34 +138,6 @@ #define CONFIG_ENV_IS_NOWHERE #endif -#ifdef CONFIG_SYS_USE_MMC -#define CONFIG_BOOTARGS \ - "console=ttyS0,115200 earlyprintk " \ - "root=/dev/mmcblk0p2 rw rootwait" -#else -#define CONFIG_BOOTARGS \ - "console=ttyS0,115200 earlyprintk " \ - "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \ - "256K(env),256k(evn_redundent),256k(spare)," \ - "512k(dtb),6M(kernel)ro,-(rootfs) " \ - "rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs" -#endif - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_SYS_PROMPT "U-Boot> " -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LONGHELP -#define CONFIG_CMDLINE_EDITING -#define CONFIG_AUTO_COMPLETE -#define CONFIG_SYS_HUSH_PARSER - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) - /* SPL */ #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_TEXT_BASE 0x300000 diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h index a99b559..d933a9e 100644 --- a/include/configs/sama5d3xek.h +++ b/include/configs/sama5d3xek.h @@ -13,30 +13,11 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include <asm/hardware.h> - -#define CONFIG_SYS_TEXT_BASE 0x26f00000 - -/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ - -#define CONFIG_ARCH_CPU_INIT - -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif - -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_DISPLAY_CPUINFO - -#define CONFIG_CMD_BOOTZ -#define CONFIG_OF_LIBFDT /* Device Tree support */ - -#define CONFIG_SYS_GENERIC_BOARD - -/* general purpose I/O */ -#define CONFIG_AT91_GPIO +/* + * If has No NOR flash, please put the definition: CONFIG_SYS_NO_FLASH + * before the common header. + */ +#include "at91-sama5_common.h" /* serial console */ #define CONFIG_ATMEL_USART @@ -69,40 +50,17 @@ /* board specific (not enough SRAM) */ #define CONFIG_SAMA5D3_LCD_BASE 0x23E00000 -#define CONFIG_BOOTDELAY 3 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - /* NOR flash */ +#ifndef CONFIG_SYS_NO_FLASH #define CONFIG_CMD_FLASH - -#ifdef CONFIG_CMD_FLASH #define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_FLASH_CFI #define CONFIG_SYS_FLASH_PROTECTION #define CONFIG_SYS_FLASH_BASE 0x10000000 #define CONFIG_SYS_MAX_FLASH_SECT 131 #define CONFIG_SYS_MAX_FLASH_BANKS 1 -#else -#define CONFIG_SYS_NO_FLASH #endif -/* - * Command line configuration. - */ -#include <config_cmd_default.h> -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_IMI -#undef CONFIG_CMD_LOADS -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP - /* SDRAM */ #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS @@ -228,34 +186,6 @@ #define CONFIG_ENV_IS_NOWHERE #endif -#ifdef CONFIG_SYS_USE_MMC -#define CONFIG_BOOTARGS \ - "console=ttyS0,115200 earlyprintk " \ - "root=/dev/mmcblk0p2 rw rootwait" -#else -#define CONFIG_BOOTARGS \ - "console=ttyS0,115200 earlyprintk " \ - "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \ - "256K(env),256k(evn_redundent),256k(spare)," \ - "512k(dtb),6M(kernel)ro,-(rootfs) " \ - "rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs" -#endif - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_SYS_PROMPT "U-Boot> " -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LONGHELP -#define CONFIG_CMDLINE_EDITING -#define CONFIG_AUTO_COMPLETE -#define CONFIG_SYS_HUSH_PARSER - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) - /* SPL */ #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_TEXT_BASE 0x300000 diff --git a/include/configs/sama5d4_xplained.h b/include/configs/sama5d4_xplained.h index 4cb0761..5fb621e 100644 --- a/include/configs/sama5d4_xplained.h +++ b/include/configs/sama5d4_xplained.h @@ -10,59 +10,16 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include <asm/hardware.h> - -#define CONFIG_SYS_TEXT_BASE 0x26f00000 - -/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ - -#define CONFIG_ARCH_CPU_INIT - -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_DISPLAY_CPUINFO - -#define CONFIG_CMD_BOOTZ -#define CONFIG_OF_LIBFDT /* Device Tree support */ - -#define CONFIG_SYS_GENERIC_BOARD +/* No NOR flash, this definition should put before common header */ +#define CONFIG_SYS_NO_FLASH -/* general purpose I/O */ -#define CONFIG_AT91_GPIO +#include "at91-sama5_common.h" /* serial console */ #define CONFIG_ATMEL_USART #define CONFIG_USART_BASE ATMEL_BASE_USART3 #define CONFIG_USART_ID ATMEL_ID_USART3 -#define CONFIG_BOOTDELAY 3 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* No NOR flash */ -#define CONFIG_SYS_NO_FLASH - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_IMI -#undef CONFIG_CMD_LOADS -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_SETEXPR - /* SDRAM */ #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS @@ -199,33 +156,6 @@ "bootz 0x22000000 - 0x21000000" #endif -#ifdef CONFIG_SYS_USE_MMC -#define CONFIG_BOOTARGS \ - "console=ttyS0,115200 earlyprintk " \ - "root=/dev/mmcblk0p2 rw rootwait" -#else -#define CONFIG_BOOTARGS \ - "console=ttyS0,115200 earlyprintk " \ - "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \ - "256K(env),256k(evn_redundent),256k(spare)," \ - "512k(dtb),6M(kernel)ro,-(rootfs) " \ - "rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs" -#endif - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_SYS_PROMPT "U-Boot> " -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LONGHELP -#define CONFIG_CMDLINE_EDITING -#define CONFIG_AUTO_COMPLETE -#define CONFIG_SYS_HUSH_PARSER - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) /* SPL */ diff --git a/include/configs/sama5d4ek.h b/include/configs/sama5d4ek.h index 897d481..546d7a3 100644 --- a/include/configs/sama5d4ek.h +++ b/include/configs/sama5d4ek.h @@ -10,59 +10,16 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include <asm/hardware.h> - -#define CONFIG_SYS_TEXT_BASE 0x26f00000 - -/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ - -#define CONFIG_ARCH_CPU_INIT - -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_DISPLAY_CPUINFO - -#define CONFIG_CMD_BOOTZ -#define CONFIG_OF_LIBFDT /* Device Tree support */ - -#define CONFIG_SYS_GENERIC_BOARD +/* No NOR flash, this definition should put before common header */ +#define CONFIG_SYS_NO_FLASH -/* general purpose I/O */ -#define CONFIG_AT91_GPIO +#include "at91-sama5_common.h" /* serial console */ #define CONFIG_ATMEL_USART #define CONFIG_USART_BASE ATMEL_BASE_USART3 #define CONFIG_USART_ID ATMEL_ID_USART3 -#define CONFIG_BOOTDELAY 3 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* No NOR flash */ -#define CONFIG_SYS_NO_FLASH - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_IMI -#undef CONFIG_CMD_LOADS -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_SETEXPR - /* SDRAM */ #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS @@ -197,35 +154,6 @@ "bootz 0x22000000 - 0x21000000" #endif -#ifdef CONFIG_SYS_USE_MMC -#define CONFIG_BOOTARGS \ - "console=ttyS0,115200 earlyprintk " \ - "root=/dev/mmcblk0p2 rw rootwait" -#else -#define CONFIG_BOOTARGS \ - "console=ttyS0,115200 earlyprintk " \ - "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \ - "256K(env),256k(evn_redundent),256k(spare)," \ - "512k(dtb),6M(kernel)ro,-(rootfs) " \ - "rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs" -#endif - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_SYS_PROMPT "U-Boot> " -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LONGHELP -#define CONFIG_CMDLINE_EDITING -#define CONFIG_AUTO_COMPLETE -#define CONFIG_SYS_HUSH_PARSER - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) - - /* SPL */ #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_TEXT_BASE 0x200000 -- 1.9.1

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