February 2015 - U-Boot

[U-Boot] [PATCH v2 0/22] x86: Add bare support for Intel Minnowboard Max
by Simon Glass 11 Jun '15

11 Jun '15

This series adds support for the Intel Minnowboard Max (called Minnowmax for short). Along the way a few refactors and additions are made: - The Intel Firmware Support Package support is moved from queensbay to a common location - PCI support for XHCI is added - A few tweaks are made to the PCI support - Support for the debug UART (early debug output) is provided - The microcode tool now also supports reading in header files This board has been lightly tested. The following seem to work: - USB2 on the blue port (not USB3), e.g. for keyboard - Ethernet - HDMI out and console - UART - uSD card - SPI SATA is detected but I have not attached a drive to try it. USB3 shows signs of life but does not detect a USB stick, and crashes when trying to use a USB Ethernet adaptor. For SPI some parts cannot be read and others cannot be written. This seems to be a feature of the Intel hardware configuration. It may be possible to fix this using the SPI registers but I cannot work out how / lost interest trying. So far, addresses from 500000 to 700000 can be used. I have not tried the ICH GPIO driver but it likely needs work before it will function. I2C is not supported as there is currently no U-Boot driver for this. The zboot command can be used to start a bzImage kernel. Verified boot is supported - use mkimage to sign images as described in this walk-through: doc/uImage.FIT/beaglebone_vboot.txt Boot time is grim: - 1423ms to set up display (Intel FSP) - 454ms to scan AHCI (when no devices are connected) - ~1000ms to power up and start cache-as-RAM init (Intel FSP) (this is not benchmarked, may be inaccurate) - ~950ms to set up memory and initial machine configuration (Intel FSP) (this is not benchmarked, may be inaccurate) So it takes over 4 seconds to get to booting a kernel. Implementing the Memory Reference Code (MRC) cache should improve this slightly (perhaps a reduction of 500-1000ms). This cache is implemented for ivybridge so that code needs to be moved into a generic x86 directory and plumbed into the FSP code. This has not been done in this series. Also the video and SATA/AHCI can be disabled if preferred. It is also possible to run as a coreboot payload. See the instructions in README.x86 for this. In this case video does not work since coreboot does not pass through the VESA display information. To support the single-core 1GB variant, changes would need to be made to arch/x86/cpu/baytrail/fsp_configs.c to select different values for the memory. The microcode update may need to change also. This series is available at u-boot-x86 branch minnow-working. Changes in v2: - Fix missing spaces (code style nit) - Add another comment in pci_find_class() - Fix README typos - Rename MMCONF_BASE_ADDRESS to PCIE_ECAM_BASE - Adjust the Kconfig help according to Bin's comments - Rename pci_rom_emul_t to pci_rom_emul - Move MMC code into a new pci_mmc.c file - Remove setup_early_uart() function prototype - Remove duplicate prototype of setup_early_uart() - Document how to change the SPI speed with ifdtool - Move CONFIG_SYS_CACHELINE_SIZE to the board CONFIG file - Add comment about FSP setting PCIE_ECAM_BASE - Put baytrail Kconfig in alphabetical order - Remove superfluous check for CONFIG_DEBUG_UART in setup_early_uart() - Fix compatible string for SPI flash - Remove commented-out DEBUG_UART_CLOCK baud rate - Rename 'Coreboot' to 'coreboot' in README.x86 Simon Glass (22): x86: Enhance the microcode tool to support header files as input pci: Add a function to find a device by class x86: pci: Add PCI IDs for Minnowboard Max x86: video: Enable video for Minnowboard Max usb: pci: Use pci_find_class() to find the device usb: pci: Add XHCI driver for PCI x86: Add an option to enabling building a ROM file x86: Rename MMCONF_BASE_ADDRESS and make it common across x86 x86: video: Allow video ROM execution to fall back to the other method x86: bootstage: Add time measurement for vesa start-up x86: Move common FSP code into a common location x86: Adjust the FSP types slightly x86: Make CAR and DRAM FSP code common x86: mmc: Move common FSP functions into a common file x86: Remove unnecessary casts and fix comment typos x86: Allow FSP Kconfig settings for all x86 x86: Allow a UART to be set up before the FSP is ready x86: spi: Support ValleyView in ICH SPI driver scsi: bootstage: Measure time taken to scan the bus x86: Enable bootstage features x86: Add some documentation on how to port U-Boot on x86 x86: Add support for Intel Minnowboard Max Makefile | 5 +- arch/x86/Kconfig | 67 + arch/x86/cpu/Makefile | 1 + arch/x86/cpu/baytrail/Kconfig | 9 + arch/x86/cpu/baytrail/Makefile | 10 + arch/x86/cpu/baytrail/early_uart.c | 78 + arch/x86/cpu/baytrail/fsp_configs.c | 156 + arch/x86/cpu/baytrail/pci.c | 47 + arch/x86/cpu/baytrail/valleyview.c | 38 + arch/x86/cpu/ivybridge/gma.c | 3 +- arch/x86/cpu/ivybridge/sdram.c | 2 +- arch/x86/cpu/queensbay/Kconfig | 38 - arch/x86/cpu/queensbay/Makefile | 4 +- arch/x86/cpu/queensbay/fsp_configs.c | 2 +- arch/x86/cpu/queensbay/tnc.c | 29 +- arch/x86/cpu/queensbay/tnc_pci.c | 17 +- arch/x86/cpu/queensbay/topcliff.c | 33 +- arch/x86/dts/Makefile | 3 +- arch/x86/dts/microcode/m0130673322.dtsi | 3284 ++++++++++++++++++++ arch/x86/dts/minnowmax.dts | 45 + arch/x86/dts/serial.dtsi | 2 +- arch/x86/include/asm/arch-baytrail/fsp/azalia.h | 39 + arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h | 95 + arch/x86/include/asm/arch-baytrail/gpio.h | 13 + arch/x86/include/asm/arch-ivybridge/sandybridge.h | 2 +- arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h | 2 - .../include/asm/{arch-queensbay => }/fsp/fsp_api.h | 6 +- .../asm/{arch-queensbay => }/fsp/fsp_bootmode.h | 0 .../include/asm/{arch-queensbay => }/fsp/fsp_ffs.h | 0 .../include/asm/{arch-queensbay => }/fsp/fsp_fv.h | 0 .../include/asm/{arch-queensbay => }/fsp/fsp_hob.h | 0 .../asm/{arch-queensbay => }/fsp/fsp_infoheader.h | 0 .../asm/{arch-queensbay => }/fsp/fsp_platform.h | 0 .../asm/{arch-queensbay => }/fsp/fsp_support.h | 6 +- .../asm/{arch-queensbay => }/fsp/fsp_types.h | 0 arch/x86/include/asm/u-boot-x86.h | 3 + arch/x86/lib/Makefile | 1 + arch/x86/lib/cmd_hob.c | 2 +- arch/x86/lib/fsp/Makefile | 10 + .../{cpu/queensbay/tnc_car.S => lib/fsp/fsp_car.S} | 0 arch/x86/lib/fsp/fsp_common.c | 55 + .../queensbay/tnc_dram.c => lib/fsp/fsp_dram.c} | 2 +- arch/x86/{cpu/queensbay => lib/fsp}/fsp_support.c | 20 +- board/google/chromebook_link/Kconfig | 3 +- board/intel/minnowmax/Kconfig | 30 + board/intel/minnowmax/MAINTAINERS | 6 + board/intel/minnowmax/Makefile | 7 + board/intel/minnowmax/minnowmax.c | 32 + board/intel/minnowmax/start.S | 9 + common/cmd_scsi.c | 2 + configs/minnowmax_defconfig | 13 + doc/README.x86 | 121 +- drivers/mmc/Makefile | 1 + drivers/mmc/pci_mmc.c | 42 + drivers/pci/pci.c | 43 + drivers/pci/pci_rom.c | 32 +- drivers/spi/ich.c | 56 +- drivers/spi/ich.h | 11 +- drivers/usb/host/Makefile | 1 + drivers/usb/host/ehci-pci.c | 53 +- drivers/usb/host/xhci-pci.c | 60 + drivers/video/vesa_fb.c | 9 +- include/bootstage.h | 1 + include/configs/minnowmax.h | 72 + include/configs/x86-common.h | 3 + include/mmc.h | 14 + include/pci.h | 3 +- include/pci_ids.h | 5 + include/pci_rom.h | 15 +- tools/microcode-tool.py | 90 +- 70 files changed, 4608 insertions(+), 255 deletions(-) create mode 100644 arch/x86/cpu/baytrail/Kconfig create mode 100644 arch/x86/cpu/baytrail/Makefile create mode 100644 arch/x86/cpu/baytrail/early_uart.c create mode 100644 arch/x86/cpu/baytrail/fsp_configs.c create mode 100644 arch/x86/cpu/baytrail/pci.c create mode 100644 arch/x86/cpu/baytrail/valleyview.c create mode 100644 arch/x86/dts/microcode/m0130673322.dtsi create mode 100644 arch/x86/dts/minnowmax.dts create mode 100644 arch/x86/include/asm/arch-baytrail/fsp/azalia.h create mode 100644 arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h create mode 100644 arch/x86/include/asm/arch-baytrail/gpio.h rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_api.h (88%) rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_bootmode.h (100%) rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_ffs.h (100%) rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_fv.h (100%) rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_hob.h (100%) rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_infoheader.h (100%) rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_platform.h (100%) rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_support.h (98%) rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_types.h (100%) create mode 100644 arch/x86/lib/fsp/Makefile rename arch/x86/{cpu/queensbay/tnc_car.S => lib/fsp/fsp_car.S} (100%) create mode 100644 arch/x86/lib/fsp/fsp_common.c rename arch/x86/{cpu/queensbay/tnc_dram.c => lib/fsp/fsp_dram.c} (98%) rename arch/x86/{cpu/queensbay => lib/fsp}/fsp_support.c (96%) create mode 100644 board/intel/minnowmax/Kconfig create mode 100644 board/intel/minnowmax/MAINTAINERS create mode 100644 board/intel/minnowmax/Makefile create mode 100644 board/intel/minnowmax/minnowmax.c create mode 100644 board/intel/minnowmax/start.S create mode 100644 configs/minnowmax_defconfig create mode 100644 drivers/mmc/pci_mmc.c create mode 100644 drivers/usb/host/xhci-pci.c create mode 100644 include/configs/minnowmax.h -- 2.2.0.rc0.207.ga3a616c

3 63

[U-Boot] [RFC PATCH] ARMv8: replace CONFIG_ARM64 with builtin __aarch64__
by fenghua＠phytium.com.cn 03 Jun '15

03 Jun '15

From: David Feng <fenghua(a)phytium.com.cn> This patch replace CONFIG_ARM64 with gcc builtin __aarch64__. CONFIG_ARM64 is still needed in makefile and config.mk. Maybe them could be replace with something like *_V8 later. Signed-off-by: David Feng <fenghua(a)phytium.com.cn> --- arch/arm/include/asm/cache.h | 2 +- arch/arm/include/asm/config.h | 2 +- arch/arm/include/asm/global_data.h | 4 ++-- arch/arm/include/asm/macro.h | 4 ++-- arch/arm/include/asm/proc-armv/ptrace.h | 6 +++--- arch/arm/include/asm/proc-armv/system.h | 8 ++++---- arch/arm/include/asm/system.h | 6 +++--- arch/arm/include/asm/types.h | 6 +++--- arch/arm/include/asm/u-boot-arm.h | 2 +- arch/arm/include/asm/u-boot.h | 2 +- arch/arm/lib/board.c | 6 +++--- arch/arm/lib/bootm.c | 4 ++-- arch/arm/lib/semihosting.c | 2 +- common/board_f.c | 2 +- common/board_r.c | 2 +- doc/README.arm64 | 4 ++-- drivers/net/smc91111.h | 4 ++-- examples/standalone/stubs.c | 2 +- 18 files changed, 34 insertions(+), 34 deletions(-) diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index 5a4ac2f..3b891bf 100644 --- a/arch/arm/include/asm/cache.h +++ b/arch/arm/include/asm/cache.h @@ -11,7 +11,7 @@ #include <asm/system.h> -#ifndef CONFIG_ARM64 +#ifndef __aarch64__ /* * Invalidate L2 Cache using co-proc instruction diff --git a/arch/arm/include/asm/config.h b/arch/arm/include/asm/config.h index 7a34a01..319451d 100644 --- a/arch/arm/include/asm/config.h +++ b/arch/arm/include/asm/config.h @@ -10,7 +10,7 @@ #define CONFIG_LMB #define CONFIG_SYS_BOOT_RAMDISK_HIGH -#ifdef CONFIG_ARM64 +#ifdef __aarch64__ #define CONFIG_PHYS_64BIT #define CONFIG_STATIC_RELA #endif diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index 438f128..3f12e36 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -61,7 +61,7 @@ static inline gd_t *get_gd(void) { gd_t *gd_ptr; -#ifdef CONFIG_ARM64 +#ifdef __aarch64__ /* * Make will already error that reserving x18 is not supported at the * time of writing, clang: error: unknown argument: '-ffixed-x18' @@ -76,7 +76,7 @@ static inline gd_t *get_gd(void) #else -#ifdef CONFIG_ARM64 +#ifdef __aarch64__ #define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("x18") #else #define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r9") diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h index 1c8c425..781497d 100644 --- a/arch/arm/include/asm/macro.h +++ b/arch/arm/include/asm/macro.h @@ -54,7 +54,7 @@ bcs 1b .endm -#ifdef CONFIG_ARM64 +#ifdef __aarch64__ /* * Register aliases. */ @@ -198,7 +198,7 @@ lr .req x30 .endm #endif -#endif /* CONFIG_ARM64 */ +#endif /* __aarch64__ */ #endif /* __ASSEMBLY__ */ #endif /* __ASM_ARM_MACRO_H__ */ diff --git a/arch/arm/include/asm/proc-armv/ptrace.h b/arch/arm/include/asm/proc-armv/ptrace.h index 71df5a9..dd58324 100644 --- a/arch/arm/include/asm/proc-armv/ptrace.h +++ b/arch/arm/include/asm/proc-armv/ptrace.h @@ -10,7 +10,7 @@ #ifndef __ASM_PROC_PTRACE_H #define __ASM_PROC_PTRACE_H -#ifdef CONFIG_ARM64 +#ifdef __aarch64__ #define PCMASK 0 @@ -27,7 +27,7 @@ struct pt_regs { #endif /* __ASSEMBLY__ */ -#else /* CONFIG_ARM64 */ +#else /* __aarch64__ */ #define USR26_MODE 0x00 #define FIQ26_MODE 0x01 @@ -125,6 +125,6 @@ static inline int valid_user_regs(struct pt_regs *regs) #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_ARM64 */ +#endif /* __aarch64__ */ #endif diff --git a/arch/arm/include/asm/proc-armv/system.h b/arch/arm/include/asm/proc-armv/system.h index c61374e..79231b1 100644 --- a/arch/arm/include/asm/proc-armv/system.h +++ b/arch/arm/include/asm/proc-armv/system.h @@ -13,7 +13,7 @@ /* * Save the current interrupt enable state & disable IRQs */ -#ifdef CONFIG_ARM64 +#ifdef __aarch64__ /* * Save the current interrupt enable state @@ -65,7 +65,7 @@ : "memory"); \ }) -#else /* CONFIG_ARM64 */ +#else /* __aarch64__ */ #define local_irq_save(x) \ ({ \ @@ -161,10 +161,10 @@ : "r" (x) \ : "memory") -#endif /* CONFIG_ARM64 */ +#endif /* __aarch64__ */ #if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110) || \ - defined(CONFIG_ARM64) + defined(__aarch64__) /* * On the StrongARM, "swp" is terminally broken since it bypasses the * cache totally. This means that the cache becomes inconsistent, and, diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 3b0fd0d..cc40197 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -1,7 +1,7 @@ #ifndef __ASM_ARM_SYSTEM_H #define __ASM_ARM_SYSTEM_H -#ifdef CONFIG_ARM64 +#ifdef __aarch64__ /* * SCTLR_EL1/SCTLR_EL2/SCTLR_EL3 bits definitions @@ -80,7 +80,7 @@ void smp_kick_all_cpus(void); #endif /* __ASSEMBLY__ */ -#else /* CONFIG_ARM64 */ +#else /* __aarch64__ */ #ifdef __KERNEL__ @@ -221,6 +221,6 @@ phys_addr_t noncached_alloc(size_t size, size_t align); #endif /* __KERNEL__ */ -#endif /* CONFIG_ARM64 */ +#endif /* __aarch64__ */ #endif diff --git a/arch/arm/include/asm/types.h b/arch/arm/include/asm/types.h index 2326420..fac7cab 100644 --- a/arch/arm/include/asm/types.h +++ b/arch/arm/include/asm/types.h @@ -39,11 +39,11 @@ typedef unsigned int u32; typedef signed long long s64; typedef unsigned long long u64; -#ifdef CONFIG_ARM64 +#ifdef __aarch64__ #define BITS_PER_LONG 64 -#else /* CONFIG_ARM64 */ +#else #define BITS_PER_LONG 32 -#endif /* CONFIG_ARM64 */ +#endif /* Dma addresses are 32-bits wide. */ diff --git a/arch/arm/include/asm/u-boot-arm.h b/arch/arm/include/asm/u-boot-arm.h index f97f3dd..085cd9a 100644 --- a/arch/arm/include/asm/u-boot-arm.h +++ b/arch/arm/include/asm/u-boot-arm.h @@ -52,7 +52,7 @@ void do_software_interrupt(struct pt_regs *pt_regs); void do_prefetch_abort(struct pt_regs *pt_regs); void do_data_abort(struct pt_regs *pt_regs); void do_not_used(struct pt_regs *pt_regs); -#ifdef CONFIG_ARM64 +#ifdef __aarch64__ void do_fiq(struct pt_regs *pt_regs, unsigned int esr); void do_irq(struct pt_regs *pt_regs, unsigned int esr); #else diff --git a/arch/arm/include/asm/u-boot.h b/arch/arm/include/asm/u-boot.h index 43cc494..2dad22f 100644 --- a/arch/arm/include/asm/u-boot.h +++ b/arch/arm/include/asm/u-boot.h @@ -43,7 +43,7 @@ typedef struct bd_info { #endif /* !CONFIG_SYS_GENERIC_BOARD */ /* For image.h:image_check_target_arch() */ -#ifndef CONFIG_ARM64 +#ifndef __aarch64__ #define IH_ARCH_DEFAULT IH_ARCH_ARM #else #define IH_ARCH_DEFAULT IH_ARCH_ARM64 diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index f606255..0ca861b 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -401,7 +401,7 @@ void board_init_f(ulong bootflag) } #endif -#ifndef CONFIG_ARM64 +#ifndef __aarch64__ /* setup stackpointer for exeptions */ gd->irq_sp = addr_sp; #ifdef CONFIG_USE_IRQ @@ -414,10 +414,10 @@ void board_init_f(ulong bootflag) /* 8-byte alignment for ABI compliance */ addr_sp &= ~0x07; -#else /* CONFIG_ARM64 */ +#else /* 16-byte alignment for ABI compliance */ addr_sp &= ~0x0f; -#endif /* CONFIG_ARM64 */ +#endif #else addr_sp += 128; /* leave 32 words for abort-stack */ gd->irq_sp = addr_sp; diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index 0c1298a..ee0035a 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -187,7 +187,7 @@ static void setup_end_tag(bd_t *bd) __weak void setup_board_tags(struct tag **in_params) {} -#ifdef CONFIG_ARM64 +#ifdef __aarch64__ static void do_nonsec_virt_switch(void) { smp_kick_all_cpus(); @@ -260,7 +260,7 @@ bool armv7_boot_nonsec(void) /* Subcommand: GO */ static void boot_jump_linux(bootm_headers_t *images, int flag) { -#ifdef CONFIG_ARM64 +#ifdef __aarch64__ void (*kernel_entry)(void *fdt_addr, void *res0, void *res1, void *res2); int fake = (flag & BOOTM_STATE_OS_FAKE_GO); diff --git a/arch/arm/lib/semihosting.c b/arch/arm/lib/semihosting.c index fd6d857..ab1d865 100644 --- a/arch/arm/lib/semihosting.c +++ b/arch/arm/lib/semihosting.c @@ -29,7 +29,7 @@ static long smh_trap(unsigned int sysnum, void *addr) { register long result asm("r0"); -#if defined(CONFIG_ARM64) +#if defined(__aarch64__) asm volatile ("hlt #0xf000" : "=r" (result) : "0"(sysnum), "r"(addr)); #else /* Note - untested placeholder */ diff --git a/common/board_f.c b/common/board_f.c index 7953137..ba8bd6d 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -595,7 +595,7 @@ static int reserve_stacks(void) * TODO(sjg(a)chromium.org): Perhaps create arch_reserve_stack() * to handle this and put in arch/xxx/lib/stack.c */ -# if defined(CONFIG_ARM) && !defined(CONFIG_ARM64) +# if defined(CONFIG_ARM) # ifdef CONFIG_USE_IRQ gd->start_addr_sp -= (CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ); debug("Reserving %zu Bytes for IRQ stack at: %08lx\n", diff --git a/common/board_r.c b/common/board_r.c index 68a9448..9f6db6c 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -866,7 +866,7 @@ void board_init_r(gd_t *new_gd, ulong dest_addr) int i; #endif -#if !defined(CONFIG_X86) && !defined(CONFIG_ARM) && !defined(CONFIG_ARM64) +#if !defined(CONFIG_X86) && !defined(CONFIG_ARM) gd = new_gd; #endif diff --git a/doc/README.arm64 b/doc/README.arm64 index 75586db..bbfe08c 100644 --- a/doc/README.arm64 +++ b/doc/README.arm64 @@ -33,8 +33,8 @@ Notes 5. Generic board is supported. -6. CONFIG_ARM64 instead of CONFIG_ARMV8 is used to distinguish aarch64 and - aarch32 specific codes. +6. __arch64__ is used to distinguish aarch64 and aarch32 specific codes. + CONFIG_ARM64 is used in makefile to select specific source files. Contributor =========== diff --git a/drivers/net/smc91111.h b/drivers/net/smc91111.h index e19c491..2e57b8d 100644 --- a/drivers/net/smc91111.h +++ b/drivers/net/smc91111.h @@ -277,7 +277,7 @@ struct smc91111_priv{ #define SMC_inw(a,r) (*((volatile word *)((a)->iobase+((r)<<1)))) #elif CONFIG_BLACKFIN #define SMC_inw(a,r) ({ word __v = (*((volatile word *)((a)->iobase+(r)))); SSYNC(); __v;}) -#elif CONFIG_ARM64 +#elif __aarch64__ #define SMC_inw(a, r) (*((volatile word*)((a)->iobase+((dword)(r))))) #else #define SMC_inw(a, r) (*((volatile word*)((a)->iobase+(r)))) @@ -291,7 +291,7 @@ struct smc91111_priv{ ({ (*((volatile word*)((a)->iobase+((r)))) = d); \ SSYNC(); \ }) -#elif CONFIG_ARM64 +#elif __aarch64__ #define SMC_outw(a, d, r) \ (*((volatile word*)((a)->iobase+((dword)(r)))) = d) #else diff --git a/examples/standalone/stubs.c b/examples/standalone/stubs.c index 920a0a9..a42c23e 100644 --- a/examples/standalone/stubs.c +++ b/examples/standalone/stubs.c @@ -38,7 +38,7 @@ gd_t *global_data; " bctr\n" \ : : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "r11"); #elif defined(CONFIG_ARM) -#ifdef CONFIG_ARM64 +#ifdef __aarch64__ /* * x18 holds the pointer to the global_data, x9 is a call-clobbered * register -- 1.7.9.5

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[U-Boot] [PATCH] Don't apply: tools: add a tool to move automatically CONFIGs from headers to defconfigs
by Masahiro Yamada 27 May '15

27 May '15

This tool can move CONFIG macros from C headers (include/configs/*.h) to defconfigs (configs/*_defconfig) all over the boards. There are tons of CONFIGs in U-boot and moving them by hand is absolutely tool painful. I wrote this script for my local use, so this patch might not clean enough to be applied to the code base. It might contain some bugs. Please do not apply this patch! This patch is here because Simon requested me to share it. See the discussion in here: http://lists.denx.de/pipermail/u-boot/2015-January/201556.html Usage: [1] Please run "git status" and make sure your git repository is clean. [2] Describe the CONFIG option you want move in the file "~/.moveconfig" Say, you want to move CONFIG_CMD_NAND, for example. In this case, the content of "~/.moveconfig" should be like this: $ cat .moveconfig CONFIG_CMD_NAND bool n y - The first field is the name of the CONFIG. - The second field is the type of the CONFIG such as "bool", "int", "hex", etc. - The third value is the default value. The value that is same as the default is omitted in each defconfig. If the type of the CONFIG is bool, the default value must be either 'y' or 'n'. - The forth field shows whether the CONFIG depends on CONFIG_SPL_BUILD. For example, CONFIG_CMD_* makes sense only on the main-image. (depends on !SPL_BUILD) In this case, specify 'y' in the forth fields. If the CONFIG should appear also on SPL, specify 'n' here. [4] Run "tools/moveconfig.py" The log will be displayed like this $ tools/moveconfig.py Moving CONFIG_CMD_NAND (type: bool, default: n, no_spl: y) ... (jobs: 8) ms7750se : (default) davinci_sonata : (default) tk71 : y db-mv784mp-gp : (default) cm_t3517 : y P2041RDB_SDCARD : y ... The left-hand side field is the board[defconfig] name and the colon is followed by the value of the CONFIG. At the last stage, you will be asked like this: Clean up CONFIG_CMD_NAND in headers? [y/n]: If you say 'y' here, the defines in C headers will be removed. Enjoy! Signed-off-by: Masahiro Yamada <yamada.m(a)jp.panasonic.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Alexey Brodkin <abrodkin(a)synopsys.com> --- tools/moveconfig.py | 439 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 439 insertions(+) create mode 100755 tools/moveconfig.py diff --git a/tools/moveconfig.py b/tools/moveconfig.py new file mode 100755 index 0000000..cb7f7ea --- /dev/null +++ b/tools/moveconfig.py @@ -0,0 +1,439 @@ +#!/usr/bin/env python +# +# Author: Masahiro Yamada <yamada.m(a)jp.panasonic.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +""" +Move the specified config option to Kconfig +""" + +import errno +import fnmatch +import multiprocessing +import optparse +import os +import re +import shutil +import subprocess +import sys +import tempfile +import time + +SHOW_GNU_MAKE = 'scripts/show-gnu-make' +SLEEP_TIME=0.03 + +CROSS_COMPILE = { + 'aarch64': 'aarch64-linux-', + 'arm': 'arm-unknown-linux-gnueabi-', + 'avr32': 'avr32-linux-', + 'blackfin': 'bfin-elf-', + 'm68k': 'm68k-linux-', + 'microblaze': 'microblaze-linux-', + 'mips': 'mips-linux-', + 'nds32': 'nds32le-linux-', + 'nios2': 'nios2-linux-', + 'openrisc': 'or32-linux-', + 'powerpc': 'powerpc-linux-', + 'sh': 'sh4-gentoo-linux-gnu-', + 'sparc': 'sparc-linux-', + 'x86': 'i386-linux-' +} + +STATE_IDLE = 0 +STATE_DEFCONFIG = 1 +STATE_SILENTOLDCONFIG = 2 + +### helper functions ### +def get_devnull(): + """Get the file object of '/dev/null' device.""" + try: + devnull = subprocess.DEVNULL # py3k + except AttributeError: + devnull = open(os.devnull, 'wb') + return devnull + +def check_top_directory(): + """Exit if we are not at the top of source directory.""" + for f in ('README', 'Licenses'): + if not os.path.exists(f): + sys.exit('Please run at the top of source directory.') + +def get_make_cmd(): + """Get the command name of GNU Make.""" + process = subprocess.Popen([SHOW_GNU_MAKE], stdout=subprocess.PIPE) + ret = process.communicate() + if process.returncode: + sys.exit('GNU Make not found') + return ret[0].rstrip() + +def cleanup_header(header_path, patterns): + with open(header_path) as f: + lines = f.readlines() + + matched = [] + for i, line in enumerate(lines): + for pattern in patterns: + m = pattern.search(line) + if m: + print '%s: %s: %s' % (header_path, i + 1, line), + matched.append(i) + break + + if not matched: + return + + with open(header_path, 'w') as f: + for i, line in enumerate(lines): + if not i in matched: + f.write(line) + +def cleanup_headers(config): + while True: + choice = raw_input('Clean up %s in headers? [y/n]: ' % config).lower() + print choice + if choice == 'y' or choice == 'n': + break + + if choice != 'y': + return + + patterns = [] + patterns.append(re.compile(r'#\s*define\s+%s\W' % config)) + patterns.append(re.compile(r'#\s*undef\s+%s\W' % config)) + + for (dirpath, dirnames, filenames) in os.walk('include'): + for filename in filenames: + if not fnmatch.fnmatch(filename, '*~'): + cleanup_header(os.path.join(dirpath, filename), patterns) + +### classes ### +class KconfigParser: + + """A parser of .config file. + + Each line of the output should have the form of: + Status, Arch, CPU, SoC, Vendor, Board, Target, Options, Maintainers + Most of them are extracted from .config file. + MAINTAINERS files are also consulted for Status and Maintainers fields. + """ + + re_arch = re.compile(r'CONFIG_SYS_ARCH="(.*)"') + re_cpu = re.compile(r'CONFIG_SYS_CPU="(.*)"') + PREFIX = { '.': '+', 'spl': 'S', 'tpl': 'T' } + + def __init__(self, build_dir, config_attr): + """Create a new .config perser. + + Arguments: + build_dir: Build directory where .config is located + output: File object which the result is written to + """ + self.build_dir = build_dir + self.config = config_attr['config'] + self.type = config_attr['type'] + self.default = config_attr['default'] + if config_attr['no_spl_support'] == 'y': + self.no_spl_support = True + else: + self.no_spl_support = False + self.re = re.compile(r'%s=(.*)' % self.config) + + def get_cross_compile(self): + """Parse .config file and return CROSS_COMPILE + + Arguments: + defconfig: Board (defconfig) name + """ + arch = '' + cpu = '' + dotconfig = os.path.join(self.build_dir, '.config') + for line in open(dotconfig): + m = self.re_arch.match(line) + if m: + arch = m.group(1) + continue + m = self.re_cpu.match(line) + if m: + cpu = m.group(1) + + assert arch, 'Error: arch is not defined in %s' % defconfig + + # fix-up for aarch64 + if arch == 'arm' and cpu == 'armv8': + arch = 'aarch64' + + return CROSS_COMPILE.get(arch, '') + + def update_defconfig(self, defconfig): + values = [] + output_lines = [] + prefixes = {} + + if self.no_spl_support: + images = ('.') + else: + images = ('.', 'spl', 'tpl') + + + for img in images: + autoconf = os.path.join(self.build_dir, img, 'include', + 'autoconf.mk') + + if not os.path.exists(autoconf): + values.append('') + continue + + if self.type == 'bool': + value = 'n' + else: + value = '(undef)' + + for line in open(autoconf): + m = self.re.match(line) + if m: + value = m.group(1) + break + + if value == self.default: + value = '(default)' + + values.append(value) + os.remove(autoconf) + + if value == '(undef)' or value == '(default)': + continue + + if self.type == 'bool' and value == 'n': + output_line = '# %s is not set' % (self.config) + else: + output_line = '%s=%s' % (self.config, value) + if output_line in output_lines: + prefixes[output_line] += self.PREFIX[img] + else: + output_lines.append(output_line) + prefixes[output_line] = self.PREFIX[img] + + output = defconfig[:-len('_defconfig')].ljust(37) + ': ' + for value in values: + output += value.ljust(12) + + print output.strip() + + with open(os.path.join('configs', defconfig), 'a') as f: + for line in output_lines: + if prefixes[line] != '+': + line = prefixes[line] + ':' + line + f.write(line + '\n') + +class Slot: + + """A slot to store a subprocess. + + Each instance of this class handles one subprocess. + This class is useful to control multiple processes + for faster processing. + """ + + def __init__(self, config_attr, devnull, make_cmd): + """Create a new slot. + + Arguments: + output: File object which the result is written to + """ + self.build_dir = tempfile.mkdtemp() + self.devnull = devnull + self.make_cmd = (make_cmd, 'O=' + self.build_dir) + self.parser = KconfigParser(self.build_dir, config_attr) + self.state = STATE_IDLE + + def __del__(self): + """Delete the working directory""" + if self.state != STATE_IDLE: + while self.ps.poll() == None: + pass + shutil.rmtree(self.build_dir) + + def add(self, defconfig): + """Add a new subprocess to the slot. + + Fails if the slot is occupied, that is, the current subprocess + is still running. + + Arguments: + defconfig: Board (defconfig) name + + Returns: + Return True on success or False on fail + """ + if self.state != STATE_IDLE: + return False + cmd = list(self.make_cmd) + cmd.append(defconfig) + self.ps = subprocess.Popen(cmd, stdout=self.devnull) + self.defconfig = defconfig + self.state = STATE_DEFCONFIG + return True + + def poll(self): + """Check if the subprocess is running and invoke the .config + parser if the subprocess is terminated. + + Returns: + Return True if the subprocess is terminated, False otherwise + """ + if self.state == STATE_IDLE: + return True + + if self.ps.poll() == None: + return False + + if self.ps.poll() != 0: + sys.exit("failed to process '%s'" % self.defconfig) + + if self.state == STATE_SILENTOLDCONFIG: + self.parser.update_defconfig(self.defconfig) + self.state = STATE_IDLE + return True + + cross_compile = self.parser.get_cross_compile() + cmd = list(self.make_cmd) + if cross_compile: + cmd.append('CROSS_COMPILE=%s' % cross_compile) + cmd.append('silentoldconfig') + self.ps = subprocess.Popen(cmd, stdout=self.devnull) + self.state = STATE_SILENTOLDCONFIG + return False + +class Slots: + + """Controller of the array of subprocess slots.""" + + def __init__(self, config_attr, jobs): + """Create a new slots controller. + + Arguments: + jobs: A number of slots to instantiate + """ + self.slots = [] + devnull = get_devnull() + make_cmd = get_make_cmd() + for i in range(jobs): + self.slots.append(Slot(config_attr, devnull, make_cmd)) + + def add(self, defconfig): + """Add a new subprocess if a vacant slot is available. + + Arguments: + defconfig: Board (defconfig) name + + Returns: + Return True on success or False on fail + """ + for slot in self.slots: + if slot.add(defconfig): + return True + return False + + def available(self): + """Check if there is a vacant slot. + + Returns: + Return True if a vacant slot is found, False if all slots are full + """ + for slot in self.slots: + if slot.poll(): + return True + return False + + def empty(self): + """Check if all slots are vacant. + + Returns: + Return True if all slots are vacant, False if at least one slot + is running + """ + ret = True + for slot in self.slots: + if not slot.poll(): + ret = False + return ret + +def move_config(config_attr, jobs=1): + check_top_directory() + print 'Moving %s (type: %s, default: %s, no_spl: %s) ... (jobs: %d)' % ( + config_attr['config'], + config_attr['type'], + config_attr['default'], + config_attr['no_spl_support'], + jobs) + + # All the defconfig files to be processed + defconfigs = [] + for (dirpath, dirnames, filenames) in os.walk('configs'): + dirpath = dirpath[len('configs') + 1:] + for filename in fnmatch.filter(filenames, '*_defconfig'): + if fnmatch.fnmatch(filename, '.*'): + continue + defconfigs.append(os.path.join(dirpath, filename)) + + slots = Slots(config_attr, jobs) + + # Main loop to process defconfig files: + # Add a new subprocess into a vacant slot. + # Sleep if there is no available slot. + for defconfig in defconfigs: + while not slots.add(defconfig): + while not slots.available(): + # No available slot: sleep for a while + time.sleep(SLEEP_TIME) + + # wait until all the subprocesses finish + while not slots.empty(): + time.sleep(SLEEP_TIME) + + cleanup_headers(config_attr['config']) + +def main(): + try: + cpu_count = multiprocessing.cpu_count() + except NotImplementedError: + cpu_count = 1 + + parser = optparse.OptionParser() + # Add options here + parser.add_option('-j', '--jobs', type='int', default=cpu_count, + help='the number of jobs to run simultaneously') + parser.usage += ' config type default no_spl_support' + (options, args) = parser.parse_args() + + args_key = ('config', 'type', 'default', 'no_spl_support') + config_attr = {} + + if len(args) >= len(args_key): + saved_attr = '' + for i, key in enumerate(args_key): + config_attr[key] = args[i] + saved_attr = saved_attr + ' %s' % args[i] + with open('.moveconfig', 'w') as f: + f.write(saved_attr) + elif os.path.exists('.moveconfig'): + f = open('.moveconfig') + try: + saved_attr = f.readline().split() + for i, key in enumerate(args_key): + config_attr[key] = saved_attr[i] + except: + sys.exit('%s: broken format' % '.moveconfig') + else: + parser.print_usage() + sys.exit(1) + + if not config_attr['config'].startswith('CONFIG_'): + config_attr['config'] = 'CONFIG_' + config_attr['config'] + + move_config(config_attr, options.jobs) + +if __name__ == '__main__': + main() -- 1.9.1

5 81

[U-Boot] [PATCH 0/20] tegra: Expand Nyan-big support
by Simon Glass 20 May '15

20 May '15

This series expands Nyan-big support: - Enable Chrome OS EC, so that the keyboard works - Add some extra clock and pre-kernel init required for reliable operation - Add Chrome OS environment variables, including 'run nvboot' to allow booting Chrome OS more easily Still missing are audio and USB. Doug Anderson (1): Add Chrome OS config header Simon Glass (19): dm: spi: Avoid setting the speed with every transfer cros_ec: Show the protocol version in the debug message cros_ec: Handle the single duplex requirement in cros_ec tegra: Provide more accurate microsecond time tegra: cros_ec: Add tegra support for Chrome OS EC tegra: spi: Drop the claim_bus() method to correct delays dm: tegra: cros_ec: Enable Chrome OS EC on Nyan-big dm: gpio: Add an implementation for gpio_get_number() tegra: spi: Support slow SPI rates tegra: clock: Support enabling external clocks tegra: clock: Adjust PLL access to avoid a warning tegra: Introduce SRAM repair on tegra124 tegra: Add missing tegra124 peripherals tegra: Increase maximum arguments to 32 tegra: lcd: Tidy up clock init tegra: Allow board-specific init tegra: nyan-big: Add additional clock and kernel init tegra: config: Allow Chrome OS environment settings to be included tegra: config: nyan-big: Add options required by Chrome OS boot arch/arm/cpu/tegra-common/Makefile | 1 + arch/arm/cpu/tegra-common/clock.c | 24 +- arch/arm/cpu/tegra-common/powergate.c | 20 +- arch/arm/cpu/tegra-common/timer.c | 87 ++++ arch/arm/cpu/tegra124-common/clock.c | 2 +- arch/arm/dts/tegra124-nyan-big.dts | 6 +- arch/arm/include/asm/arch-tegra/clock.h | 8 + arch/arm/include/asm/arch-tegra/sys_proto.h | 7 + arch/arm/include/asm/arch-tegra124/clock-tables.h | 12 +- arch/arm/include/asm/arch-tegra124/flow.h | 12 + board/nvidia/common/board.c | 8 +- board/nvidia/nyan-big/nyan-big.c | 76 ++++ configs/nyan-big_defconfig | 5 + drivers/gpio/gpio-uclass.c | 12 + drivers/misc/cros_ec.c | 3 +- drivers/misc/cros_ec_spi.c | 23 +- drivers/spi/spi-uclass.c | 9 +- drivers/spi/tegra114_spi.c | 51 +-- drivers/video/tegra124/tegra124-lcd.c | 4 +- include/configs/chromeos.h | 464 ++++++++++++++++++++++ include/configs/nyan-big.h | 8 + include/configs/tegra-common-post.h | 15 +- include/configs/tegra-common.h | 2 +- include/spi.h | 3 + 24 files changed, 804 insertions(+), 58 deletions(-) create mode 100644 arch/arm/cpu/tegra-common/timer.c create mode 100644 include/configs/chromeos.h -- 2.2.0.rc0.207.ga3a616c

5 54

[U-Boot] sunxi: Initial A80 support
by Hans de Goede 19 May '15

19 May '15

Hi Ian, ChenYu, I'm very happy to present this patch series which adds initial A80 support, with this series a u-boot.bin can be build which can then be fel booted using Allwinners boot0 fel binary, and then can load linux from a sdcard using a standard extlinux.conf setup. Next step getting RSB going and finding out how the 2 pmics are hooked up, and then slowly work towards getting SPL going. Ian, as always, can you please review these patches ? ChenYu, if you want to play with this, it is probably easiest to use my sunxi-wip branch. Regards, Hans

3 35

[U-Boot] [PATCH 0/2 v3] arm: socfpga: Add Cadence QSPI support
by Stefan Roese 15 May '15

15 May '15

Hi! So this is my 3rd posting regarding the Candence SPI driver on SoCFPGA. The current status is, that SPI NOR flash works now without problems. And dcache is still enabled. The previous disabling was not needed. And only caused problems while booting into Linux. No cache flush or invalidate is needed. As no DMA engine is involved in this transfer. The "solution" I used to get SPI NOR flash support working now is implemented in patch 0004 (still marked as RFC). Here a software reset is issued on the Micron N25Q256A SPI NOR flash. This seems to solve all problems and reading / writing to the SPI NOR flash seems to work now just fine. Even rebooting via pushbutton-reset or reset command works. I think this version is now in much better state. Thats why I removed the WIP from the subject lines. Again, this is tested on the EBV SoCrates eval board. Thanks, Stefan Cc: Chin Liang See <clsee(a)altera.com> Cc: Dinh Nguyen <dinguyen(a)altera.com> Cc: Vince Bridgers <vbridger(a)altera.com> Cc: Marek Vasut <marex(a)denx.de> Cc: Pavel Machek <pavel(a)denx.de> Cc: Michael Trimarchi <michael(a)amarulasolutions.com> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki(a)gmail.com>

5 45

[U-Boot] [PATCH] am33xx, spl, siemens: enable debug uart output again
by Heiko Schocher 15 May '15

15 May '15

a6b541b090: TI ARMv7: Don't use GD before crt0.S has set it moves the init of the debug uart at the very end of SPL code. Enable it for the siemens board earlier, as they print ddr settings ... all debug output before board_init_r() is here currently useless. Maybe we must rework this globally? Signed-off-by: Heiko Schocher <hs(a)denx.de> --- board/siemens/common/board.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/board/siemens/common/board.c b/board/siemens/common/board.c index cc0ac6b..fb2de48 100644 --- a/board/siemens/common/board.c +++ b/board/siemens/common/board.c @@ -43,6 +43,11 @@ void set_mux_conf_regs(void) /* Initalize the board header */ enable_i2c0_pin_mux(); i2c_set_bus_num(0); + + /* enable early the console */ + gd->baudrate = CONFIG_BAUDRATE; + serial_init(); + gd->have_console = 1; if (read_eeprom() < 0) puts("Could not get board ID.\n"); -- 2.1.0

3 14

[U-Boot] [PATCH V2] sf: Add support for flag status register on Micron chips
by Hou Zhiqiang 09 May '15

09 May '15

Enter 3 Byte address mode at first, because it may change to 4 Byte address mode in kernel driver and not reset to 3 Byte address mode after reboot. Add clear flag status register operation that some Micron SPI flash chips required after reading the flag status register to check some operations completion. Signed-off-by: Hou Zhiqiang <B48286(a)freescale.com> Signed-off-by: Mingkai.Hu <Mingkai.Hu(a)freescale.com> --- V1: Based on git://git.denx.de/u-boot.git. Also can be applied to git://www.denx.de/git/u-boot-mpc85xx.git. Tested on board T2080QDS and T2080RDB. V2: Add the operation of enter 3 Byte address mode in probe. drivers/mtd/spi/sf_internal.h | 17 ++++++++++++ drivers/mtd/spi/sf_ops.c | 64 +++++++++++++++++++++++++++++++++++++------ drivers/mtd/spi/sf_probe.c | 5 ++++ 3 files changed, 78 insertions(+), 8 deletions(-) diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index 19d4914..49e5a2c 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -36,6 +36,11 @@ #define CMD_WRITE_ENABLE 0x06 #define CMD_READ_CONFIG 0x35 #define CMD_FLAG_STATUS 0x70 +#define CMD_CLEAR_FLAG_STATUS 0x50 + +/* Used for Macronix and Winbond flashes */ +#define CMD_ENTER_4B_ADDR 0xB7 +#define CMD_EXIT_4B_ADDR 0xE9 /* Read commands */ #define CMD_READ_ARRAY_SLOW 0x03 @@ -59,6 +64,8 @@ #define STATUS_QEB_WINSPAN (1 << 1) #define STATUS_QEB_MXIC (1 << 6) #define STATUS_PEC (1 << 7) +#define STATUS_PROT (1 << 1) +#define STATUS_ERASE (1 << 5) #ifdef CONFIG_SYS_SPI_ST_ENABLE_WP_PIN #define STATUS_SRWD (1 << 7) /* SR write protect */ @@ -124,6 +131,12 @@ static inline int spi_flash_cmd_write_disable(struct spi_flash *flash) return spi_flash_cmd(flash->spi, CMD_WRITE_DISABLE, NULL, 0); } +/* Clear flag status register */ +static inline int spi_flash_cmd_clear_flag_status(struct spi_flash *flash) +{ + return spi_flash_cmd(flash->spi, CMD_CLEAR_FLAG_STATUS, NULL, 0); +} + /* * Send the read status command to the device and wait for the wip * (write-in-progress) bit to clear itself. @@ -160,4 +173,8 @@ int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, size_t len, void *data); +#if defined(CONFIG_SPI_FLASH_STMICRO) +int spi_flash_cmd_4B_addr_switch(struct spi_flash *flash, int enable); +#endif + #endif /* _SF_INTERNAL_H_ */ diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c index 85cf22d..8a532b8 100644 --- a/drivers/mtd/spi/sf_ops.c +++ b/drivers/mtd/spi/sf_ops.c @@ -93,6 +93,30 @@ int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc) } #endif +#if defined(CONFIG_SPI_FLASH_STMICRO) +int spi_flash_cmd_4B_addr_switch(struct spi_flash *flash, int enable) +{ + int ret; + u8 cmd; + + cmd = enable ? CMD_ENTER_4B_ADDR : CMD_EXIT_4B_ADDR; + + ret = spi_claim_bus(flash->spi); + if (ret) { + debug("SF: unable to claim SPI bus\n"); + return ret; + } + + ret = spi_flash_cmd_write_enable(flash); + if (ret < 0) { + debug("SF: enabling write failed\n"); + return ret; + } + + return spi_flash_cmd(flash->spi, cmd, NULL, 0); +} +#endif + #ifdef CONFIG_SPI_FLASH_BAR static int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel) { @@ -160,6 +184,7 @@ int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout) unsigned long timebase; unsigned long flags = SPI_XFER_BEGIN; int ret; + int out_of_time = 1; u8 status; u8 check_status = 0x0; u8 poll_bit = STATUS_WIP; @@ -186,22 +211,45 @@ int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout) WATCHDOG_RESET(); ret = spi_xfer(spi, 8, NULL, &status, 0); - if (ret) + if (ret) { + spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END); return -1; + } - if ((status & poll_bit) == check_status) + if ((status & poll_bit) == check_status) { + out_of_time = 0; break; + } } while (get_timer(timebase) < timeout); spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END); - if ((status & poll_bit) == check_status) - return 0; + if (out_of_time) { + /* Timed out */ + debug("SF: time out!\n"); + if (cmd == CMD_FLAG_STATUS) { + if (spi_flash_cmd_clear_flag_status(flash) < 0) + debug("SF: clear flag status failed\n"); + } + ret = -1; + } +#ifdef CONFIG_SPI_FLASH_STMICRO + else if (cmd == CMD_FLAG_STATUS) { + if (!(status & (STATUS_PROT | STATUS_ERASE))) { + ret = 0; + } else { + debug("SF: flag status error"); + ret = -1; + } - /* Timed out */ - debug("SF: time out!\n"); - return -1; + if (spi_flash_cmd_clear_flag_status(flash) < 0) { + debug("SF: clear flag status failed\n"); + ret = -1; + } + } +#endif + return ret; } int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd, @@ -234,7 +282,7 @@ int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd, ret = spi_flash_cmd_wait_ready(flash, timeout); if (ret < 0) { - debug("SF: write %s timed out\n", + debug("SF: write %s failed\n", timeout == SPI_FLASH_PROG_TIMEOUT ? "program" : "page erase"); return ret; diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c index 4d148d1..79b876d 100644 --- a/drivers/mtd/spi/sf_probe.c +++ b/drivers/mtd/spi/sf_probe.c @@ -221,6 +221,11 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi, #ifdef CONFIG_SPI_FLASH_STMICRO if (params->flags & E_FSR) flash->poll_cmd = CMD_FLAG_STATUS; + + if (flash->size > SPI_FLASH_16MB_BOUN) { + if (spi_flash_cmd_4B_addr_switch(flash, 0) < 0) + debug("SF: enter 3B address mode failed\n"); + } #endif /* Configure the BAR - discover bank cmds and read current bank */ -- 2.1.0.27.g96db324

3 2

[U-Boot] Recommended SH toolchain
by Vasili Galka 08 May '15

08 May '15

Hi Nobuhiro, I'm trying to verify the correct build of all SH boards in U-Boot. What is the recommended toolchain to use? I tried the one from kernel.org [1], but it does not work for all the boards, I get build errors like this one: Building rsk7203 board... sh4-linux-gcc: error: command line option '-m3e' is not supported by this configuration sh4-linux-gcc: error: command line option '-m3e' is not supported by this configuration make[3]: *** [include/autoconf.mk] Error 1 make[3]: *** [include/autoconf.mk.dep] Error 1 make[2]: *** [silentoldconfig] Error 1 make: *** [sub-make] Error 2 sh4-linux-size: '/home/lab/dev/u-boot/out/all_sh/u-boot': No such file sh4-linux-gcc: error: command line option '-m3e' is not supported by this configuration sh4-linux-gcc: error: command line option '-m3e' is not supported by this configuration make[3]: *** [include/autoconf.mk] Error 1 make[3]: *** Waiting for unfinished jobs.... make[3]: *** [include/autoconf.mk.dep] Error 1 'make -f /home/lab/dev/u-boot/scripts/Makefile.autoconf obj=include include/autoconf.mk include/autoconf.mk.dep' Failed make[2]: *** [silentoldconfig] Error 1 make[1]: *** No rule to make target `include/config/auto.conf', needed by `include/config/uboot.release'. Stop. make: *** [sub-make] Error 2 I'll appreciate your help. [1] https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.6.3/ Regards, Vasili

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[U-Boot] [PATCH v2 0/9] PSCI v0.2 framework for ARMv8
by Arnab Basu 08 May '15

08 May '15

Apologies for the long delay, this is v2 of the series of patches that creates a generic PSCI v0.2 framework for ARMv8. The first 3 patches refactor existing code so that ARMv7 PSCI, ARMv8 spin-table and ARMv8 PSCI can coexist. The 4th patch modifies the spin table implementation for the ARMv8 foundation model to create per cpu release addresses The next 5 patches create a generic framework for PSCI v0.2 in ARMv8. The implementation is modelled on the pre-existing PSCI v0.1 support in ARMv7. PSCI support patches for the ARMv8 Foundation model that implement the mandatory PSCI functions and enable PCSI will follow very soon. Arnab Basu (9): ARM: PSCI: Update psci.h for psci v0.2 ARM: PSCI: Alow arch specific DT patching ARMv8/fsl-lsch3: Refactor spin-table code vexpress_aemv8a: Add spin table handling with per cpu release addresses ARMv8: PSCI: Add linker section to hold PSCI code ARMv8: PCSI: Add generic ARMv8 PSCI code ARMv8: PSCI: Fixup the device tree for PSCI v0.2 ARMv8: PSCI: Setup ARMv8 PSCI ARMv8: PSCI: Enable SMC arch/arm/config.mk | 2 +- arch/arm/cpu/armv7/virt-dt.c | 7 +- arch/arm/cpu/armv8/Makefile | 4 +- arch/arm/cpu/armv8/cpu-dt.c | 189 +++++++++++++++++++++++++++++++++++++ arch/arm/cpu/armv8/cpu.c | 136 ++++++++++++++++++++++++++ arch/arm/cpu/armv8/fsl-lsch3/fdt.c | 48 ++++------ arch/arm/cpu/armv8/psci.S | 168 +++++++++++++++++++++++++++++++++ arch/arm/cpu/armv8/start.S | 141 ++++++++++++++++++++------- arch/arm/cpu/armv8/u-boot.lds | 30 ++++++ arch/arm/include/asm/armv8/esr.h | 12 +++ arch/arm/include/asm/armv8/mp.h | 36 +++++++ arch/arm/include/asm/config.h | 1 + arch/arm/include/asm/macro.h | 5 + arch/arm/include/asm/psci.h | 42 ++++++++- arch/arm/include/asm/system.h | 7 ++ arch/arm/lib/bootm-fdt.c | 11 ++- arch/arm/lib/bootm.c | 3 + include/configs/vexpress_aemv8a.h | 2 + 18 files changed, 772 insertions(+), 72 deletions(-) create mode 100644 arch/arm/cpu/armv8/cpu-dt.c create mode 100644 arch/arm/cpu/armv8/psci.S create mode 100644 arch/arm/include/asm/armv8/esr.h create mode 100644 arch/arm/include/asm/armv8/mp.h -- 1.9.1

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