December 2015 - U-Boot

[U-Boot] [PATCH 00/10] Moving Axi emac to DM
by Michal Simek 16 Dec '15

16 Dec '15

Hi, This patch series depends on microblaze cleanup series. All these patches will be available in git://git.denx.de/u-boot-microblaze.git also with patches which I am going to send now. Thanks, Michal Michal Simek (10): net: axi_emac: Fix parentheses around operand ! net: axi_emac: Show phy address instead of register content net: axi_emac: Pass directly pointer to register space net: axi_emac: Put iobase to private structure net: axi_emac: Pass private structure to phyread/phywrite net: axi_emac: Pass private structure where possible net: axi_emac: Move driver to DM net: axi_emac: Enable access to MDIO in probe net: axi_emac: Split recv from free_pkt net: Add axi emac to Kconfig .../xilinx/microblaze-generic/microblaze-generic.c | 5 - board/xilinx/zynq/board.c | 4 - drivers/net/Kconfig | 8 + drivers/net/xilinx_axi_emac.c | 278 +++++++++++++-------- include/netdev.h | 2 - 5 files changed, 183 insertions(+), 114 deletions(-) -- 1.9.1

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[U-Boot] [PATCH 1/5] net: gem: Setup default phy address to -1
by Michal Simek 16 Dec '15

16 Dec '15

Undefined phy address is -1 not 0. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- drivers/net/zynq_gem.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 0a41281e901d..b0755f5e3b48 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -666,11 +666,12 @@ static int zynq_gem_ofdata_to_platdata(struct udevice *dev) priv->iobase = (struct zynq_gem_regs *)pdata->iobase; /* Hardcode for now */ priv->emio = 0; + priv->phyaddr = -1; offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset, "phy-handle"); if (offset > 0) - priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", 0); + priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1); phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL); if (phy_mode) -- 1.9.1

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[U-Boot] [PATCH] driver/ddr/fsl: Add workaround for A009663
by Shengzhou Liu 16 Dec '15

16 Dec '15

Erratum A-009663 workaround requires to set DDR_INTERVAL[BSTOPRE] to 0 before setting DDR_SDRAM_CFG[MEM_EN] and set DDR_INTERVAL[BSTOPRE] to the desired value after DDR initialization has completed. Signed-off-by: Shengzhou Liu <Shengzhou.Liu(a)freescale.com> --- arch/arm/include/asm/arch-fsl-layerscape/config.h | 3 +++ arch/arm/include/asm/arch-ls102xa/config.h | 1 + arch/powerpc/cpu/mpc85xx/cmd_errata.c | 3 +++ arch/powerpc/include/asm/config_mpc85xx.h | 2 ++ drivers/ddr/fsl/fsl_ddr_gen4.c | 10 ++++++++++ include/fsl_ddr_sdram.h | 1 + 6 files changed, 20 insertions(+) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 6e5224e..fac82ff 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -118,6 +118,8 @@ #define CONFIG_SYS_FSL_ERRATUM_A008585 #define CONFIG_SYS_FSL_ERRATUM_A008751 #define CONFIG_SYS_FSL_ERRATUM_A009635 +#define CONFIG_SYS_FSL_ERRATUM_A009663 + #elif defined(CONFIG_LS1043A) #define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_CACHELINE_SIZE 64 @@ -165,6 +167,7 @@ /* Generic Interrupt Controller Definitions */ #define GICD_BASE 0x01401000 #define GICC_BASE 0x01402000 +#define CONFIG_SYS_FSL_ERRATUM_A009663 #else #error SoC not defined diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index f066480..424fe87 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -131,6 +131,7 @@ #define CONFIG_SYS_FSL_SEC_COMPAT 5 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_ERRATUM_A008378 +#define CONFIG_SYS_FSL_ERRATUM_A009663 #else #error SoC not defined #endif diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index a493556..3b06ae4 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -326,6 +326,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #if defined(CONFIG_SYS_FSL_B4860QDS_XFI_ERR) && defined(CONFIG_B4860QDS) puts("Work-around for Erratum XFI on B4860QDS enabled\n"); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A009663 + puts("Work-around for Erratum A009663 enabled\n"); +#endif return 0; } diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 674fac8..eccc146 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -808,6 +808,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define QE_NUM_OF_SNUM 28 #define CONFIG_SYS_FSL_SFP_VER_3_0 #define CONFIG_SYS_FSL_ERRATUM_A008378 +#define CONFIG_SYS_FSL_ERRATUM_A009663 #elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) ||\ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) @@ -856,6 +857,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) #define QE_NUM_OF_SNUM 28 #define CONFIG_SYS_FSL_SFP_VER_3_0 #define CONFIG_SYS_FSL_ERRATUM_A008378 +#define CONFIG_SYS_FSL_ERRATUM_A009663 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) #define CONFIG_E6500 diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c index 3fca5c2..6bd447d 100644 --- a/drivers/ddr/fsl/fsl_ddr_gen4.c +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c @@ -151,7 +151,12 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, ddr_out32(&ddr->sdram_mode_15, regs->ddr_sdram_mode_15); ddr_out32(&ddr->sdram_mode_16, regs->ddr_sdram_mode_16); ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl); +#ifdef CONFIG_SYS_FSL_ERRATUM_A009663 + ddr_out32(&ddr->sdram_interval, + regs->ddr_sdram_interval & ~SDRAM_INTERVAL_BSTOPRE); +#else ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval); +#endif ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init); ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); #ifndef CONFIG_SYS_FSL_DDR_EMU @@ -379,6 +384,11 @@ step2: if (timeout <= 0) printf("Waiting for D_INIT timeout. Memory may not work.\n"); + +#ifdef CONFIG_SYS_FSL_ERRATUM_A009663 + ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval); +#endif + #ifdef CONFIG_DEEP_SLEEP if (is_warm_boot()) { /* exit self-refresh */ diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h index 4b022d4..504903d 100644 --- a/include/fsl_ddr_sdram.h +++ b/include/fsl_ddr_sdram.h @@ -131,6 +131,7 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t; #define SDRAM_CFG2_ODT_ONLY_READ 2 #define SDRAM_CFG2_ODT_ALWAYS 3 +#define SDRAM_INTERVAL_BSTOPRE 0x3FFF #define TIMING_CFG_2_CPO_MASK 0x0F800000 #if defined(CONFIG_SYS_FSL_DDR_VER) && \ -- 2.1.0.27.g96db324

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[U-Boot] [PATCH 1/3] sf: Fix quad bit set for micron devices
by Jagan Teki 16 Dec '15

16 Dec '15

Setting up quad bit for micron devices need to do the same way as other flash devices like spansion, winbond etc does using enhanced volatile config register so this patch adds this support instead of printing "QEB is volatile" Cc: Simon Glass <sjg(a)chromium.org> Cc: Bin Meng <bmeng.cn(a)gmail.com> Cc: Peter Pan <peterpandong(a)micron.com> Cc: Fabio Estevam <fabio.estevam(a)freescale.com> Cc: Michal Simek <michal.simek(a)xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> Signed-off-by: Jagan Teki <jteki(a)openedev.com> --- drivers/mtd/spi/sf_internal.h | 3 +++ drivers/mtd/spi/spi_flash.c | 62 +++++++++++++++++++++++++++++++++++++++++-- 2 files changed, 63 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index 561abc3..55ba81e 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -77,6 +77,7 @@ enum spi_nor_option_flags { #define CMD_WRITE_DISABLE 0x04 #define CMD_WRITE_ENABLE 0x06 #define CMD_QUAD_PAGE_PROGRAM 0x32 +#define CMD_WRITE_EVCR 0x61 /* Read commands */ #define CMD_READ_ARRAY_SLOW 0x03 @@ -90,6 +91,7 @@ enum spi_nor_option_flags { #define CMD_READ_STATUS1 0x35 #define CMD_READ_CONFIG 0x35 #define CMD_FLAG_STATUS 0x70 +#define CMD_READ_EVCR 0x65 /* Bank addr access commands */ #ifdef CONFIG_SPI_FLASH_BAR @@ -104,6 +106,7 @@ enum spi_nor_option_flags { #define STATUS_QEB_WINSPAN BIT(1) #define STATUS_QEB_MXIC BIT(6) #define STATUS_PEC BIT(7) +#define STATUS_QEB_MICRON BIT(7) #define SR_BP0 BIT(2) /* Block protect 0 */ #define SR_BP1 BIT(3) /* Block protect 1 */ #define SR_BP2 BIT(4) /* Block protect 2 */ diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index 6fe8c9d..fc1538c 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -73,6 +73,37 @@ static int write_sr(struct spi_flash *flash, u8 ws) return 0; } +#ifdef CONFIG_SPI_FLASH_STMICRO +static int read_evcr(struct spi_flash *flash, u8 *evcr) +{ + int ret; + const u8 cmd = CMD_READ_EVCR; + + ret = spi_flash_read_common(flash, &cmd, 1, evcr, 1); + if (ret < 0) { + debug("SF: error reading EVCR\n"); + return ret; + } + + return 0; +} + +static int write_evcr(struct spi_flash *flash, u8 evcr) +{ + u8 cmd; + int ret; + + cmd = CMD_WRITE_EVCR; + ret = spi_flash_write_common(flash, &cmd, 1, &evcr, 1); + if (ret < 0) { + debug("SF: error while writing EVCR register\n"); + return ret; + } + + return 0; +} +#endif + #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) static int read_cr(struct spi_flash *flash, u8 *rc) { @@ -843,6 +874,34 @@ static int spansion_quad_enable(struct spi_flash *flash) } #endif +#ifdef CONFIG_SPI_FLASH_STMICRO +static int micron_quad_enable(struct spi_flash *flash) +{ + u8 qeb_status; + int ret; + + ret = read_evcr(flash, &qeb_status); + if (ret < 0) + return ret; + + if (!(qeb_status & STATUS_QEB_MICRON)) + return 0; + + ret = write_evcr(flash, qeb_status & ~STATUS_QEB_MICRON); + if (ret < 0) + return ret; + + /* read EVCR and check it */ + ret = read_evcr(flash, &qeb_status); + if (!(ret > 0 && !(qeb_status & STATUS_QEB_MICRON))) { + printf("SF: Micron EVCR Quad bit not clear\n"); + return -EINVAL; + } + + return ret; +} +#endif + static int set_quad_mode(struct spi_flash *flash, u8 idcode0) { switch (idcode0) { @@ -857,8 +916,7 @@ static int set_quad_mode(struct spi_flash *flash, u8 idcode0) #endif #ifdef CONFIG_SPI_FLASH_STMICRO case SPI_FLASH_CFI_MFR_STMICRO: - debug("SF: QEB is volatile for %02x flash\n", idcode0); - return 0; + return micron_quad_enable(flash); #endif default: printf("SF: Need set QEB func for %02x flash\n", idcode0); -- 1.9.1

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[U-Boot] [PATCH 1/5][v5] armv8: define usec2ticks function
by Aneesh Bansal 16 Dec '15

16 Dec '15

usec2ticks() function has been defined for ARMv8 which will be used by SEC Driver. Signed-off-by: Aneesh Bansal <aneesh.bansal(a)freescale.com> --- Changes in v5: - Commit Subject modified Changes in v4: None Changes in v3: None Changes in v2: None (New Patch set created with an additional patch) arch/arm/cpu/armv8/generic_timer.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/cpu/armv8/generic_timer.c b/arch/arm/cpu/armv8/generic_timer.c index 8e60bae..8f47a82 100644 --- a/arch/arm/cpu/armv8/generic_timer.c +++ b/arch/arm/cpu/armv8/generic_timer.c @@ -40,3 +40,14 @@ unsigned long timer_read_counter(void) #endif return cntpct; } + +unsigned long usec2ticks(unsigned long usec) +{ + ulong ticks; + if (usec < 1000) + ticks = ((usec * (get_tbclk()/1000)) + 500) / 1000; + else + ticks = ((usec / 10) * (get_tbclk() / 100000)); + + return ticks; +} -- 1.8.1.4

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[U-Boot] Please pull u-boot-fsl-qoriq master
by York Sun 16 Dec '15

16 Dec '15

Tom, The following changes since commit 5076c64a08d2083af5a7761b12a30116ef0da967: Merge branch 'master' of git://git.denx.de/u-boot-spi (2015-12-11 15:07:44 -0500) are available in the git repository at: git://git.denx.de/u-boot-fsl-qoriq.git master for you to fetch changes up to 989c5f0a8f8694ac92eb0d6cff8745ae8659364f: armv8: Add sata support on Layerscape ARMv8 board (2015-12-15 08:57:35 +0800) ---------------------------------------------------------------- Alexander Stein (1): fsl_qspi: Pet the watchdog while reading/writing Aneesh Bansal (5): armv8: define usec2ticks function armv8: Make SEC read/write as snoopable for LS1043 include/linux: move typdef for uintptr_t armv8/ls1043ardb: add SECURE BOOT target for NOR drivers/crypto/fsl: fix endianness issue in RNG Pratiyush Mohan Srivastava (1): Enable console log from earlyconsole in Linux bootargs Shaohui Xie (2): freescale: fman: make sure phy-handle property is big endian armv8/ls1043ardb: Add support for >2GB memory Shengzhou Liu (3): arm: ls102x: add get_svr and IS_SVR_REV helper fsl/errata: move fsl_errata.h to common directory fsl/ddr: updated ddr errata-A008378 for arm and power SoCs Tang Yuantian (1): armv8: Add sata support on Layerscape ARMv8 board Tom Rini (2): fsl_*_serdes.c: Modify memset call in serdes_init qbman_portal.c: Update BUG_ON() call in qbman_swp_mc_submit Yao Yuan (5): arm: ls1021a: merge SoC specific code in a separate file arm: ls102xa: enable all the snoop signal for masters. armv7: ls102xa: cci-400: Enable snoop and DVM message requests. armv7/fsl-ls102xa: Workaround for DDR erratum A008514 move erratum a008336 and a008514 to soc specific file York Sun (11): driver/ddr/fsl: Update DDR4 RTT values driver/ddr/fsl: Update DDR4 MR6 for Vref range driver/ddr/fsl: Update MR5 RTT park driver/ddr/fsl: Update workaround for A008511 for vref range driver/ddr/fsl: Update timing config for heavy load armv8/ls2080aqds: Update DDR settings for four chip-select case armv8/ls2080ardb: Update DDR settings for four chip-select case Reserve secure memory armv8: fsl-layerscape: Make DDR non secure in MMU tables common: Rewrite hiding the end of memory armv8: fsl-layerscale: Rewrite reserving memory for MC and debug server README | 14 +- arch/arm/cpu/armv7/ls102xa/Makefile | 1 + arch/arm/cpu/armv7/ls102xa/cpu.c | 8 + arch/arm/cpu/armv7/ls102xa/soc.c | 90 ++++++++ arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 142 ++++++++++-- .../cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c | 2 +- .../cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c | 2 +- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 85 +++++++ arch/arm/cpu/armv8/generic_timer.c | 11 + arch/arm/include/asm/arch-fsl-layerscape/config.h | 14 +- arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 14 +- .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 2 +- .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 4 + arch/arm/include/asm/arch-fsl-layerscape/soc.h | 31 +++ arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 13 +- arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h | 12 + arch/arm/include/asm/fsl_secure_boot.h | 6 +- arch/powerpc/cpu/mpc85xx/cmd_errata.c | 2 +- arch/powerpc/cpu/mpc85xx/cpu_init.c | 2 +- arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c | 4 +- arch/powerpc/include/asm/config_mpc85xx.h | 2 + board/freescale/common/fman.c | 2 + board/freescale/common/fsl_validate.c | 34 ++- board/freescale/ls1021aqds/ls1021aqds.c | 49 +--- board/freescale/ls1021atwr/ls1021atwr.c | 42 +--- board/freescale/ls1043aqds/ddr.c | 9 + board/freescale/ls1043ardb/MAINTAINERS | 5 + board/freescale/ls1043ardb/ddr.c | 24 +- board/freescale/ls1043ardb/ls1043ardb.c | 28 ++- board/freescale/ls2080a/ddr.c | 15 ++ board/freescale/ls2080a/ls2080a.c | 17 -- board/freescale/ls2080aqds/ddr.c | 31 ++- board/freescale/ls2080aqds/ls2080aqds.c | 17 -- board/freescale/ls2080ardb/ddr.c | 31 ++- board/freescale/ls2080ardb/ls2080ardb.c | 17 -- common/board_f.c | 32 ++- common/cmd_bdinfo.c | 6 + common/cmd_blob.c | 6 +- configs/ls1043ardb_SECURE_BOOT_defconfig | 9 + drivers/crypto/fsl/jr.c | 8 +- drivers/ddr/fsl/ctrl_regs.c | 48 +++- drivers/ddr/fsl/fsl_ddr_gen4.c | 65 ++---- drivers/ddr/fsl/options.c | 237 +++++++++++++++++++- drivers/net/fsl-mc/dpio/qbman_portal.c | 2 +- drivers/spi/fsl_qspi.c | 5 + include/asm-generic/global_data.h | 14 ++ include/compiler.h | 3 - include/configs/ls1043a_common.h | 1 + include/configs/ls1043aqds.h | 17 ++ include/configs/ls1043ardb.h | 12 +- include/configs/ls2080a_common.h | 11 +- include/configs/ls2080aqds.h | 18 ++ include/configs/ls2080ardb.h | 20 +- include/fsl_ddr_sdram.h | 9 + {arch/powerpc/include/asm => include}/fsl_errata.h | 47 +++- include/fsl_validate.h | 9 +- include/linux/types.h | 1 + 57 files changed, 1079 insertions(+), 283 deletions(-) create mode 100644 arch/arm/cpu/armv7/ls102xa/soc.c create mode 100644 arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h create mode 100644 configs/ls1043ardb_SECURE_BOOT_defconfig rename {arch/powerpc/include/asm => include}/fsl_errata.h (57%) Thanks. York

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[U-Boot] [PATCH 1/5] common: env_mmc: support loading env from different cards
by Peng Fan 16 Dec '15

16 Dec '15

Some boards support booting from different SD card slots. For example, mx6dpsabresd board supports booting from SD2, SD3, EMMC4, using different boot switch. And the index numbers are SD2(0), SD3(1), EMMC4(2). But CONFIG_SYS_MMC_ENV_DEV is hardcoded to 1(for SD3), so when booting from SD2(using 0), uboot complains "MMC: no card present", since there is no card in SD3 slot. This patch introduces a weak function which still returns CONFIG_SYS_MMC_ENV_DEV to avoid break other boards. Then different boards can implement mmc_get_env_devno to read env from the correct sd/emmc. Signed-off-by: Peng Fan <Peng.Fan(a)freescale.com> Cc: Stefano Babic <sbabic(a)denx.de> Cc: Simon Glass <sjg(a)chromium.org> Cc: Tim Harvey <tharvey(a)gateworks.com> Cc: Hans de Goede <hdegoede(a)redhat.com> --- common/env_mmc.c | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/common/env_mmc.c b/common/env_mmc.c index 9639822..d2e2a40 100644 --- a/common/env_mmc.c +++ b/common/env_mmc.c @@ -63,6 +63,11 @@ int env_init(void) return 0; } +__weak uint mmc_get_env_devno(void) +{ + return CONFIG_SYS_MMC_ENV_DEV; +} + #ifdef CONFIG_SYS_MMC_ENV_PART __weak uint mmc_get_env_part(struct mmc *mmc) { @@ -72,7 +77,7 @@ __weak uint mmc_get_env_part(struct mmc *mmc) static int mmc_set_env_part(struct mmc *mmc) { uint part = mmc_get_env_part(mmc); - int dev = CONFIG_SYS_MMC_ENV_DEV; + int dev = mmc_get_env_devno(); int ret = 0; #ifdef CONFIG_SPL_BUILD @@ -108,7 +113,7 @@ static const char *init_mmc_for_env(struct mmc *mmc) static void fini_mmc_for_env(struct mmc *mmc) { #ifdef CONFIG_SYS_MMC_ENV_PART - int dev = CONFIG_SYS_MMC_ENV_DEV; + int dev = mmc_get_env_devno(); #ifdef CONFIG_SPL_BUILD dev = 0; @@ -127,7 +132,7 @@ static inline int write_env(struct mmc *mmc, unsigned long size, blk_start = ALIGN(offset, mmc->write_bl_len) / mmc->write_bl_len; blk_cnt = ALIGN(size, mmc->write_bl_len) / mmc->write_bl_len; - n = mmc->block_dev.block_write(CONFIG_SYS_MMC_ENV_DEV, blk_start, + n = mmc->block_dev.block_write(mmc_get_env_devno(), blk_start, blk_cnt, (u_char *)buffer); return (n == blk_cnt) ? 0 : -1; @@ -140,7 +145,8 @@ static unsigned char env_flags; int saveenv(void) { ALLOC_CACHE_ALIGN_BUFFER(env_t, env_new, 1); - struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV); + int mmc_env_devno = mmc_get_env_devno(); + struct mmc *mmc = find_mmc_device(mmc_env_devno); u32 offset; int ret, copy = 0; const char *errmsg; @@ -168,7 +174,7 @@ int saveenv(void) } printf("Writing to %sMMC(%d)... ", copy ? "redundant " : "", - CONFIG_SYS_MMC_ENV_DEV); + mmc_env_devno); if (write_env(mmc, CONFIG_ENV_SIZE, offset, (u_char *)env_new)) { puts("failed\n"); ret = 1; @@ -192,7 +198,7 @@ static inline int read_env(struct mmc *mmc, unsigned long size, unsigned long offset, const void *buffer) { uint blk_start, blk_cnt, n; - int dev = CONFIG_SYS_MMC_ENV_DEV; + int dev = mmc_get_env_devno(); #ifdef CONFIG_SPL_BUILD dev = 0; @@ -216,7 +222,7 @@ void env_relocate_spec(void) int crc1_ok = 0, crc2_ok = 0; env_t *ep; int ret; - int dev = CONFIG_SYS_MMC_ENV_DEV; + int dev = mmc_get_env_devno(); const char *errmsg = NULL; ALLOC_CACHE_ALIGN_BUFFER(env_t, tmp_env1, 1); @@ -302,7 +308,7 @@ void env_relocate_spec(void) struct mmc *mmc; u32 offset; int ret; - int dev = CONFIG_SYS_MMC_ENV_DEV; + int dev = mmc_get_env_devno(); const char *errmsg; #ifdef CONFIG_SPL_BUILD -- 2.6.2

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[U-Boot] [PATCH 0/3] Moving Uartlite to DM
by Michal Simek 16 Dec '15

16 Dec '15

Hi, This patch series depends on microblaze cleanup series. All these patches will be available in git://git.denx.de/u-boot-microblaze.git also with patches which I am going to send now. Thanks, Michal Michal Simek (3): serial: uartlite: Move driver to DM serial: uartlite: Add support for debug console serial: uartlite: Add uartlite to Kconfig arch/microblaze/Kconfig | 1 + board/xilinx/microblaze-generic/xparameters.h | 4 - configs/microblaze-generic_defconfig | 3 + doc/driver-model/serial-howto.txt | 1 - drivers/serial/Kconfig | 14 ++ drivers/serial/serial_xuartlite.c | 191 ++++++++++++-------------- include/configs/microblaze-generic.h | 7 +- 7 files changed, 106 insertions(+), 115 deletions(-) -- 1.9.1

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[U-Boot] [PATCH 1/5] nios2: Calculate the env position from monitor size
by Marek Vasut 16 Dec '15

16 Dec '15

Reorder the 10m50 and 3c120 config files such, that the environment position can be calculated from the monitor size. The environment is placed right after the monitor. This removes one more ad-hoc variable. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Thomas Chou <thomas(a)wytron.com.tw> --- include/configs/10m50_devboard.h | 26 +++++++++++++------------- include/configs/3c120_devboard.h | 26 +++++++++++++------------- 2 files changed, 26 insertions(+), 26 deletions(-) diff --git a/include/configs/10m50_devboard.h b/include/configs/10m50_devboard.h index 8a91cdb..c99177c 100644 --- a/include/configs/10m50_devboard.h +++ b/include/configs/10m50_devboard.h @@ -54,19 +54,6 @@ #define CONFIG_LMB /* - * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above - * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the - * reset address, no? This will keep the environment in user region - * of flash. NOTE: the monitor length must be multiple of sector size - * (which is common practice). - */ -#define CONFIG_ENV_IS_IN_FLASH - -#define CONFIG_ENV_SIZE 0x10000 /* 64k, 1 sector */ -#define CONFIG_ENV_OVERWRITE /* Serial change Ok */ -#define CONFIG_ENV_ADDR 0xf4040000 - -/* * MEMORY ORGANIZATION * -Monitor at top of sdram. * -The heap is placed below the monitor @@ -83,6 +70,19 @@ #define CONFIG_SYS_MALLOC_LEN 0x20000 /* + * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above + * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the + * reset address, no? This will keep the environment in user region + * of flash. NOTE: the monitor length must be multiple of sector size + * (which is common practice). + */ +#define CONFIG_ENV_IS_IN_FLASH + +#define CONFIG_ENV_SIZE 0x10000 /* 64k, 1 sector */ +#define CONFIG_ENV_OVERWRITE /* Serial change Ok */ +#define CONFIG_ENV_ADDR (0xf4000000 + CONFIG_SYS_MONITOR_LEN) + +/* * MISC */ #define CONFIG_SYS_LONGHELP /* Provide extended help */ diff --git a/include/configs/3c120_devboard.h b/include/configs/3c120_devboard.h index 2ecdd5d..0f494e5 100644 --- a/include/configs/3c120_devboard.h +++ b/include/configs/3c120_devboard.h @@ -57,19 +57,6 @@ #define CONFIG_LMB /* - * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above - * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the - * reset address, no? This will keep the environment in user region - * of flash. NOTE: the monitor length must be multiple of sector size - * (which is common practice). - */ -#define CONFIG_ENV_IS_IN_FLASH - -#define CONFIG_ENV_SIZE 0x20000 /* 128k, 1 sector */ -#define CONFIG_ENV_OVERWRITE /* Serial change Ok */ -#define CONFIG_ENV_ADDR 0xe2840000 - -/* * MEMORY ORGANIZATION * -Monitor at top of sdram. * -The heap is placed below the monitor @@ -86,6 +73,19 @@ #define CONFIG_SYS_MALLOC_LEN 0x20000 /* + * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above + * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the + * reset address, no? This will keep the environment in user region + * of flash. NOTE: the monitor length must be multiple of sector size + * (which is common practice). + */ +#define CONFIG_ENV_IS_IN_FLASH + +#define CONFIG_ENV_SIZE 0x20000 /* 128k, 1 sector */ +#define CONFIG_ENV_OVERWRITE /* Serial change Ok */ +#define CONFIG_ENV_ADDR (0xe2800000 + CONFIG_SYS_MONITOR_LEN) + +/* * MISC */ #define CONFIG_SYS_LONGHELP /* Provide extended help */ -- 2.1.4

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[U-Boot] [PATCH] armv7: omap-common: Rework SPL board_mmc_init()
by Tom Rini 16 Dec '15

16 Dec '15

Since the changes in a1e56cf the way that we had board_mmc_init() structured for OMAP parts (so that we always report device 0) are no longer functional. For now, make the case of booting from the second device initialize both devices (we have no devices that only have the second device as MMC). A further rework and consolidation of the functions should be done at a later date. Tested on Beaglebone Black (SD and eMMC boot). Reported-by: Vagrant Cascadian <vagrant(a)debian.org> Signed-off-by: Tom Rini <trini(a)konsulko.com> --- arch/arm/cpu/armv7/omap-common/boot-common.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c index 8e5d5c9..0456263 100644 --- a/arch/arm/cpu/armv7/omap-common/boot-common.c +++ b/arch/arm/cpu/armv7/omap-common/boot-common.c @@ -208,6 +208,7 @@ int board_mmc_init(bd_t *bis) break; case BOOT_DEVICE_MMC2: case BOOT_DEVICE_MMC2_2: + omap_mmc_init(0, 0, 0, -1, -1); omap_mmc_init(1, 0, 0, -1, -1); break; } -- 1.7.9.5

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