December 2015 - U-Boot

[U-Boot] [PATCH] powerpc: mpc85xx: Move set_liodns, setup_portals to common boot seq
by Prabhakar Kushwaha 15 Dec '15

15 Dec '15

Users migrating Freescale's PowerPC SoC U-Boot code to their custom board, often overlook the need to execute set_liodns() and setup_portals() being called by platform files. So Move set_liodns() and setup_portals() to common u-boot boot sequence Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 7 +++++++ board/freescale/b4860qds/b4860qds.c | 5 ----- board/freescale/corenet_ds/corenet_ds.c | 6 ------ board/freescale/p2041rdb/p2041rdb.c | 3 --- board/freescale/t102xqds/t102xqds.c | 5 ----- board/freescale/t102xrdb/t102xrdb.c | 5 ----- board/freescale/t1040qds/t1040qds.c | 5 ----- board/freescale/t104xrdb/t104xrdb.c | 6 ------ board/freescale/t208xqds/t208xqds.c | 6 ------ board/freescale/t208xrdb/t208xrdb.c | 6 ------ board/freescale/t4qds/t4240emu.c | 6 ------ board/freescale/t4qds/t4240qds.c | 6 ------ board/freescale/t4rdb/t4240rdb.c | 6 ------ 13 files changed, 7 insertions(+), 65 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 4cf8853..c506ab8 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -23,6 +23,8 @@ #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> #include <asm/fsl_srio.h> +#include <asm/fsl_portals.h> +#include <asm/fsl_liodn.h> #include <fsl_usb.h> #include <hwconfig.h> #include <linux/compiler.h> @@ -788,6 +790,11 @@ int cpu_init_r(void) spin_table_compat = 1; #endif + set_liodns(); +#ifdef CONFIG_SYS_DPAA_QBMAN + setup_portals(); +#endif + l2cache_init(); #if defined(CONFIG_RAMBOOT_PBL) disable_cpc_sram(); diff --git a/board/freescale/b4860qds/b4860qds.c b/board/freescale/b4860qds/b4860qds.c index 6a8fca6..e582abb 100644 --- a/board/freescale/b4860qds/b4860qds.c +++ b/board/freescale/b4860qds/b4860qds.c @@ -16,7 +16,6 @@ #include <asm/immap_85xx.h> #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> -#include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> #include <fm_eth.h> #include <hwconfig.h> @@ -1023,10 +1022,6 @@ int board_early_init_r(void) MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); - set_liodns(); -#ifdef CONFIG_SYS_DPAA_QBMAN - setup_portals(); -#endif /* * Adjust core voltage according to voltage ID * This function changes I2C mux to channel 2. diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c index 6f0fea1..f41985d 100644 --- a/board/freescale/corenet_ds/corenet_ds.c +++ b/board/freescale/corenet_ds/corenet_ds.c @@ -14,7 +14,6 @@ #include <asm/immap_85xx.h> #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> -#include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> #include <fm_eth.h> @@ -125,11 +124,6 @@ int board_early_init_r(void) MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ - set_liodns(); -#ifdef CONFIG_SYS_DPAA_QBMAN - setup_portals(); -#endif - return 0; } diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c index e600bdb..c6a7242 100644 --- a/board/freescale/p2041rdb/p2041rdb.c +++ b/board/freescale/p2041rdb/p2041rdb.c @@ -14,7 +14,6 @@ #include <asm/immap_85xx.h> #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> -#include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> #include <fm_eth.h> @@ -140,8 +139,6 @@ int board_early_init_r(void) MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); - set_liodns(); - setup_portals(); board_config_lanes_mux(); return 0; diff --git a/board/freescale/t102xqds/t102xqds.c b/board/freescale/t102xqds/t102xqds.c index 708afca..76793a1 100644 --- a/board/freescale/t102xqds/t102xqds.c +++ b/board/freescale/t102xqds/t102xqds.c @@ -15,7 +15,6 @@ #include <asm/immap_85xx.h> #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> -#include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> #include <fm_eth.h> #include <hwconfig.h> @@ -280,10 +279,6 @@ int board_early_init_r(void) MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); #endif - set_liodns(); -#ifdef CONFIG_SYS_DPAA_QBMAN - setup_portals(); -#endif select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); board_mux_lane_to_slot(); board_retimer_ds125df111_init(); diff --git a/board/freescale/t102xrdb/t102xrdb.c b/board/freescale/t102xrdb/t102xrdb.c index fddd240..01dbf38 100644 --- a/board/freescale/t102xrdb/t102xrdb.c +++ b/board/freescale/t102xrdb/t102xrdb.c @@ -14,7 +14,6 @@ #include <asm/immap_85xx.h> #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> -#include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> #include <fm_eth.h> #include "t102xrdb.h" @@ -151,10 +150,6 @@ int board_early_init_r(void) 0, flash_esel, BOOKE_PAGESZ_256M, 1); #endif - set_liodns(); -#ifdef CONFIG_SYS_DPAA_QBMAN - setup_portals(); -#endif #ifdef CONFIG_T1024RDB board_mux_lane(); #endif diff --git a/board/freescale/t1040qds/t1040qds.c b/board/freescale/t1040qds/t1040qds.c index eaca57f..d7d56b4 100644 --- a/board/freescale/t1040qds/t1040qds.c +++ b/board/freescale/t1040qds/t1040qds.c @@ -15,7 +15,6 @@ #include <asm/immap_85xx.h> #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> -#include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> #include <fm_eth.h> #include <hwconfig.h> @@ -153,10 +152,6 @@ int board_early_init_r(void) MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); #endif - set_liodns(); -#ifdef CONFIG_SYS_DPAA_QBMAN - setup_portals(); -#endif select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); return 0; diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c index 3227652..ec97677 100644 --- a/board/freescale/t104xrdb/t104xrdb.c +++ b/board/freescale/t104xrdb/t104xrdb.c @@ -16,7 +16,6 @@ #include <asm/fsl_fdt.h> #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> -#include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> #include <fm_eth.h> #include "../common/sleep.h" @@ -84,11 +83,6 @@ int board_early_init_r(void) MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); #endif - set_liodns(); -#ifdef CONFIG_SYS_DPAA_QBMAN - setup_portals(); -#endif - return 0; } diff --git a/board/freescale/t208xqds/t208xqds.c b/board/freescale/t208xqds/t208xqds.c index 7c89cd5..bfea3a1 100644 --- a/board/freescale/t208xqds/t208xqds.c +++ b/board/freescale/t208xqds/t208xqds.c @@ -14,7 +14,6 @@ #include <asm/immap_85xx.h> #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> -#include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> #include <fm_eth.h> @@ -356,11 +355,6 @@ int board_early_init_r(void) MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); - set_liodns(); -#ifdef CONFIG_SYS_DPAA_QBMAN - setup_portals(); -#endif - /* Disable remote I2C connection to qixis fpga */ QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE); diff --git a/board/freescale/t208xrdb/t208xrdb.c b/board/freescale/t208xrdb/t208xrdb.c index 0c2c1c5..0cb05aa 100644 --- a/board/freescale/t208xrdb/t208xrdb.c +++ b/board/freescale/t208xrdb/t208xrdb.c @@ -14,7 +14,6 @@ #include <asm/immap_85xx.h> #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> -#include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> #include <fm_eth.h> #include "t208xrdb.h" @@ -81,11 +80,6 @@ int board_early_init_r(void) MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); - set_liodns(); -#ifdef CONFIG_SYS_DPAA_QBMAN - setup_portals(); -#endif - /* * Adjust core voltage according to voltage ID * This function changes I2C mux to channel 2. diff --git a/board/freescale/t4qds/t4240emu.c b/board/freescale/t4qds/t4240emu.c index 5441094..f1393f2 100644 --- a/board/freescale/t4qds/t4240emu.c +++ b/board/freescale/t4qds/t4240emu.c @@ -15,7 +15,6 @@ #include <asm/immap_85xx.h> #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> -#include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> DECLARE_GLOBAL_DATA_PTR; @@ -56,11 +55,6 @@ int board_early_init_r(void) MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); - set_liodns(); -#ifdef CONFIG_SYS_DPAA_QBMAN - setup_portals(); -#endif - return 0; } diff --git a/board/freescale/t4qds/t4240qds.c b/board/freescale/t4qds/t4240qds.c index 4f2cccd..d6df144 100644 --- a/board/freescale/t4qds/t4240qds.c +++ b/board/freescale/t4qds/t4240qds.c @@ -15,7 +15,6 @@ #include <asm/immap_85xx.h> #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> -#include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> #include <fm_eth.h> @@ -552,11 +551,6 @@ int board_early_init_r(void) MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); - set_liodns(); -#ifdef CONFIG_SYS_DPAA_QBMAN - setup_portals(); -#endif - /* Disable remote I2C connection to qixis fpga */ QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE); diff --git a/board/freescale/t4rdb/t4240rdb.c b/board/freescale/t4rdb/t4240rdb.c index fac442b..4f0bbed 100644 --- a/board/freescale/t4rdb/t4240rdb.c +++ b/board/freescale/t4rdb/t4240rdb.c @@ -15,7 +15,6 @@ #include <asm/immap_85xx.h> #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> -#include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> #include <fm_eth.h> @@ -75,11 +74,6 @@ int board_early_init_r(void) MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); - set_liodns(); -#ifdef CONFIG_SYS_DPAA_QBMAN - setup_portals(); -#endif - return 0; } -- 1.9.1

2 1

[U-Boot] [PATCH v3 0/5] arm: ls1021a: merge SoC specific code in a separate file
by Yuan Yao 15 Dec '15

15 Dec '15

arm: ls1021a: merge SoC specific code in a separate file arm: ls102xa: enable all the snoop signal for masters. ls102xa: Enable snoop and DVM message requests. armv7/fsl-ls102xa: Workaround for DDR erratum A008514 Changed in v2: Update the write value to 63b2_0042h; move erratum a008336 and a008514 to soc specific file Changed in v3: Fix a typo issue. In function "erratum_a008514" "#ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR" should be "#ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR" Changed in v2: Update the patch commit message.

3 14

[U-Boot] [PATCH v6] arm: Add sata support on Layerscape ARMv8 board
by Yuantian.Tang＠freescale.com 15 Dec '15

15 Dec '15

From: Tang Yuantian <Yuantian.Tang(a)freescale.com> Freescale ARM-based Layerscape contains a SATA controller which comply with the serial ATA 3.0 specification and the AHCI 1.3 specification. This patch adds SATA feature on ls2080aqds, ls2080ardb and ls1043aqds boards. Signed-off-by: Tang Yuantian <Yuantian.Tang(a)freescale.com> --- v6: - update rx watermark from 0x25 to 0x29 to improve compatibility v5: - re-organize the code v4: - rebase to lastest git tree - add another ARMv8 platform which is ls1043aqds v3: - rename ls2085a to ls2080a - rebase to the latest git tree - replace the magic number with micro variable v2: - rebase to the latest git tree arch/arm/cpu/armv8/fsl-layerscape/soc.c | 43 ++++++++++++++++++++++ .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 4 ++ arch/arm/include/asm/arch-fsl-layerscape/soc.h | 31 ++++++++++++++++ include/configs/ls1043aqds.h | 17 +++++++++ include/configs/ls2080aqds.h | 18 +++++++++ include/configs/ls2080ardb.h | 18 +++++++++ 6 files changed, 131 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 8896b70..574ffc4 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -6,6 +6,8 @@ #include <common.h> #include <fsl_ifc.h> +#include <ahci.h> +#include <scsi.h> #include <asm/arch/soc.h> #include <asm/io.h> #include <asm/global_data.h> @@ -120,7 +122,44 @@ void fsl_lsch3_early_init_f(void) erratum_a009203(); } +#ifdef CONFIG_SCSI_AHCI_PLAT +int sata_init(void) +{ + struct ccsr_ahci __iomem *ccsr_ahci; + + ccsr_ahci = (void *)CONFIG_SYS_SATA2; + out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); + out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); + + ccsr_ahci = (void *)CONFIG_SYS_SATA1; + out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); + out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); + + ahci_init((void __iomem *)CONFIG_SYS_SATA1); + scsi_scan(0); + + return 0; +} +#endif + #elif defined(CONFIG_LS1043A) +#ifdef CONFIG_SCSI_AHCI_PLAT +int sata_init(void) +{ + struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA; + + out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); + out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG); + out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG); + out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); + + ahci_init((void __iomem *)CONFIG_SYS_SATA); + scsi_scan(0); + + return 0; +} +#endif + void fsl_lsch2_early_init_f(void) { struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; @@ -141,6 +180,10 @@ void fsl_lsch2_early_init_f(void) #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { +#ifdef CONFIG_SCSI_AHCI_PLAT + sata_init(); +#endif + return 0; } #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index cd96604..91f3ce8 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -69,6 +69,10 @@ #define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110) #define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114) +/* SATA */ +#define AHCI_BASE_ADDR1 (CONFIG_SYS_IMMR + 0x02200000) +#define AHCI_BASE_ADDR2 (CONFIG_SYS_IMMR + 0x02210000) + /* PCIe */ #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 504c1f9..1565592 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -51,6 +51,37 @@ struct cpu_type { #define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E) #define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1)) +/* ahci port register default value */ +#define AHCI_PORT_PHY_1_CFG 0xa003fffe +#define AHCI_PORT_PHY_2_CFG 0x28184d1f +#define AHCI_PORT_PHY_3_CFG 0x0e081509 +#define AHCI_PORT_TRANS_CFG 0x08000029 + +/* AHCI (sata) register map */ +struct ccsr_ahci { + u32 res1[0xa4/4]; /* 0x0 - 0xa4 */ + u32 pcfg; /* port config */ + u32 ppcfg; /* port phy1 config */ + u32 pp2c; /* port phy2 config */ + u32 pp3c; /* port phy3 config */ + u32 pp4c; /* port phy4 config */ + u32 pp5c; /* port phy5 config */ + u32 axicc; /* AXI cache control */ + u32 paxic; /* port AXI config */ + u32 axipc; /* AXI PROT control */ + u32 ptc; /* port Trans Config */ + u32 pts; /* port Trans Status */ + u32 plc; /* port link config */ + u32 plc1; /* port link config1 */ + u32 plc2; /* port link config2 */ + u32 pls; /* port link status */ + u32 pls1; /* port link status1 */ + u32 pcmdc; /* port CMD config */ + u32 ppcs; /* port phy control status */ + u32 pberr; /* port 0/1 BIST error */ + u32 cmds; /* port 0/1 CMD status error */ +}; + #ifdef CONFIG_FSL_LSCH3 void fsl_lsch3_early_init_f(void); #elif defined(CONFIG_FSL_LSCH2) diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index 4aeb238..398f1c3 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -88,6 +88,23 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg #endif +/* SATA */ +#define CONFIG_LIBATA +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_CMD_SCSI +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#define CONFIG_DOS_PARTITION +#define CONFIG_BOARD_LATE_INIT + +#define CONFIG_SYS_SATA AHCI_BASE_ADDR + +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) + /* * IFC Definitions */ diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index b8bdf62..100c0ee 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -40,6 +40,24 @@ unsigned long get_board_ddr_clk(void); #endif #define CONFIG_FSL_DDR_BIST /* enable built-in memory test */ +/* SATA */ +#define CONFIG_LIBATA +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_CMD_SCSI +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#define CONFIG_DOS_PARTITION +#define CONFIG_BOARD_LATE_INIT + +#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 +#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2 + +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) + /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */ #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 65d4f64..75d98dc 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -42,6 +42,24 @@ unsigned long get_board_sys_clk(void); #endif #define CONFIG_FSL_DDR_BIST /* enable built-in memory test */ +/* SATA */ +#define CONFIG_LIBATA +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_CMD_SCSI +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#define CONFIG_DOS_PARTITION +#define CONFIG_BOARD_LATE_INIT + +#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 +#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2 + +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) + /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */ #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) -- 2.1.0.27.g96db324

2 1

[U-Boot] [PATCH 1/1] fsl_qspi: Pet the watchdog while reading/writing
by Alexander Stein 15 Dec '15

15 Dec '15

When reading a large blob. e.g. a linux kernel (several MiBs) a watchdog timeout might occur meanwhile. So pet the watchdog while operating on the flash. Signed-off-by: Alexander Stein <alexander.stein(a)systec-electronic.com> --- drivers/spi/fsl_qspi.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index ed39114..feec3e8 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -13,6 +13,7 @@ #include <linux/sizes.h> #include <dm.h> #include <errno.h> +#include <watchdog.h> #include "fsl_qspi.h" DECLARE_GLOBAL_DATA_PTR; @@ -527,6 +528,8 @@ static void qspi_op_read(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len) to_or_from = priv->sf_addr + priv->cur_amba_base; while (len > 0) { + WATCHDOG_RESET(); + qspi_write32(priv->flags, &regs->sfar, to_or_from); size = (len > RX_BUFFER_SIZE) ? @@ -574,6 +577,8 @@ static void qspi_op_write(struct fsl_qspi_priv *priv, u8 *txbuf, u32 len) status_reg = 0; while ((status_reg & FLASH_STATUS_WEL) != FLASH_STATUS_WEL) { + WATCHDOG_RESET(); + qspi_write32(priv->flags, &regs->ipcr, (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0); while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK) -- 2.4.10

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[U-Boot] [PATCH v5 1/2] common: Rewrite hiding the end of memory
by York Sun 15 Dec '15

15 Dec '15

As the name may be confusing, the CONFIG_SYS_MEM_TOP_HIDE reserves some memory from the end of ram, tracked by gd->ram_size. It is not always the top of u-boot visible memory. Rewrite the macro with a weak function to provide flexibility for complex calcuation. Legacy use of this macro is still supported. Signed-off-by: York Sun <yorksun(a)freescale.com> --- Changes in v5: Separated as a new patch Changes in v4: None Changes in v3: None Changes in v2: None README | 2 +- common/board_f.c | 23 +++++++++++++++-------- 2 files changed, 16 insertions(+), 9 deletions(-) diff --git a/README b/README index 6ea1af2..4aa2aae 100644 --- a/README +++ b/README @@ -3877,7 +3877,7 @@ Configuration Settings: the RAM base is not zero, or RAM is divided into banks, this variable needs to be recalcuated to get the address. -- CONFIG_SYS_MEM_TOP_HIDE (PPC only): +- CONFIG_SYS_MEM_TOP_HIDE: If CONFIG_SYS_MEM_TOP_HIDE is defined in the board config header, this specified memory area will get subtracted from the top (end) of RAM and won't get "touched" at all by U-Boot. By diff --git a/common/board_f.c b/common/board_f.c index e13657f..51d8814 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -317,6 +317,15 @@ __weak ulong board_get_usable_ram_top(ulong total_size) return gd->ram_top; } +__weak phys_size_t board_reserve_ram_top(phys_size_t ram_size) +{ +#ifdef CONFIG_SYS_MEM_TOP_HIDE + return ram_size - CONFIG_SYS_MEM_TOP_HIDE; +#else + return ram_size; +#endif +} + static int setup_dest_addr(void) { debug("Monitor len: %08lX\n", gd->mon_len); @@ -333,19 +342,17 @@ static int setup_dest_addr(void) */ gd->secure_ram = gd->ram_size; #endif -#if defined(CONFIG_SYS_MEM_TOP_HIDE) /* * Subtract specified amount of memory to hide so that it won't * get "touched" at all by U-Boot. By fixing up gd->ram_size * the Linux kernel should now get passed the now "corrected" - * memory size and won't touch it either. This should work - * for arch/ppc and arch/powerpc. Only Linux board ports in - * arch/powerpc with bootwrapper support, that recalculate the - * memory size from the SDRAM controller setup will have to - * get fixed. + * memory size and won't touch it either. This has been used + * by arch/powerpc exclusively. Now ARMv8 takes advantage of + * thie mechanism. If memory is split into banks, addresses + * need to be calculated. */ - gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE; -#endif + gd->ram_size = board_reserve_ram_top(gd->ram_size); + #ifdef CONFIG_SYS_SDRAM_BASE gd->ram_top = CONFIG_SYS_SDRAM_BASE; #endif -- 1.7.9.5

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[U-Boot] [PATCH v7 0/2] Make most DDR non-secure in MMU while keep a small block secure
by York Sun 15 Dec '15

15 Dec '15

This set is to change MMU tables so DDR is in non-secure mode that non-secure master such as SDHC DMA can access the data. To mix secure and non-secure MMU entries, the MMU tables themselves have to be in secure memory. A small portion memory is reserved at the end of DDR (before debug server and MC) to host secure application and the MMU tables. This is different from existing armv7 secure_ram_addr() solution. U-boot can run in the middle of memory if the memory is large. Having security memory at the very end simplifies MMU setup. Tested on LS2085AQDS with a known non-secure master test. Changes in v7: Rebase to recent master Update ls1043ardb ddr.c Add change to ls1043qds ddr.c Check exception level before setting secure memory Leave gd->arch.tlb_addr unused if secure memory is setup Changes in v6: Move cmd_bdinfo change into this patch Move flag macros and comments of secure_ram into this patch Move cmd_bdinfo change to 1st patch in this set Rearrange #ifdef CONFIG_SYS_MEM_RESERVE_SECURE Changes in v5: Put ifdef where gd->secure_ram is used Changes in v4: Drop RFC from patch prefix Drop excessive mmu table for secure ram for early MMU Update commit message accordingly Mark QBMan cacheable portal memory non-secure Changes in v3: Put ifdef around secure_ram Move defining CONFIG_SYS_MEM_RESERVE_SECURE to patch 2/2 Replace CONFIG_FSL_PPA_RESERVED_DRAM_SIZE with CONFIG_SYS_MEM_RESERVE_SECURE Sanity check gd->secure_ram before using Define CONFIG_SYS_MEM_RESERVE_SECURE in SoC header file Include ls1043ardb Modified commit message. Changes in v2: Do not use CONFIG_SYS_MEM_TOP_HIDE mechanism Move gd->arch.secure_ram to gd->secure_ram. Change the calculation of gd->secure_ram accordingly. Chnage commit message slightly accordingly. Changes in v1: Initial patch. Depends on http://patchwork.ozlabs.org/patch/540248/ York Sun (2): Reserve secure memory armv8: fsl-layerscape: Make DDR non secure in MMU tables README | 8 ++ arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 121 ++++++++++++++++++--- arch/arm/include/asm/arch-fsl-layerscape/config.h | 6 + arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 14 ++- board/freescale/ls1043aqds/ddr.c | 9 ++ board/freescale/ls1043ardb/ddr.c | 15 +++ board/freescale/ls2080a/ddr.c | 15 +++ board/freescale/ls2080aqds/ddr.c | 15 +++ board/freescale/ls2080ardb/ddr.c | 15 +++ common/board_f.c | 9 ++ common/cmd_bdinfo.c | 6 + include/asm-generic/global_data.h | 14 +++ 12 files changed, 228 insertions(+), 19 deletions(-) -- 1.7.9.5

1 4

[U-Boot] [PATCH] Enable console log from earlyconsole in Linux bootargs
by Pratiyush Mohan Srivastava 15 Dec '15

15 Dec '15

Remove 115200 from "earlycon" to avoid loss of initial log messages during linux kernel 4.1 bootup Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava(a)freescale.com> --- include/configs/ls2080a_common.h | 2 +- include/configs/ls2080ardb.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 31f6441..c39e294 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -263,7 +263,7 @@ unsigned long long get_qixis_addr(void); "console=ttyAMA0,38400n8\0" #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ - "earlycon=uart8250,mmio,0x21c0500,115200 " \ + "earlycon=uart8250,mmio,0x21c0500" \ "ramdisk_size=0x2000000 default_hugepagesz=2m" \ " hugepagesz=2m hugepages=16" #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 69bac8b..23d121a 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -314,7 +314,7 @@ unsigned long get_board_sys_clk(void); #undef CONFIG_BOOTARGS #define CONFIG_BOOTARGS "console=ttyS1,115200 root=/dev/ram0 " \ - "earlycon=uart8250,mmio,0x21c0600,115200 " \ + "earlycon=uart8250,mmio,0x21c0600" \ "ramdisk_size=0x2000000 default_hugepagesz=2m" \ " hugepagesz=2m hugepages=16" -- 1.9.1

2 2

[U-Boot] [PATCH] armv8/ls1043ardb: Add support for >2GB memory
by Mingkai Hu 15 Dec '15

15 Dec '15

From: Shaohui Xie <Shaohui.Xie(a)freescale.com> This patch also expose the complete DDR region(s) to Linux. Signed-off-by: Shaohui Xie <Shaohui.Xie(a)freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu(a)freescale.com> --- arch/arm/include/asm/arch-fsl-layerscape/config.h | 4 ++-- board/freescale/ls1043ardb/ddr.c | 9 ++++++++- board/freescale/ls1043ardb/ls1043ardb.c | 10 ++++++++++ include/configs/ls1043a_common.h | 1 + include/configs/ls1043ardb.h | 2 +- 5 files changed, 22 insertions(+), 4 deletions(-) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 87bb937..aba360e 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -103,8 +103,8 @@ #define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */ #define CONFIG_SYS_FSL_OCRAM_SIZE 0x200000 /* 2 MiB */ #define CONFIG_SYS_FSL_DDR_BE -#define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS1_DDR_BLOCK1_SIZE +#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE #define CONFIG_SYS_FSL_CCSR_GUR_BE #define CONFIG_SYS_FSL_CCSR_SCFG_BE diff --git a/board/freescale/ls1043ardb/ddr.c b/board/freescale/ls1043ardb/ddr.c index b181579..249d056 100644 --- a/board/freescale/ls1043ardb/ddr.c +++ b/board/freescale/ls1043ardb/ddr.c @@ -187,5 +187,12 @@ phys_size_t initdram(int board_type) void dram_init_banksize(void) { gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; + if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { + gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; + gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; + gd->bd->bi_dram[1].size = gd->ram_size - + CONFIG_SYS_DDR_BLOCK1_SIZE; + } else { + gd->bd->bi_dram[0].size = gd->ram_size; + } } diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c index 9032ed3..c4f2603 100644 --- a/board/freescale/ls1043ardb/ls1043ardb.c +++ b/board/freescale/ls1043ardb/ls1043ardb.c @@ -114,6 +114,16 @@ int misc_init_r(void) int ft_board_setup(void *blob, bd_t *bd) { + u64 base[CONFIG_NR_DRAM_BANKS]; + u64 size[CONFIG_NR_DRAM_BANKS]; + + /* fixup DT for the two DDR banks */ + base[0] = gd->bd->bi_dram[0].start; + size[0] = gd->bd->bi_dram[0].size; + base[1] = gd->bd->bi_dram[1].start; + size[1] = gd->bd->bi_dram[1].size; + + fdt_fixup_memory_banks(blob, base, size, 2); ft_cpu_setup(blob, bd); #ifdef CONFIG_SYS_DPAA_FMAN diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 6b9856a..677d281 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -44,6 +44,7 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL #define CPU_RELEASE_ADDR secondary_boot_func diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index 307d947..acffe6e 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -27,7 +27,7 @@ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 /* Physical Memory Map */ #define CONFIG_CHIP_SELECTS_PER_CTRL 4 -#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_NR_DRAM_BANKS 2 #define CONFIG_SYS_SPD_BUS_NUM 0 -- 2.1.0.27.g96db324

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[U-Boot] [PATCH 1/3] arm: ls102x: add get_svr and IS_SVR_REV helper
by Shengzhou Liu 15 Dec '15

15 Dec '15

Signed-off-by: Shengzhou Liu <Shengzhou.Liu(a)freescale.com> --- arch/arm/cpu/armv7/ls102xa/cpu.c | 8 ++++++++ arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 5 +++++ 2 files changed, 13 insertions(+) diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c index 14ae2a3..74cd2cb 100644 --- a/arch/arm/cpu/armv7/ls102xa/cpu.c +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c @@ -209,6 +209,14 @@ void enable_caches(void) } #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */ + +uint get_svr(void) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + + return in_be32(&gur->svr); +} + #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) { diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index c59c93a..2d0832a 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -11,6 +11,8 @@ #define SVR_MIN(svr) (((svr) >> 0) & 0xf) #define SVR_SOC_VER(svr) (((svr) >> 8) & 0x7ff) #define IS_E_PROCESSOR(svr) (svr & 0x80000) +#define IS_SVR_REV(svr, maj, min) \ + ((SVR_MAJ(svr) == maj) && (SVR_MIN(svr) == min)) #define SOC_VER_SLS1020 0x00 #define SOC_VER_LS1020 0x10 @@ -427,4 +429,7 @@ struct ccsr_ahci { u32 pberr; /* port 0/1 BIST error */ u32 cmds; /* port 0/1 CMD status error */ }; + +uint get_svr(void); + #endif /* __ASM_ARCH_LS102XA_IMMAP_H_ */ -- 2.1.0.27.g96db324

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[U-Boot] [PATCH] freescale: fman: make sure phy-handle property is big endian
by shh.xie＠gmail.com 15 Dec '15

15 Dec '15

From: Shaohui Xie <Shaohui.Xie(a)freescale.com> When creating phy-handle property, an unsigned int value is created by fdt_create_phandle, and memcpy is used to get the value, since DTS is big endian, the value cannot be used directly on little endian SoCs, it should be converted by cpu_to_fdt32. Signed-off-by: Shaohui Xie <Shaohui.Xie(a)freescale.com> --- board/freescale/common/fman.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/board/freescale/common/fman.c b/board/freescale/common/fman.c index 26cf517..b5025ab 100644 --- a/board/freescale/common/fman.c +++ b/board/freescale/common/fman.c @@ -52,6 +52,8 @@ int fdt_set_phy_handle(void *fdt, char *compat, phys_addr_t addr, if (!ph) return -FDT_ERR_BADPHANDLE; + ph = cpu_to_fdt32(ph); + offset = fdt_node_offset_by_compat_reg(fdt, compat, addr); if (offset < 0) return offset; -- 2.1.0.27.g96db324

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