November 2015 - U-Boot

[U-Boot] [PATCH 1/6] mx6sabresd: Remove empty reset_cpu()
by Fabio Estevam 03 Nov '15

03 Nov '15

From: Fabio Estevam <fabio.estevam(a)freescale.com> There is really no need to provide an empty reset_cpu() implementation, so just remove it. Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- board/freescale/mx6sabresd/mx6sabresd.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index 5644167..de2561d 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -857,8 +857,4 @@ void board_init_f(ulong dummy) /* load/boot image from boot device */ board_init_r(NULL, 0); } - -void reset_cpu(ulong addr) -{ -} #endif -- 1.9.1

4 8

[U-Boot] [PATCH] u-boot/mpc85xx/u-boot*.lds: remove _GLOBAL_OFFSET_TABLE_ definition
by Prabhakar Kushwaha 03 Nov '15

03 Nov '15

From: Zhenhua Luo <zhenhua.luo(a)freescale.com> In binutils-2.25, the _GLOBAL_OFFSET_TABLE_ symbols defined by PROVIDE in u-boot.lds overrides the linker built-in symbols (https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=commitdiff;h=b89…), so the linker is treating _GLOBAL_OFFSET_TABLE_ as a definition into the .reloc section. To align with the change of binutils-2.25, the _GLOBAL_OFFSET_TABLE_ symbol should not be defined in sections, and the symbols in linker generated .got section should be used(https://sourceware.org/ml/binutils/2008-09/msg00122.html). Fixed the following build errors with binutils-2.25: | powerpc-poky-linux-gnuspe-ld.bfd: _GLOBAL_OFFSET_TABLE_ not defined in linker created .got Signed-off-by: Zhenhua Luo <zhenhua.luo(a)freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- arch/powerpc/cpu/mpc85xx/u-boot-nand.lds | 1 - arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds | 1 - arch/powerpc/cpu/mpc85xx/u-boot-spl.lds | 1 - arch/powerpc/cpu/mpc85xx/u-boot.lds | 1 - 4 files changed, 4 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds b/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds index f933b21..0399f93 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds @@ -44,7 +44,6 @@ SECTIONS _GOT2_TABLE_ = .; KEEP(*(.got2)) KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); _FIXUP_TABLE_ = .; KEEP(*(.fixup)) } diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds index b83c553..f044564 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds @@ -22,7 +22,6 @@ SECTIONS _GOT2_TABLE_ = .; KEEP(*(.got2)) KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); _FIXUP_TABLE_ = .; KEEP(*(.fixup)) } diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds index 5ae7b3e..889a4c2 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds @@ -29,7 +29,6 @@ SECTIONS _GOT2_TABLE_ = .; KEEP(*(.got2)) KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); _FIXUP_TABLE_ = .; KEEP(*(.fixup)) } diff --git a/arch/powerpc/cpu/mpc85xx/u-boot.lds b/arch/powerpc/cpu/mpc85xx/u-boot.lds index 2cf0b25..f15eaf3 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot.lds @@ -50,7 +50,6 @@ SECTIONS _GOT2_TABLE_ = .; KEEP(*(.got2)) KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); _FIXUP_TABLE_ = .; KEEP(*(.fixup)) } -- 1.9.1

3 2

[U-Boot] [PATCH] armv8: ls2085a: Add workaround of errata A009635
by Prabhakar Kushwaha 03 Nov '15

03 Nov '15

Description: When an A57 core is waiting for certain condition, it might use WFE to put itself into lower power mode to save power if the condition is not met. Another core can send an event to wake up the first core to check if the condition is met or not. When the second A57 core executes SEV instruction,it drives EVENTO for 3 core cycles. The SoC Run Control block samples the signal with the platform clock, ORed with its own EVENTI event and drive it back to A57 cores as EVENTI. If the core runs at higher than x3 speed of the platform, EVENTO is shorter than one platform clock and might be missed by the platform sampling logic. Taking into the consideration of jitter between A57 PLL and the platform PLL, A57 must run at no greater than 2.5x speed of the platform to guarantee the reliable sampling. Workaround: Configure Run Control and EPU to periodically send out EVENTI signals to wake up A57 cores so that cores that are in WFE loop have chance to check whether the condition for it to exit WFE loop is true or not. This will make sure that in case SEV instruction is lost, the core in WFE loop has a bounded time to exit the WFE loop. Followings are the register values the software need to write to set up Run Control and EPU: 0x7_0007_0914 = 0x0000_0200; 0x7_0006_0914 = <interval>; 0x7_0006_0814 = 0x8282_0000; 0x7_0006_0228 = 0x002f_0000; 0x7_0006_0314 = 0x2000_0000; 0x7_0006_0000 = 0x8000_0000; For <interval> value above, it is the number of platform cycles between wake up events generated by EPU. For example: A typical value is 1 microsecond. If the platform frequency is 500MHz, each cycle is 2ns. interval = 1us/2ns=500=0x1F4. Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 6 ++++ arch/arm/cpu/armv8/fsl-layerscape/soc.c | 39 +++++++++++++++++++++++ arch/arm/include/asm/arch-fsl-layerscape/config.h | 9 ++++++ arch/arm/include/asm/arch-fsl-layerscape/soc.h | 3 ++ 4 files changed, 57 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 0cb0afa..dbb12c2 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -484,7 +484,13 @@ int arch_early_init_r(void) { #ifdef CONFIG_MP int rv = 1; +#endif + +#ifdef CONFIG_SYS_FSL_ERRATUM_A009635 + erratum_a009635(); +#endif +#ifdef CONFIG_MP rv = fsl_layerscape_wake_seconday_cores(); if (rv) printf("Did not wake secondary cores\n"); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 637853d..e8cdb10 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -9,10 +9,49 @@ #include <asm/arch/soc.h> #include <asm/io.h> #include <asm/global_data.h> +#include <asm/arch-fsl-layerscape/config.h> DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_LS2085A +#ifdef CONFIG_SYS_FSL_ERRATUM_A009635 +#define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val" + +static unsigned long get_internval_val_mhz(void) +{ + char *interval = getenv(PLATFORM_CYCLE_ENV_VAR); + ulong interval_mhz = get_bus_freq(0) / (1000 * 1000); + + if (interval) + interval_mhz = simple_strtoul(interval, NULL, 10); + + return interval_mhz; +} + +void erratum_a009635(void) +{ + u32 val; + unsigned long interval_mhz = get_internval_val_mhz(); + + if (!interval_mhz) + return; + + val = in_le32(DCSR_CGACRE5); + writel(val | 0x00000200, DCSR_CGACRE5); + + val = in_le32(EPU_EPCMPR5); + writel(interval_mhz, EPU_EPCMPR5); + val = in_le32(EPU_EPCCR5); + writel(val | 0x82820000, EPU_EPCCR5); + val = in_le32(EPU_EPSMCR5); + writel(val | 0x002f0000, EPU_EPSMCR5); + val = in_le32(EPU_EPECR5); + writel(val | 0x20000000, EPU_EPECR5); + val = in_le32(EPU_EPGCR); + writel(val | 0x80000000, EPU_EPGCR); +} +#endif + static void erratum_a008751(void) { #ifdef CONFIG_SYS_FSL_ERRATUM_A008751 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 87bb937..c7169ab 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -84,11 +84,20 @@ #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C) #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820) +#define DCSR_CGACRE5 0x700070914ULL +#define EPU_EPCMPR5 0x700060914ULL +#define EPU_EPCCR5 0x700060814ULL +#define EPU_EPSMCR5 0x700060228ULL +#define EPU_EPECR5 0x700060314ULL +#define EPU_EPCTR5 0x700060a14ULL +#define EPU_EPGCR 0x700060000ULL + #define CONFIG_SYS_FSL_ERRATUM_A008336 #define CONFIG_SYS_FSL_ERRATUM_A008511 #define CONFIG_SYS_FSL_ERRATUM_A008514 #define CONFIG_SYS_FSL_ERRATUM_A008585 #define CONFIG_SYS_FSL_ERRATUM_A008751 +#define CONFIG_SYS_FSL_ERRATUM_A009635 #elif defined(CONFIG_LS1043A) #define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_CACHELINE_SIZE 64 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 5ed456e..80354f0 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -50,4 +50,7 @@ void fsl_lsch2_early_init_f(void); #endif void cpu_name(char *name); +#ifdef CONFIG_SYS_FSL_ERRATUM_A009635 +void erratum_a009635(void); +#endif #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */ -- 1.9.1

3 2

[U-Boot] [PATCH 1/8] serial: altera_jtag_uart: use BIT macro
by Thomas Chou 03 Nov '15

03 Nov '15

Replace numerical bit shift with BIT macro in altera_jtag_uart :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Signed-off-by: Thomas Chou <thomas(a)wytron.com.tw> --- drivers/serial/altera_jtag_uart.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/serial/altera_jtag_uart.c b/drivers/serial/altera_jtag_uart.c index 39d4a4e..0aa741c 100644 --- a/drivers/serial/altera_jtag_uart.c +++ b/drivers/serial/altera_jtag_uart.c @@ -22,11 +22,11 @@ struct altera_jtaguart_platdata { }; /* data register */ -#define ALTERA_JTAG_RVALID (1<<15) /* Read valid */ +#define ALTERA_JTAG_RVALID BIT(15) /* Read valid */ /* control register */ -#define ALTERA_JTAG_AC (1 << 10) /* activity indicator */ -#define ALTERA_JTAG_RRDY (1 << 12) /* read available */ +#define ALTERA_JTAG_AC BIT(10) /* activity indicator */ +#define ALTERA_JTAG_RRDY BIT(12) /* read available */ #define ALTERA_JTAG_WSPACE(d) ((d)>>16) /* Write space avail */ /* Write fifo size. FIXME: this should be extracted with sopc2dts */ #define ALTERA_JTAG_WRITE_DEPTH 64 -- 2.5.0

2 23

[U-Boot] [PATCH 1/2] nios2: clean up macros that do not need a value in board header
by Thomas Chou 03 Nov '15

03 Nov '15

Clean up macros that do not need a value as suggested by Marek. Signed-off-by: Thomas Chou <thomas(a)wytron.com.tw> --- include/configs/nios2-generic.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/include/configs/nios2-generic.h b/include/configs/nios2-generic.h index 4283c95..144534d 100644 --- a/include/configs/nios2-generic.h +++ b/include/configs/nios2-generic.h @@ -35,10 +35,10 @@ /* * MII/PHY */ -#define CONFIG_CMD_MII 1 -#define CONFIG_PHY_GIGE 1 -#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1 -#define CONFIG_PHY_MARVELL 1 +#define CONFIG_CMD_MII +#define CONFIG_PHY_GIGE +#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +#define CONFIG_PHY_MARVELL /* * BOOTP options -- 2.1.4

2 4

[U-Boot] [PATCH] nios2: remove the useless parenthesis in asm/io.h
by Thomas Chou 03 Nov '15

03 Nov '15

Remove the useless parenthesis in asm/io.h as suggested by Marek. Signed-off-by: Thomas Chou <thomas(a)wytron.com.tw> --- arch/nios2/include/asm/io.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/nios2/include/asm/io.h b/arch/nios2/include/asm/io.h index 3443408..03a3418 100644 --- a/arch/nios2/include/asm/io.h +++ b/arch/nios2/include/asm/io.h @@ -18,10 +18,10 @@ static inline void sync(void) * that can be used to access the memory range with the caching * properties specified by "flags". */ -#define MAP_NOCACHE (1) -#define MAP_WRCOMBINE (0) -#define MAP_WRBACK (0) -#define MAP_WRTHROUGH (0) +#define MAP_NOCACHE 1 +#define MAP_WRCOMBINE 0 +#define MAP_WRBACK 0 +#define MAP_WRTHROUGH 0 static inline void * map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) -- 2.1.4

2 2

[U-Boot] [PATCH] nios2: use common sequence for reserve_uboot
by Thomas Chou 03 Nov '15

03 Nov '15

Use common sequence for reserve_uboot, as the result is the same. Signed-off-by: Thomas Chou <thomas(a)wytron.com.tw> --- common/board_f.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/common/board_f.c b/common/board_f.c index d88ada3..64c33b3 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -894,7 +894,7 @@ static init_fnc_t init_sequence_f[] = { * - board info struct */ setup_dest_addr, -#if defined(CONFIG_BLACKFIN) || defined(CONFIG_NIOS2) +#if defined(CONFIG_BLACKFIN) /* Blackfin u-boot monitor should be on top of the ram */ reserve_uboot, #endif @@ -919,7 +919,7 @@ static init_fnc_t init_sequence_f[] = { !defined(CONFIG_BLACKFIN) && !defined(CONFIG_M68K) reserve_video, #endif -#if !defined(CONFIG_BLACKFIN) && !defined(CONFIG_NIOS2) +#if !defined(CONFIG_BLACKFIN) reserve_uboot, #endif #ifndef CONFIG_SPL_BUILD -- 2.1.4

2 4

[U-Boot] [PATCH] nios2: add memory to board info
by Thomas Chou 03 Nov '15

03 Nov '15

Run setup_board_part1/2 and add memory information to board info structure. So that it can display correct values in bdinfo command. Signed-off-by: Thomas Chou <thomas(a)wytron.com.tw> --- common/board_f.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/common/board_f.c b/common/board_f.c index d88ada3..6ab74d9 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -551,7 +551,7 @@ static int display_new_sp(void) return 0; } -#if defined(CONFIG_PPC) || defined(CONFIG_M68K) +#if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_NIOS2) static int setup_board_part1(void) { bd_t *bd = gd->bd; @@ -933,7 +933,7 @@ static init_fnc_t init_sequence_f[] = { reserve_stacks, setup_dram_config, show_dram_config, -#if defined(CONFIG_PPC) || defined(CONFIG_M68K) +#if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_NIOS2) setup_board_part1, INIT_FUNC_WATCHDOG_RESET setup_board_part2, -- 2.1.4

2 5

[U-Boot] [PATCH] nios2: fix map_physmem to do real cache mapping
by Thomas Chou 03 Nov '15

03 Nov '15

Fix the map_physmem() to do real cache mapping. Signed-off-by: Thomas Chou <thomas(a)wytron.com.tw> --- arch/nios2/cpu/cpu.c | 3 ++- arch/nios2/include/asm/global_data.h | 1 + arch/nios2/include/asm/io.h | 8 ++++++-- 3 files changed, 9 insertions(+), 3 deletions(-) diff --git a/arch/nios2/cpu/cpu.c b/arch/nios2/cpu/cpu.c index ff0fa20..88c4e18 100644 --- a/arch/nios2/cpu/cpu.c +++ b/arch/nios2/cpu/cpu.c @@ -117,7 +117,8 @@ static int altera_nios2_probe(struct udevice *dev) "altr,has-initda", 0); gd->arch.has_mmu = fdtdec_get_int(blob, node, "altr,has-mmu", 0); - gd->arch.io_region_base = gd->arch.has_mmu ? 0xe0000000 : 0x8000000; + gd->arch.io_region_base = gd->arch.has_mmu ? 0xe0000000 : 0x80000000; + gd->arch.mem_region_base = gd->arch.has_mmu ? 0xc0000000 : 0x00000000; return 0; } diff --git a/arch/nios2/include/asm/global_data.h b/arch/nios2/include/asm/global_data.h index d6a2cfa..9f3bd00 100644 --- a/arch/nios2/include/asm/global_data.h +++ b/arch/nios2/include/asm/global_data.h @@ -18,6 +18,7 @@ struct arch_global_data { int has_initda; int has_mmu; u32 io_region_base; + u32 mem_region_base; }; #include <asm-generic/global_data.h> diff --git a/arch/nios2/include/asm/io.h b/arch/nios2/include/asm/io.h index e7da35b..007df8d 100644 --- a/arch/nios2/include/asm/io.h +++ b/arch/nios2/include/asm/io.h @@ -18,7 +18,7 @@ static inline void sync(void) * that can be used to access the memory range with the caching * properties specified by "flags". */ -#define MAP_NOCACHE (0) +#define MAP_NOCACHE (1) #define MAP_WRCOMBINE (0) #define MAP_WRBACK (0) #define MAP_WRTHROUGH (0) @@ -26,7 +26,11 @@ static inline void sync(void) static inline void * map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) { - return (void *)paddr; + DECLARE_GLOBAL_DATA_PTR; + if (flags) + return (void *)(paddr | gd->arch.io_region_base); + else + return (void *)(paddr | gd->arch.mem_region_base); } /* -- 2.1.4

2 2

[U-Boot] [PATCH] nios2: change virt_to_phys to use physaddr_mask in global data
by Thomas Chou 03 Nov '15

03 Nov '15

As virt_to_phys() is used a lot in DMA transfer, change it to use physaddr_mask in global data. This will save an "if" statement and get a little faster. Signed-off-by: Thomas Chou <thomas(a)wytron.com.tw> --- arch/nios2/cpu/cpu.c | 1 + arch/nios2/include/asm/global_data.h | 1 + arch/nios2/include/asm/io.h | 5 +---- 3 files changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/nios2/cpu/cpu.c b/arch/nios2/cpu/cpu.c index 88c4e18..f6d5cd3 100644 --- a/arch/nios2/cpu/cpu.c +++ b/arch/nios2/cpu/cpu.c @@ -119,6 +119,7 @@ static int altera_nios2_probe(struct udevice *dev) "altr,has-mmu", 0); gd->arch.io_region_base = gd->arch.has_mmu ? 0xe0000000 : 0x80000000; gd->arch.mem_region_base = gd->arch.has_mmu ? 0xc0000000 : 0x00000000; + gd->arch.physaddr_mask = gd->arch.has_mmu ? 0x1fffffff : 0x7fffffff; return 0; } diff --git a/arch/nios2/include/asm/global_data.h b/arch/nios2/include/asm/global_data.h index 9f3bd00..9863fd9 100644 --- a/arch/nios2/include/asm/global_data.h +++ b/arch/nios2/include/asm/global_data.h @@ -19,6 +19,7 @@ struct arch_global_data { int has_mmu; u32 io_region_base; u32 mem_region_base; + u32 physaddr_mask; }; #include <asm-generic/global_data.h> diff --git a/arch/nios2/include/asm/io.h b/arch/nios2/include/asm/io.h index 007df8d..3443408 100644 --- a/arch/nios2/include/asm/io.h +++ b/arch/nios2/include/asm/io.h @@ -44,10 +44,7 @@ static inline void unmap_physmem(void *vaddr, unsigned long flags) static inline phys_addr_t virt_to_phys(void * vaddr) { DECLARE_GLOBAL_DATA_PTR; - if (gd->arch.has_mmu) - return (phys_addr_t)vaddr & 0x1fffffff; - else - return (phys_addr_t)vaddr & 0x7fffffff; + return (phys_addr_t)vaddr & gd->arch.physaddr_mask; } static inline void *ioremap(unsigned long physaddr, unsigned long size) -- 2.1.4

2 2