November 2015 - U-Boot

[U-Boot] [v2, 4/4] mmc: fsl_esdhc: enable EVDD automatic control for SD/MMC Legacy Adapter Card
by Yangbo Lu 02 Nov '15

02 Nov '15

When detecting SDHC Adapter Card Type 2(SD/MMC Legacy Adapter Card), enable EVDD automatic control via SDHC_VS. This could support SD card IO voltage switching for UHS-1 speed mode. Signed-off-by: Yangbo Lu <yangbo.lu(a)freescale.com> --- board/freescale/common/qixis.h | 3 +++ drivers/mmc/fsl_esdhc.c | 3 +++ 2 files changed, 6 insertions(+) diff --git a/board/freescale/common/qixis.h b/board/freescale/common/qixis.h index 450cd0d..0aa56a0 100644 --- a/board/freescale/common/qixis.h +++ b/board/freescale/common/qixis.h @@ -125,10 +125,13 @@ void qixis_write_i2c(unsigned int reg, u8 value); #define QIXIS_ESDHC_ADAPTER_TYPE_MMC 0x5 /* MMC Card */ #define QIXIS_ESDHC_ADAPTER_TYPE_SD 0x6 /* SD Card Rev2.0 3.0 */ #define QIXIS_ESDHC_NO_ADAPTER 0x7 /* No Card is Present*/ + #define QIXIS_SDCLKIN 0x08 #define QIXIS_SDCLKOUT 0x02 #define QIXIS_DAT5_6_7 0X02 #define QIXIS_DAT4 0X01 + +#define QIXIS_EVDD_BY_SDHC_VS 0x0c #endif #endif diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 639ec02..f400dc9 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -752,6 +752,9 @@ void mmc_adapter_card_type_ident(void) QIXIS_WRITE(brdcfg[5], value); break; case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY: + value = QIXIS_READ(pwr_ctl[1]); + value |= QIXIS_EVDD_BY_SDHC_VS; + QIXIS_WRITE(pwr_ctl[1], value); break; case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44: value = QIXIS_READ(brdcfg[5]); -- 2.1.0.27.g96db324

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[U-Boot] [v2, 3/4] powerpc/t1040qds: enable peripheral clock for eSDHC
by Yangbo Lu 02 Nov '15

02 Nov '15

Signed-off-by: Yangbo Lu <yangbo.lu(a)freescale.com> --- include/configs/T1040QDS.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 8353b8f..92bc295 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -593,6 +593,7 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_MMC #define CONFIG_FSL_ESDHC +#define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR #define CONFIG_CMD_MMC #define CONFIG_GENERIC_MMC -- 2.1.0.27.g96db324

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[U-Boot] [v2, 2/4] powerpc/t1040qds: enable adapter card type identification support
by Yangbo Lu 02 Nov '15

02 Nov '15

Signed-off-by: Yangbo Lu <yangbo.lu(a)freescale.com> --- include/configs/T1040QDS.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index a0390a8..8353b8f 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -599,6 +599,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMD_EXT2 #define CONFIG_CMD_FAT #define CONFIG_DOS_PARTITION +#define CONFIG_FSL_ESDHC_ADAPTER_IDENT #endif /* Qman/Bman */ -- 2.1.0.27.g96db324

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[U-Boot] [v2, 1/4] mmc: fsl_esdhc: enable dat[4:7] for eMMC4.5 Adapter Card
by Yangbo Lu 02 Nov '15

02 Nov '15

If adapter card type identification is supported for platform, we would enable dat[4:7] for eMMC4.5 Adapter Card. Signed-off-by: Yangbo Lu <yangbo.lu(a)freescale.com> --- Changes for v2: - Modified the commit message - Added a patch enabling EVDD automatic control --- board/freescale/common/qixis.h | 2 ++ drivers/mmc/fsl_esdhc.c | 3 +++ 2 files changed, 5 insertions(+) diff --git a/board/freescale/common/qixis.h b/board/freescale/common/qixis.h index 51ce9c3..450cd0d 100644 --- a/board/freescale/common/qixis.h +++ b/board/freescale/common/qixis.h @@ -127,6 +127,8 @@ void qixis_write_i2c(unsigned int reg, u8 value); #define QIXIS_ESDHC_NO_ADAPTER 0x7 /* No Card is Present*/ #define QIXIS_SDCLKIN 0x08 #define QIXIS_SDCLKOUT 0x02 +#define QIXIS_DAT5_6_7 0X02 +#define QIXIS_DAT4 0X01 #endif #endif diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 0b37002..639ec02 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -747,6 +747,9 @@ void mmc_adapter_card_type_ident(void) switch (card_id) { case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45: + value = QIXIS_READ(brdcfg[5]); + value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7); + QIXIS_WRITE(brdcfg[5], value); break; case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY: break; -- 2.1.0.27.g96db324

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[U-Boot] [PATCH] Powerpc: eSDHC: expand a fix to T4160
by shh.xie＠gmail.com 02 Nov '15

02 Nov '15

From: Shaohui Xie <Shaohui.Xie(a)freescale.com> commit b8e5b07225 "Powerpc: eSDHC: Fix mmc read write err in uboot of T4240QDS board", T4160 also needs this fix. Signed-off-by: Shaohui Xie <Shaohui.Xie(a)freescale.com> --- drivers/mmc/fsl_esdhc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 0b37002..73730b3 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -106,7 +106,8 @@ static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) xfertyp |= XFERTYP_RSPTYP_48; #if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240) || \ - defined(CONFIG_LS102XA) || defined(CONFIG_LS2085A) + defined(CONFIG_LS102XA) || defined(CONFIG_LS2085A) || \ + defined(CONFIG_PPC_T4160) if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) xfertyp |= XFERTYP_CMDTYP_ABORT; #endif -- 2.1.0.27.g96db324

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[U-Boot] [PATCH V2] t1040d4rdb: assign muxed pins to qe-tdm when set hwconfig qe-tdm
by Zhao Qiang 02 Nov '15

02 Nov '15

qe-tdm is muxed with diu, if hwconfig setted as qe-tdm, assign muxed pins to qe-tdm, then delete diu node from device tree. Signed-off-by: Zhao Qiang <qiang.zhao(a)freescale.com> --- changes for v2 - move fdt_del_diu to arch/powerpc/cpu/mpc85xx/fdt.c - add new .h file arch/powerpc/include/asm/fsl_fdt.h for FSL-FDT arch/powerpc/cpu/mpc85xx/fdt.c | 11 +++++++++++ arch/powerpc/include/asm/fsl_fdt.h | 11 +++++++++++ board/freescale/t104xrdb/cpld.h | 1 + board/freescale/t104xrdb/t104xrdb.c | 10 ++++++++++ 4 files changed, 33 insertions(+) create mode 100644 arch/powerpc/include/asm/fsl_fdt.h diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index d4c3d9d..7270be1 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -13,6 +13,7 @@ #include <asm/processor.h> #include <linux/ctype.h> #include <asm/io.h> +#include <asm/fsl_fdt.h> #include <asm/fsl_portals.h> #include <hwconfig.h> #ifdef CONFIG_FSL_ESDHC @@ -943,3 +944,13 @@ int ft_verify_fdt(void *fdt) return 1; } + +void fdt_del_diu(void *blob) +{ + int nodeoff = 0; + + while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, + "fsl,diu")) >= 0) { + fdt_del_node(blob, nodeoff); + } +} diff --git a/arch/powerpc/include/asm/fsl_fdt.h b/arch/powerpc/include/asm/fsl_fdt.h new file mode 100644 index 0000000..82e8f45 --- /dev/null +++ b/arch/powerpc/include/asm/fsl_fdt.h @@ -0,0 +1,11 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _FSL_FDT_H_ +#define _FSL_FDT_H_ + +void fdt_del_diu(void *blob); + +#endif diff --git a/board/freescale/t104xrdb/cpld.h b/board/freescale/t104xrdb/cpld.h index 2fb4105..86de26c 100644 --- a/board/freescale/t104xrdb/cpld.h +++ b/board/freescale/t104xrdb/cpld.h @@ -44,3 +44,4 @@ void cpld_write(unsigned int reg, u8 value); cpld_write(offsetof(struct cpld_data, reg), value) #define MISC_CTL_SG_SEL 0x80 #define MISC_CTL_AURORA_SEL 0x02 +#define MISC_MUX_QE_TDM 0xc0 diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c index d982dfc..3227652 100644 --- a/board/freescale/t104xrdb/t104xrdb.c +++ b/board/freescale/t104xrdb/t104xrdb.c @@ -6,12 +6,14 @@ #include <common.h> #include <command.h> +#include <hwconfig.h> #include <netdev.h> #include <linux/compiler.h> #include <asm/mmu.h> #include <asm/processor.h> #include <asm/cache.h> #include <asm/immap_85xx.h> +#include <asm/fsl_fdt.h> #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> #include <asm/fsl_portals.h> @@ -110,6 +112,12 @@ int misc_init_r(void) MISC_CTL_SG_SEL | MISC_CTL_AURORA_SEL); #if defined(CONFIG_T1040D4RDB) + if (hwconfig("qe-tdm")) { + CPLD_WRITE(sfp_ctl_status, CPLD_READ(sfp_ctl_status) | + MISC_MUX_QE_TDM); + printf("QECSR : 0x%02x, mux to qe-tdm\n", + CPLD_READ(sfp_ctl_status)); + } /* Mask all CPLD interrupt sources, except QSGMII interrupts */ if (CPLD_READ(sw_ver) < 0x03) { debug("CPLD SW version 0x%02x doesn't support int_mask\n", @@ -149,5 +157,7 @@ int ft_board_setup(void *blob, bd_t *bd) fdt_fixup_fman_ethernet(blob); #endif + if (hwconfig("qe-tdm")) + fdt_del_diu(blob); return 0; } -- 2.1.0.27.g96db324

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[U-Boot] genboardscfg.py doesn't generate boards.cfg in my cygwin env
by jo.van.montfort1＠telenet.be 02 Nov '15

02 Nov '15

After I run ./tools/genboardscfg.py my boards.cfg stays empty. I use python 2.7 in a cygwin env. Can someone look at my output .txt file pls. Tnx!

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[U-Boot] dm-spi: Convert to driver model
by Jagan Teki 02 Nov '15

02 Nov '15

Hi All, I'm trying to port or helping anyone from below driver authors to convert these drivers to driver model [1] And I couldn't find any dts for the boards which uses these spi drivers if anyone knows if there is a dts which already exist in the code or in Linux please let me know. armada100_spi.c atmel_spi.c bfin_spi6xx.c bfin_spi.c cf_qspi.c cf_spi.c davinci_spi.c ep93xx_spi.c fsl_espi.c kirkwood_spi.c lpc32xx_ssp.c mpc52xx_spi.c mpc8xxx_spi.c mxc_spi.c mxs_spi.c omap3_spi.c sh_qspi.c sh_spi.c soft_spi_legacy.c ti_qspi.c [1] doc/driver-model/spi-howto.txt thanks! -- Jagan | openedev.

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[U-Boot] [RFC PATCH] x86: Support booting SeaBIOS
by Bin Meng 02 Nov '15

02 Nov '15

SeaBIOS is an open source implementation of a 16-bit X86 BIOS. It can run in an emulator or natively on X86 hardware with the use of coreboot. With SeaBIOS's help, we can boot some OSes that require 16-bit BIOS services like Windows/DOS. As U-Boot, we have to manually create a table where SeaBIOS gets system information (eg: E820) from. The table unfortunately has to follow the coreboot table format as SeaBIOS currently supports booting as a coreboot payload. No U-Boot native support there. Booting SeaBIOS is done via U-Boot's bootelf command. This is the initial attempt to support booting SeaBIOS from U-Boot. If the basic concept is good, I can spend time working on follow-on patches to enable BIOS tables as well as graphics support. One issue is that U-Boot x86 does not has a ROM file system like coreboot. This brings difficulities to pass PCI option ROM to SeaBIOS, if we don't modify SeaBIOS's source codes. Maybe we should promote CBFS in U-Boot x86? This is tested on an Intel Crown Bay board with VGA card, booting SeaBIOS then chain loading a GRUB on a USB drive, then Linux kernel finally. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- arch/x86/Kconfig | 10 ++++++++++ arch/x86/include/asm/tables.h | 29 +++++++++++++++++++++++++++++ arch/x86/lib/tables.c | 39 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 78 insertions(+) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 5e42d7d..b432ff8 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -401,6 +401,16 @@ config PCIE_ECAM_SIZE so a default 0x10000000 size covers all of the 256 buses which is the maximum number of PCI buses as defined by the PCI specification. +config SEABIOS + bool "Support booting SeaBIOS" + help + SeaBIOS is an open source implementation of a 16-bit X86 BIOS. + It can run in an emulator or natively on X86 hardware with the use + of coreboot/U-Boot. By turning on this option, U-Boot prepares + all the configuration tables that are necessary to boot SeaBIOS. + + Check http://www.seabios.org/SeaBIOS for details. + source "arch/x86/lib/efi/Kconfig" endmenu diff --git a/arch/x86/include/asm/tables.h b/arch/x86/include/asm/tables.h index 0aa6d9b..a083cac 100644 --- a/arch/x86/include/asm/tables.h +++ b/arch/x86/include/asm/tables.h @@ -7,6 +7,32 @@ #ifndef _X86_TABLES_H_ #define _X86_TABLES_H_ +#ifdef CONFIG_SEABIOS + +#define CB_TAG_MEMORY 1 + +struct cb_header { + u8 signature[4]; + u32 header_bytes; + u32 header_checksum; + u32 table_bytes; + u32 table_checksum; + u32 table_entries; +}; + +struct cb_memory_range { + u64 start; + u64 size; + u32 type; +}; + +struct cb_memory { + u32 tag; + u32 size; + struct cb_memory_range map[0]; +}; +#endif + /* * All x86 tables happen to like the address range from 0xf0000 to 0x100000. * We use 0xf0000 as the starting address to store those tables, including @@ -14,6 +40,9 @@ */ #define ROM_TABLE_ADDR 0xf0000 +/* SeaBIOS expects coreboot tables at address range 0x0000-0x1000 */ +#define CB_TABLE_ADDR 0x800 + /** * table_compute_checksum() - Compute a table checksum * diff --git a/arch/x86/lib/tables.c b/arch/x86/lib/tables.c index f15b2e2..5849b2f 100644 --- a/arch/x86/lib/tables.c +++ b/arch/x86/lib/tables.c @@ -9,6 +9,7 @@ #include <asm/mpspec.h> #include <asm/tables.h> #include <asm/acpi_table.h> +#include <asm/e820.h> u8 table_compute_checksum(void *v, int len) { @@ -36,6 +37,41 @@ void table_fill_string(char *dest, const char *src, size_t n, char pad) dest[i] = pad; } +#ifdef CONFIG_SEABIOS +static u32 write_cb_tables(u32 addr) +{ + struct cb_header *cbh = (struct cb_header *)addr; + struct cb_memory *mem; + struct cb_memory_range *map; + struct e820entry entry[32]; + int num, i; + + memset(cbh, 0, sizeof(struct cb_header)); + strncpy((char *)cbh->signature, "LBIO", 4); + cbh->header_bytes = sizeof(struct cb_header); + + /* populate memory map table */ + mem = (struct cb_memory *)(cbh + 1); + mem->tag = CB_TAG_MEMORY; + map = mem->map; + num = install_e820_map(32, entry); + for (i = 0; i < num; i++) { + map->start = entry[i].addr; + map->size = entry[i].size; + map->type = entry[i].type; + map++; + } + mem->size = num * sizeof(struct cb_memory_range) + 8; + + cbh->table_bytes = mem->size; + cbh->table_checksum = compute_ip_checksum(mem, cbh->table_bytes); + cbh->table_entries = 1; + cbh->header_checksum = compute_ip_checksum(cbh, cbh->header_bytes); + + return (u32)map; +} +#endif + void write_tables(void) { u32 __maybe_unused rom_table_end = ROM_TABLE_ADDR; @@ -56,4 +92,7 @@ void write_tables(void) rom_table_end = write_acpi_tables(rom_table_end); rom_table_end = ALIGN(rom_table_end, 1024); #endif +#ifdef CONFIG_SEABIOS + write_cb_tables(CB_TABLE_ADDR); +#endif } -- 1.8.2.1

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[U-Boot] [PATCH 5/5] samsung: clean up checkpatch issues
by Minkyu Kang 02 Nov '15

02 Nov '15

This patch will fix these checkpatch issues. CHECK: Alignment should match open parenthesis + printf("Enter: %s %s\n", mode_name[mode][0], + mode_info[mode]); CHECK: Alignment should match open parenthesis + lcd_printf("\n\n\t%s %s\n", mode_name[mode][0], + mode_info[mode]); CHECK: Alignment should match open parenthesis + lcd_printf("\t%s %s - %s\n\n", selection[i], + mode_name[i][0], Signed-off-by: Minkyu Kang <mk7.kang(a)samsung.com> --- board/samsung/common/misc.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c index e0e2c48..e46c6c6 100644 --- a/board/samsung/common/misc.c +++ b/board/samsung/common/misc.c @@ -256,9 +256,9 @@ static int mode_leave_menu(int mode) cmd = find_cmd(mode_name[mode][1]); if (cmd) { printf("Enter: %s %s\n", mode_name[mode][0], - mode_info[mode]); + mode_info[mode]); lcd_printf("\n\n\t%s %s\n", mode_name[mode][0], - mode_info[mode]); + mode_info[mode]); lcd_puts("\n\tDo not turn off device before finish!\n"); cmd_result = run_command(mode_cmd[mode], 0); @@ -315,8 +315,7 @@ static void display_download_menu(int mode) for (i = 0; i <= BOOT_MODE_EXIT; i++) lcd_printf("\t%s %s - %s\n\n", selection[i], - mode_name[i][0], - mode_info[i]); + mode_name[i][0], mode_info[i]); } static void download_menu(void) -- 1.7.9.5 -- Thanks, Minkyu Kang.

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