November 2015 - U-Boot

[U-Boot] [PATCH 1/4] x86: ivybridge: Remove NORTHBRIDGE_INTEL_SANDYBRIDGE
by Bin Meng 25 Nov '15

25 Nov '15

NORTHBRIDGE_INTEL_SANDYBRIDGE is for sandybridge, not ivybridge. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- arch/x86/cpu/ivybridge/Kconfig | 33 +-------------------------------- 1 file changed, 1 insertion(+), 32 deletions(-) diff --git a/arch/x86/cpu/ivybridge/Kconfig b/arch/x86/cpu/ivybridge/Kconfig index 0e249a4..d20c038 100644 --- a/arch/x86/cpu/ivybridge/Kconfig +++ b/arch/x86/cpu/ivybridge/Kconfig @@ -5,37 +5,11 @@ # # SPDX-License-Identifier: GPL-2.0 - -config NORTHBRIDGE_INTEL_SANDYBRIDGE - bool - select CACHE_MRC_BIN - select CPU_INTEL_MODEL_206AX - config NORTHBRIDGE_INTEL_IVYBRIDGE bool select CACHE_MRC_BIN select CPU_INTEL_MODEL_306AX -if NORTHBRIDGE_INTEL_SANDYBRIDGE - -config VGA_BIOS_ID - string - default "8086,0106" - -config CACHE_MRC_SIZE_KB - int - default 256 - -config DCACHE_RAM_BASE - hex - default 0xff7f0000 - -config DCACHE_RAM_SIZE - hex - default 0x10000 - -endif - if NORTHBRIDGE_INTEL_IVYBRIDGE config VGA_BIOS_ID @@ -58,10 +32,6 @@ config DCACHE_RAM_SIZE hex default 0x20000 -endif - -if NORTHBRIDGE_INTEL_SANDYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE - config HAVE_MRC bool "Add a System Agent binary" help @@ -83,8 +53,7 @@ config DCACHE_RAM_MRC_VAR_SIZE config MRC_FILE string "Intel System Agent path and filename" depends on HAVE_MRC - default "systemagent-ivybridge.bin" if NORTHBRIDGE_INTEL_IVYBRIDGE - default "systemagent-sandybridge.bin" if NORTHBRIDGE_INTEL_SANDYBRIDGE + default "systemagent-ivybridge.bin" help The path and filename of the file to use as System Agent binary. -- 1.8.2.1

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[U-Boot] [PATCH 1/6] arm: ls1021a: merge SoC specific code in a separate file
by Yuan Yao 25 Nov '15

25 Nov '15

Create a soc.c file to put the code for soc special settings. Signed-off-by: Yuan Yao <yao.yuan(a)freescale.com> --- arch/arm/cpu/armv7/ls102xa/Makefile | 1 + arch/arm/cpu/armv7/ls102xa/soc.c | 66 +++++++++++++++++++++++++ arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h | 12 +++++ board/freescale/ls1021aqds/ls1021aqds.c | 49 +----------------- board/freescale/ls1021atwr/ls1021atwr.c | 42 +--------------- 5 files changed, 83 insertions(+), 87 deletions(-) create mode 100644 arch/arm/cpu/armv7/ls102xa/soc.c create mode 100644 arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h diff --git a/arch/arm/cpu/armv7/ls102xa/Makefile b/arch/arm/cpu/armv7/ls102xa/Makefile index 2311468..0228300 100644 --- a/arch/arm/cpu/armv7/ls102xa/Makefile +++ b/arch/arm/cpu/armv7/ls102xa/Makefile @@ -8,6 +8,7 @@ obj-y += cpu.o obj-y += clock.o obj-y += timer.o obj-y += fsl_epu.o +obj-y += soc.o obj-$(CONFIG_SCSI_AHCI_PLAT) += ls102xa_sata.o obj-$(CONFIG_OF_LIBFDT) += fdt.o diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c new file mode 100644 index 0000000..0fdd6d4 --- /dev/null +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -0,0 +1,66 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/clock.h> +#include <asm/io.h> +#include <asm/arch/immap_ls102xa.h> +#include <asm/arch/ls102xa_soc.h> + +unsigned int get_soc_major_rev(void) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + unsigned int svr, major; + + svr = in_be32(&gur->svr); + major = SVR_MAJ(svr); + + return major; +} + +int arch_soc_init(void) +{ + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; + struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; + unsigned int major; + +#ifdef CONFIG_FSL_QSPI + out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); +#endif + +#ifdef CONFIG_FSL_DCU_FB + out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN); +#endif + + /* Configure Little endian for SAI, ASRC and SPDIF */ + out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE); + + /* + * Enable snoop requests and DVM message requests for + * Slave insterface S4 (A7 core cluster) + */ + out_le32(&cci->slave[4].snoop_ctrl, + CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); + + major = get_soc_major_rev(); + if (major == SOC_MAJOR_VER_1_0) { + /* + * Set CCI-400 Slave interface S1, S2 Shareable Override + * Register All transactions are treated as non-shareable + */ + out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); + out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); + + /* Workaround for the issue that DDR could not respond to + * barrier transaction which is generated by executing DSB/ISB + * instruction. Set CCI-400 control override register to + * terminate the barrier transaction. After DDR is initialized, + * allow barrier transaction to DDR again */ + out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); + } + + return 0; +} diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h new file mode 100644 index 0000000..f10cb91 --- /dev/null +++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h @@ -0,0 +1,12 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_LS102XA_SOC_H +#define __FSL_LS102XA_SOC_H + +unsigned int get_soc_major_rev(void); +int arch_soc_init(void); +#endif /* __FSL_LS102XA_SOC_H */ diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index d889ad5..be3358a 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -11,6 +11,7 @@ #include <asm/arch/clock.h> #include <asm/arch/fsl_serdes.h> #include <asm/arch/ls102xa_stream_id.h> +#include <asm/arch/ls102xa_soc.h> #include <asm/arch/ls102xa_devdis.h> #include <asm/arch/ls102xa_sata.h> #include <hwconfig.h> @@ -140,17 +141,6 @@ unsigned long get_board_ddr_clk(void) return 66666666; } -unsigned int get_soc_major_rev(void) -{ - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); - unsigned int svr, major; - - svr = in_be32(&gur->svr); - major = SVR_MAJ(svr); - - return major; -} - int select_i2c_ch_pca9547(u8 ch) { int ret; @@ -193,8 +183,6 @@ int board_mmc_init(bd_t *bis) int board_early_init_f(void) { struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; - struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; - unsigned int major; #ifdef CONFIG_TSEC_ENET /* clear BD & FR bits for BE BD's and frame data */ @@ -205,40 +193,7 @@ int board_early_init_f(void) init_early_memctl_regs(); #endif -#ifdef CONFIG_FSL_QSPI - out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); -#endif - -#ifdef CONFIG_FSL_DCU_FB - out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN); -#endif - - /* Configure Little endian for SAI, ASRC and SPDIF */ - out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE); - - /* - * Enable snoop requests and DVM message requests for - * Slave insterface S4 (A7 core cluster) - */ - out_le32(&cci->slave[4].snoop_ctrl, - CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); - - major = get_soc_major_rev(); - if (major == SOC_MAJOR_VER_1_0) { - /* - * Set CCI-400 Slave interface S1, S2 Shareable Override - * Register All transactions are treated as non-shareable - */ - out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); - out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); - - /* Workaround for the issue that DDR could not respond to - * barrier transaction which is generated by executing DSB/ISB - * instruction. Set CCI-400 control override register to - * terminate the barrier transaction. After DDR is initialized, - * allow barrier transaction to DDR again */ - out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); - } + arch_soc_init(); #if defined(CONFIG_DEEP_SLEEP) if (is_warm_boot()) diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index 4918c11..8eaff5f 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -12,6 +12,7 @@ #include <asm/arch/fsl_serdes.h> #include <asm/arch/ls102xa_stream_id.h> #include <asm/arch/ls102xa_devdis.h> +#include <asm/arch/ls102xa_soc.h> #include <asm/arch/ls102xa_sata.h> #include <hwconfig.h> #include <mmc.h> @@ -138,17 +139,6 @@ int checkboard(void) return 0; } -unsigned int get_soc_major_rev(void) -{ - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); - unsigned int svr, major; - - svr = in_be32(&gur->svr); - major = SVR_MAJ(svr); - - return major; -} - void ddrmc_init(void) { struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR; @@ -394,8 +384,6 @@ conflict: int board_early_init_f(void) { struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; - struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; - unsigned int major; #ifdef CONFIG_TSEC_ENET /* clear BD & FR bits for BE BD's and frame data */ @@ -407,33 +395,7 @@ int board_early_init_f(void) init_early_memctl_regs(); #endif -#ifdef CONFIG_FSL_DCU_FB - out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN); -#endif - -#ifdef CONFIG_FSL_QSPI - out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); -#endif - - /* Configure Little endian for SAI, ASRC and SPDIF */ - out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE); - - /* - * Enable snoop requests and DVM message requests for - * Slave insterface S4 (A7 core cluster) - */ - out_le32(&cci->slave[4].snoop_ctrl, - CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); - - major = get_soc_major_rev(); - if (major == SOC_MAJOR_VER_1_0) { - /* - * Set CCI-400 Slave interface S1, S2 Shareable Override - * Register All transactions are treated as non-shareable - */ - out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); - out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); - } + arch_soc_init(); #if defined(CONFIG_DEEP_SLEEP) if (is_warm_boot()) { -- 2.1.0.27.g96db324

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[U-Boot] [PATCH 3/4] mx6: clock: Modify GPMI clock to support mx6sx
by Bärtsch Peter 25 Nov '15

25 Nov '15

Hello Stefano, I have seen , that my patch already exist :o but not active in master branch. Follow patch is the original from Ye.Le Kind regards Peter Bärtsch On mx6sx, the CCM register bits for GPMI are different as other mx6 platforms. Modify the GPMI clock function to support mx6sx. Signed-off-by: Ye.Li <b37...(a)freescale.com> --- arch/arm/cpu/armv7/mx6/clock.c | 12 ++++++++++++ 1 files changed, 12 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index fd57f22..ce7f0f7 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -47,6 +47,17 @@ void setup_gpmi_io_clk(u32 cfg) MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK); +#if defined(CONFIG_MX6SX) + clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK); + + clrsetbits_le32(&imx_ccm->cs2cdr, + MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK | + MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK | + MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK, + cfg); + + setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK); +#else clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); clrsetbits_le32(&imx_ccm->cs2cdr, @@ -56,6 +67,7 @@ void setup_gpmi_io_clk(u32 cfg) cfg); setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); +#endif setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | --

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Re: [U-Boot] Rpi Uboot not working ; USB keyboard undetected
by Sumeet Jauhar 25 Nov '15

25 Nov '15

In fact I tried each of the branches ; mainline ; Stephen Warren and also Olex's branch. Olex branch seems to have USB support but it does not work for me . I get a different error now . Saying the "Unrecognized filesystem type **" https://www.dropbox.com/s/n987ko6fxajco7p/P_20151125_182109.jpg?dl=0 Any clues how to go about fixing this ? From: Sumeet Jauhar Sent: Wednesday, 25 November, 2015 4:56 PM To: 'u-boot(a)lists.denx.de' Subject: Rpi Uboot not working ; USB keyboard undetected Hello All, I am new to Rpi and for a project I need to install Uboot for Rpi. For starters I installed Raspbian-jessie to the pi and it worked fine. Now I am attempting to use uboot but I don't succeed. I am trying to follow the instructions http://elinux.org/RPi_U-Boot and http://arrizza.org/wiki/index.php/RPI_U-boot . Here is what i have done so far. 1) Downloaded and compiled the code from "Stephen Warren's work-in-progress branch" (and also from the mainline when the former did not work). I used a Debian box to compile and and used CROSS_COMPILE=arm-linux-gnueabi- . I am able to successfully build uboot.bin 2) Now I copy uboot.bin to the SD card. I replace the config.txt to have a line kernel=uboot.bin . ( I also tried to replace the kernel.bin directly as uboot.bin) Now when I boot the pi I stop at the uboot prompt but my USB keyboard and USB mouse are not recognized . I can't do anything ! How do I communicate with the pi ?? My question seems similar to https://www.raspberrypi.org/forums/viewtopic.php?f=28&t=104383 but I see no fix for the problem. I am attaching an image of the bootup so maybe you guys can point the error .. https://www.dropbox.com/s/dn4njagoes5f7 ... R.jpg?dl=0<https://www.dropbox.com/s/dn4njagoes5f7ll/P_20151124_204301_HDR.jpg?dl=0> Regards

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[U-Boot] GCC5.x support for old u-boot version
by Ayoub Zaki 25 Nov '15

25 Nov '15

Hello, we have an am335x based custom board that use for our Project. At the moment only a customized version of uboot-2013.01.01 supports this board. As we use Yocto toolchains and we plan to upgrade to latest Yocto-2.0 that comes with GCC5.2. I would like to be able to build this custom old version with newer toolchains. For that I added from new u-boot the file : include/linux/compiler-gcc5.h But still having some compile errors : | arm-poky-linux-gnueabi-gcc --sysroot=/yocto/build/tmp/sysroots/shc -g -Os -fno-common -ffixed-r8 -msoft-float -D__KERNEL__ -DCONFIG_SYS_TEXT_BASE=0x80800000 -DCONFIG_SPL_TEXT_BASE=0x402F0400 -I/yocto/build/tmp/work/shc-poky-linux-gnueabi/u-boot-shc/1.0-r1/git/include -fno-builtin -ffreestanding -nostdinc -isystem /yocto/build/tmp/sysroots/x86_64-linux/usr/lib/arm-poky-linux-gnueabi/gcc/arm-poky-linux-gnueabi/5.2.0/include -pipe -DCONFIG_ARM -D__ARM__ -marm -mno-thumb-interwork -mabi=aapcs-linux -march=armv7-a -mcpu=cortex-a8 -Wall -Wstrict-prototypes -fno-stack-protector -Wno-format-nonliteral -Wno-format-security -fstack-usage -o s_record.o s_record.c -c | main.c:62:6: error: 'show_boot_progress' aliased to external symbol '__show_boot_progress' | void show_boot_progress (int val) __attribute__((weak, alias("__show_boot_progress"))); | ^ | make[1]: *** [main.o] Error 1 | make[1]: Leaving directory `/yocto/build/tmp/work/shc-poky-linux-gnueabi/u-boot/1.0-r1/git/common' | make: *** [common/libcommon.o] Error 2 Any chance to backport GCC5 support to old u-boot version ? Thank you for suggestions. Best regards, Ayoub Zaki

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[U-Boot] [PATCH v1] kirkwood_spi: move all pin multiplexing to spi_claim
by Valentin Longchamp 25 Nov '15

25 Nov '15

The pin multiplexing for the chip select pin was until now done in spi_setup_slave/spi_free_slave. If an SPI slave was probed, its chip select pin was never configured back to the possible alternate pin usage until spi_free_slave was called, even if the bus was released and the pins give back to the alternate function at the end of the accesses. This is now regrouped with the pin multiplexing for the MISO/MOSI/SCK signals in the spi_claim_bus/spi_release_bus. It allows to make sure that the pin multiplexing in working correctly even if an SPI slave remains "probed/active". Signed-off-by: Valentin Longchamp <valentin.longchamp(a)keymile.com> --- drivers/spi/kirkwood_spi.c | 39 ++++++++++++++++++++------------------- 1 file changed, 20 insertions(+), 19 deletions(-) diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c index e7b0982..a95ce78 100644 --- a/drivers/spi/kirkwood_spi.c +++ b/drivers/spi/kirkwood_spi.c @@ -21,22 +21,11 @@ static struct kwspi_registers *spireg = (struct kwspi_registers *)MVEBU_SPI_BASE; -#ifdef CONFIG_KIRKWOOD -static u32 cs_spi_mpp_back[2]; -#endif - struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, unsigned int max_hz, unsigned int mode) { struct spi_slave *slave; u32 data; -#ifdef CONFIG_KIRKWOOD - static const u32 kwspi_mpp_config[2][2] = { - { MPP0_SPI_SCn, 0 }, /* if cs == 0 */ - { MPP7_SPI_SCn, 0 } /* if cs != 0 */ - }; -#endif - if (!spi_cs_is_valid(bus, cs)) return NULL; @@ -58,19 +47,11 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, writel(KWSPI_SMEMRDIRQ, &spireg->irq_cause); writel(KWSPI_IRQMASK, &spireg->irq_mask); -#ifdef CONFIG_KIRKWOOD - /* program mpp registers to select SPI_CSn */ - kirkwood_mpp_conf(kwspi_mpp_config[cs ? 1 : 0], cs_spi_mpp_back); -#endif - return slave; } void spi_free_slave(struct spi_slave *slave) { -#ifdef CONFIG_KIRKWOOD - kirkwood_mpp_conf(cs_spi_mpp_back, NULL); -#endif free(slave); } @@ -83,8 +64,20 @@ __attribute__((weak)) int board_spi_claim_bus(struct spi_slave *slave) return 0; } +#ifdef CONFIG_KIRKWOOD +static u32 cs_spi_mpp_back[2]; +#endif + int spi_claim_bus(struct spi_slave *slave) { +#ifdef CONFIG_KIRKWOOD + static const u32 kwspi_mpp_config[2][2] = { + { MPP0_SPI_SCn, 0 }, /* if cs == 0 */ + { MPP7_SPI_SCn, 0 } /* if cs != 0 */ + }; + unsigned int cs = slave->cs; +#endif + #if defined(CONFIG_SYS_KW_SPI_MPP) u32 config; u32 spi_mpp_config[4]; @@ -113,6 +106,11 @@ int spi_claim_bus(struct spi_slave *slave) kirkwood_mpp_conf(spi_mpp_config, spi_mpp_backup); #endif +#ifdef CONFIG_KIRKWOOD + /* program mpp registers to select SPI_CSn */ + kirkwood_mpp_conf(kwspi_mpp_config[cs ? 1 : 0], cs_spi_mpp_back); +#endif + return board_spi_claim_bus(slave); } @@ -126,6 +124,9 @@ void spi_release_bus(struct spi_slave *slave) kirkwood_mpp_conf(spi_mpp_backup, NULL); #endif +#ifdef CONFIG_KIRKWOOD + kirkwood_mpp_conf(cs_spi_mpp_back, NULL); +#endif board_spi_release_bus(slave); } -- 1.8.3.1

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[U-Boot] [PATCH 0/6] gpt: command: Add support for "gpt verify" command
by Lukasz Majewski 25 Nov '15

25 Nov '15

Up till now "gpt" command was only able to write (i.e. restore) GPT partition on specified medium with information provided at "$partitions" env variable. This patch series adds complementary feature - namely "gpt verify", which allows checking (at e.g. boot time) if previously created GPT layout is still correct. This patch series clearly applies on top of u-boot/master: SHA1: cad04990715f7eaecd45196e84cf10e9e3248dae It has been tested on Beaglebone Black development board (Sitara AM335x CPU). Lukasz Majewski (6): gpt: command: Remove duplicated check for empty partition description gpt: command: cosmetic: Replace printf with puts gpt: doc: README: Update README entry for gpt verify extension gpt: doc: Update gpt command's help description gpt: part: Definition and declaration of GPT verification functions gpt: command: Extend gpt command to support GPT table verification common/cmd_gpt.c | 106 ++++++++++++++++++++++++++++++++++++++----------------- disk/part_efi.c | 101 ++++++++++++++++++++++++++++++++++++++++++++++++++++ doc/README.gpt | 26 +++++++++++++- include/part.h | 35 ++++++++++++++++++ 4 files changed, 235 insertions(+), 33 deletions(-) -- 2.1.4

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[U-Boot] [PATCH v3 0/3] Serial Flash: call spi_flash_free more coherently
by Valentin Longchamp 25 Nov '15

25 Nov '15

Some board require spi_flash_free to be called after all the accesses, in order, for instance, to restore the pin multiplexing configuration in the case where the SPI pins are multiplexed. This patch series tries to enhance this. Patch 1 adds spi_flash_free calls to env_sf so that the SPI interface is always "cleaned up" after the env read/writes. Patch 2 adds a 'sf release' command that implicitly calls spi_flash_free and is thus the pendant of 'sf probe'. Patch 3 uses the 'sf command' for the km_arm board scripts. The whole series had already been sent more than 2 years ago [1] but it was rejected without any feedback. So I send this rebased v2 so that it finally gets reviewed and merged. This was not successfull either, again without any given feedback. So this is a 3rd attempt to get some feedback to get this mailined. [1] http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/169723 Changes in v3: - Rebased on v2015.10 - Rebased on v2015.10 Changes in v2: - Rebased on v2014.10 Valentin Longchamp (3): cmd_sf: add 'release' command env_sf: generalize call to spi_flash_free after accesses km_arm: call 'sf release' in the newenv and update scripts common/cmd_sf.c | 11 +++++++++++ common/env_sf.c | 28 ++++++++++++++-------------- include/configs/km/km_arm.h | 6 ++++-- 3 files changed, 29 insertions(+), 16 deletions(-) -- 1.8.3.1

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[U-Boot] [PATCH v3 05/11] dm: timer: Support 64-bit counter
by Simon Glass 25 Nov '15

25 Nov '15

From: Bin Meng <bmeng.cn(a)gmail.com> There are timers with a 64-bit counter value but current timer uclass driver assumes a 32-bit one. Modify timer_get_count() to ask timer driver to always return a 64-bit counter value, and provide an inline helper function timer_conv_64() to handle the 32-bit/64-bit conversion automatically. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> Acked-by: Simon Glass <sjg(a)chromium.org> Signed-off-by: Simon Glass <sjg(a)chromium.org> --- Changes in v3: - Change timer_conv_64() to a normal function instead of inline - Avoid using DECLARE_GLOBAL_DATA_PTR in the timer.h header file drivers/timer/altera_timer.c | 4 ++-- drivers/timer/sandbox_timer.c | 2 +- drivers/timer/timer-uclass.c | 15 ++++++++++++--- include/timer.h | 14 +++++++++++--- lib/time.c | 9 ++++++--- 5 files changed, 32 insertions(+), 12 deletions(-) diff --git a/drivers/timer/altera_timer.c b/drivers/timer/altera_timer.c index 2364f1b..89fe05b 100644 --- a/drivers/timer/altera_timer.c +++ b/drivers/timer/altera_timer.c @@ -34,7 +34,7 @@ struct altera_timer_platdata { struct altera_timer_regs *regs; }; -static int altera_timer_get_count(struct udevice *dev, unsigned long *count) +static int altera_timer_get_count(struct udevice *dev, u64 *count) { struct altera_timer_platdata *plat = dev->platdata; struct altera_timer_regs *const regs = plat->regs; @@ -46,7 +46,7 @@ static int altera_timer_get_count(struct udevice *dev, unsigned long *count) /* Read timer value */ val = readl(&regs->snapl) & 0xffff; val |= (readl(&regs->snaph) & 0xffff) << 16; - *count = ~val; + *count = timer_conv_64(~val); return 0; } diff --git a/drivers/timer/sandbox_timer.c b/drivers/timer/sandbox_timer.c index 4b20af2..00a9944 100644 --- a/drivers/timer/sandbox_timer.c +++ b/drivers/timer/sandbox_timer.c @@ -18,7 +18,7 @@ void sandbox_timer_add_offset(unsigned long offset) sandbox_timer_offset += offset; } -static int sandbox_timer_get_count(struct udevice *dev, unsigned long *count) +static int sandbox_timer_get_count(struct udevice *dev, u64 *count) { *count = os_get_nsec() / 1000 + sandbox_timer_offset * 1000; diff --git a/drivers/timer/timer-uclass.c b/drivers/timer/timer-uclass.c index 0218591..aca421b 100644 --- a/drivers/timer/timer-uclass.c +++ b/drivers/timer/timer-uclass.c @@ -13,14 +13,14 @@ DECLARE_GLOBAL_DATA_PTR; /* * Implement a timer uclass to work with lib/time.c. The timer is usually - * a 32 bits free-running up counter. The get_rate() method is used to get + * a 32/64 bits free-running up counter. The get_rate() method is used to get * the input clock frequency of the timer. The get_count() method is used - * to get the current 32 bits count value. If the hardware is counting down, + * to get the current 64 bits count value. If the hardware is counting down, * the value should be inversed inside the method. There may be no real * tick, and no timer interrupt. */ -int timer_get_count(struct udevice *dev, unsigned long *count) +int timer_get_count(struct udevice *dev, u64 *count) { const struct timer_ops *ops = device_get_ops(dev); @@ -47,6 +47,15 @@ static int timer_pre_probe(struct udevice *dev) return 0; } +u64 timer_conv_64(u32 count) +{ + /* increment tbh if tbl has rolled over */ + if (count < gd->timebase_l) + gd->timebase_h++; + gd->timebase_l = count; + return ((u64)gd->timebase_h << 32) | gd->timebase_l; +} + UCLASS_DRIVER(timer) = { .id = UCLASS_TIMER, .name = "timer", diff --git a/include/timer.h b/include/timer.h index ed5c685..7fee17e 100644 --- a/include/timer.h +++ b/include/timer.h @@ -8,13 +8,21 @@ #define _TIMER_H_ /* + * timer_conv_64 - convert 32-bit counter value to 64-bit + * + * @count: 32-bit counter value + * @return: 64-bit counter value + */ +u64 timer_conv_64(u32 count); + +/* * Get the current timer count * * @dev: The timer device * @count: pointer that returns the current timer count * @return: 0 if OK, -ve on error */ -int timer_get_count(struct udevice *dev, unsigned long *count); +int timer_get_count(struct udevice *dev, u64 *count); /* * Get the timer input clock frequency @@ -35,10 +43,10 @@ struct timer_ops { * Get the current timer count * * @dev: The timer device - * @count: pointer that returns the current timer count + * @count: pointer that returns the current 64-bit timer count * @return: 0 if OK, -ve on error */ - int (*get_count)(struct udevice *dev, unsigned long *count); + int (*get_count)(struct udevice *dev, u64 *count); }; /* diff --git a/lib/time.c b/lib/time.c index b001745..f37a662 100644 --- a/lib/time.c +++ b/lib/time.c @@ -69,9 +69,9 @@ ulong notrace get_tbclk(void) return timer_get_rate(gd->timer); } -unsigned long notrace timer_read_counter(void) +uint64_t notrace get_ticks(void) { - unsigned long count; + u64 count; int ret; ret = dm_timer_init(); @@ -84,7 +84,8 @@ unsigned long notrace timer_read_counter(void) return count; } -#endif /* CONFIG_TIMER */ + +#else /* !CONFIG_TIMER */ uint64_t __weak notrace get_ticks(void) { @@ -97,6 +98,8 @@ uint64_t __weak notrace get_ticks(void) return ((uint64_t)gd->timebase_h << 32) | gd->timebase_l; } +#endif /* CONFIG_TIMER */ + /* Returns time in milliseconds */ static uint64_t notrace tick_to_time(uint64_t tick) { -- 2.6.0.rc2.230.g3dd15c0

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[U-Boot] [PATCH V2] arm: novena: Switch novena to config_distro_bootcmd
by Marek Vasut 25 Nov '15

25 Nov '15

From: Vagrant Cascadian <vagrant(a)aikidev.net> Switch Novena to distro bootcmd, so it can be used with debian easily. Signed-off-by: Vagrant Cascadian <vagrant(a)aikidev.net> Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Sean Cross <xobs(a)kosagi.com> Cc: Stefano Babic <sbabic(a)denx.de> --- include/configs/novena.h | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) V2: Drop the duplicate kernel_addr_r setting diff --git a/include/configs/novena.h b/include/configs/novena.h index 718989f..3bb406d 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -16,6 +16,7 @@ #define CONFIG_FIT #define CONFIG_KEYBOARD +#include <config_distro_defaults.h> #include "mx6_common.h" /* U-Boot Commands */ @@ -58,7 +59,7 @@ /* Booting Linux */ #define CONFIG_BOOTFILE "fitImage" #define CONFIG_BOOTARGS "console=ttymxc1,115200 " -#define CONFIG_BOOTCOMMAND "run net_nfs" +#define CONFIG_BOOTCOMMAND "run distro_bootcmd ; run net_nfs" #define CONFIG_HOSTNAME novena /* Physical Memory Map */ @@ -190,6 +191,7 @@ #endif /* Extra U-Boot environment. */ +#ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ @@ -199,6 +201,10 @@ "rootdev=/dev/mmcblk0p2\0" \ "netdev=eth0\0" \ "kernel_addr_r="__stringify(CONFIG_LOADADDR)"\0" \ + "pxefile_addr_r="__stringify(CONFIG_LOADADDR)"\0" \ + "scriptaddr="__stringify(CONFIG_LOADADDR)"\0" \ + "ramdisk_addr_r=0x28000000\0" \ + "fdt_addr_r=0x10000000\0" \ "addcons=" \ "setenv bootargs ${bootargs} " \ "console=${consdev},${baudrate}\0" \ @@ -242,5 +248,19 @@ "fatwrite mmc 0:1 ${loadaddr} u-boot.img ${filesize} ; "\ "fi ; " \ "fi\0" \ + BOOTENV + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(USB, usb, 0) \ + func(SATA, sata, 0) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) + +#include <config_distro_bootcmd.h> + +#else +#define CONFIG_EXTRA_ENV_SETTINGS +#endif /* CONFIG_SPL_BUILD */ #endif /* __CONFIG_H */ -- 2.1.4

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