November 2015 - U-Boot

[U-Boot] PCIE_MEM_BUS for Freescale SoC
by York Sun 23 Nov '15

23 Nov '15

Roy, Do you remember the reason why we use different virtual memory address from pci bus address with 36-bit? For example include/configs/P1022DS.h-496-#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 include/configs/P1022DS.h-497-#ifdef CONFIG_PHYS_64BIT include/configs/P1022DS.h:498:#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 include/configs/P1022DS.h-499-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull include/configs/P1022DS.h-500-#else include/configs/P1022DS.h:501:#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 include/configs/P1022DS.h-502-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 include/configs/P1022DS.h-503-#endif As far as I can tell, the following is the mapping TLB: MEM_VIRT=>MEM_PHYS PCI: MEM_BUS=>MEM_PHYS LAW: MEM_PHYS=>pcie interface Being different for MEM_VIRT and MEM_BUS cause confusion. When I run "pci header" command to show the BARs, I expect I can use "md" to access the BAR address. That's not the case if MEM_BUS is different from MEM_VIRT. I forget why we did this for 36-bit addressing. The MEM_VIRT is the same as MEM_BUS for 32-bit addressing. And why do we use the same MEM_BUS address for all PCIe hose? I know they are not conflicting, but is it necessary? Let me know if you have any concerns. Otherwise I will change all platforms to use consistent addresses. York

2 6

[U-Boot] [PATCH V2] ARM: tegra: refactor common Kconfig options
by Stephen Warren 23 Nov '15

23 Nov '15

From: Stephen Warren <swarren(a)nvidia.com> This makes it easier to select common options in a single place, rather than having to add them separately for different SoCs or architectures. The lists of select statements are now also sorted for easy searching. Signed-off-by: Stephen Warren <swarren(a)nvidia.com> Reviewed-by: Simon Glass <sjg(a)chromium.org> --- v2: Rebase on latest Kconfig changes in u-boot/master. --- arch/arm/mach-tegra/Kconfig | 38 ++++++++++++++++++++------------------ 1 file changed, 20 insertions(+), 18 deletions(-) diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index de2454e691d2..75b9208a33e3 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -1,18 +1,27 @@ if TEGRA -config TEGRA_ARMV7_COMMON - bool "Tegra 32-bit" - select SUPPORT_SPL - select SPL - select OF_CONTROL - select CPU_V7 +config TEGRA_COMMON + bool "Tegra common options" select DM - select DM_SPI_FLASH - select DM_SERIAL - select DM_I2C - select DM_SPI select DM_GPIO + select DM_I2C select DM_KEYBOARD + select DM_SERIAL + select DM_SPI + select DM_SPI_FLASH + select OF_CONTROL + +config TEGRA_ARMV7_COMMON + bool "Tegra 32-bit common options" + select CPU_V7 + select SPL + select SUPPORT_SPL + select TEGRA_COMMON + +config TEGRA_ARMV8_COMMON + bool "Tegra 64-bit common options" + select ARM64 + select TEGRA_COMMON choice prompt "Tegra SoC select" @@ -36,14 +45,7 @@ config TEGRA124 config TEGRA210 bool "Tegra210 family" - select OF_CONTROL - select ARM64 - select DM - select DM_SPI_FLASH - select DM_SERIAL - select DM_I2C - select DM_SPI - select DM_GPIO + select TEGRA_ARMV8_COMMON endchoice -- 1.9.1

4 4

[U-Boot] Riotboard FEC broken
by Catalin Crenguta 23 Nov '15

23 Nov '15

Hello, I have ran git bisect commit and found out that commit 59370f3fcd135089c402c93720a87c688abe600c breaks FEC on Riotboard. Reverting this change makes it working again. Full log below: git bisect start # bad: [5ec0003b19cbdf06ccd6941237cbc0d1c3468e2d] Prepare v2015.10 git bisect bad 5ec0003b19cbdf06ccd6941237cbc0d1c3468e2d # good: [f33cdaa4c3da4a8fd35aa2f9a3172f31cc887b35] Prepare v2015.04 git bisect good f33cdaa4c3da4a8fd35aa2f9a3172f31cc887b35 # good: [8ed43b966ccf7f1153f553dce86de60a6e0e9d9a] arm: mvebu: Add SPL SDIO/MMC boot support git bisect good 8ed43b966ccf7f1153f553dce86de60a6e0e9d9a # bad: [ce2cb1d3ed92e91b24db516802be3688f7c28e26] arm: mvebu: db-88f6820-gp: Enable PCI support git bisect bad ce2cb1d3ed92e91b24db516802be3688f7c28e26 # good: [9bbd2132e3af95ac225f3641b69bd129da11457f] driver/ddr/altera: Add DDR driver for Altera's SDRAM controller git bisect good 9bbd2132e3af95ac225f3641b69bd129da11457f # good: [15f8876b1dd95dd6bcee686ada36369871bbcdc9] Merge branch 'master' of http://git.denx.de/u-boot-sunxi git bisect good 15f8876b1dd95dd6bcee686ada36369871bbcdc9 # bad: [fcd78fa604d994477fd209b9faab4a974b103250] Merge branch 'master' of git://git.denx.de/u-boot-net git bisect bad fcd78fa604d994477fd209b9faab4a974b103250 # good: [3f394e70f0cc31a5d63d3650fd4f48e450ea16cd] integrator: switch to DM serial port git bisect good 3f394e70f0cc31a5d63d3650fd4f48e450ea16cd # good: [b5d92ba1ad97c06985ebc689e1ac1462a146832d] ARM: SPL: Use CONFIG_SPL_DM not CONFIG_DM git bisect good b5d92ba1ad97c06985ebc689e1ac1462a146832d # bad: [59370f3fcd135089c402c93720a87c688abe600c] net: phy: delay only if reset handler is registered git bisect bad 59370f3fcd135089c402c93720a87c688abe600c # good: [8396d0ab8b46907bd89e9f3a35fbb727f077d28a] net: Add support for Marvell 88E1510 PHY git bisect good 8396d0ab8b46907bd89e9f3a35fbb727f077d28a # good: [23f5db0e26f0e6c25ba143e700b4812efdd5f941] net: lpc32xx: improve MAC configuration on reset and initialization git bisect good 23f5db0e26f0e6c25ba143e700b4812efdd5f941 # good: [466f775e02bcde5ea7454cd73ecf1a0f79275a30] qoriq eth.c bugfix: handle received corrupted frames correctly git bisect good 466f775e02bcde5ea7454cd73ecf1a0f79275a30 # good: [2c171a2a5fc0865501a2e5043e9728036dac6dc3] net: phy: fix data type of phy_id git bisect good 2c171a2a5fc0865501a2e5043e9728036dac6dc3 # first bad commit: [59370f3fcd135089c402c93720a87c688abe600c] net: phy: delay only if reset handler is registered Best regards, Catalin Crenguta

3 3

[U-Boot] [PATCH] mx6sxsabresd: Fix Ethernet PHY reset sequence
by Fabio Estevam 23 Nov '15

23 Nov '15

From: Fabio Estevam <fabio.estevam(a)freescale.com> Since commit 59370f3fcd1350 ("net: phy: delay only if reset handler is registered") Ethernet is no longer functional. This commit does not have an issue in itself, but it revelead a problem with the Ethernet initialization. Fix this by calling enable_fec_anatop_clock() earlier and also by adding a 10ms reset delay as recommended in the AR8031 datasheet. Suggested-by: Jörg Krause <joerg.krause(a)embedded.rock> Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- board/freescale/mx6sxsabresd/mx6sxsabresd.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c index 3ee4662..56dc020 100644 --- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c +++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c @@ -150,11 +150,15 @@ static int setup_fec(void) { struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; - int reg; + int reg, ret; /* Use 125MHz anatop loopback REF_CLK1 for ENET1 */ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0); + ret = enable_fec_anatop_clock(0, ENET_125MHZ); + if (ret) + return ret; + imx_iomux_v3_setup_multiple_pads(phy_control_pads, ARRAY_SIZE(phy_control_pads)); @@ -163,14 +167,14 @@ static int setup_fec(void) /* Reset AR8031 PHY */ gpio_direction_output(IMX_GPIO_NR(2, 7) , 0); - udelay(500); + mdelay(10); gpio_set_value(IMX_GPIO_NR(2, 7), 1); reg = readl(&anatop->pll_enet); reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE; writel(reg, &anatop->pll_enet); - return enable_fec_anatop_clock(0, ENET_125MHZ); + return 0; } int board_eth_init(bd_t *bis) -- 1.9.1

1 0

[U-Boot] [PATCH v1] powerpc: Set PCIe MEM_BUS same as MEM_VIRT
by York Sun 23 Nov '15

23 Nov '15

For 36-bit addressing mode, PCIe virtual memory addresses have been different from PCI bus addresses. This causes confusion when trying to access the PCI address manually. Previously it was believed overlapping PCI(e) controllers' space would leave more room for large memory. Actually u-boot has been using no more than 512MB for each controller. Making the bus address same as virtual address simplifies the address space, and users can access PCI(e) space under u-boot prompt without calcuating the offset. No change for 32-bit mode as the addresses are consistent. Signed-off-by: York Sun <yorksun(a)freescale.com> --- Tested on P4080DS, P1022DS, T2080QDS. include/configs/B4860QDS.h | 3 +-- include/configs/MPC8536DS.h | 12 ++++-------- include/configs/MPC8548CDS.h | 6 ++---- include/configs/MPC8572DS.h | 9 +++------ include/configs/MPC8641HPCN.h | 12 +----------- include/configs/P1010RDB.h | 6 ++---- include/configs/P1022DS.h | 9 +++------ include/configs/P2041RDB.h | 9 +++------ include/configs/T102xQDS.h | 9 +++------ include/configs/T102xRDB.h | 12 ++++-------- include/configs/T1040QDS.h | 8 ++++---- include/configs/T104xRDB.h | 8 ++++---- include/configs/T208xQDS.h | 8 ++++---- include/configs/T208xRDB.h | 8 ++++---- include/configs/T4240RDB.h | 9 +++++---- include/configs/controlcenterd.h | 3 +-- include/configs/corenet_ds.h | 12 +++++------- include/configs/cyrus.h | 12 +++++------- include/configs/km/kmp204x-common.h | 4 ++-- include/configs/p1_p2_rdb_pc.h | 6 ++---- include/configs/t4qds.h | 6 +++--- 21 files changed, 65 insertions(+), 106 deletions(-) diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index c83e5ce..66ead35 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -609,11 +609,10 @@ unsigned long get_board_ddr_clk(void); /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull #else -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 #endif #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 29c27fa..51d69c5 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -435,11 +435,10 @@ */ #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_VIRT #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCI1_MEM_BUS 0xf0000000 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull #else -#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 #endif #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ @@ -455,11 +454,10 @@ /* controller 1, Slot 1, tgtid 1, Base address a000 */ #define CONFIG_SYS_PCIE1_NAME "Slot 1" #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 +#define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull #else -#define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 #endif #define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */ @@ -475,11 +473,10 @@ /* controller 2, Slot 2, tgtid 2, Base address 9000 */ #define CONFIG_SYS_PCIE2_NAME "Slot 2" #define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000 +#define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE2_MEM_VIRT #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc18000000ull #else -#define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000 #endif #define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */ @@ -495,11 +492,10 @@ /* controller 3, direct to uli, tgtid 3, Base address 8000 */ #define CONFIG_SYS_PCIE3_NAME "Slot 3" #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE3_MEM_BUS CONFIG_SYS_PCIE3_MEM_VIRT #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull #else -#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 #endif #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 517b449..eed97b1 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -362,11 +362,10 @@ extern unsigned long get_clock_freq(void); * Memory space is mapped 1-1, but I/O space must start from 0. */ #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_VIRT #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull #else -#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 #endif #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ @@ -382,11 +381,10 @@ extern unsigned long get_clock_freq(void); #ifdef CONFIG_PCIE1 #define CONFIG_SYS_PCIE1_NAME "Slot" #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull #else -#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 #endif #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 19da477..afe96fc 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -423,11 +423,10 @@ /* controller 3, direct to uli, tgtid 3, Base address 8000 */ #define CONFIG_SYS_PCIE3_NAME "ULI" #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE3_MEM_BUS CONFIG_SYS_PCIE3_MEM_VIRT #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull #else -#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 #endif #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ @@ -443,11 +442,10 @@ /* controller 2, Slot 2, tgtid 2, Base address 9000 */ #define CONFIG_SYS_PCIE2_NAME "Slot 1" #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE2_MEM_VIRT #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull #else -#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 #endif #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ @@ -463,11 +461,10 @@ /* controller 1, Slot 1, tgtid 1, Base address a000 */ #define CONFIG_SYS_PCIE1_NAME "Slot 2" #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 +#define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull #else -#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 #endif #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 6f1535e..c088b92 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -313,12 +313,11 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_PCIE1_NAME "ULI" #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW 0x00000000 #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x0000000c #else -#define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW CONFIG_SYS_PCIE1_MEM_VIRT #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x00000000 #endif @@ -334,17 +333,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); CONFIG_SYS_PHYS_ADDR_HIGH) #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64K */ -#ifdef CONFIG_PHYS_64BIT -/* - * Use the same PCI bus address on PCIE1 and PCIE2 if we have PHYS_64BIT. - * This will increase the amount of PCI address space available for - * for mapping RAM. - */ -#define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE1_MEM_BUS -#else #define CONFIG_SYS_PCIE2_MEM_BUS (CONFIG_SYS_PCIE1_MEM_BUS \ + CONFIG_SYS_PCIE1_MEM_SIZE) -#endif #define CONFIG_SYS_PCIE2_MEM_VIRT (CONFIG_SYS_PCIE1_MEM_VIRT \ + CONFIG_SYS_PCIE1_MEM_SIZE) #define CONFIG_SYS_PCIE2_MEM_PHYS_LOW (CONFIG_SYS_PCIE1_MEM_PHYS_LOW \ diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 81b0855..24b8146 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -193,11 +193,10 @@ /* controller 1, Slot 1, tgtid 1, Base address a000 */ #define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot" #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull #else -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 #endif #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ @@ -217,11 +216,10 @@ #define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot" #endif #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE2_MEM_VIRT #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull #else -#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 #endif #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index a9d825b..5d31712 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -494,11 +494,10 @@ /* controller 1, Slot 2, tgtid 1, Base address a000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 +#define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull #else -#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 #endif #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ @@ -513,11 +512,10 @@ /* controller 2, direct to uli, tgtid 2, Base address 9000 */ #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE2_MEM_VIRT #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull #else -#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 #endif #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ @@ -532,11 +530,10 @@ /* controller 3, Slot 1, tgtid 3, Base address b000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE3_MEM_BUS CONFIG_SYS_PCIE3_MEM_VIRT #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull #else -#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 #endif #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 2c4c8b5..d9c7677 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -423,11 +423,10 @@ unsigned long get_board_sys_clk(unsigned long dummy); /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull #else -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 #endif #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ @@ -442,11 +441,10 @@ unsigned long get_board_sys_clk(unsigned long dummy); /* controller 2, Slot 2, tgtid 2, Base address 201000 */ #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE2_MEM_VIRT #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull #else -#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 #endif #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ @@ -461,11 +459,10 @@ unsigned long get_board_sys_clk(unsigned long dummy); /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 +#define CONFIG_SYS_PCIE3_MEM_BUS CONFIG_SYS_PCIE3_MEM_VIRT #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull #else -#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 #endif #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h index 52942ed..15ec054 100644 --- a/include/configs/T102xQDS.h +++ b/include/configs/T102xQDS.h @@ -606,11 +606,10 @@ unsigned long get_board_ddr_clk(void); /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #ifdef CONFIG_PCIE1 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull #else -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 #endif #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ @@ -627,11 +626,10 @@ unsigned long get_board_ddr_clk(void); /* controller 2, Slot 2, tgtid 2, Base address 201000 */ #ifdef CONFIG_PCIE2 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 +#define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE2_MEM_VIRT #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull #else -#define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 #endif #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ @@ -648,11 +646,10 @@ unsigned long get_board_ddr_clk(void); /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #ifdef CONFIG_PCIE3 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE3_MEM_BUS CONFIG_SYS_PCIE3_MEM_VIRT #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull #else -#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 #endif #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 39fa5e2..65f7e4c 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -598,11 +598,10 @@ unsigned long get_board_ddr_clk(void); /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #ifdef CONFIG_PCIE1 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull #else -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 #endif #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ @@ -619,11 +618,10 @@ unsigned long get_board_ddr_clk(void); /* controller 2, Slot 2, tgtid 2, Base address 201000 */ #ifdef CONFIG_PCIE2 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 +#define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE2_MEM_VIRT #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull #else -#define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 #endif #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ @@ -640,11 +638,10 @@ unsigned long get_board_ddr_clk(void); /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #ifdef CONFIG_PCIE3 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE3_MEM_BUS CONFIG_SYS_PCIE3_MEM_VIRT #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull #else -#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 #endif #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ @@ -661,11 +658,10 @@ unsigned long get_board_ddr_clk(void); /* controller 4, Base address 203000, to be removed */ #ifdef CONFIG_PCIE4 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 +#define CONFIG_SYS_PCIE4_MEM_BUS CONFIG_SYS_PCIE4_MEM_VIRT #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull #else -#define CONFIG_SYS_PCIE4_MEM_BUS 0xb0000000 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xb0000000 #endif #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index fc263df..e4e410c 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -500,7 +500,7 @@ unsigned long get_board_ddr_clk(void); /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #ifdef CONFIG_PCIE1 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 @@ -512,7 +512,7 @@ unsigned long get_board_ddr_clk(void); /* controller 2, Slot 2, tgtid 2, Base address 201000 */ #ifdef CONFIG_PCIE2 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE2_MEM_VIRT #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 @@ -524,7 +524,7 @@ unsigned long get_board_ddr_clk(void); /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #ifdef CONFIG_PCIE3 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_BUS CONFIG_SYS_PCIE3_MEM_VIRT #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 @@ -536,7 +536,7 @@ unsigned long get_board_ddr_clk(void); /* controller 4, Base address 203000 */ #ifdef CONFIG_PCIE4 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 -#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_BUS CONFIG_SYS_PCIE4_MEM_VIRT #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 840be04..918c72a 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -558,7 +558,7 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #ifdef CONFIG_PCIE1 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 @@ -570,7 +570,7 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg /* controller 2, Slot 2, tgtid 2, Base address 201000 */ #ifdef CONFIG_PCIE2 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE2_MEM_VIRT #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 @@ -582,7 +582,7 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #ifdef CONFIG_PCIE3 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_BUS CONFIG_SYS_PCIE3_MEM_VIRT #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 @@ -594,7 +594,7 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg /* controller 4, Base address 203000 */ #ifdef CONFIG_PCIE4 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 -#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_BUS CONFIG_SYS_PCIE4_MEM_VIRT #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index a81f1e6..0d71568 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -578,7 +578,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 @@ -588,7 +588,7 @@ unsigned long get_board_ddr_clk(void); /* controller 2, Slot 2, tgtid 2, Base address 201000 */ #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE2_MEM_VIRT #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 @@ -598,7 +598,7 @@ unsigned long get_board_ddr_clk(void); /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_BUS CONFIG_SYS_PCIE3_MEM_VIRT #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 @@ -608,7 +608,7 @@ unsigned long get_board_ddr_clk(void); /* controller 4, Base address 203000 */ #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 -#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_BUS CONFIG_SYS_PCIE4_MEM_VIRT #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 8b76234..b86e353 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -526,7 +526,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 @@ -536,7 +536,7 @@ unsigned long get_board_ddr_clk(void); /* controller 2, Slot 2, tgtid 2, Base address 201000 */ #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE2_MEM_VIRT #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 @@ -546,7 +546,7 @@ unsigned long get_board_ddr_clk(void); /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_BUS CONFIG_SYS_PCIE3_MEM_VIRT #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 @@ -556,7 +556,7 @@ unsigned long get_board_ddr_clk(void); /* controller 4, Base address 203000 */ #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 -#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_BUS CONFIG_SYS_PCIE4_MEM_VIRT #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 2e875d2..1ad2029 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -238,7 +238,7 @@ /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 @@ -248,7 +248,7 @@ /* controller 2, Slot 2, tgtid 2, Base address 201000 */ #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE2_MEM_VIRT #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 @@ -258,7 +258,7 @@ /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_BUS CONFIG_SYS_PCIE3_MEM_VIRT #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 @@ -267,7 +267,8 @@ #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ /* controller 4, Base address 203000 */ -#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_BUS (CONFIG_SYS_PCIE3_MEM_BUS +\ + CONFIG_SYS_PCIE3_MEM_SIZE) #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h index 600bb83..4ed987b 100644 --- a/include/configs/controlcenterd.h +++ b/include/configs/controlcenterd.h @@ -266,11 +266,10 @@ #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 +#define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull #else -#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 #endif #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 9210216..77a8d62 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -428,11 +428,10 @@ /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull #else -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 #endif #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ @@ -447,11 +446,10 @@ /* controller 2, Slot 2, tgtid 2, Base address 201000 */ #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE2_MEM_VIRT #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull #else -#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 #endif #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ @@ -466,11 +464,10 @@ /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 +#define CONFIG_SYS_PCIE3_MEM_BUS CONFIG_SYS_PCIE3_MEM_VIRT #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull #else -#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 #endif #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ @@ -484,7 +481,8 @@ #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ /* controller 4, Base address 203000 */ -#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_BUS (CONFIG_SYS_PCIE3_MEM_BUS +\ + CONFIG_SYS_PCIE3_MEM_SIZE) #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 diff --git a/include/configs/cyrus.h b/include/configs/cyrus.h index 5d25fb1..7a87c7e 100644 --- a/include/configs/cyrus.h +++ b/include/configs/cyrus.h @@ -289,11 +289,10 @@ /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull #else -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 #endif #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ @@ -308,11 +307,10 @@ /* controller 2, Slot 2, tgtid 2, Base address 201000 */ #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE2_MEM_VIRT #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull #else -#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 #endif #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ @@ -327,11 +325,10 @@ /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 +#define CONFIG_SYS_PCIE3_MEM_BUS CONFIG_SYS_PCIE3_MEM_VIRT #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull #else -#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 #endif #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ @@ -345,7 +342,8 @@ #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ /* controller 4, Base address 203000 */ -#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_BUS (CONFIG_SYS_PCIE3_MEM_BUS +\ + CONFIG_SYS_PCIE3_MEM_SIZE) #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h index e163edb..342536f 100644 --- a/include/configs/km/kmp204x-common.h +++ b/include/configs/km/kmp204x-common.h @@ -312,7 +312,7 @@ int get_scl(void); /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 @@ -322,7 +322,7 @@ int get_scl(void); /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_BUS CONFIG_SYS_PCIE3_MEM_VIRT #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8010000 diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 433c409..cce7db1 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -728,11 +728,10 @@ /* controller 2, direct to uli, tgtid 2, Base address 9000 */ #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT" #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE2_MEM_VIRT #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull #else -#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 #endif #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ @@ -748,11 +747,10 @@ /* controller 1, Slot 2, tgtid 1, Base address a000 */ #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull #else -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 #endif #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h index 5754369..0a7ccf6 100644 --- a/include/configs/t4qds.h +++ b/include/configs/t4qds.h @@ -193,7 +193,7 @@ /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 @@ -203,7 +203,7 @@ /* controller 2, Slot 2, tgtid 2, Base address 201000 */ #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE2_MEM_VIRT #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 @@ -213,7 +213,7 @@ /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_BUS CONFIG_SYS_PCIE3_MEM_VIRT #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -- 1.7.9.5

1 1

[U-Boot] [PATCH] arm: socfpga: Repair SoCrates board
by Marek Vasut 23 Nov '15

23 Nov '15

This board was constantly parasiting on the CV SoCDK, so split it into it's own separate directory. Moreover, the board config was missing important bits, like simple-bus support in SPL, the DRAM configuration was incorrect and the DTS was also missing the pre reloc bits. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Stefan Roese <sr(a)denx.de> Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> Cc: Dinh Nguyen <dinh.linux(a)gmail.com> --- arch/arm/dts/socfpga_cyclone5_socrates.dts | 5 + arch/arm/mach-socfpga/Kconfig | 7 + board/ebv/socrates/MAINTAINERS | 6 + board/ebv/socrates/Makefile | 9 + board/ebv/socrates/qts/iocsr_config.h | 660 +++++++++++++++++++++++++++++ board/ebv/socrates/qts/pinmux_config.h | 219 ++++++++++ board/ebv/socrates/qts/pll_config.h | 85 ++++ board/ebv/socrates/qts/sdram_config.h | 341 +++++++++++++++ board/ebv/socrates/socfpga.c | 85 ++++ configs/socfpga_socrates_defconfig | 3 +- include/configs/socfpga_socrates.h | 97 +++++ 11 files changed, 1516 insertions(+), 1 deletion(-) create mode 100644 board/ebv/socrates/MAINTAINERS create mode 100644 board/ebv/socrates/Makefile create mode 100644 board/ebv/socrates/qts/iocsr_config.h create mode 100644 board/ebv/socrates/qts/pinmux_config.h create mode 100644 board/ebv/socrates/qts/pll_config.h create mode 100644 board/ebv/socrates/qts/sdram_config.h create mode 100644 board/ebv/socrates/socfpga.c create mode 100644 include/configs/socfpga_socrates.h diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts index 6782691..05b935d 100644 --- a/arch/arm/dts/socfpga_cyclone5_socrates.dts +++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts @@ -19,6 +19,10 @@ device_type = "memory"; reg = <0x0 0x40000000>; /* 1GB */ }; + + soc { + u-boot,dm-pre-reloc; + }; }; &gmac1 { @@ -37,6 +41,7 @@ &mmc0 { status = "okay"; + u-boot,dm-pre-reloc; }; &qspi { diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index a413ea4..f885703 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -22,6 +22,10 @@ config TARGET_SOCFPGA_DENX_MCVEVK bool "DENX MCVEVK (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 +config TARGET_SOCFPGA_EBV_SOCRATES + bool "EBV SoCrates (Cyclone V)" + select TARGET_SOCFPGA_CYCLONE5 + config TARGET_SOCFPGA_TERASIC_DE0_NANO bool "Terasic DE0-Nano-Atlas (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 @@ -38,11 +42,13 @@ config SYS_BOARD default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT + default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES config SYS_VENDOR default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK default "denx" if TARGET_SOCFPGA_DENX_MCVEVK + default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT @@ -55,5 +61,6 @@ config SYS_CONFIG_NAME default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT + default "socfpga_sockit" if TARGET_SOCFPGA_EBV_SOCRATES endif diff --git a/board/ebv/socrates/MAINTAINERS b/board/ebv/socrates/MAINTAINERS new file mode 100644 index 0000000..e48236f --- /dev/null +++ b/board/ebv/socrates/MAINTAINERS @@ -0,0 +1,6 @@ +SOCRATES BOARD +M: Stefan Roese <sr(a)denx.de> +S: Maintained +F: board/ebv/socrates/ +F: include/configs/socfpga_socrates.h +F: configs/socfpga_socrates_defconfig diff --git a/board/ebv/socrates/Makefile b/board/ebv/socrates/Makefile new file mode 100644 index 0000000..86f9b78 --- /dev/null +++ b/board/ebv/socrates/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# (C) Copyright 2010, Thomas Chou <thomas(a)wytron.com.tw> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := socfpga.o diff --git a/board/ebv/socrates/qts/iocsr_config.h b/board/ebv/socrates/qts/iocsr_config.h new file mode 100644 index 0000000..f1bbe68 --- /dev/null +++ b/board/ebv/socrates/qts/iocsr_config.h @@ -0,0 +1,660 @@ +/* + * Altera SoCFPGA IOCSR configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_IOCSR_CONFIG_H__ +#define __SOCFPGA_IOCSR_CONFIG_H__ + +#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 +#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 +#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 +#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 + +const unsigned long iocsr_scan_chain0_table[] = { + 0x00000000, + 0x00000000, + 0x0FF00000, + 0xC0000000, + 0x0000003F, + 0x00008000, + 0x00004824, + 0x01209000, + 0x82400000, + 0x00018004, + 0x00000000, + 0x00004000, + 0x00002412, + 0x00904800, + 0x41200000, + 0x80000002, + 0x00000904, + 0x00002000, + 0x00001209, + 0x00482400, + 0x20900000, + 0x40000001, + 0x00000482, + 0x00001000, +}; + +const unsigned long iocsr_scan_chain1_table[] = { + 0x00009048, + 0x02412000, + 0x048000C0, + 0x00000009, + 0x00002412, + 0x00008000, + 0x00004824, + 0x01209000, + 0x82400000, + 0x00000004, + 0x00001209, + 0x00004000, + 0x00002412, + 0x00904800, + 0x41200000, + 0x80000002, + 0x00000904, + 0x00002000, + 0x06001209, + 0x00482400, + 0x01FE0000, + 0xF8000000, + 0x00000007, + 0x80001000, + 0x00000904, + 0x00241200, + 0x90480000, + 0x20003000, + 0x00000241, + 0x00000800, + 0x00000000, + 0x00000000, + 0x48240000, + 0x90000000, + 0x00000120, + 0x00000400, + 0x00000000, + 0x00090480, + 0x00000003, + 0x00000000, + 0x00000000, + 0x90000200, + 0x00600120, + 0x00000000, + 0x12090000, + 0x24000600, + 0x00000048, + 0x48000100, + 0x00300090, + 0xC0024120, + 0x09048000, + 0x12000300, + 0x000C0024, + 0x00000080, +}; + +const unsigned long iocsr_scan_chain2_table[] = { + 0x30009048, + 0x00000000, + 0x0FF00000, + 0x00000000, + 0x0C002412, + 0x00008000, + 0x18004824, + 0x00000000, + 0x82400000, + 0x00018004, + 0x06001209, + 0x00004000, + 0x20002412, + 0x00904800, + 0x00000030, + 0x80000000, + 0x03000904, + 0x00002000, + 0x10001209, + 0x00482400, + 0x20900000, + 0x40010001, + 0x00000482, + 0x80001000, + 0x00000904, + 0x00000000, + 0x90480000, + 0x20008000, + 0x00C00241, + 0x00000800, +}; + +const unsigned long iocsr_scan_chain3_table[] = { + 0x0CC20D80, + 0x0C3000FF, + 0x0A804001, + 0x07900000, + 0x08020000, + 0x00100000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0x20430000, + 0x0C003001, + 0x00C00481, + 0x00000000, + 0x00000021, + 0x82000004, + 0x05400000, + 0x03C80000, + 0x04010000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0x90218000, + 0x86001800, + 0x00600240, + 0x80090218, + 0x00000001, + 0x40000002, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x4810C000, + 0x43000C00, + 0x00300120, + 0xC004810C, + 0x12043000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000010, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0xC0680A28, + 0x45034030, + 0x12481A01, + 0x80A280D0, + 0x34030C06, + 0x01A01450, + 0x280D0000, + 0x30C0680A, + 0x02490340, + 0xD000001A, + 0x0680A280, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x18000000, + 0x01800902, + 0x00240860, + 0x007F8006, + 0x00000000, + 0x0A800001, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0x20430000, + 0x0C003001, + 0x00C00481, + 0x00000FF0, + 0x4810C000, + 0x80000C00, + 0x05400000, + 0x02480000, + 0x04000000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0x90218000, + 0x86001800, + 0x00600240, + 0x80090218, + 0x24086001, + 0x40000600, + 0x02A00040, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x4810C000, + 0x43000C00, + 0x00300120, + 0xC004810C, + 0x12043000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000010, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0xC0680A28, + 0x49034030, + 0x12481A02, + 0x80A280D0, + 0x34030C06, + 0x01A00040, + 0x280D0002, + 0x30C0680A, + 0x02490340, + 0xD00A281A, + 0x0680A280, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x18000000, + 0x01800902, + 0x00240860, + 0x007F8006, + 0x00000000, + 0x99300001, + 0x34343400, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x01000000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x2043090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x18864000, + 0x49247A06, + 0xF228A3D5, + 0xF6D1451E, + 0x0342E388, + 0x821A0000, + 0x0000D000, + 0x05140680, + 0xD949247A, + 0x1EF228A3, + 0x88F6D145, + 0x000352E3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x00003FC2, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00015000, + 0x0000F200, + 0x00000000, + 0x00000482, + 0x86120800, + 0x00600240, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x18864000, + 0x49247A06, + 0xF3CF23D5, + 0xF4D1451E, + 0x034A9248, + 0x821A038E, + 0x0000D000, + 0x00000680, + 0xD949247A, + 0x1EF3CF23, + 0x88F4D145, + 0x000352E3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x2043090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x18864000, + 0x49247A06, + 0xF228A3D9, + 0xF4D1451E, + 0x034A9248, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xD949247A, + 0x1EF228A3, + 0x88F4D145, + 0x000352E3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00400000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F1690D, + 0x1A041414, + 0x00D00000, + 0x08864000, + 0x49247A02, + 0xF3CF23D9, + 0xF4D1451E, + 0x0342E388, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xD949247A, + 0x1EF3CF23, + 0x88F4DE79, + 0x000342A2, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0x00489800, + 0x801A1A1A, + 0x00000200, + 0x80000004, + 0x00000200, + 0x80000004, + 0x00000200, + 0x80000004, + 0x00000200, + 0x00000004, + 0x00040000, + 0x10000000, + 0x00000000, + 0x00000040, + 0x00010000, + 0x40002000, + 0x00000100, + 0x40000002, + 0x00000100, + 0x40000002, + 0x00000100, + 0x40000002, + 0x00000100, + 0x00000002, + 0x00020000, + 0x08000000, + 0x00000000, + 0x00000020, + 0x00008000, + 0x20001000, + 0x00000080, + 0x20000001, + 0x00000080, + 0x20000001, + 0x00000080, + 0x20000001, + 0x00000080, + 0x00000001, + 0x00010000, + 0x04000000, + 0x00FF0000, + 0x00000000, + 0x00004000, + 0x00000800, + 0xC0000001, + 0x00041419, + 0x40000000, + 0x04000816, + 0x000D0000, + 0x00006800, + 0x00000340, + 0xD000001A, + 0x06800000, + 0x00340000, + 0x0001A000, + 0x00000D00, + 0x40000068, + 0x1A000003, + 0x00D00000, + 0x00068000, + 0x00003400, + 0x000001A0, + 0x00000401, + 0x00000008, + 0x00000401, + 0x00000008, + 0x00000401, + 0x00000008, + 0x00000401, + 0x80000008, + 0x0000007F, + 0x20000000, + 0x00000000, + 0xE0000080, + 0x0000001F, + 0x00004000, +}; + + +#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */ diff --git a/board/ebv/socrates/qts/pinmux_config.h b/board/ebv/socrates/qts/pinmux_config.h new file mode 100644 index 0000000..4bb654f --- /dev/null +++ b/board/ebv/socrates/qts/pinmux_config.h @@ -0,0 +1,219 @@ +/* + * Altera SoCFPGA PinMux configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_PINMUX_CONFIG_H__ +#define __SOCFPGA_PINMUX_CONFIG_H__ + +const u8 sys_mgr_init_table[] = { + 0, /* EMACIO0 */ + 2, /* EMACIO1 */ + 2, /* EMACIO2 */ + 2, /* EMACIO3 */ + 2, /* EMACIO4 */ + 2, /* EMACIO5 */ + 2, /* EMACIO6 */ + 2, /* EMACIO7 */ + 2, /* EMACIO8 */ + 0, /* EMACIO9 */ + 2, /* EMACIO10 */ + 2, /* EMACIO11 */ + 2, /* EMACIO12 */ + 2, /* EMACIO13 */ + 0, /* EMACIO14 */ + 0, /* EMACIO15 */ + 0, /* EMACIO16 */ + 0, /* EMACIO17 */ + 0, /* EMACIO18 */ + 0, /* EMACIO19 */ + 3, /* FLASHIO0 */ + 0, /* FLASHIO1 */ + 3, /* FLASHIO2 */ + 3, /* FLASHIO3 */ + 0, /* FLASHIO4 */ + 0, /* FLASHIO5 */ + 0, /* FLASHIO6 */ + 0, /* FLASHIO7 */ + 0, /* FLASHIO8 */ + 3, /* FLASHIO9 */ + 3, /* FLASHIO10 */ + 3, /* FLASHIO11 */ + 0, /* GENERALIO0 */ + 1, /* GENERALIO1 */ + 1, /* GENERALIO2 */ + 1, /* GENERALIO3 */ + 1, /* GENERALIO4 */ + 0, /* GENERALIO5 */ + 0, /* GENERALIO6 */ + 1, /* GENERALIO7 */ + 1, /* GENERALIO8 */ + 3, /* GENERALIO9 */ + 3, /* GENERALIO10 */ + 3, /* GENERALIO11 */ + 3, /* GENERALIO12 */ + 2, /* GENERALIO13 */ + 2, /* GENERALIO14 */ + 1, /* GENERALIO15 */ + 1, /* GENERALIO16 */ + 1, /* GENERALIO17 */ + 1, /* GENERALIO18 */ + 0, /* GENERALIO19 */ + 0, /* GENERALIO20 */ + 0, /* GENERALIO21 */ + 0, /* GENERALIO22 */ + 0, /* GENERALIO23 */ + 0, /* GENERALIO24 */ + 0, /* GENERALIO25 */ + 0, /* GENERALIO26 */ + 0, /* GENERALIO27 */ + 0, /* GENERALIO28 */ + 0, /* GENERALIO29 */ + 0, /* GENERALIO30 */ + 0, /* GENERALIO31 */ + 2, /* MIXED1IO0 */ + 2, /* MIXED1IO1 */ + 2, /* MIXED1IO2 */ + 2, /* MIXED1IO3 */ + 2, /* MIXED1IO4 */ + 2, /* MIXED1IO5 */ + 2, /* MIXED1IO6 */ + 2, /* MIXED1IO7 */ + 2, /* MIXED1IO8 */ + 2, /* MIXED1IO9 */ + 2, /* MIXED1IO10 */ + 2, /* MIXED1IO11 */ + 2, /* MIXED1IO12 */ + 2, /* MIXED1IO13 */ + 0, /* MIXED1IO14 */ + 3, /* MIXED1IO15 */ + 3, /* MIXED1IO16 */ + 3, /* MIXED1IO17 */ + 3, /* MIXED1IO18 */ + 3, /* MIXED1IO19 */ + 3, /* MIXED1IO20 */ + 0, /* MIXED1IO21 */ + 0, /* MIXED2IO0 */ + 0, /* MIXED2IO1 */ + 0, /* MIXED2IO2 */ + 0, /* MIXED2IO3 */ + 0, /* MIXED2IO4 */ + 0, /* MIXED2IO5 */ + 0, /* MIXED2IO6 */ + 0, /* MIXED2IO7 */ + 0, /* GPLINMUX48 */ + 0, /* GPLINMUX49 */ + 0, /* GPLINMUX50 */ + 0, /* GPLINMUX51 */ + 0, /* GPLINMUX52 */ + 0, /* GPLINMUX53 */ + 0, /* GPLINMUX54 */ + 0, /* GPLINMUX55 */ + 0, /* GPLINMUX56 */ + 0, /* GPLINMUX57 */ + 0, /* GPLINMUX58 */ + 0, /* GPLINMUX59 */ + 0, /* GPLINMUX60 */ + 0, /* GPLINMUX61 */ + 0, /* GPLINMUX62 */ + 0, /* GPLINMUX63 */ + 0, /* GPLINMUX64 */ + 0, /* GPLINMUX65 */ + 0, /* GPLINMUX66 */ + 0, /* GPLINMUX67 */ + 0, /* GPLINMUX68 */ + 0, /* GPLINMUX69 */ + 0, /* GPLINMUX70 */ + 1, /* GPLMUX0 */ + 1, /* GPLMUX1 */ + 1, /* GPLMUX2 */ + 1, /* GPLMUX3 */ + 1, /* GPLMUX4 */ + 1, /* GPLMUX5 */ + 1, /* GPLMUX6 */ + 1, /* GPLMUX7 */ + 1, /* GPLMUX8 */ + 1, /* GPLMUX9 */ + 1, /* GPLMUX10 */ + 1, /* GPLMUX11 */ + 1, /* GPLMUX12 */ + 1, /* GPLMUX13 */ + 1, /* GPLMUX14 */ + 1, /* GPLMUX15 */ + 1, /* GPLMUX16 */ + 1, /* GPLMUX17 */ + 1, /* GPLMUX18 */ + 1, /* GPLMUX19 */ + 1, /* GPLMUX20 */ + 1, /* GPLMUX21 */ + 1, /* GPLMUX22 */ + 1, /* GPLMUX23 */ + 1, /* GPLMUX24 */ + 1, /* GPLMUX25 */ + 1, /* GPLMUX26 */ + 1, /* GPLMUX27 */ + 1, /* GPLMUX28 */ + 1, /* GPLMUX29 */ + 1, /* GPLMUX30 */ + 1, /* GPLMUX31 */ + 1, /* GPLMUX32 */ + 1, /* GPLMUX33 */ + 1, /* GPLMUX34 */ + 1, /* GPLMUX35 */ + 1, /* GPLMUX36 */ + 1, /* GPLMUX37 */ + 1, /* GPLMUX38 */ + 1, /* GPLMUX39 */ + 1, /* GPLMUX40 */ + 1, /* GPLMUX41 */ + 1, /* GPLMUX42 */ + 1, /* GPLMUX43 */ + 1, /* GPLMUX44 */ + 1, /* GPLMUX45 */ + 1, /* GPLMUX46 */ + 1, /* GPLMUX47 */ + 1, /* GPLMUX48 */ + 1, /* GPLMUX49 */ + 1, /* GPLMUX50 */ + 1, /* GPLMUX51 */ + 1, /* GPLMUX52 */ + 1, /* GPLMUX53 */ + 1, /* GPLMUX54 */ + 1, /* GPLMUX55 */ + 1, /* GPLMUX56 */ + 1, /* GPLMUX57 */ + 1, /* GPLMUX58 */ + 1, /* GPLMUX59 */ + 1, /* GPLMUX60 */ + 1, /* GPLMUX61 */ + 1, /* GPLMUX62 */ + 1, /* GPLMUX63 */ + 1, /* GPLMUX64 */ + 1, /* GPLMUX65 */ + 1, /* GPLMUX66 */ + 1, /* GPLMUX67 */ + 1, /* GPLMUX68 */ + 1, /* GPLMUX69 */ + 1, /* GPLMUX70 */ + 0, /* NANDUSEFPGA */ + 0, /* UART0USEFPGA */ + 0, /* RGMII1USEFPGA */ + 0, /* SPIS0USEFPGA */ + 0, /* CAN0USEFPGA */ + 0, /* I2C0USEFPGA */ + 0, /* SDMMCUSEFPGA */ + 0, /* QSPIUSEFPGA */ + 0, /* SPIS1USEFPGA */ + 0, /* RGMII0USEFPGA */ + 0, /* UART1USEFPGA */ + 0, /* CAN1USEFPGA */ + 0, /* USB1USEFPGA */ + 0, /* I2C3USEFPGA */ + 0, /* I2C2USEFPGA */ + 0, /* I2C1USEFPGA */ + 0, /* SPIM1USEFPGA */ + 0, /* USB0USEFPGA */ + 0 /* SPIM0USEFPGA */ +}; +#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */ diff --git a/board/ebv/socrates/qts/pll_config.h b/board/ebv/socrates/qts/pll_config.h new file mode 100644 index 0000000..c5aea9d --- /dev/null +++ b/board/ebv/socrates/qts/pll_config.h @@ -0,0 +1,85 @@ +/* + * Altera SoCFPGA Clock and PLL configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_PLL_CONFIG_H__ +#define __SOCFPGA_PLL_CONFIG_H__ + +#define CONFIG_HPS_DBCTRL_STAYOSC1 1 + +#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 +#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63 +#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 +#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 +#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 +#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3 +#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 +#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 +#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1 +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1 + +#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0 +#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39 +#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 +#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 +#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 +#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 +#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 +#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 +#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 +#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0 +#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0 +#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 1 +#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4 +#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 +#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2 +#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 +#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1 + +#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 2 +#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 79 +#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 + +#define CONFIG_HPS_CLK_OSC1_HZ 25000000 +#define CONFIG_HPS_CLK_OSC2_HZ 25000000 +#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 +#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000 +#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 +#define CONFIG_HPS_CLK_SDRVCO_HZ 666666666 +#define CONFIG_HPS_CLK_EMAC0_HZ 1953125 +#define CONFIG_HPS_CLK_EMAC1_HZ 250000000 +#define CONFIG_HPS_CLK_USBCLK_HZ 200000000 +#define CONFIG_HPS_CLK_NAND_HZ 50000000 +#define CONFIG_HPS_CLK_SDMMC_HZ 200000000 +#define CONFIG_HPS_CLK_QSPI_HZ 400000000 +#define CONFIG_HPS_CLK_SPIM_HZ 200000000 +#define CONFIG_HPS_CLK_CAN0_HZ 100000000 +#define CONFIG_HPS_CLK_CAN1_HZ 12500000 +#define CONFIG_HPS_CLK_GPIODB_HZ 32000 +#define CONFIG_HPS_CLK_L4_MP_HZ 100000000 +#define CONFIG_HPS_CLK_L4_SP_HZ 100000000 + +#define CONFIG_HPS_ALTERAGRP_MPUCLK 1 +#define CONFIG_HPS_ALTERAGRP_MAINCLK 3 +#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3 + + +#endif /* __SOCFPGA_PLL_CONFIG_H__ */ diff --git a/board/ebv/socrates/qts/sdram_config.h b/board/ebv/socrates/qts/sdram_config.h new file mode 100644 index 0000000..cf9d1d3 --- /dev/null +++ b/board/ebv/socrates/qts/sdram_config.h @@ -0,0 +1,341 @@ +/* + * Altera SoCFPGA SDRAM configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_SDRAM_CONFIG_H__ +#define __SOCFPGA_SDRAM_CONFIG_H__ + +/* SDRAM configuration */ +#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A +#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 +#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 +#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 14 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 117 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 5 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1300 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 5 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 5 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 12 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 17 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 +#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 +#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0 +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 +#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 +#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 +#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 +#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 +#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 +#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 +#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 + +/* Sequencer auto configuration */ +#define RW_MGR_ACTIVATE_0_AND_1 0x0D +#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E +#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10 +#define RW_MGR_ACTIVATE_1 0x0F +#define RW_MGR_CLEAR_DQS_ENABLE 0x49 +#define RW_MGR_GUARANTEED_READ 0x4C +#define RW_MGR_GUARANTEED_READ_CONT 0x54 +#define RW_MGR_GUARANTEED_WRITE 0x18 +#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1B +#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1F +#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x19 +#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1D +#define RW_MGR_IDLE 0x00 +#define RW_MGR_IDLE_LOOP1 0x7B +#define RW_MGR_IDLE_LOOP2 0x7A +#define RW_MGR_INIT_RESET_0_CKE_0 0x6F +#define RW_MGR_INIT_RESET_1_CKE_0 0x74 +#define RW_MGR_LFSR_WR_RD_BANK_0 0x22 +#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x25 +#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x24 +#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x23 +#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x32 +#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x21 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x36 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x39 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x46 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x35 +#define RW_MGR_MRS0_DLL_RESET 0x02 +#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08 +#define RW_MGR_MRS0_USER 0x07 +#define RW_MGR_MRS0_USER_MIRR 0x0C +#define RW_MGR_MRS1 0x03 +#define RW_MGR_MRS1_MIRR 0x09 +#define RW_MGR_MRS2 0x04 +#define RW_MGR_MRS2_MIRR 0x0A +#define RW_MGR_MRS3 0x05 +#define RW_MGR_MRS3_MIRR 0x0B +#define RW_MGR_PRECHARGE_ALL 0x12 +#define RW_MGR_READ_B2B 0x59 +#define RW_MGR_READ_B2B_WAIT1 0x61 +#define RW_MGR_READ_B2B_WAIT2 0x6B +#define RW_MGR_REFRESH_ALL 0x14 +#define RW_MGR_RETURN 0x01 +#define RW_MGR_SGLE_READ 0x7D +#define RW_MGR_ZQCL 0x06 + +/* Sequencer defines configuration */ +#define AFI_RATE_RATIO 1 +#define CALIB_LFIFO_OFFSET 7 +#define CALIB_VFIFO_OFFSET 5 +#define ENABLE_SUPER_QUICK_CALIBRATION 0 +#define IO_DELAY_PER_DCHAIN_TAP 25 +#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25 +#define IO_DELAY_PER_OPA_TAP 375 +#define IO_DLL_CHAIN_LENGTH 8 +#define IO_DQDQS_OUT_PHASE_MAX 0 +#define IO_DQS_EN_DELAY_MAX 31 +#define IO_DQS_EN_DELAY_OFFSET 0 +#define IO_DQS_EN_PHASE_MAX 7 +#define IO_DQS_IN_DELAY_MAX 31 +#define IO_DQS_IN_RESERVE 4 +#define IO_DQS_OUT_RESERVE 4 +#define IO_IO_IN_DELAY_MAX 31 +#define IO_IO_OUT1_DELAY_MAX 31 +#define IO_IO_OUT2_DELAY_MAX 0 +#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0 +#define MAX_LATENCY_COUNT_WIDTH 5 +#define READ_VALID_FIFO_SIZE 16 +#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048d +#define RW_MGR_MEM_ADDRESS_MIRRORING 0 +#define RW_MGR_MEM_DATA_MASK_WIDTH 4 +#define RW_MGR_MEM_DATA_WIDTH 32 +#define RW_MGR_MEM_DQ_PER_READ_DQS 8 +#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8 +#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4 +#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4 +#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1 +#define RW_MGR_MEM_NUMBER_OF_RANKS 1 +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1 +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1 +#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4 +#define TINIT_CNTR0_VAL 82 +#define TINIT_CNTR1_VAL 32 +#define TINIT_CNTR2_VAL 32 +#define TRESET_CNTR0_VAL 82 +#define TRESET_CNTR1_VAL 99 +#define TRESET_CNTR2_VAL 10 + +/* Sequencer ac_rom_init configuration */ +const u32 ac_rom_init[] = { + 0x20700000, + 0x20780000, + 0x10080221, + 0x10080320, + 0x10090044, + 0x100a0008, + 0x100b0000, + 0x10380400, + 0x10080241, + 0x100802c0, + 0x100a0024, + 0x10090010, + 0x100b0000, + 0x30780000, + 0x38780000, + 0x30780000, + 0x10680000, + 0x106b0000, + 0x10280400, + 0x10480000, + 0x1c980000, + 0x1c9b0000, + 0x1c980008, + 0x1c9b0008, + 0x38f80000, + 0x3cf80000, + 0x38780000, + 0x18180000, + 0x18980000, + 0x13580000, + 0x135b0000, + 0x13580008, + 0x135b0008, + 0x33780000, + 0x10580008, + 0x10780000 +}; + +/* Sequencer inst_rom_init configuration */ +const u32 inst_rom_init[] = { + 0x80000, + 0x80680, + 0x8180, + 0x8200, + 0x8280, + 0x8300, + 0x8380, + 0x8100, + 0x8480, + 0x8500, + 0x8580, + 0x8600, + 0x8400, + 0x800, + 0x8680, + 0x880, + 0xa680, + 0x80680, + 0x900, + 0x80680, + 0x980, + 0xa680, + 0x8680, + 0x80680, + 0xb68, + 0xcce8, + 0xae8, + 0x8ce8, + 0xb88, + 0xec88, + 0xa08, + 0xac88, + 0x80680, + 0xce00, + 0xcd80, + 0xe700, + 0xc00, + 0x20ce0, + 0x20ce0, + 0x20ce0, + 0x20ce0, + 0xd00, + 0x680, + 0x680, + 0x680, + 0x680, + 0x60e80, + 0x61080, + 0x61080, + 0x61080, + 0xa680, + 0x8680, + 0x80680, + 0xce00, + 0xcd80, + 0xe700, + 0xc00, + 0x30ce0, + 0x30ce0, + 0x30ce0, + 0x30ce0, + 0xd00, + 0x680, + 0x680, + 0x680, + 0x680, + 0x70e80, + 0x71080, + 0x71080, + 0x71080, + 0xa680, + 0x8680, + 0x80680, + 0x1158, + 0x6d8, + 0x80680, + 0x1168, + 0x7e8, + 0x7e8, + 0x87e8, + 0x40fe8, + 0x410e8, + 0x410e8, + 0x410e8, + 0x1168, + 0x7e8, + 0x7e8, + 0xa7e8, + 0x80680, + 0x40e88, + 0x41088, + 0x41088, + 0x41088, + 0x40f68, + 0x410e8, + 0x410e8, + 0x410e8, + 0xa680, + 0x40fe8, + 0x410e8, + 0x410e8, + 0x410e8, + 0x41008, + 0x41088, + 0x41088, + 0x41088, + 0x1100, + 0xc680, + 0x8680, + 0xe680, + 0x80680, + 0x0, + 0x8000, + 0xa000, + 0xc000, + 0x80000, + 0x80, + 0x8080, + 0xa080, + 0xc080, + 0x80080, + 0x9180, + 0x8680, + 0xa680, + 0x80680, + 0x40f08, + 0x80680 +}; + +#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */ diff --git a/board/ebv/socrates/socfpga.c b/board/ebv/socrates/socfpga.c new file mode 100644 index 0000000..a1dbc49 --- /dev/null +++ b/board/ebv/socrates/socfpga.c @@ -0,0 +1,85 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/reset_manager.h> +#include <asm/io.h> + +#include <usb.h> +#include <usb/s3c_udc.h> +#include <usb_mass_storage.h> + +#include <micrel.h> +#include <netdev.h> +#include <phy.h> + +DECLARE_GLOBAL_DATA_PTR; + +void s_init(void) {} + +/* + * Miscellaneous platform dependent initialisations + */ +int board_init(void) +{ + /* Address of boot parameters for ATAG (if ATAG is used) */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + return 0; +} + +/* + * PHY configuration + */ +#ifdef CONFIG_PHY_MICREL_KSZ9021 +int board_phy_config(struct phy_device *phydev) +{ + int ret; + /* + * These skew settings for the KSZ9021 ethernet phy is required for ethernet + * to work reliably on most flavors of cyclone5 boards. + */ + ret = ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, + 0x0); + if (ret) + return ret; + + ret = ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, + 0x0); + if (ret) + return ret; + + ret = ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, + 0xf0f0); + if (ret) + return ret; + + if (phydev->drv->config) + return phydev->drv->config(phydev); + + return 0; +} +#endif + +#ifdef CONFIG_USB_GADGET +struct s3c_plat_otg_data socfpga_otg_data = { + .regs_otg = CONFIG_USB_DWC2_REG_ADDR, + .usb_gusbcfg = 0x1417, +}; + +int board_usb_init(int index, enum usb_init_type init) +{ + return s3c_udc_probe(&socfpga_otg_data); +} + +int g_dnl_board_usb_cable_connected(void) +{ + return 1; +} +#endif diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig index 07b8447..90a8fb1 100644 --- a/configs/socfpga_socrates_defconfig +++ b/configs/socfpga_socrates_defconfig @@ -3,7 +3,7 @@ CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_SPL_DM=y CONFIG_DM_GPIO=y -CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK=y +CONFIG_TARGET_SOCFPGA_EBV_SOCRATES=y CONFIG_SPL_STACK_R_ADDR=0x00800000 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates" CONFIG_SPL=y @@ -11,6 +11,7 @@ CONFIG_SPL_STACK_R=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y +CONFIG_SPL_SIMPLE_BUS=y CONFIG_DWAPB_GPIO=y CONFIG_SPI_FLASH=y CONFIG_DM_ETH=y diff --git a/include/configs/socfpga_socrates.h b/include/configs/socfpga_socrates.h new file mode 100644 index 0000000..b300e8f --- /dev/null +++ b/include/configs/socfpga_socrates.h @@ -0,0 +1,97 @@ +/* + * Copyright (C) 2015 Marek Vasut <marex(a)denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __CONFIG_SOCFPGA_SOCRATES_H__ +#define __CONFIG_SOCFPGA_SOCRATES_H__ + +#include <asm/arch/socfpga_base_addrs.h> + +/* U-Boot Commands */ +#define CONFIG_SYS_NO_FLASH +#define CONFIG_DOS_PARTITION +#define CONFIG_FAT_WRITE +#define CONFIG_HW_WATCHDOG + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DFU +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE +#define CONFIG_CMD_FAT +#define CONFIG_CMD_FS_GENERIC +#define CONFIG_CMD_GPIO +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_MII +#define CONFIG_CMD_MMC +#define CONFIG_CMD_PING +#define CONFIG_CMD_USB +#define CONFIG_CMD_USB_MASS_STORAGE + +/* Memory configurations */ +#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCrates */ + +/* Booting Linux */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE "zImage" +#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) +#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" +#define CONFIG_LOADADDR 0x01000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* Ethernet on SoC (EMAC) */ +#if defined(CONFIG_CMD_NET) + +/* PHY */ +#define CONFIG_PHY_MICREL +#define CONFIG_PHY_MICREL_KSZ9021 +#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew" +#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0 +#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew" +#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0 + +#endif + +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ +#define CONFIG_ENV_OFFSET 512 /* just after the MBR */ + +/* USB */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS +#endif +#define CONFIG_G_DNL_MANUFACTURER "EBV" + +/* Extra Environment */ +#define CONFIG_HOSTNAME socfpga_socrates + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "verify=n\0" \ + "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "bootimage=zImage\0" \ + "fdt_addr=100\0" \ + "fdtimage=socfpga.dtb\0" \ + "fsloadcmd=ext2load\0" \ + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "mmcroot=/dev/mmcblk0p2\0" \ + "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${mmcroot} rw rootwait;" \ + "bootz ${loadaddr} - ${fdt_addr}\0" \ + "mmcload=mmc rescan;" \ + "load mmc 0:1 ${loadaddr} ${bootimage};" \ + "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ + "qspiroot=/dev/mtdblock0\0" \ + "qspirootfstype=jffs2\0" \ + "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ + "bootm ${loadaddr} - ${fdt_addr}\0" + +/* The rest of the configuration is shared */ +#include <configs/socfpga_common.h> + +#endif /* __CONFIG_SOCFPGA_SOCRATES_H__ */ -- 2.1.4

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Re: [U-Boot] arm: socfpga: Repair SoCrates board
by Marek Vasut 23 Nov '15

23 Nov '15

On Monday, November 23, 2015 at 03:12:48 PM, Jan Viktorin wrote: > Hello again, > > I have a couple of short questions bellow... > > On Fri, 20 Nov 2015 17:17:33 +0100 > > Marek Vasut <marex(a)denx.de> wrote: > > [snip] > > +/* Booting Linux */ > > +#define CONFIG_BOOTDELAY 3 > > +#define CONFIG_BOOTFILE "zImage" > > This is quite a general question. Why would one prefer zImage over > uImage (or vice-versa)? Is there some mainstream idea with this? Or is > it selected at random? General rule is to use fitImage if you want the extended features. zImage was picked by altera some time ago, so it just sticks for no real reason. uImage is deprecated/legacy for years. > > +#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) > > +#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" > > [snip] > > + > > +#define CONFIG_EXTRA_ENV_SETTINGS \ > > + "verify=n\0" \ > > + "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ > > + "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ > > + "bootm ${loadaddr} - ${fdt_addr}\0" \ > > + "bootimage=zImage\0" \ > > + "fdt_addr=100\0" \ > > + "fdtimage=socfpga.dtb\0" \ > > + "fsloadcmd=ext2load\0" \ > > + "bootm ${loadaddr} - ${fdt_addr}\0" \ > > + "mmcroot=/dev/mmcblk0p2\0" \ > > [snip] > > + "mmcload=mmc rescan;" \ > > + "load mmc 0:1 ${loadaddr} ${bootimage};" \ > > + "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ > > The FAT partition is supposed to be the first and the Linux one as the > second. So the boot partition is to be placed at the end of the SD card. Not necessarily, the 0xa2 partition can be placed at arbitrary location. > I find it quite weird as it makes the fdisk call more complex then > necessary. I have to compute the position of the boot partition based > on the size of the SD card. If I just create the paritions in the (say) > natural order a2, b, 83 everything is pretty straight-forward. That's right. > So, what is the reason of this? Why anybody likes to use such layout? That's what the EBV SD card ships with, but this can be changed easily. Best regards, Marek Vasut

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[U-Boot] Zynq: Unable to boot from MMC
by Jagan Teki 23 Nov '15

23 Nov '15

Hi Michal, I'm unable to boot the zynq board from MMC, here is my trails: 1. zynq-boot-bin.py -o boot.bin -u spl/u-boot-spl-dtb.bin copied boot.bin and u-boot-dtb.img on to sd card 2. zynq-boot-bin.py -o boot.bin -u spl/u-boot-spl.bin copied boot.bin and u-boot.img on to sd card For both above steps, board is not booting - I was checked on top of master and step 2 succeeded with u-boot-xlnx[1] Could you please help? [1] https://github.com/Xilinx/u-boot-xlnx -- Jagan | openedev.

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[U-Boot] [PATCH v1 00/21] sparc: Update SPARC architecture to generic board init
by Francois Retief 23 Nov '15

23 Nov '15

The SPARC architecture has not yet been updated to the new generic board init codebase. This patch series is an first attempt at that. The changes has been tested on a TSIM simulator (grsim_defconfig). Any feedback, comments or suggestions would be appreciated. Daniel Hellstrom (6): sparc: Added function that checks if IRQ is on or off sparc: Serial baud rate register support multiple buses with different frequency sparc: leon3: Clear all unused GPTIMER registers. sparc: Removed USB stop from linux bootm, arch-independent bootm stop USB sparc: leon3: Added CPU count and frequency detection. sparc: leon3: Added busy wait function, made wait_ms() work when IRQ is disabled Francois Retief (15): sparc: Move SYS_SPARC_NWINDOWS to Kconfig sparc: Remove version_string variable from start.S file sparc: leon3: Clear GD_FLAG_SERIAL_READY flag on AMBA failure sparc: leon3: Updated serial driver to use CONFIG_CONS_INDEX sparc: Fix whitespace in cpu/leon2/cpu_init.c sparc: Initial ground work for generic board initialization sparc: leon3: Move snoop detection from startup.S to arch_cpu_init() sparc: leon3: Move ambapp_bus_init() call to arch_cpu_init() function sparc: leon3: Updates for generic board initialization sparc: leon2: Updates for generic board initialization sparc: Update cpu_init.c to use generic timer infrastructure sparc: Update PROM initialization code for generic board sparc: Add CONFIG_DISPLAY_BOARDINFO variable to all LEON boards sparc: Use microseconds instead of ticks for timeout sparc: Remove non-generic board init files: board.c, time.c arch/Kconfig | 1 + arch/sparc/Kconfig | 9 + arch/sparc/cpu/leon2/cpu.c | 14 +- arch/sparc/cpu/leon2/cpu_init.c | 94 +++------ arch/sparc/cpu/leon2/interrupts.c | 14 -- arch/sparc/cpu/leon2/prom.c | 2 + arch/sparc/cpu/leon2/serial.c | 2 +- arch/sparc/cpu/leon2/start.S | 213 +++++++++++-------- arch/sparc/cpu/leon3/ambapp.c | 2 +- arch/sparc/cpu/leon3/cpu.c | 60 +++++- arch/sparc/cpu/leon3/cpu_init.c | 175 ++++++++------- arch/sparc/cpu/leon3/interrupts.c | 11 - arch/sparc/cpu/leon3/prom.c | 2 + arch/sparc/cpu/leon3/serial.c | 23 +- arch/sparc/cpu/leon3/start.S | 303 +++++++++++++------------- arch/sparc/cpu/leon3/usb_uhci.c | 7 +- arch/sparc/include/asm/config.h | 8 +- arch/sparc/include/asm/global_data.h | 9 +- arch/sparc/include/asm/irq.h | 3 + arch/sparc/include/asm/leon3.h | 13 ++ arch/sparc/include/asm/u-boot.h | 36 +--- arch/sparc/lib/Makefile | 4 +- arch/sparc/lib/board.c | 398 ----------------------------------- arch/sparc/lib/bootm.c | 8 - arch/sparc/lib/interrupts.c | 42 +--- arch/sparc/lib/time.c | 62 ------ common/board_f.c | 20 +- common/board_r.c | 10 +- drivers/net/greth.c | 2 +- include/configs/gr_cpci_ax2000.h | 8 +- include/configs/gr_ep2s60.h | 8 +- include/configs/gr_xc3s_1500.h | 8 +- include/configs/grsim.h | 8 +- include/configs/grsim_leon2.h | 12 +- 34 files changed, 602 insertions(+), 989 deletions(-) delete mode 100644 arch/sparc/lib/board.c delete mode 100644 arch/sparc/lib/time.c -- 2.4.3

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[U-Boot] [PATCH] i2c, avr32: fix compiler warning "input is not relaxable"
by Heiko Schocher 23 Nov '15

23 Nov '15

compiling U-Boot for avr32 boards shows since commit 3d1957f0ea01 "dm: i2c: Add support for multiplexed I2C buses" this warning: Building current source for 4 boards (4 threads, 8 jobs per thread) avr32: + atstk1002 +(atstk1002) drivers/i2c/built-in.o: warning: input is not relaxable avr32: + grasshopper +(grasshopper) drivers/i2c/built-in.o: warning: input is not relaxable avr32: + atngw100 +(atngw100) drivers/i2c/built-in.o: warning: input is not relaxable avr32: + atngw100mkii +(atngw100mkii) drivers/i2c/built-in.o: warning: input is not relaxable 0 4 0 /4 0:00:16 : atngw100mkii Fix it. Signed-off-by: Heiko Schocher <hs(a)denx.de> --- drivers/i2c/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 32198bd..811ad9b 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -40,4 +40,4 @@ obj-$(CONFIG_SYS_I2C_UNIPHIER) += i2c-uniphier.o obj-$(CONFIG_SYS_I2C_UNIPHIER_F) += i2c-uniphier-f.o obj-$(CONFIG_SYS_I2C_ZYNQ) += zynq_i2c.o -obj-y += muxes/ +obj-$(CONFIG_I2C_MUX) += muxes/ -- 2.1.0

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