November 2015 - U-Boot

[U-Boot] [PATCH 0/2] Fix linux-rock booting on rockchip 3288
by Sjoerd Simons 27 Nov '15

27 Nov '15

Booting on Rockchip 3288 broke in linux-rockchip as the defaults for the SPL relocation code made the heap start at a negative address (or really wrap around). First patch reverts an old relocation workaround from me, which can be dropped since there is now proper support for relocating in the SPL. Second patch updates the configuration for RK3288 which fixes booting. Sjoerd Simons (2): Revert "rockchip: Reconfigure the malloc based to point to system memory" rockchip: Explicitely set CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN arch/arm/mach-rockchip/board-spl.c | 7 ------- configs/chromebook_jerry_defconfig | 1 + configs/firefly-rk3288_defconfig | 1 + 3 files changed, 2 insertions(+), 7 deletions(-) -- 2.6.2

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[U-Boot] [PATCH] i2c: Fix the comment to match the function described
by Stefan Roese 26 Nov '15

26 Nov '15

Use the correct function name in the function description. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Simon Glass <sjg(a)chromium.org> Cc: Heiko Schocher <hs(a)denx.de> --- include/i2c.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/i2c.h b/include/i2c.h index 6493931..1f5ae45 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -499,7 +499,8 @@ int i2c_get_chip(struct udevice *bus, uint chip_addr, uint offset_len, struct udevice **devp); /** - * i2c_get_chip() - get a device to use to access a chip on a bus number + * i2c_get_chip_for_busnum() - get a device to use to access a chip on + * a bus number * * This returns the device for the given chip address on a particular bus * number. -- 2.6.3

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[U-Boot] [PATCH v3 00/11] dm: timer: x86: 64-bit counter support and tsc timer dm conversion
by Bin Meng 26 Nov '15

26 Nov '15

This series enhances timer uclass driver to support 64-bit counter value, and convert tsc timer to driver model to be used by all x86 boards. As a result of dm conversion, the TSC_CALIBRATION_BYPASS Kconfig option is no longer needed, and the TSC frequency can be specified in the board device tree. This v2 is rebased on top of u-boot-dm/master, to resolve conflicts with Altera timer updates and the new Sandbox timer driver. Changes in v3: - Update commit message to reflect the v2 changes (ie: there is no "counter-64bit" property) - Really remove "counter-64bit" property from tsc_timer.dtsi Changes in v2: - Rebase on u-boot-dm/master - Change 'Timer' to 'timer' in the sandbox timer Kconfig - New patch to use device tree to pass the clock frequency - Do not use "counter-64bit" property, instead create an inline function for 32-bit timer driver to construct a 64-bit timer value. - Remove "counter-64bit" property Bin Meng (11): dm: timer: Fix several nits dm: timer: Implement pre_probe() timer: altera: Remove the codes to get clock frequency timer: sandbox: Use device tree to pass the clock frequency dm: timer: Support 64-bit counter x86: Reomve MIN_PORT80_KCLOCKS_DELAY x86: tsc: Use notrace from <linux/compiler.h> x86: tsc: Add driver model timer support x86: Convert to use driver model timer x86: tsc: Remove legacy timer codes x86: tsc: Move tsc_timer.c to drivers/timer arch/sandbox/dts/sandbox.dts | 1 + arch/x86/Kconfig | 20 ------ arch/x86/cpu/baytrail/valleyview.c | 3 - arch/x86/cpu/coreboot/timestamp.c | 22 ------ arch/x86/cpu/cpu.c | 18 ----- arch/x86/cpu/efi/efi.c | 4 -- arch/x86/cpu/ivybridge/cpu.c | 1 - arch/x86/cpu/qemu/Kconfig | 1 - arch/x86/cpu/qemu/qemu.c | 3 - arch/x86/cpu/quark/Kconfig | 5 -- arch/x86/cpu/quark/quark.c | 3 - arch/x86/cpu/queensbay/tnc.c | 3 - arch/x86/dts/bayleybay.dts | 1 + arch/x86/dts/broadwell_som-6896.dts | 1 + arch/x86/dts/chromebook_link.dts | 1 + arch/x86/dts/chromebox_panther.dts | 1 + arch/x86/dts/crownbay.dts | 1 + arch/x86/dts/efi.dts | 5 ++ arch/x86/dts/galileo.dts | 5 ++ arch/x86/dts/minnowmax.dts | 1 + arch/x86/dts/qemu-x86_i440fx.dts | 5 ++ arch/x86/dts/qemu-x86_q35.dts | 5 ++ arch/x86/dts/tsc_timer.dtsi | 6 ++ arch/x86/include/asm/global_data.h | 3 - arch/x86/lib/Makefile | 1 - configs/bayleybay_defconfig | 1 + configs/chromebook_link_defconfig | 2 +- configs/chromebox_panther_defconfig | 2 +- configs/coreboot-x86_defconfig | 3 +- configs/crownbay_defconfig | 1 + configs/efi-x86_defconfig | 2 +- configs/galileo_defconfig | 1 + configs/minnowmax_defconfig | 1 + configs/qemu-x86_defconfig | 1 + drivers/timer/Kconfig | 19 +++-- drivers/timer/Makefile | 1 + drivers/timer/altera_timer.c | 10 +-- drivers/timer/sandbox_timer.c | 6 +- drivers/timer/timer-uclass.c | 19 +++-- {arch/x86/lib => drivers/timer}/tsc_timer.c | 104 ++++++++++++++++------------ include/configs/x86-common.h | 2 - include/timer.h | 34 ++++++--- lib/time.c | 9 ++- 43 files changed, 164 insertions(+), 174 deletions(-) create mode 100644 arch/x86/dts/tsc_timer.dtsi rename {arch/x86/lib => drivers/timer}/tsc_timer.c (87%) -- 1.8.2.1

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[U-Boot] [PATCH v3 1/2] mmc: socfpga_dw_mmc: Move drvsel and smplsel to dts
by Chin Liang See 26 Nov '15

26 Nov '15

socfpga_dw_mmc driver will obtain the drvsel and smplsel value from device tree instead of definition in config header file. Signed-off-by: Chin Liang See <clsee(a)altera.com> Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> Cc: Dinh Nguyen <dinh.linux(a)gmail.com> Cc: Pavel Machek <pavel(a)denx.de> Cc: Marek Vasut <marex(a)denx.de> Cc: Stefan Roese <sr(a)denx.de> Cc: Pantelis Antoniou <pantelis.antoniou(a)konsulko.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Jaehoon Chung <jh80.chung(a)samsung.com> Acked-by: Marek Vasut <marex(a)denx.de> --- Changes for v3 - Split patch to separte DTS and driver patches Changes for v2 - Put default value for drvsel to 3 in case node in DT missing - Remove unnecessary ad-hoc vairable - Free up first calloc if second calloc failed --- drivers/mmc/socfpga_dw_mmc.c | 29 +++++++++++++++++++++-------- include/configs/socfpga_common.h | 2 -- 2 files changed, 21 insertions(+), 10 deletions(-) diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c index 8076761..2bd0ebd 100644 --- a/drivers/mmc/socfpga_dw_mmc.c +++ b/drivers/mmc/socfpga_dw_mmc.c @@ -19,21 +19,23 @@ static const struct socfpga_clock_manager *clock_manager_base = static const struct socfpga_system_manager *system_manager_base = (void *)SOCFPGA_SYSMGR_ADDRESS; -static void socfpga_dwmci_clksel(struct dwmci_host *host) -{ +/* socfpga implmentation specific drver private data */ +struct dwmci_socfpga_priv_data { unsigned int drvsel; unsigned int smplsel; +}; + +static void socfpga_dwmci_clksel(struct dwmci_host *host) +{ + struct dwmci_socfpga_priv_data *priv = host->priv; /* Disable SDMMC clock. */ clrbits_le32(&clock_manager_base->per_pll.en, CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK); - /* Configures drv_sel and smpl_sel */ - drvsel = CONFIG_SOCFPGA_DWMMC_DRVSEL; - smplsel = CONFIG_SOCFPGA_DWMMC_SMPSEL; - - debug("%s: drvsel %d smplsel %d\n", __func__, drvsel, smplsel); - writel(SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel), + debug("%s: drvsel %d smplsel %d\n", __func__, + priv->drvsel, priv->smplsel); + writel(SYSMGR_SDMMC_CTRL_SET(priv->smplsel, priv->drvsel), &system_manager_base->sdmmcgrp_ctrl); debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__, @@ -50,6 +52,7 @@ static int socfpga_dwmci_of_probe(const void *blob, int node, const int idx) const unsigned long clk = cm_get_mmc_controller_clk_hz(); struct dwmci_host *host; + struct dwmci_socfpga_priv_data *priv; fdt_addr_t reg_base; int bus_width, fifo_depth; @@ -83,6 +86,13 @@ static int socfpga_dwmci_of_probe(const void *blob, int node, const int idx) if (!host) return -ENOMEM; + /* Allocate the priv */ + priv = calloc(1, sizeof(*priv)); + if (!priv) { + free(host); + return -ENOMEM; + } + host->name = "SOCFPGA DWMMC"; host->ioaddr = (void *)reg_base; host->buswidth = bus_width; @@ -92,6 +102,9 @@ static int socfpga_dwmci_of_probe(const void *blob, int node, const int idx) host->bus_hz = clk; host->fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2); + priv->drvsel = fdtdec_get_uint(blob, node, "drvsel", 3); + priv->smplsel = fdtdec_get_uint(blob, node, "smplsel", 0); + host->priv = priv; return add_dwmci(host, host->bus_hz, 400000); } diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index f6808b5..b661cc2 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -153,8 +153,6 @@ #define CONFIG_DWMMC #define CONFIG_SOCFPGA_DWMMC #define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024 -#define CONFIG_SOCFPGA_DWMMC_DRVSEL 3 -#define CONFIG_SOCFPGA_DWMMC_SMPSEL 0 /* FIXME */ /* using smaller max blk cnt to avoid flooding the limited stack we have */ #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */ -- 2.2.0

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[U-Boot] [PATCH] pmic: Fix pfuze100 bit definitions
by Marek Vasut 26 Nov '15

26 Nov '15

The following patch changed the PFUZE100 swbst register bit definitions and broke PMIC configuration on multiple boards, at least on the novena and gw_ventana. This patch fixes it. commit 8fa46350a4c7dca7710362f6c871098557b934ad Author: Peng Fan <Peng.Fan(a)freescale.com> Date: Fri Aug 7 16:43:45 2015 +0800 power: regulator: add pfuze100 support Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Fabio Estevam <fabio.estevam(a)freescale.com> Cc: Peng Fan <Peng.Fan(a)freescale.com> Cc: Przemyslaw Marczak <p.marczak(a)samsung.com> Cc: Tim Harvey <tharvey(a)gateworks.com> Cc: Vagrant Cascadian <vagrant(a)aikidev.net> --- include/power/pfuze100_pmic.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/include/power/pfuze100_pmic.h b/include/power/pfuze100_pmic.h index 41cb710..cc019a9 100644 --- a/include/power/pfuze100_pmic.h +++ b/include/power/pfuze100_pmic.h @@ -215,10 +215,10 @@ enum { #define SWBST_VOL_MASK 0x3 #define SWBST_MODE_MASK 0xC #define SWBST_MODE_SHIFT 0x2 -#define SWBST_MODE_OFF 0 -#define SWBST_MODE_PFM 1 -#define SWBST_MODE_AUTO 2 -#define SWBST_MODE_APS 3 +#define SWBST_MODE_OFF (0 << 2) +#define SWBST_MODE_PFM (1 << 2) +#define SWBST_MODE_AUTO (2 << 2) +#define SWBST_MODE_APS (3 << 2) /* * Regulator Mode Control -- 2.6.2

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[U-Boot] mxs: HAB experiments
by Florian Achleitner 26 Nov '15

26 Nov '15

Hi Marek, thanks for you contributions to support mxs HAB v4 in u-boot. I'm currently experimenting with HAB on my imx28 board. I think I put everything together quite well. But examining the HAB event log I see two successful authentications for the u-boot.bin and the IVT followed by a FAILURE with "unsupported command" in the "CSF Context". It is the same for both the SPL and the main u-boot. Did you see something similar? It suggests a wrong command in the CSF file, but I think there is not a lot that can be wrong in the CSF input file for the cst tool. But probably the cst output is different between versions? I use version BLN_CST_MAIN_02.03.00. I use u-boot's mkimage, which can generate a signed boot stream, together with your hand-crafted IVT generator in the Makefile. I wonder if the image size field, which is appended to IVT is critical. In 9c2c8a3 you mention that the HAB Rom accepts a not exact size field value of your SPL image layout. So it seems to be not that critical. I found that my .sig file created by freescale's cst tool is 3372B, while yours seems to have been 3904B. Currently, I am experimenting with the image memory layout and the size field. My CSF file is virtually identical to the example in the freescale's application notes, which uses sha256. I programmed the SRK fuses, but did not set any lock bits. HAB is in the open configuration. The SRK seems to be ok, otherwise there would be no SUCCESS events in the log. Did HAB work without FAILURE events for you? Did anybody else on the list see something similar? Below, you can find the HAB event log. Thanks! Florian Status: Operation failed (0x33) Config: Non-secure IC (0xf0) State: No security state machine (0xf0) -------- HAB Event 0 -------- event data: db 00 10 40 f0 00 db 00 00 00 10 00 00 00 26 c0 status: HAB_STATUS_SUCCESS reason: HAB_RSN_ANY context: HAB_CTX_AUT_DAT -------- HAB Event 1 -------- event data: db 00 10 40 f0 00 db 00 00 00 80 00 00 00 00 40 status: HAB_STATUS_SUCCESS reason: HAB_RSN_ANY context: HAB_CTX_AUT_DAT -------- HAB Event 2 -------- event data: db 00 08 40 33 03 cf 00 status: HAB_STATUS_FAILURE reason: HAB_UNS_COMMAND context: HAB_CTX_CSF -------- HAB Event 3 -------- event data: db 00 10 40 f0 00 db 00 40 00 20 00 00 06 ef 00 status: HAB_STATUS_SUCCESS reason: HAB_RSN_ANY context: HAB_CTX_AUT_DAT -------- HAB Event 4 -------- event data: db 00 10 40 f0 00 db 00 40 00 10 00 00 00 00 40 status: HAB_STATUS_SUCCESS reason: HAB_RSN_ANY context: HAB_CTX_AUT_DAT -------- HAB Event 5 -------- event data: db 00 08 40 33 03 cf 00 status: HAB_STATUS_FAILURE reason: HAB_UNS_COMMAND context: HAB_CTX_CSF

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[U-Boot] [RFC] Removal of superfluous gd assignments
by Albert ARIBAUD 26 Nov '15

26 Nov '15

Hello all, This is a follow-up to discussions on the IRC chan re: the fact that gd (the global data pointer) is being assigned in various places, which is not too much of a good thing. In all architectures, common/init/board_init.c is built in, which provides board_init_f_{mem,init_reserve}, in which gd is assigned by calling arch_setup_gd(). (two architectures, ARM and x86, cannot assign gd from C code, so they don't call arch_setup_gd() but assign GD from another single location) However, there are several places apart from arch_setup_gd() where gd is assigned to. Superfluous assignments lead, at best, to confusion, and at worst, to subtle as well as not-so-subtle bugs, so we need to find and remove such superfluous assignments. This post gives a list of places where gd is being assigned (courtesy of a git grep '^\s\+gd\s*=\s*.*$' command) and suggestions re removal. Comments welcome, of course. ----------------------------------- arch/arm/cpu/arm926ejs/mxs/spl_boot.c:126: gd = &gdata; This assignment is in mxs_common_spl_init() which is called from a board_init_ll() defined by various boards, and itself is called from arch/arm/cpu/arm926ejs/mxs/start.S. Setting gs is required because mxs_common_spl_init() calls lots of functions which depend on gd. Removal: requires MXS SPL to move over to using crt0.S. Note: since MXS SPL actually returns to ROM to get U-Boot launched, it may require cooperation from crt0.S for saving important registers at reset entry point and restoring them and returning to ROM. See OMAP (for register saving) and FEL. Boards affected are: mx28evk_nand xfi3 bg0900 sansa_fuze_plus mx23evk m28evk sc_sps_1 mx28evk_spi axm mx28evk apx4devkit mx23_olinuxino firefly-rk3288 x600 mx28evk_auart_console taurus arch/arm/cpu/armv8/fsl-layerscape/spl.c:48: gd = &gdata; Performed in board_init_f() by boards: ls1043ardb_nand ls2085ardb_nand ls1043ardb_sdcard ls2085aqds_nand These four boards build SPL using arch/arm/lib/crt0_64.S which unconditionally executes arch_set_gd() and thereby has gd properly set when arch_set_ board_init_f() is entered, so that assignment is redundant. Removal: unconditional. arch/arm/lib/spl.c:40: gd = &gdata; This assignment is in a weak board_init_f(), therefore executed from crt0.S (no ARM board calls board_init_f() from elsewhere); therefore gd is already set when this assignment is reached. Removal: unconditional. arch/arm/mach-exynos/spl_boot.c:279: gd = gdp; This assignment occurs from withing a machine-specific board_init_f(), therefore executed from crt0.S (no ARM board calls board_init_f() from elsewhere); therefore gd is already set when this assignment is reached. Removal: unconditional. (non-ARM architectures skipped over) (non-ARM boards skipped over) common/board_f.c:982: gd = &data; Only m68k, avr32 and nds32 use this. It could be conditioned to these architectures and later removed if and when they switch to the same boot sequence as ARM et al. Removal: only if and when arch switches to a boot sequence similar to ARM's. common/board_r.c:942: gd = new_gd; Done by arches other than ARM, AARCH64 and X86. For ARM, gd is switched from early to final location in crt0. For x86? In any case, this assignment cannot be removed unless all arches have switched to a boot sequence similar to ARM's. Removal: only if and when arch switches to a boot sequence similar to ARM's. common/init/board_init.c:28: gd = gd_ptr; That is the only assignment we should keep, for architectures other than ARM or x86. Removal: no. common/spl/spl.c:450: gd = new_gd; This is the second place where gd assignment should be kept, and for ARM it must be fixed the same way arch_setup_gd was, since this assignment to gd may not work with ARM gcc (this change will go in v8 of my patch) Removal: no. Amicalement, -- Albert.

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[U-Boot] [PATCH] common: board_f: Dont relocate FDT incase of CONFIG_OF_EMBED
by Michal Simek 26 Nov '15

26 Nov '15

From: Siva Durga Prasad Paladugu <siva.durga.paladugu(a)xilinx.com> Done relocate fdt incase of CONFIG_OF EMBED as the fdt is already embedded with u-boot image. Also update the fdt_blob correctly in this case Signed-off-by: Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- common/board_f.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/common/board_f.c b/common/board_f.c index b035c90ff3b7..91bf8beea1c6 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -508,7 +508,7 @@ static int reserve_global_data(void) return 0; } -static int reserve_fdt(void) +static int __maybe_unused reserve_fdt(void) { /* * If the device tree is sitting immediately above our image then we @@ -658,7 +658,7 @@ static int setup_dram_config(void) return 0; } -static int reloc_fdt(void) +static int __maybe_unused reloc_fdt(void) { if (gd->flags & GD_FLG_SKIP_RELOC) return 0; @@ -687,6 +687,9 @@ static int setup_reloc(void) gd->reloc_off = gd->relocaddr - (CONFIG_SYS_TEXT_BASE + 0x400); #endif #endif +#ifdef CONFIG_OF_EMBED + gd->fdt_blob += gd->reloc_off; +#endif memcpy(gd->new_gd, (char *)gd, sizeof(gd_t)); debug("Relocation Offset is: %08lx\n", gd->reloc_off); @@ -938,7 +941,9 @@ static init_fnc_t init_sequence_f[] = { #endif setup_machine, reserve_global_data, +#ifndef CONFIG_OF_EMBED reserve_fdt, +#endif reserve_arch, reserve_stacks, setup_dram_config, @@ -955,7 +960,9 @@ static init_fnc_t init_sequence_f[] = { setup_board_extra, #endif INIT_FUNC_WATCHDOG_RESET +#ifndef CONFIG_OF_EMBED reloc_fdt, +#endif setup_reloc, #if defined(CONFIG_X86) || defined(CONFIG_ARC) copy_uboot_to_ram, -- 1.9.1

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[U-Boot] [PATCH v2 0/7] tools: env: simplify argument parsing
by Andreas Fenkart 26 Nov '15

26 Nov '15

In it's current state paramter parsing is quite hard to understand since it happens in two places. One is using getopt at the beginning of main, the second is using adhoc parsing where the order of arguments is important. This patch will parse arguments only in one place using getopt and store the parsed flags in a global struct. v2: - rebased on top of current master Andreas Fenkart (7): tools: env validate: pass values as 0-based array tools: env: make parse_aes_key stateless tools: env: introduce setenv/printenv argument structs tools: env: parse aes key / suppress flag into argument struct tools: env: shift optind arguments and fix argument indices tools: env: factor out parse_common_args tools: env: update usage strings common/env_flags.c | 14 +-- include/env_flags.h | 2 +- tools/env/fw_env.c | 127 ++++++------------------ tools/env/fw_env.h | 22 +++++ tools/env/fw_env_main.c | 250 ++++++++++++++++++++++++++++++++++-------------- 5 files changed, 238 insertions(+), 177 deletions(-) -- 2.6.2

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[U-Boot] [PATCH] ARM: zynq: Remove unused SERIAL macros for serial_zynq
by Michal Simek 26 Nov '15

26 Nov '15

Remove unused macros when driver was moved to DM. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- arch/arm/include/asm/arch-zynqmp/hardware.h | 3 --- arch/arm/mach-zynq/include/mach/hardware.h | 2 -- 2 files changed, 5 deletions(-) diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h index 0f03c246d72d..96d25ee8daed 100644 --- a/arch/arm/include/asm/arch-zynqmp/hardware.h +++ b/arch/arm/include/asm/arch-zynqmp/hardware.h @@ -8,9 +8,6 @@ #ifndef _ASM_ARCH_HARDWARE_H #define _ASM_ARCH_HARDWARE_H -#define ZYNQ_SERIAL_BASEADDR0 0xFF000000 -#define ZYNQ_SERIAL_BASEADDR1 0xFF001000 - #define ZYNQ_GEM_BASEADDR0 0xFF0B0000 #define ZYNQ_GEM_BASEADDR1 0xFF0C0000 #define ZYNQ_GEM_BASEADDR2 0xFF0D0000 diff --git a/arch/arm/mach-zynq/include/mach/hardware.h b/arch/arm/mach-zynq/include/mach/hardware.h index 9a51d6ba3b5e..513b1117b9de 100644 --- a/arch/arm/mach-zynq/include/mach/hardware.h +++ b/arch/arm/mach-zynq/include/mach/hardware.h @@ -7,8 +7,6 @@ #ifndef _ASM_ARCH_HARDWARE_H #define _ASM_ARCH_HARDWARE_H -#define ZYNQ_SERIAL_BASEADDR0 0xE0000000 -#define ZYNQ_SERIAL_BASEADDR1 0xE0001000 #define ZYNQ_SYS_CTRL_BASEADDR 0xF8000000 #define ZYNQ_DEV_CFG_APB_BASEADDR 0xF8007000 #define ZYNQ_SCU_BASEADDR 0xF8F00000 -- 1.9.1

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