November 2015 - U-Boot

[U-Boot] please pull u-boot-samsung master
by Minkyu Kang 30 Nov '15

30 Nov '15

Dear Tom, The following changes since commit fa8883a1e39a20e72aaa5093af0c80062cb95757: Merge branch 'master' of git://git.denx.de/u-boot-i2c (2015-11-27 08:41:03 -0500) are available in the git repository at: http://git.denx.de/u-boot-samsung for you to fetch changes up to 225f5eeccd6c0d376a20c15897edd8c69500d8cc: arm: s5pc1xx: move SoC to mach-s5pc1xx (2015-11-30 17:17:01 +0900) ---------------------------------------------------------------- Minkyu Kang (1): arm: s5pc1xx: move SoC to mach-s5pc1xx MAINTAINERS | 6 ++---- arch/arm/Kconfig | 2 +- arch/arm/Makefile | 1 + arch/arm/cpu/armv7/Makefile | 1 - arch/arm/{cpu/armv7/s5pc1xx => mach-s5pc1xx}/Kconfig | 0 arch/arm/{cpu/armv7/s5pc1xx => mach-s5pc1xx}/Makefile | 0 arch/arm/{cpu/armv7/s5pc1xx => mach-s5pc1xx}/cache.c | 0 arch/arm/{cpu/armv7/s5pc1xx => mach-s5pc1xx}/clock.c | 0 .../{include/asm/arch-s5pc1xx => mach-s5pc1xx/include/mach}/clk.h | 0 .../{include/asm/arch-s5pc1xx => mach-s5pc1xx/include/mach}/clock.h | 0 .../{include/asm/arch-s5pc1xx => mach-s5pc1xx/include/mach}/cpu.h | 0 .../{include/asm/arch-s5pc1xx => mach-s5pc1xx/include/mach}/gpio.h | 0 .../{include/asm/arch-s5pc1xx => mach-s5pc1xx/include/mach}/mmc.h | 0 .../asm/arch-s5pc1xx => mach-s5pc1xx/include/mach}/periph.h | 0 .../asm/arch-s5pc1xx => mach-s5pc1xx/include/mach}/pinmux.h | 0 .../{include/asm/arch-s5pc1xx => mach-s5pc1xx/include/mach}/power.h | 0 .../{include/asm/arch-s5pc1xx => mach-s5pc1xx/include/mach}/pwm.h | 0 .../{include/asm/arch-s5pc1xx => mach-s5pc1xx/include/mach}/sromc.h | 0 .../asm/arch-s5pc1xx => mach-s5pc1xx/include/mach}/sys_proto.h | 0 .../{include/asm/arch-s5pc1xx => mach-s5pc1xx/include/mach}/uart.h | 0 .../asm/arch-s5pc1xx => mach-s5pc1xx/include/mach}/watchdog.h | 0 arch/arm/{cpu/armv7/s5pc1xx => mach-s5pc1xx}/reset.S | 0 22 files changed, 4 insertions(+), 6 deletions(-) rename arch/arm/{cpu/armv7/s5pc1xx => mach-s5pc1xx}/Kconfig (100%) rename arch/arm/{cpu/armv7/s5pc1xx => mach-s5pc1xx}/Makefile (100%) rename arch/arm/{cpu/armv7/s5pc1xx => mach-s5pc1xx}/cache.c (100%) rename arch/arm/{cpu/armv7/s5pc1xx => mach-s5pc1xx}/clock.c (100%) rename arch/arm/{include/asm/arch-s5pc1xx => mach-s5pc1xx/include/mach}/clk.h (100%) rename arch/arm/{include/asm/arch-s5pc1xx => mach-s5pc1xx/include/mach}/clock.h (100%) rename arch/arm/{include/asm/arch-s5pc1xx => mach-s5pc1xx/include/mach}/cpu.h (100%) rename arch/arm/{include/asm/arch-s5pc1xx => mach-s5pc1xx/include/mach}/gpio.h (100%) rename arch/arm/{include/asm/arch-s5pc1xx => mach-s5pc1xx/include/mach}/mmc.h (100%) rename arch/arm/{include/asm/arch-s5pc1xx => mach-s5pc1xx/include/mach}/periph.h (100%) rename arch/arm/{include/asm/arch-s5pc1xx => mach-s5pc1xx/include/mach}/pinmux.h (100%) rename arch/arm/{include/asm/arch-s5pc1xx => mach-s5pc1xx/include/mach}/power.h (100%) rename arch/arm/{include/asm/arch-s5pc1xx => mach-s5pc1xx/include/mach}/pwm.h (100%) rename arch/arm/{include/asm/arch-s5pc1xx => mach-s5pc1xx/include/mach}/sromc.h (100%) rename arch/arm/{include/asm/arch-s5pc1xx => mach-s5pc1xx/include/mach}/sys_proto.h (100%) rename arch/arm/{include/asm/arch-s5pc1xx => mach-s5pc1xx/include/mach}/uart.h (100%) rename arch/arm/{include/asm/arch-s5pc1xx => mach-s5pc1xx/include/mach}/watchdog.h (100%) rename arch/arm/{cpu/armv7/s5pc1xx => mach-s5pc1xx}/reset.S (100%) -- Thanks, Minkyu Kang.

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[U-Boot] Pull request: u-boot-video/master
by Anatolij Gustschin 30 Nov '15

30 Nov '15

Hello Tom, The following changes since commit 736d1746fb7b8f7cd70657a4a72db2b6bd8de40e: itest: add missing break statements to evalexp() (2015-11-18 15:29:00 -0500) are available in the git repository at: git://git.denx.de/u-boot-video.git master for you to fetch changes up to 3dbdb4dd4f8e5847b8f7d6dbd849e0b9a0907a5b: video: ipu: fix out of bounds access (2015-11-30 09:18:36 +0100) ---------------------------------------------------------------- Peng Fan (1): video: ipu: fix out of bounds access Stephane Ayotte (1): LCD: Add an option to skip registration as an stdio output common/lcd.c | 13 +++++++++++++ drivers/video/ipu_disp.c | 2 +- drivers/video/ipu_regs.h | 1 + 3 files changed, 15 insertions(+), 1 deletion(-) Please pull. Thanks! Anatolij

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[U-Boot] Please pull u-boot-marvell master
by Luka Perkov 30 Nov '15

30 Nov '15

Hi Tom, please pull the queued changes below from Marvell tree. Additional work from Stefan will be sent later on. The following changes since commit fa8883a1e39a20e72aaa5093af0c80062cb95757: Merge branch 'master' of git://git.denx.de/u-boot-i2c (2015-11-27 08:41:03 -0500) are available in the git repository at: git://git.denx.de/u-boot-marvell.git for you to fetch changes up to f1df81c4008c8e0edbc1a2738cf2490b2f7be661: arm: kirkwood: add ZyXEL NSA310S device (2015-11-29 22:16:14 +0100) ---------------------------------------------------------------- Gerald Kerma (1): arm: kirkwood: add ZyXEL NSA310S device Reinhard Pfau (2): tools/kwbimage: fix endianess issue tools/kwbimage: fix size computations for v1 images Stefan Roese (2): arm: mvebu: Configure ARP timeout and retry count tools/kwbimage.c: Make sure that the resulting image is 4-byte aligned arch/arm/mach-kirkwood/Kconfig | 4 + arch/arm/mach-mvebu/include/mach/config.h | 2 + board/zyxel/nsa310s/Kconfig | 20 +++++ board/zyxel/nsa310s/MAINTAINERS | 8 ++ board/zyxel/nsa310s/Makefile | 9 ++ board/zyxel/nsa310s/kwbimage.cfg | 43 ++++++++++ board/zyxel/nsa310s/nsa310s.c | 133 ++++++++++++++++++++++++++++++ board/zyxel/nsa310s/nsa310s.h | 47 +++++++++++ configs/nsa310s_defconfig | 13 +++ include/configs/nsa310s.h | 99 ++++++++++++++++++++++ tools/kwbimage.c | 60 ++++++++------ tools/kwbimage.h | 3 +- 12 files changed, 417 insertions(+), 24 deletions(-) create mode 100644 board/zyxel/nsa310s/Kconfig create mode 100644 board/zyxel/nsa310s/MAINTAINERS create mode 100644 board/zyxel/nsa310s/Makefile create mode 100644 board/zyxel/nsa310s/kwbimage.cfg create mode 100644 board/zyxel/nsa310s/nsa310s.c create mode 100644 board/zyxel/nsa310s/nsa310s.h create mode 100644 configs/nsa310s_defconfig create mode 100644 include/configs/nsa310s.h Regards, Luka

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[U-Boot] [PATCH v2] armv8: fsl-layerscape: Fix early MMU table for nand boot
by York Sun 30 Nov '15

30 Nov '15

The early MMU table doesn't enable all addresses. Unused addresses are marked as invalid, as introduced by commit 9979922. An entry was missing for NAND flash space, causing nand boot failure. Signed-off-by: York Sun <yorksun(a)freescale.com> CC: Alison Wang <alison.wang(a)freescale.com> CC: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- Changes in v2: Reduce the IFC mapped for early MMU, up to NOR flash base to avoid conflict Tested on LS2085AQDS arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index 727fd24..4544094 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -130,6 +130,10 @@ static const struct sys_mmu_table early_mmu_table[] = { CONFIG_SYS_FSL_IFC_SIZE1, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE }, + /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */ + { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, + CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2, + MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, -- 1.7.9.5

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[U-Boot] [PATCH] armv8: README: Update README for DPAA2 commands for MC
by Prabhakar Kushwaha 30 Nov '15

30 Nov '15

Update README for DPAA2 commands used to manage MC - Upldate details - Added example Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- Based upon u-boot-fsl-qoriq.git branch next arch/arm/cpu/armv8/fsl-layerscape/README.lsch3 | 88 +++++++++++++++++--------- 1 file changed, 59 insertions(+), 29 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3 b/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3 index b924134..f9323c1 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3 +++ b/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3 @@ -244,35 +244,65 @@ MMU Translation Tables ... ... -DPAA2 commands to manage Management complex -------------------------------------------- -Management complex Firmware, DPL and DPC are depolyed during u-boot boot -sequence. - -New DPAA2 commands has been added to manage Management Complex (MC) i.e. -start mc, aiop and apply DPL from command prompt. - -a) fsl_mc start mc [FW_addr] [DPC_addr] - Start Management Complex -b) fsl_mc apply DPL [DPL_addr] - Apply DPL file -c) fsl_mc start aiop [FW_addr] - Start AIOP - -u-boot etherenet support sequence :- -a) fsl_mc start mc [FW_addr] [DPC_addr] - Start Management Complex -b) DPMACs device will be available now for use - -Linux boot sequence :- -a) fsl_mc start mc [FW_addr] [DPC_addr] - Start Management Complex -b) fsl_mc apply DPL [DPL_addr] - Apply DPL file -c) No DPMACs availabe for use in u-boot -c) boot Linux - -AIOP boot sequence :- -a) fsl_mc start mc [FW_addr] [DPC_addr] - Start Management Complex -b) fsl_mc start aiop [FW_addr] - Start AIOP -c) fsl_mc apply DPL [DPL_addr] - Apply DPL file -d) No DPMACs availabe for use in u-boot -Please note actual AIOP start will happen during DPL parsing of Management complex - +DPAA2 commands to manage Management Complex (MC) +------------------------------------------------ +DPAA2 commands has been introduced to manage Management Complex +(MC). These commands are used to start mc, aiop and apply DPL +from u-boot command prompt. + +Please note Management complex Firmware(MC), DPL and DPC are no +more deployed during u-boot boot-sequence. + +Commands: +a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex +b) fsl_mc apply DPL <DPL_addr> - Apply DPL file +c) fsl_mc start aiop <FW_addr> - Start AIOP + +How to use commands :- +1. Command sequence for u-boot ethernet: + a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex + b) DPMAC net-devices are now available for use + + Example- + Assumption: MC firmware, DPL and DPC dtb is already programmed + on NOR flash. + + => fsl_mc start mc 580300000 580800000 + => setenv ethact DPMAC1@xgmii + => ping $serverip + +2. Command sequence for Linux boot: + a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex + b) fsl_mc apply DPL <DPL_addr> - Apply DPL file + c) No DPMAC net-devices are available for use in u-boot + d) boot Linux + + Example- + Assumption: MC firmware, DPL and DPC dtb is already programmed + on NOR flash. + + => fsl_mc start mc 580300000 580800000 + => setenv ethact DPMAC1@xgmii + => tftp a0000000 kernel.itb + => fsl_mc apply dpl 580700000 + => bootm a0000000 + +3. Command sequence for AIOP boot: + a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex + b) fsl_mc start aiop <FW_addr> - Start AIOP + c) fsl_mc apply DPL <DPL_addr> - Apply DPL file + d) No DPMAC net-devices are availabe for use in u-boot + Please note actual AIOP start will happen during DPL parsing of + Management complex + + Example- + Assumption: MC firmware, DPL, DPC dtb and AIOP firmware is already + programmed on NOR flash. + + => fsl_mc start mc 580300000 580800000 + => fsl_mc start aiop 0x580900000 + => setenv ethact DPMAC1@xgmii + => fsl_mc apply dpl 580700000 Errata A009635 --------------- -- 1.9.1

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[U-Boot] [PULL] u-boot-usb/master
by Marek Vasut 30 Nov '15

30 Nov '15

The following changes since commit fa8883a1e39a20e72aaa5093af0c80062cb95757: Merge branch 'master' of git://git.denx.de/u-boot-i2c (2015-11-27 08:41:03 -0500) are available in the git repository at: git://git.denx.de/u-boot-usb.git for you to fetch changes up to b5c6f21bf9761f12b43dfc652e5635ab8ec0d7c2: drivers:usb:fsl: Add T4080 as affected soc for Erratum A007792 sw workaround (2015-11-30 13:33:22 +0100) ---------------------------------------------------------------- Alexey Brodkin (1): usb: add support for generic EHCI devices Felipe Balbi (2): usb: host: xhci-omap: fix build break usb: dwc3: fix build warnings Rajesh Bhagat (1): drivers:usb:fsl: Add T4080 as affected soc for Erratum A007792 sw workaround Siva Durga Prasad Paladugu (2): usb: zynqmp: Add XHCI driver support usb: zynqmp: Enable USB XHCI support drivers/usb/dwc3/core.c | 2 +- drivers/usb/dwc3/dwc3-omap.c | 2 +- drivers/usb/host/Kconfig | 7 +++++ drivers/usb/host/Makefile | 2 ++ drivers/usb/host/ehci-generic.c | 51 +++++++++++++++++++++++++++++++++++++ drivers/usb/host/xhci-omap.c | 2 +- drivers/usb/host/xhci-zynqmp.c | 143 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ include/configs/xilinx_zynqmp.h | 8 ++++++ include/configs/xilinx_zynqmp_ep.h | 2 ++ include/fsl_usb.h | 1 + 10 files changed, 217 insertions(+), 3 deletions(-) create mode 100644 drivers/usb/host/ehci-generic.c create mode 100644 drivers/usb/host/xhci-zynqmp.c

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[U-Boot] [PATCH] driver: net: ldpaa: Update the lane number to DPMAC mapping
by Prabhakar Kushwaha 30 Nov '15

30 Nov '15

As of patch "http://patchwork.ozlabs.org/patch/539748/", serdes_init() is passing correct DPMAC id. So Update the lane to DPMAC mapping. Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- drivers/net/ldpaa_eth/ldpaa_wriop.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/drivers/net/ldpaa_eth/ldpaa_wriop.c b/drivers/net/ldpaa_eth/ldpaa_wriop.c index 357b35a..f7f26c2 100644 --- a/drivers/net/ldpaa_eth/ldpaa_wriop.c +++ b/drivers/net/ldpaa_eth/ldpaa_wriop.c @@ -23,18 +23,17 @@ __weak phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtc) void wriop_init_dpmac(int sd, int dpmac_id, int lane_prtcl) { phy_interface_t enet_if; - int index = dpmac_id + sd * 8; - dpmac_info[index].enabled = 0; - dpmac_info[index].id = 0; - dpmac_info[index].phy_addr = -1; - dpmac_info[index].enet_if = PHY_INTERFACE_MODE_NONE; + dpmac_info[dpmac_id].enabled = 0; + dpmac_info[dpmac_id].id = 0; + dpmac_info[dpmac_id].phy_addr = -1; + dpmac_info[dpmac_id].enet_if = PHY_INTERFACE_MODE_NONE; - enet_if = wriop_dpmac_enet_if(index, lane_prtcl); + enet_if = wriop_dpmac_enet_if(dpmac_id, lane_prtcl); if (enet_if != PHY_INTERFACE_MODE_NONE) { - dpmac_info[index].enabled = 1; - dpmac_info[index].id = index; - dpmac_info[index].enet_if = enet_if; + dpmac_info[dpmac_id].enabled = 1; + dpmac_info[dpmac_id].id = dpmac_id; + dpmac_info[dpmac_id].enet_if = enet_if; } } -- 1.9.1

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[U-Boot] [PATCH] armv8: ls2080a: Define CONFIG_ENV_OVERWRITE to overwrite serial and ethaddr
by Alison Wang 30 Nov '15

30 Nov '15

As the environment variables "serial#" and "ethaddr" need to be overwriten by the users, CONFIG_ENV_OVERWRITE is defined to disable the write protection. Anybody can change or delete these parameters. Signed-off-by: Alison Wang <alison.wang(a)freescale.com> --- include/configs/ls2085a_common.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h index 0011e72..2d2396a 100644 --- a/include/configs/ls2085a_common.h +++ b/include/configs/ls2085a_common.h @@ -245,6 +245,9 @@ unsigned long long get_qixis_addr(void); #define CONFIG_DISPLAY_CPUINFO +/* Allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ -- 2.1.0.27.g96db324

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[U-Boot] [PATCH] net: phy: added aquantia PHY AQR405 support
by shh.xie＠gmail.com 30 Nov '15

30 Nov '15

From: Shaohui Xie <Shaohui.Xie(a)freescale.com> The phy can share driver with other aquantia PHYs, so we only added PHY ID. Signed-off-by: Shaohui Xie <Shaohui.Xie(a)freescale.com> --- drivers/net/phy/aquantia.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c index ef4da4e..f90c2ae 100644 --- a/drivers/net/phy/aquantia.c +++ b/drivers/net/phy/aquantia.c @@ -146,11 +146,26 @@ struct phy_driver aqr105_driver = { .startup = &aquantia_startup, .shutdown = &gen10g_shutdown, }; + +struct phy_driver aqr405_driver = { + .name = "Aquantia AQR405", + .uid = 0x3a1b4b2, + .mask = 0xfffffff0, + .features = PHY_10G_FEATURES, + .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS| + MDIO_MMD_PHYXS | MDIO_MMD_AN | + MDIO_MMD_VEND1), + .config = &aquantia_config, + .startup = &aquantia_startup, + .shutdown = &gen10g_shutdown, +}; + int phy_aquantia_init(void) { phy_register(&aq1202_driver); phy_register(&aq2104_driver); phy_register(&aqr105_driver); + phy_register(&aqr405_driver); return 0; } -- 2.1.0.27.g96db324

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[U-Boot] [PATCH][v3] armv8: ls2085a: Add workaround of errata A009635
by Prabhakar Kushwaha 30 Nov '15

30 Nov '15

If the core runs at higher than x3 speed of the platform, there is possiblity about sev instruction to getting missed by other cores. This is because of SoC Run Control block may not able to sample the EVENTI(Sev) signals. Configure Run Control and EPU to periodically send out EVENTI signals to wake up A57 cores. Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- Changes for v2: Updated description Changes for v3: Added README and comments arch/arm/cpu/armv8/fsl-layerscape/README.lsch3 | 21 +++++++++++ arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 6 ++++ arch/arm/cpu/armv8/fsl-layerscape/soc.c | 43 +++++++++++++++++++++++ arch/arm/include/asm/arch-fsl-layerscape/config.h | 9 +++++ arch/arm/include/asm/arch-fsl-layerscape/soc.h | 3 ++ 5 files changed, 82 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3 b/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3 index d1f92c4..baa80b7 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3 +++ b/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3 @@ -272,3 +272,24 @@ b) fsl_mc start aiop [FW_addr] - Start AIOP c) fsl_mc apply DPL [DPL_addr] - Apply DPL file d) No DPMACs availabe for use in u-boot Please note actual AIOP start will happen during DPL parsing of Management complex + + +Errata A009635 +--------------- +If the core runs at higher than x3 speed of the platform, there is +possiblity about sev instruction to getting missed by other cores. +This is because of SoC Run Control block may not able to sample +the EVENTI(Sev) signals. + +Workaround: Configure Run Control and EPU to periodically send out EVENTI signals to +wake up A57 cores + +Errata workaround uses Env variable "a009635_interval_val". It uses decimal +value. +- Default value of env variable is platform clock (MHz) + +- User can modify default value by updating the env variable + setenv a009635_interval_val 600; saveenv; + It configure platform clock as 600 MHz + +- Env variable as 0 signifies no workaround diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 0cb0afa..dbb12c2 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -484,7 +484,13 @@ int arch_early_init_r(void) { #ifdef CONFIG_MP int rv = 1; +#endif + +#ifdef CONFIG_SYS_FSL_ERRATUM_A009635 + erratum_a009635(); +#endif +#ifdef CONFIG_MP rv = fsl_layerscape_wake_seconday_cores(); if (rv) printf("Did not wake secondary cores\n"); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 637853d..34f9a94 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -9,10 +9,53 @@ #include <asm/arch/soc.h> #include <asm/io.h> #include <asm/global_data.h> +#include <asm/arch-fsl-layerscape/config.h> DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_LS2085A +#ifdef CONFIG_SYS_FSL_ERRATUM_A009635 +#define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val" + +static unsigned long get_internval_val_mhz(void) +{ + char *interval = getenv(PLATFORM_CYCLE_ENV_VAR); + /* + * interval is the number of platform cycles(MHz) between + * wake up events generated by EPU. + */ + ulong interval_mhz = get_bus_freq(0) / (1000 * 1000); + + if (interval) + interval_mhz = simple_strtoul(interval, NULL, 10); + + return interval_mhz; +} + +void erratum_a009635(void) +{ + u32 val; + unsigned long interval_mhz = get_internval_val_mhz(); + + if (!interval_mhz) + return; + + val = in_le32(DCSR_CGACRE5); + writel(val | 0x00000200, DCSR_CGACRE5); + + val = in_le32(EPU_EPCMPR5); + writel(interval_mhz, EPU_EPCMPR5); + val = in_le32(EPU_EPCCR5); + writel(val | 0x82820000, EPU_EPCCR5); + val = in_le32(EPU_EPSMCR5); + writel(val | 0x002f0000, EPU_EPSMCR5); + val = in_le32(EPU_EPECR5); + writel(val | 0x20000000, EPU_EPECR5); + val = in_le32(EPU_EPGCR); + writel(val | 0x80000000, EPU_EPGCR); +} +#endif + static void erratum_a008751(void) { #ifdef CONFIG_SYS_FSL_ERRATUM_A008751 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 87bb937..c7169ab 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -84,11 +84,20 @@ #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C) #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820) +#define DCSR_CGACRE5 0x700070914ULL +#define EPU_EPCMPR5 0x700060914ULL +#define EPU_EPCCR5 0x700060814ULL +#define EPU_EPSMCR5 0x700060228ULL +#define EPU_EPECR5 0x700060314ULL +#define EPU_EPCTR5 0x700060a14ULL +#define EPU_EPGCR 0x700060000ULL + #define CONFIG_SYS_FSL_ERRATUM_A008336 #define CONFIG_SYS_FSL_ERRATUM_A008511 #define CONFIG_SYS_FSL_ERRATUM_A008514 #define CONFIG_SYS_FSL_ERRATUM_A008585 #define CONFIG_SYS_FSL_ERRATUM_A008751 +#define CONFIG_SYS_FSL_ERRATUM_A009635 #elif defined(CONFIG_LS1043A) #define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_CACHELINE_SIZE 64 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 5ed456e..80354f0 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -50,4 +50,7 @@ void fsl_lsch2_early_init_f(void); #endif void cpu_name(char *name); +#ifdef CONFIG_SYS_FSL_ERRATUM_A009635 +void erratum_a009635(void); +#endif #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */ -- 1.9.1

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