November 2015 - U-Boot

[U-Boot] [PATCH v4] arm: Add sata support on Layerscape ARMv8 board
by Yuantian.Tang＠freescale.com 02 Dec '15

02 Dec '15

From: Tang Yuantian <Yuantian.Tang(a)freescale.com> Freescale ARM-based Layerscape contains a SATA controller which comply with the serial ATA 3.0 specification and the AHCI 1.3 specification. This patch adds SATA feature on ls2080aqds, ls2080ardb and ls1043aqds boards. Signed-off-by: Tang Yuantian <Yuantian.Tang(a)freescale.com> --- v4: - rebase to lastest git tree - add another ARMv8 platform which is ls1043aqds v3: - rename ls2085a to ls2080a - rebase to the latest git tree - replace the magic number with micro variable v2: - rebase to the latest git tree arch/arm/cpu/armv8/fsl-layerscape/soc.c | 43 +++++++++++++++++++++++ arch/arm/include/asm/arch-fsl-layerscape/config.h | 18 ++++++++++ arch/arm/include/asm/arch-fsl-layerscape/soc.h | 31 ++++++++++++++++ include/configs/ls1043aqds.h | 17 +++++++++ 4 files changed, 109 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 8896b70..574ffc4 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -6,6 +6,8 @@ #include <common.h> #include <fsl_ifc.h> +#include <ahci.h> +#include <scsi.h> #include <asm/arch/soc.h> #include <asm/io.h> #include <asm/global_data.h> @@ -120,7 +122,44 @@ void fsl_lsch3_early_init_f(void) erratum_a009203(); } +#ifdef CONFIG_SCSI_AHCI_PLAT +int sata_init(void) +{ + struct ccsr_ahci __iomem *ccsr_ahci; + + ccsr_ahci = (void *)CONFIG_SYS_SATA2; + out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); + out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); + + ccsr_ahci = (void *)CONFIG_SYS_SATA1; + out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); + out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); + + ahci_init((void __iomem *)CONFIG_SYS_SATA1); + scsi_scan(0); + + return 0; +} +#endif + #elif defined(CONFIG_LS1043A) +#ifdef CONFIG_SCSI_AHCI_PLAT +int sata_init(void) +{ + struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA; + + out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); + out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG); + out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG); + out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); + + ahci_init((void __iomem *)CONFIG_SYS_SATA); + scsi_scan(0); + + return 0; +} +#endif + void fsl_lsch2_early_init_f(void) { struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; @@ -141,6 +180,10 @@ void fsl_lsch2_early_init_f(void) #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { +#ifdef CONFIG_SCSI_AHCI_PLAT + sata_init(); +#endif + return 0; } #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index b5a2d28..be3acc3 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -54,6 +54,24 @@ #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN +/* SATA */ +#define CONFIG_LIBATA +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_CMD_SCSI +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#define CONFIG_DOS_PARTITION +#define CONFIG_BOARD_LATE_INIT + +#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + 0x02200000) +#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + 0x02210000) + +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) + /* Generic Interrupt Controller Definitions */ #define GICD_BASE 0x06000000 #define GICR_BASE 0x06100000 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 504c1f9..83186d6 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -51,6 +51,37 @@ struct cpu_type { #define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E) #define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1)) +/* ahci port register default value */ +#define AHCI_PORT_PHY_1_CFG 0xa003fffe +#define AHCI_PORT_PHY_2_CFG 0x28184d1f +#define AHCI_PORT_PHY_3_CFG 0x0e081509 +#define AHCI_PORT_TRANS_CFG 0x08000025 + +/* AHCI (sata) register map */ +struct ccsr_ahci { + u32 res1[0xa4/4]; /* 0x0 - 0xa4 */ + u32 pcfg; /* port config */ + u32 ppcfg; /* port phy1 config */ + u32 pp2c; /* port phy2 config */ + u32 pp3c; /* port phy3 config */ + u32 pp4c; /* port phy4 config */ + u32 pp5c; /* port phy5 config */ + u32 axicc; /* AXI cache control */ + u32 paxic; /* port AXI config */ + u32 axipc; /* AXI PROT control */ + u32 ptc; /* port Trans Config */ + u32 pts; /* port Trans Status */ + u32 plc; /* port link config */ + u32 plc1; /* port link config1 */ + u32 plc2; /* port link config2 */ + u32 pls; /* port link status */ + u32 pls1; /* port link status1 */ + u32 pcmdc; /* port CMD config */ + u32 ppcs; /* port phy control status */ + u32 pberr; /* port 0/1 BIST error */ + u32 cmds; /* port 0/1 CMD status error */ +}; + #ifdef CONFIG_FSL_LSCH3 void fsl_lsch3_early_init_f(void); #elif defined(CONFIG_FSL_LSCH2) diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index 4aeb238..bd7af00 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -88,6 +88,23 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg #endif +/* SATA */ +#define CONFIG_LIBATA +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_CMD_SCSI +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#define CONFIG_DOS_PARTITION +#define CONFIG_BOARD_LATE_INIT + +#define CONFIG_SYS_SATA (CONFIG_SYS_IMMR + 0x02200000) + +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) + /* * IFC Definitions */ -- 2.1.0.27.g96db324

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[U-Boot] U-boot broken on e500v2 soc
by York Sun 02 Dec '15

02 Dec '15

Valentin, Can you refresh my memory why you needed this commitac337168ad81a18e768e5e3cfff8d229adeb2b25 (patch http://patchwork.ozlabs.org/patch/455439)? Today I bisect an issue back to this commit. Scott, Can you help to examine this u-boot commit? Before this commit, 512x/5xxx/83xx/85xx do nothing on function invalidate_dcache_range() and flush_dcache_range(). With this patch, I found e500v2 is broken on Intel e1000 card when testing v2016-rc1. I didn't catch this issue when testing this patch. I wonder if this code is not safe for e500v2, or because the cache line size should be determined by reading L1CFG0. Why didn't we see any issue with Linux with the same code. Log for testing on e500v2 P1023RDB U-Boot 2016.01-rc1-00115-g2b24e09 (Nov 20 2015 - 22:01:56 -0800) CPU0: P1023E, Version: 1.1, (0x80fe0011) Core: e500, Version: 5.1, (0x80212151) Clock Configuration: CPU0:500 MHz, CPU1:500 MHz, CCB:333.333 MHz, DDR:333.333 MHz (666.667 MT/s data rate) (Asynchronous), LBC:41.667 MHz FMAN1: 333.333 MHz QMAN: 0 MHz L1: D-cache 32 KiB enabled I-cache 32 KiB enabled Board: P1023 RDB I2C: ready DRAM: DIMM 0: is not a DDR3 SPD. SPD error on controller 0! Trying fallback to raw timing calculation Detected UDIMM Fixed DDR on board 512 MiB (DDR3, 32-bit, CL=5, ECC off) Flash: 64 MiB L2: 256 KiB enabled NAND: 128 MiB EEPROM: CRC mismatch (a7fdad5b != ffffffff) PCIe1: Root Complex of Slot 1, no link, regs @ 0xff60a000 PCIe1: Bus 00 - 00 PCIe2: Root Complex of Slot 2, x1 gen1, regs @ 0xff609000 02:00.0 - 8086:107d - Network controller PCIe2: Bus 01 - 02 PCIe3: Root Complex of Slot 3, x1 gen1, regs @ 0xff60b000 04:00.0 - 168c:0030 - Network controller PCIe3: Bus 03 - 04 In: serial Out: serial Err: serial Net: Fman1: Uploading microcode version 160.0.18 e1000: 00:15:17:8e:7b:8d FM1@DTSEC1, FM1@DTSEC2, e1000#0 [PRIME] Warning: e1000#0 MAC addresses don't match: Address in SROM is 00:15:17:8e:7b:8d Address in environment is 00:e0:0c:00:06:02 => ping $serverip Using e1000#0 device Bad trap at PC: 1ffc6f10, SR: 6049434, vector=e00 NIP: 1FFC6F10 XER: 00000000 LR: 1FEF0B6C REGS: 1f8eda70 TRAP: 0e00 DAR: 20000000 MSR: 06049434 EE: 1 PR: 0 FP: 0 ME: 1 IR/DR: 11 GPR00: 1FF457D4 1F8EDB60 1F8EDF14 20000000 00020000 0000001F 00000000 1F8EDAB8 GPR08: A0003818 00004000 00000003 1F8EDB80 1FF457D4 EC662032 1FFC8D50 1FFC6F24 GPR16: 1FFB0074 1FFB005C 1FF59701 1FF5971F 1FF49C37 1FFB0068 00000000 1FFC6F10 GPR24: 1FFB00CC 1FF48D60 00000000 1F8F3D70 1FFC5600 00400000 1FF5C610 00400000 Call backtrace: 1FF2F350 1FF457D4 1FF06888 1FF13AF8 1FEFA180 1FEFA7FC 1FEF9A90 1FEFA124 1FEFA7FC 1FEFAA1C 1FF12B54 1FEFB140 1FF3AA7C 1FEFB454 1FEF0F4C Exception in kernel pc 1ffc6f10 signal 0 ### ERROR ### Please RESET the board ### P1022DS log U-Boot 2016.01-rc1-00115-g2b24e09 (Nov 20 2015 - 22:17:10 -0800) CPU0: P1022E, Version: 1.0, (0x80ee0010) Core: e500, Version: 5.0, (0x80211050) Clock Configuration: CPU0:999.990 MHz, CPU1:999.990 MHz, CCB:499.995 MHz, DDR:333.330 MHz (666.660 MT/s data rate) (Asynchronous), LBC:31.250 MHz L1: D-cache 32 KiB enabled I-cache 32 KiB enabled Board: P1022DS Sys ID: 0x19, Sys Ver: 0x03, FPGA Ver: 0x09, vBank: 0 I2C: ready SPI: ready DRAM: Detected RDIMM 18JSF51272PDZ1G4D1 Detected 4 GiB of memory This U-Boot only supports < 4G of DDR You could rebuild it with CONFIG_PHYS_64BIT 2 GiB (DDR3, 64-bit, CL=5, ECC off) Flash: 128 MiB L2: 256 KiB enabled NAND: 1024 MiB MMC: FSL_SDHC: 0 EEPROM: NXID v0 PCIe1: Root Complex of Slot 1, no link, regs @ 0xffe0a000 PCIe1: Bus 00 - 00 PCIe2: Root Complex of Slot 3, x1 gen1, regs @ 0xffe09000 02:00.0 - 8086:10b9 - Network controller PCIe2: Bus 01 - 02 PCIe3: Root Complex of Slot 2, no link, regs @ 0xffe0b000 PCIe3: Bus 03 - 03 In: serial Out: serial Err: serial Net: e1000: 00:15:17:0b:8c:74 eTSEC1, eTSEC2, e1000#0 [PRIME] Hit any key to stop autoboot: 0 => ping $serverip Using e1000#0 device pci_bus_to_hose() failed pci_hose_phys_to_bus: invalid hose pci_bus_to_hose() failed pci_hose_phys_to_bus: invalid hose Abort

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[U-Boot] [PATCH v3] usb: add support for generic EHCI devices
by Alexey Brodkin 01 Dec '15

01 Dec '15

From: Alexey Brodkin <Alexey.Brodkin(a)synopsys.com> This driver is meant to be used with any EHCI-compatible host controller in case if there's no need for platform-specific glue such as setup of controller or PHY's power mode via GPIOs etc. Signed-off-by: Alexey Brodkin <abrodkin(a)synopsys.com> Reviewed-by: Simon Glass <sjg(a)chromium.org> Reviewed-by: Marek Vasut <marex(a)denx.de> Cc: Stephen Warren <swarren(a)nvidia.com> --- Changes compared to v2: * Driver is disabled by default now * Use uintptr_t instead of uint32_t for "struct ehci_hcor" address calculation Changes compared to v1: * Updated commit message with removal of Synopsys board mention * Cleaned-up ehci_usb_remove() drivers/usb/host/Kconfig | 7 ++++++ drivers/usb/host/Makefile | 1 + drivers/usb/host/ehci-generic.c | 51 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 59 insertions(+) create mode 100644 drivers/usb/host/ehci-generic.c diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 2a2bffe..6bb9caa 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -73,4 +73,11 @@ config USB_EHCI_UNIPHIER ---help--- Enables support for the on-chip EHCI controller on UniPhier SoCs. +config USB_EHCI_GENERIC + bool "Support for generic EHCI USB controller" + depends on OF_CONTROL + default n + ---help--- + Enables support for generic EHCI controller. + endif diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index f70f38c..b9b4471 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -32,6 +32,7 @@ else obj-$(CONFIG_USB_EHCI_FSL) += ehci-fsl.o endif obj-$(CONFIG_USB_EHCI_FARADAY) += ehci-faraday.o +obj-$(CONFIG_USB_EHCI_GENERIC) += ehci-generic.o obj-$(CONFIG_USB_EHCI_EXYNOS) += ehci-exynos.o obj-$(CONFIG_USB_EHCI_MXC) += ehci-mxc.o obj-$(CONFIG_USB_EHCI_MXS) += ehci-mxs.o diff --git a/drivers/usb/host/ehci-generic.c b/drivers/usb/host/ehci-generic.c new file mode 100644 index 0000000..22e1ad0 --- /dev/null +++ b/drivers/usb/host/ehci-generic.c @@ -0,0 +1,51 @@ +/* + * Copyright (C) 2015 Alexey Brodkin <abrodkin(a)synopsys.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include "ehci.h" + +/* + * Even though here we don't explicitly use "struct ehci_ctrl" + * ehci_register() expects it to be the first thing that resides in + * device's private data. + */ +struct generic_ehci { + struct ehci_ctrl ctrl; +}; + +static int ehci_usb_probe(struct udevice *dev) +{ + struct ehci_hccr *hccr = (struct ehci_hccr *)dev_get_addr(dev); + struct ehci_hcor *hcor; + + hcor = (struct ehci_hcor *)((uintptr_t)hccr + + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); + + return ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST); +} + +static int ehci_usb_remove(struct udevice *dev) +{ + return ehci_deregister(dev); +} + +static const struct udevice_id ehci_usb_ids[] = { + { .compatible = "generic-ehci" }, + { } +}; + +U_BOOT_DRIVER(usb_ehci) = { + .name = "ehci_generic", + .id = UCLASS_USB, + .of_match = ehci_usb_ids, + .probe = ehci_usb_probe, + .remove = ehci_usb_remove, + .ops = &ehci_usb_ops, + .priv_auto_alloc_size = sizeof(struct generic_ehci), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; + -- 2.5.0

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[U-Boot] [PATCH v5 00/21] Bring up rk3036 uboot
by Lin Huang 01 Dec '15

01 Dec '15

This series patch bring up rk3036 uboot, since rk3036 only 4K size SRAM for SPL, so in SPL stage only support timer, uart, sdram driver, and back to bootrom when finish ddr initial, and boot up second stage from bootrom.You can boot to command line(mmc info etc) for now use this patchset. Jeffy Chen (2): rockchip: Add max init size & chip tag configs rockchip: Add support for rk's second level loader Lin Huang (19): rockchip: add timer driver rockchip: move SYS_MALLOC_F_LEN to rk3288 own Kconfig rockchip: rename board-spl.c to rk3288-board-spl.c rockchip: add config decide whether to build common.c dm: core: Add SPL Kconfig for REGMAP and SYSCON rockchip: serial driver support rk3036 rockchip: Bring in RK3036 device tree file includes and bindings rockchip: rk3036: Add clock driver rockchip: rk3036: Add header files for GRF rockchip: rk3036: Add Soc reset driver rockchip: rk3036: Add a simple syscon driver rockchip: rk3036: Add pinctrl driver mmc: dw_mmc: support fifo mode in dwc mmc driver rockchip: mmc: get the fifo mode and fifo depth property from dts rockchip: add early uart driver rockchip: add rk3036 sdram driver rockchip: rk3036: Add core Soc start-up code rockchip: Add basic support for evb-rk3036 board rockchip: doc: show packet rk3036 uboot image arch/arm/dts/Makefile | 3 +- arch/arm/dts/rk3036-sdk.dts | 46 ++ arch/arm/dts/rk3036.dtsi | 428 ++++++++++++ arch/arm/include/asm/arch-rockchip/cru_rk3036.h | 168 +++++ arch/arm/include/asm/arch-rockchip/grf_rk3036.h | 493 ++++++++++++++ arch/arm/include/asm/arch-rockchip/sdram_rk3036.h | 341 ++++++++++ arch/arm/include/asm/arch-rockchip/timer.h | 22 + arch/arm/include/asm/arch-rockchip/uart.h | 44 ++ arch/arm/mach-rockchip/Kconfig | 24 +- arch/arm/mach-rockchip/Makefile | 10 +- arch/arm/mach-rockchip/board-spl.c | 294 --------- arch/arm/mach-rockchip/board.c | 1 + arch/arm/mach-rockchip/rk3036-board-spl.c | 53 ++ arch/arm/mach-rockchip/rk3036/Kconfig | 23 + arch/arm/mach-rockchip/rk3036/Makefile | 13 + arch/arm/mach-rockchip/rk3036/reset_rk3036.c | 45 ++ arch/arm/mach-rockchip/rk3036/save_boot_param.S | 34 + arch/arm/mach-rockchip/rk3036/sdram_rk3036.c | 766 ++++++++++++++++++++++ arch/arm/mach-rockchip/rk3036/syscon_rk3036.c | 21 + arch/arm/mach-rockchip/rk3288-board-spl.c | 277 ++++++++ arch/arm/mach-rockchip/rk3288/Kconfig | 9 + arch/arm/mach-rockchip/rk_early_print.c | 56 ++ arch/arm/mach-rockchip/rk_timer.c | 48 ++ board/evb_rk3036/evb_rk3036/Kconfig | 15 + board/evb_rk3036/evb_rk3036/MAINTAINERS | 0 board/evb_rk3036/evb_rk3036/Makefile | 7 + board/evb_rk3036/evb_rk3036/evb_rk3036.c | 48 ++ configs/chromebook_jerry_defconfig | 2 + configs/evb-rk3036_defconfig | 26 + configs/firefly-rk3288_defconfig | 2 + configs/sandbox_defconfig | 2 + doc/README.rockchip | 11 + drivers/clk/Makefile | 1 + drivers/clk/clk_rk3036.c | 414 ++++++++++++ drivers/core/Kconfig | 19 + drivers/core/Makefile | 4 +- drivers/mmc/dw_mmc.c | 81 ++- drivers/mmc/rockchip_dw_mmc.c | 28 +- drivers/pinctrl/Kconfig | 18 + drivers/pinctrl/rockchip/Makefile | 1 + drivers/pinctrl/rockchip/pinctrl_rk3036.c | 276 ++++++++ drivers/serial/serial_rockchip.c | 1 + include/configs/evb_rk3036.h | 12 + include/configs/rk3036_common.h | 100 +++ include/configs/rk3288_common.h | 6 +- include/dt-bindings/clock/rk3036-cru.h | 186 ++++++ include/dwmmc.h | 5 + tools/Makefile | 6 + tools/rkcommon.c | 26 +- tools/rkcommon.h | 4 +- tools/rkimage.c | 2 +- tools/rksd.c | 6 +- tools/rkspi.c | 6 +- 53 files changed, 4185 insertions(+), 349 deletions(-) create mode 100644 arch/arm/dts/rk3036-sdk.dts create mode 100644 arch/arm/dts/rk3036.dtsi create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3036.h create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3036.h create mode 100644 arch/arm/include/asm/arch-rockchip/sdram_rk3036.h create mode 100644 arch/arm/include/asm/arch-rockchip/timer.h create mode 100644 arch/arm/include/asm/arch-rockchip/uart.h delete mode 100644 arch/arm/mach-rockchip/board-spl.c create mode 100644 arch/arm/mach-rockchip/rk3036-board-spl.c create mode 100644 arch/arm/mach-rockchip/rk3036/Kconfig create mode 100644 arch/arm/mach-rockchip/rk3036/Makefile create mode 100644 arch/arm/mach-rockchip/rk3036/reset_rk3036.c create mode 100644 arch/arm/mach-rockchip/rk3036/save_boot_param.S create mode 100644 arch/arm/mach-rockchip/rk3036/sdram_rk3036.c create mode 100644 arch/arm/mach-rockchip/rk3036/syscon_rk3036.c create mode 100644 arch/arm/mach-rockchip/rk3288-board-spl.c create mode 100644 arch/arm/mach-rockchip/rk_early_print.c create mode 100644 arch/arm/mach-rockchip/rk_timer.c create mode 100644 board/evb_rk3036/evb_rk3036/Kconfig create mode 100644 board/evb_rk3036/evb_rk3036/MAINTAINERS create mode 100644 board/evb_rk3036/evb_rk3036/Makefile create mode 100644 board/evb_rk3036/evb_rk3036/evb_rk3036.c create mode 100644 configs/evb-rk3036_defconfig create mode 100644 drivers/clk/clk_rk3036.c create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3036.c create mode 100644 include/configs/evb_rk3036.h create mode 100644 include/configs/rk3036_common.h create mode 100644 include/dt-bindings/clock/rk3036-cru.h -- 1.9.1

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[U-Boot] [PATCH v2] common: board_f: Dont relocate FDT incase of CONFIG_OF_EMBED
by Michal Simek 01 Dec '15

01 Dec '15

From: Siva Durga Prasad Paladugu <siva.durga.paladugu(a)xilinx.com> Don't relocate fdt in case of CONFIG_OF EMBED as the fdt is already embedded with u-boot image. Also update the fdt_blob correctly in this case Signed-off-by: Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> Reviewed-by: Alexey Brodkin <abrodkin(a)synopsys.com> --- Changes in v2: - Fix commit message reported by Alexey common/board_f.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/common/board_f.c b/common/board_f.c index b035c90ff3b7..91bf8beea1c6 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -508,7 +508,7 @@ static int reserve_global_data(void) return 0; } -static int reserve_fdt(void) +static int __maybe_unused reserve_fdt(void) { /* * If the device tree is sitting immediately above our image then we @@ -658,7 +658,7 @@ static int setup_dram_config(void) return 0; } -static int reloc_fdt(void) +static int __maybe_unused reloc_fdt(void) { if (gd->flags & GD_FLG_SKIP_RELOC) return 0; @@ -687,6 +687,9 @@ static int setup_reloc(void) gd->reloc_off = gd->relocaddr - (CONFIG_SYS_TEXT_BASE + 0x400); #endif #endif +#ifdef CONFIG_OF_EMBED + gd->fdt_blob += gd->reloc_off; +#endif memcpy(gd->new_gd, (char *)gd, sizeof(gd_t)); debug("Relocation Offset is: %08lx\n", gd->reloc_off); @@ -938,7 +941,9 @@ static init_fnc_t init_sequence_f[] = { #endif setup_machine, reserve_global_data, +#ifndef CONFIG_OF_EMBED reserve_fdt, +#endif reserve_arch, reserve_stacks, setup_dram_config, @@ -955,7 +960,9 @@ static init_fnc_t init_sequence_f[] = { setup_board_extra, #endif INIT_FUNC_WATCHDOG_RESET +#ifndef CONFIG_OF_EMBED reloc_fdt, +#endif setup_reloc, #if defined(CONFIG_X86) || defined(CONFIG_ARC) copy_uboot_to_ram, -- 1.9.1

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[U-Boot] [PATCH v7 01/21] include: Add log2 header from the kernel
by Fabio Estevam 01 Dec '15

01 Dec '15

Use the log2 header files from the kernel. Imported from kernel 4.2.3. Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> Reviewed-by: Tom Rini <trini(a)konsulko.com> Reviewed-by: Heiko Schocher <hs(a)denx.de> Reviewed-by: Jagan Teki <jteki(a)openedev.com> --- Changes since v6: - None include/linux/log2.h | 205 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 205 insertions(+) create mode 100644 include/linux/log2.h diff --git a/include/linux/log2.h b/include/linux/log2.h new file mode 100644 index 0000000..aa1de63 --- /dev/null +++ b/include/linux/log2.h @@ -0,0 +1,205 @@ +/* Integer base 2 logarithm calculation + * + * Copyright (C) 2006 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells(a)redhat.com) + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _LINUX_LOG2_H +#define _LINUX_LOG2_H + +#include <linux/types.h> +#include <linux/bitops.h> + +/* + * deal with unrepresentable constant logarithms + */ +extern __attribute__((const, noreturn)) +int ____ilog2_NaN(void); + +/* + * non-constant log of base 2 calculators + * - the arch may override these in asm/bitops.h if they can be implemented + * more efficiently than using fls() and fls64() + * - the arch is not required to handle n==0 if implementing the fallback + */ +#ifndef CONFIG_ARCH_HAS_ILOG2_U32 +static inline __attribute__((const)) +int __ilog2_u32(u32 n) +{ + return fls(n) - 1; +} +#endif + +#ifndef CONFIG_ARCH_HAS_ILOG2_U64 +static inline __attribute__((const)) +int __ilog2_u64(u64 n) +{ + return fls64(n) - 1; +} +#endif + +/* + * Determine whether some value is a power of two, where zero is + * *not* considered a power of two. + */ + +static inline __attribute__((const)) +bool is_power_of_2(unsigned long n) +{ + return (n != 0 && ((n & (n - 1)) == 0)); +} + +/* + * round up to nearest power of two + */ +static inline __attribute__((const)) +unsigned long __roundup_pow_of_two(unsigned long n) +{ + return 1UL << fls_long(n - 1); +} + +/* + * round down to nearest power of two + */ +static inline __attribute__((const)) +unsigned long __rounddown_pow_of_two(unsigned long n) +{ + return 1UL << (fls_long(n) - 1); +} + +/** + * ilog2 - log of base 2 of 32-bit or a 64-bit unsigned value + * @n - parameter + * + * constant-capable log of base 2 calculation + * - this can be used to initialise global variables from constant data, hence + * the massive ternary operator construction + * + * selects the appropriately-sized optimised version depending on sizeof(n) + */ +#define ilog2(n) \ +( \ + __builtin_constant_p(n) ? ( \ + (n) < 1 ? ____ilog2_NaN() : \ + (n) & (1ULL << 63) ? 63 : \ + (n) & (1ULL << 62) ? 62 : \ + (n) & (1ULL << 61) ? 61 : \ + (n) & (1ULL << 60) ? 60 : \ + (n) & (1ULL << 59) ? 59 : \ + (n) & (1ULL << 58) ? 58 : \ + (n) & (1ULL << 57) ? 57 : \ + (n) & (1ULL << 56) ? 56 : \ + (n) & (1ULL << 55) ? 55 : \ + (n) & (1ULL << 54) ? 54 : \ + (n) & (1ULL << 53) ? 53 : \ + (n) & (1ULL << 52) ? 52 : \ + (n) & (1ULL << 51) ? 51 : \ + (n) & (1ULL << 50) ? 50 : \ + (n) & (1ULL << 49) ? 49 : \ + (n) & (1ULL << 48) ? 48 : \ + (n) & (1ULL << 47) ? 47 : \ + (n) & (1ULL << 46) ? 46 : \ + (n) & (1ULL << 45) ? 45 : \ + (n) & (1ULL << 44) ? 44 : \ + (n) & (1ULL << 43) ? 43 : \ + (n) & (1ULL << 42) ? 42 : \ + (n) & (1ULL << 41) ? 41 : \ + (n) & (1ULL << 40) ? 40 : \ + (n) & (1ULL << 39) ? 39 : \ + (n) & (1ULL << 38) ? 38 : \ + (n) & (1ULL << 37) ? 37 : \ + (n) & (1ULL << 36) ? 36 : \ + (n) & (1ULL << 35) ? 35 : \ + (n) & (1ULL << 34) ? 34 : \ + (n) & (1ULL << 33) ? 33 : \ + (n) & (1ULL << 32) ? 32 : \ + (n) & (1ULL << 31) ? 31 : \ + (n) & (1ULL << 30) ? 30 : \ + (n) & (1ULL << 29) ? 29 : \ + (n) & (1ULL << 28) ? 28 : \ + (n) & (1ULL << 27) ? 27 : \ + (n) & (1ULL << 26) ? 26 : \ + (n) & (1ULL << 25) ? 25 : \ + (n) & (1ULL << 24) ? 24 : \ + (n) & (1ULL << 23) ? 23 : \ + (n) & (1ULL << 22) ? 22 : \ + (n) & (1ULL << 21) ? 21 : \ + (n) & (1ULL << 20) ? 20 : \ + (n) & (1ULL << 19) ? 19 : \ + (n) & (1ULL << 18) ? 18 : \ + (n) & (1ULL << 17) ? 17 : \ + (n) & (1ULL << 16) ? 16 : \ + (n) & (1ULL << 15) ? 15 : \ + (n) & (1ULL << 14) ? 14 : \ + (n) & (1ULL << 13) ? 13 : \ + (n) & (1ULL << 12) ? 12 : \ + (n) & (1ULL << 11) ? 11 : \ + (n) & (1ULL << 10) ? 10 : \ + (n) & (1ULL << 9) ? 9 : \ + (n) & (1ULL << 8) ? 8 : \ + (n) & (1ULL << 7) ? 7 : \ + (n) & (1ULL << 6) ? 6 : \ + (n) & (1ULL << 5) ? 5 : \ + (n) & (1ULL << 4) ? 4 : \ + (n) & (1ULL << 3) ? 3 : \ + (n) & (1ULL << 2) ? 2 : \ + (n) & (1ULL << 1) ? 1 : \ + (n) & (1ULL << 0) ? 0 : \ + ____ilog2_NaN() \ + ) : \ + (sizeof(n) <= 4) ? \ + __ilog2_u32(n) : \ + __ilog2_u64(n) \ + ) + +/** + * roundup_pow_of_two - round the given value up to nearest power of two + * @n - parameter + * + * round the given value up to the nearest power of two + * - the result is undefined when n == 0 + * - this can be used to initialise global variables from constant data + */ +#define roundup_pow_of_two(n) \ +( \ + __builtin_constant_p(n) ? ( \ + (n == 1) ? 1 : \ + (1UL << (ilog2((n) - 1) + 1)) \ + ) : \ + __roundup_pow_of_two(n) \ + ) + +/** + * rounddown_pow_of_two - round the given value down to nearest power of two + * @n - parameter + * + * round the given value down to the nearest power of two + * - the result is undefined when n == 0 + * - this can be used to initialise global variables from constant data + */ +#define rounddown_pow_of_two(n) \ +( \ + __builtin_constant_p(n) ? ( \ + (1UL << ilog2(n))) : \ + __rounddown_pow_of_two(n) \ + ) + +/** + * order_base_2 - calculate the (rounded up) base 2 order of the argument + * @n: parameter + * + * The first few values calculated by this routine: + * ob2(0) = 0 + * ob2(1) = 0 + * ob2(2) = 1 + * ob2(3) = 2 + * ob2(4) = 2 + * ob2(5) = 3 + * ... and so on. + */ + +#define order_base_2(n) ilog2(roundup_pow_of_two(n)) + +#endif /* _LINUX_LOG2_H */ -- 1.9.1

7 65

[U-Boot] [PATCH v2] arm: socfpga: Enable load zImage and Linux DTB from USB
by Chin Liang See 01 Dec '15

01 Dec '15

Adding new environment usbload which will load zImage and Linux DTB from USB mass storage through FAT file system. Signed-off-by: Chin Liang See <clsee(a)altera.com> Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> Cc: Dinh Nguyen <dinh.linux(a)gmail.com> Cc: Pavel Machek <pavel(a)denx.de> Cc: Marek Vasut <marex(a)denx.de> Cc: Stefan Roese <sr(a)denx.de> --- Changes for v2 - Using load command instead of fatload --- include/configs/socfpga_arria5_socdk.h | 5 ++++- include/configs/socfpga_cyclone5_socdk.h | 5 ++++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/include/configs/socfpga_arria5_socdk.h b/include/configs/socfpga_arria5_socdk.h index 9337a58..1d335c4 100644 --- a/include/configs/socfpga_arria5_socdk.h +++ b/include/configs/socfpga_arria5_socdk.h @@ -99,7 +99,10 @@ "sf read ${fdt_addr} ${qspifdtaddr} ${fdtimagesize};\0" \ "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ - "bootm ${loadaddr} - ${fdt_addr}\0" + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "usbload=usb reset;" \ + "load usb 0 ${loadaddr} ${bootimage};" \ + "load usb 0 ${fdt_addr} ${fdtimage}\0" /* The rest of the configuration is shared */ #include <configs/socfpga_common.h> diff --git a/include/configs/socfpga_cyclone5_socdk.h b/include/configs/socfpga_cyclone5_socdk.h index 3b2cfb0..d045127 100644 --- a/include/configs/socfpga_cyclone5_socdk.h +++ b/include/configs/socfpga_cyclone5_socdk.h @@ -99,7 +99,10 @@ "sf read ${fdt_addr} ${qspifdtaddr} ${fdtimagesize};\0" \ "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ - "bootm ${loadaddr} - ${fdt_addr}\0" + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "usbload=usb reset;" \ + "load usb 0 ${loadaddr} ${bootimage};" \ + "load usb 0 ${fdt_addr} ${fdtimage}\0" /* The rest of the configuration is shared */ #include <configs/socfpga_common.h> -- 2.2.0

4 9

[U-Boot] [PATCH 01/14] ARM: zynq: Remove PHYLIB from config to defconfig
by Michal Simek 01 Dec '15

01 Dec '15

Move PHYLIB from board config to defconfig Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- configs/zynq_microzed_defconfig | 1 + configs/zynq_picozed_defconfig | 1 + configs/zynq_zc702_defconfig | 1 + configs/zynq_zc706_defconfig | 1 + configs/zynq_zc770_xm010_defconfig | 1 + configs/zynq_zc770_xm011_defconfig | 1 + configs/zynq_zc770_xm012_defconfig | 1 + configs/zynq_zc770_xm013_defconfig | 1 + configs/zynq_zed_defconfig | 1 + configs/zynq_zybo_defconfig | 1 + include/configs/zynq-common.h | 1 - 11 files changed, 10 insertions(+), 1 deletion(-) diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig index 3bf17cfc7ab7..0608d8a733cf 100644 --- a/configs/zynq_microzed_defconfig +++ b/configs/zynq_microzed_defconfig @@ -15,4 +15,5 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y +CONFIG_PHYLIB=y CONFIG_ZYNQ_QSPI=y diff --git a/configs/zynq_picozed_defconfig b/configs/zynq_picozed_defconfig index 600ca8b2f347..d6f0ce388832 100644 --- a/configs/zynq_picozed_defconfig +++ b/configs/zynq_picozed_defconfig @@ -8,3 +8,4 @@ CONFIG_SPL=y CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_PHYLIB=y diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig index e3c1e23638ff..8318b94ecbb2 100644 --- a/configs/zynq_zc702_defconfig +++ b/configs/zynq_zc702_defconfig @@ -14,4 +14,5 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y +CONFIG_PHYLIB=y CONFIG_ZYNQ_QSPI=y diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig index eaf15f2d700c..533aff9a7531 100644 --- a/configs/zynq_zc706_defconfig +++ b/configs/zynq_zc706_defconfig @@ -15,4 +15,5 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y +CONFIG_PHYLIB=y CONFIG_ZYNQ_QSPI=y diff --git a/configs/zynq_zc770_xm010_defconfig b/configs/zynq_zc770_xm010_defconfig index 381ace8ace6f..689d19e992da 100644 --- a/configs/zynq_zc770_xm010_defconfig +++ b/configs/zynq_zc770_xm010_defconfig @@ -17,5 +17,6 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_WINBOND=y +CONFIG_PHYLIB=y CONFIG_ZYNQ_SPI=y CONFIG_ZYNQ_QSPI=y diff --git a/configs/zynq_zc770_xm011_defconfig b/configs/zynq_zc770_xm011_defconfig index 49dd02554c88..c7125c304ab8 100644 --- a/configs/zynq_zc770_xm011_defconfig +++ b/configs/zynq_zc770_xm011_defconfig @@ -12,3 +12,4 @@ CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM011" CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_PHYLIB=y diff --git a/configs/zynq_zc770_xm012_defconfig b/configs/zynq_zc770_xm012_defconfig index d50594371aaa..a8f28da11767 100644 --- a/configs/zynq_zc770_xm012_defconfig +++ b/configs/zynq_zc770_xm012_defconfig @@ -10,3 +10,4 @@ CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM012" CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_PHYLIB=y diff --git a/configs/zynq_zc770_xm013_defconfig b/configs/zynq_zc770_xm013_defconfig index c2ae2ab2809d..6b2fd8ca4ebb 100644 --- a/configs/zynq_zc770_xm013_defconfig +++ b/configs/zynq_zc770_xm013_defconfig @@ -12,3 +12,4 @@ CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM013" CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_PHYLIB=y diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig index f603bb360106..4076c30707b1 100644 --- a/configs/zynq_zed_defconfig +++ b/configs/zynq_zed_defconfig @@ -15,4 +15,5 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y +CONFIG_PHYLIB=y CONFIG_ZYNQ_QSPI=y diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig index 1227b7a14c32..c51049e664b1 100644 --- a/configs/zynq_zybo_defconfig +++ b/configs/zynq_zybo_defconfig @@ -11,6 +11,7 @@ CONFIG_FIT_SIGNATURE=y CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_PHYLIB=y CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ZYNQ=y CONFIG_DEBUG_UART_BASE=0xe0001000 diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index fa83ac7b15d0..a9e6bf046a97 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -50,7 +50,6 @@ # define CONFIG_ZYNQ_GEM # define CONFIG_MII # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN -# define CONFIG_PHYLIB # define CONFIG_PHY_MARVELL # define CONFIG_BOOTP_SERVERIP # define CONFIG_BOOTP_BOOTPATH -- 1.9.1

3 18

[U-Boot] [PATCH 1/2] rockchip: add CONFIG_SPL_ROCKCHIP_SERIAL
by Lin Huang 01 Dec '15

01 Dec '15

we can use this config to disable rockchip serial driver in SPL stage, since some rockchip soc sram size is small(rk3036 etc), so we don't want rockchip serial driver build in SPL, but we still want use common debug driver in SPL. Signed-off-by: Lin Huang <hl(a)rock-chips.com> --- arch/arm/mach-rockchip/Kconfig | 3 +++ drivers/serial/Makefile | 2 +- include/configs/rk3288_common.h | 1 + 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index ccff81a..595263c 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -59,6 +59,9 @@ config DM_GPIO config ROCKCHIP_SERIAL default y +config SPL_ROCKCHIP_SERIAL + default n + source "arch/arm/mach-rockchip/rk3288/Kconfig" source "arch/arm/mach-rockchip/rk3036/Kconfig" endif diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 1818c7c..73e30c6 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -41,7 +41,7 @@ obj-$(CONFIG_ZYNQ_SERIAL) += serial_zynq.o obj-$(CONFIG_BFIN_SERIAL) += serial_bfin.o obj-$(CONFIG_FSL_LPUART) += serial_lpuart.o obj-$(CONFIG_MXS_AUART) += mxs_auart.o -obj-$(CONFIG_ROCKCHIP_SERIAL) += serial_rockchip.o +obj-$(CONFIG_$(SPL_)ROCKCHIP_SERIAL) += serial_rockchip.o obj-$(CONFIG_ARC_SERIAL) += serial_arc.o obj-$(CONFIG_TEGRA_SERIAL) += serial_tegra.o obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index 74c7ee1..7f3d1ee 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -30,6 +30,7 @@ #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_ROCKCHIP_SERIAL #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SPL_BOARD_INIT -- 1.9.1

3 6

[U-Boot] [PATCH] arm: imx6: novena: Enable extfs support in SPL
by Marek Vasut 01 Dec '15

01 Dec '15

Simple patch to enable support for extfs filesystem in SPL, this is useful to those who want to avoid vfat like plague. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Stefano Babic <sbabic(a)denx.de> --- include/configs/novena.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/novena.h b/include/configs/novena.h index fc953f6..d5f517c 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -83,6 +83,7 @@ /* SPL */ #define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_EXT_SUPPORT #define CONFIG_SPL_MMC_SUPPORT #include "imx6_spl.h" /* common IMX6 SPL configuration */ -- 2.1.4

2 1