November 2015 - U-Boot

[U-Boot] [PATCH] usb: zynqmp: Fix build warnings
by Marek Vasut 30 Nov '15

30 Nov '15

The driver does "return 0" in function with void type. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Michal Simek <monstr(a)monstr.eu> Cc: Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> --- drivers/usb/host/xhci-zynqmp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/host/xhci-zynqmp.c b/drivers/usb/host/xhci-zynqmp.c index e76a0c6..530d97c 100644 --- a/drivers/usb/host/xhci-zynqmp.c +++ b/drivers/usb/host/xhci-zynqmp.c @@ -139,5 +139,5 @@ void xhci_hcd_stop(int index) * sw. But this support may be added in future socs. */ - return 0; + return; } -- 2.1.4

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[U-Boot] [PATCH] board/ls2085qds: Fix typo in README for QSGMII riser card
by Prabhakar Kushwaha 30 Nov '15

30 Nov '15

DPMACx to PHY mapping for SGMII is mentioned as QSGMII. So fix typo in README for QSGMII rise card. Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- board/freescale/ls2085aqds/README | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/freescale/ls2085aqds/README b/board/freescale/ls2085aqds/README index e4a6f69..b3ed854 100644 --- a/board/freescale/ls2085aqds/README +++ b/board/freescale/ls2085aqds/README @@ -172,7 +172,7 @@ Supported PHY addresses during SGMII: #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe -Mapping DPMACx to PHY during QSGMII +Mapping DPMACx to PHY during SGMII DPMAC1 -> PHY1-P0 DPMAC2 -> PHY2-P0 DPMAC3 -> PHY3-P0 -- 1.9.1

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[U-Boot] [PATCH] axs10x: add support of generic ECHI USB 2.0 controller
by Alexey Brodkin 30 Nov '15

30 Nov '15

This commit adds support of USB 2.0 storage media on AXS10x boards. Signed-off-by: Alexey Brodkin <abrodkin(a)synopsys.com> --- arch/arc/dts/axs10x.dts | 6 ++++++ configs/axs101_defconfig | 5 +++++ configs/axs103_defconfig | 5 +++++ 3 files changed, 16 insertions(+) diff --git a/arch/arc/dts/axs10x.dts b/arch/arc/dts/axs10x.dts index 8fe1837..80e6d6b 100644 --- a/arch/arc/dts/axs10x.dts +++ b/arch/arc/dts/axs10x.dts @@ -42,4 +42,10 @@ clock-names = "stmmaceth"; max-speed = <100>; }; + + ehci@0xe0040000 { + compatible = "generic-ehci"; + reg = < 0xe0040000 0x100 >; + interrupts = < 8 >; + }; }; diff --git a/configs/axs101_defconfig b/configs/axs101_defconfig index 52d5e2f..b7d487b 100644 --- a/configs/axs101_defconfig +++ b/configs/axs101_defconfig @@ -8,6 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="axs10x" CONFIG_SYS_PROMPT="AXS# " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set +CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y @@ -18,5 +19,9 @@ CONFIG_DM=y CONFIG_CLK=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y CONFIG_SYS_NS16550=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/axs103_defconfig b/configs/axs103_defconfig index a7f3c38..d25539e 100644 --- a/configs/axs103_defconfig +++ b/configs/axs103_defconfig @@ -7,6 +7,7 @@ CONFIG_DEFAULT_DEVICE_TREE="axs10x" CONFIG_SYS_PROMPT="AXS# " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set +CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y @@ -17,5 +18,9 @@ CONFIG_DM=y CONFIG_CLK=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y CONFIG_SYS_NS16550=y CONFIG_USE_PRIVATE_LIBGCC=y -- 2.5.0

2 1

[U-Boot] [PATCH] arm: ls102xa: Update fdt_high and initrd_high for LS1021AQDS board
by Alison Wang 30 Nov '15

30 Nov '15

As 3G/1G user/kernel memory split is used on LS1021A, the Linux kernel fails to access the device tree blob on boot. The reason is that u-boot relocates the device tree blob into high memory when booting the kernel and the kernel is unable to access the blob. To avoid this issue, fdt_high is set to the value of 0xffffffff. The device tree blob will not get relocated and is still in low memory to make it accessible to the kernel. For the same reason, initrd_high is set to the value of 0xffffffff too. This patch is to update fdt_high and initrd_high for LS1021AQDS board. Signed-off-by: Alison Wang <alison.wang(a)freescale.com> --- include/configs/ls1021aqds.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 562e78f..489db9c 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -579,14 +579,14 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_LPUART #define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ - "fdt_high=0xcfffffff\0" \ - "initrd_high=0xcfffffff\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" #else #define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ - "fdt_high=0xcfffffff\0" \ - "initrd_high=0xcfffffff\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" #endif -- 2.1.0.27.g96db324

2 1

[U-Boot] [PATCH v1] armv8: fsl-layerscape: Fix "cpu release" command
by York Sun 30 Nov '15

30 Nov '15

When one core is released, other cores may not have valid entry address. Those cores are trapped by "wfe" and wait for further instruction. When their address is set, they need to be kicked off by "sev". Signed-off-by: York Sun <yorksun(a)freescale.com> --- arch/arm/cpu/armv8/fsl-layerscape/mp.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c index 0d600db..df7ffb8 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c @@ -192,6 +192,12 @@ int cpu_release(int nr, int argc, char * const argv[]) (unsigned long)table + SPIN_TABLE_ELEM_SIZE); asm volatile("dsb st"); smp_kick_all_cpus(); /* only those with entry addr set will run */ + /* + * When the first release command runs, all cores are set to go. Those + * without a valid entry address will be trapped by "wfe". "sev" kicks + * them off to check the address again. When set, they continue to run. + */ + asm volatile("sev"); return 0; } -- 1.7.9.5

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[U-Boot] [PATCH] drivers/ddr/fsl: Fix typo in BIST test for DDR4
by York Sun 30 Nov '15

30 Nov '15

BIST test code has a typo, resulting the binding registers not maintained as expected. This typo results BIST runs twice on the covered memory. Signed-off-by: York Sun <yorksun(a)freescale.com> Reported-by: Shengzhou Liu <Shengzhou.Liu(a)freescale.com> --- drivers/ddr/fsl/fsl_ddr_gen4.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c index 49e4688..114c811 100644 --- a/drivers/ddr/fsl/fsl_ddr_gen4.c +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c @@ -423,16 +423,16 @@ step2: if (getenv_f("ddr_bist", buffer, CONFIG_SYS_CBSIZE) >= 0) { puts("Running BIST test. This will take a while..."); cs0_config = ddr_in32(&ddr->cs0_config); + cs0_bnds = ddr_in32(&ddr->cs0_bnds); + cs1_bnds = ddr_in32(&ddr->cs1_bnds); + cs2_bnds = ddr_in32(&ddr->cs2_bnds); + cs3_bnds = ddr_in32(&ddr->cs3_bnds); if (cs0_config & CTLR_INTLV_MASK) { - cs0_bnds = ddr_in32(&cs0_bnds); - cs1_bnds = ddr_in32(&cs1_bnds); - cs2_bnds = ddr_in32(&cs2_bnds); - cs3_bnds = ddr_in32(&cs3_bnds); /* set bnds to non-interleaving */ - ddr_out32(&cs0_bnds, (cs0_bnds & 0xfffefffe) >> 1); - ddr_out32(&cs1_bnds, (cs1_bnds & 0xfffefffe) >> 1); - ddr_out32(&cs2_bnds, (cs2_bnds & 0xfffefffe) >> 1); - ddr_out32(&cs3_bnds, (cs3_bnds & 0xfffefffe) >> 1); + ddr_out32(&ddr->cs0_bnds, (cs0_bnds & 0xfffefffe) >> 1); + ddr_out32(&ddr->cs1_bnds, (cs1_bnds & 0xfffefffe) >> 1); + ddr_out32(&ddr->cs2_bnds, (cs2_bnds & 0xfffefffe) >> 1); + ddr_out32(&ddr->cs3_bnds, (cs3_bnds & 0xfffefffe) >> 1); } ddr_out32(&ddr->mtp1, BIST_PATTERN1); ddr_out32(&ddr->mtp2, BIST_PATTERN1); @@ -469,10 +469,10 @@ step2: if (cs0_config & CTLR_INTLV_MASK) { /* restore bnds registers */ - ddr_out32(&cs0_bnds, cs0_bnds); - ddr_out32(&cs1_bnds, cs1_bnds); - ddr_out32(&cs2_bnds, cs2_bnds); - ddr_out32(&cs3_bnds, cs3_bnds); + ddr_out32(&ddr->cs0_bnds, cs0_bnds); + ddr_out32(&ddr->cs1_bnds, cs1_bnds); + ddr_out32(&ddr->cs2_bnds, cs2_bnds); + ddr_out32(&ddr->cs3_bnds, cs3_bnds); } } #endif -- 1.7.9.5

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[U-Boot] [PATCH] armv8/layerscape: Update MMU table with execute-never bits
by Alison Wang 30 Nov '15

30 Nov '15

For most device addresses excution shouldn't be allowed. Revise the MMU table to enforce execute-never bits. OCRAM, DDR and IFC are allowed for excution. Signed-off-by: York Sun <yorksun(a)freescale.com> Signed-off-by: Alison Wang <alison.wang(a)freescale.com> Reported-by: Zhichun Hua <zhichun.hua(a)freescale.com> --- arch/arm/cpu/armv8/cache_v8.c | 4 +- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 2 +- arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 79 +++++++++++++++++--------- arch/arm/include/asm/armv8/mmu.h | 2 +- 4 files changed, 56 insertions(+), 31 deletions(-) diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index b1ea822..8f3ca40 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -13,13 +13,13 @@ DECLARE_GLOBAL_DATA_PTR; #ifndef CONFIG_SYS_DCACHE_OFF inline void set_pgtable_section(u64 *page_table, u64 index, u64 section, - u64 memory_type, u64 share) + u64 memory_type, u64 attribute) { u64 value; value = section | PMD_TYPE_SECT | PMD_SECT_AF; value |= PMD_ATTRINDX(memory_type); - value |= share; + value |= attribute; page_table[index] = value; } diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 0cb0afa..9d1c70f 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -76,7 +76,7 @@ static int set_block_entry(const struct sys_mmu_table *list, index, block_addr, list->memory_type, - list->share); + list->attribute); block_addr += block_size; index++; } diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index 2903996..b4b85a8 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -103,7 +103,7 @@ struct sys_mmu_table { u64 phys_addr; u64 size; u64 memory_type; - u64 share; + u64 attribute; }; struct table_info { @@ -115,7 +115,8 @@ struct table_info { static const struct sys_mmu_table early_mmu_table[] = { #ifdef CONFIG_FSL_LSCH3 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, - CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE }, /* For IFC Region #1, only the first 4MB is cache-enabled */ @@ -130,16 +131,19 @@ static const struct sys_mmu_table early_mmu_table[] = { { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE }, { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, - CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE }, #elif defined(CONFIG_FSL_LSCH2) { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, - CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE }, { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, - CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, @@ -152,72 +156,93 @@ static const struct sys_mmu_table early_mmu_table[] = { static const struct sys_mmu_table final_mmu_table[] = { #ifdef CONFIG_FSL_LSCH3 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, - CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE }, { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE }, { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2, - CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, - CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE, - CONFIG_SYS_FSL_MC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_MC_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE, - CONFIG_SYS_FSL_NI_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_NI_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, /* For QBMAN portal, only the first 64MB is cache-enabled */ { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE, - CONFIG_SYS_FSL_QBMAN_SIZE_1, MT_NORMAL, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_QBMAN_SIZE_1, MT_NORMAL, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1, CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1, CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1, - MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, - CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, - CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, - CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, #ifdef CONFIG_LS2085A { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR, - CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, #endif { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE, - CONFIG_SYS_FSL_WRIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_WRIOP1_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE, - CONFIG_SYS_FSL_AIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_AIOP1_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE, - CONFIG_SYS_FSL_PEBUF_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_PEBUF_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE }, #elif defined(CONFIG_FSL_LSCH2) { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE, - CONFIG_SYS_FSL_BOOTROM_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_BOOTROM_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, - CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE }, { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, - CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE, - CONFIG_SYS_FSL_QSPI_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_QSPI_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE | PMD_SECT_NS }, { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE, - CONFIG_SYS_FSL_QBMAN_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_QBMAN_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE }, { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, - CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, - CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, - CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL, PMD_SECT_OUTER_SHARE }, #endif diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index d8d9af4..2e2a3a8 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -119,7 +119,7 @@ void set_pgtable_section(u64 *page_table, u64 index, u64 section, u64 memory_type, - u64 share); + u64 attribute); void set_pgtable_table(u64 *page_table, u64 index, u64 *table_addr); -- 2.1.0.27.g96db324

2 1

[U-Boot] [PATCH v1] drivers/ddr/fsl: Enable detection of one DDR controller operation for LSCH3
by York Sun 30 Nov '15

30 Nov '15

Freescale LSCH3 platforms use two DDR controlers interleaving mode out of reset. It can be configured to disable one controller. To support this operation, the driver needs to detect and skip the disabled controller. Signed-off-by: York Sun <yorksun(a)freescale.com> --- Change log v1: Initial patch. Tested on LS2085AQDS and LS2085ARDB. arch/arm/include/asm/arch-fsl-layerscape/config.h | 7 ++++ drivers/ddr/fsl/main.c | 1 + drivers/ddr/fsl/util.c | 40 +++++++++++++++++++++ include/fsl_ddr.h | 1 + 4 files changed, 49 insertions(+) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 87bb937..b0f0957 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -60,6 +60,13 @@ #define CCI_MN_DVM_DOMAIN_CTL 0x200 #define CCI_MN_DVM_DOMAIN_CTL_SET 0x210 +#define CCI_HN_F_0_BASE (CCI_MN_BASE + 0x200000) +#define CCI_HN_F_1_BASE (CCI_MN_BASE + 0x210000) +#define CCN_HN_F_SAM_CTL 0x8 /* offset on base HN_F base */ +#define CCN_HN_F_SAM_NODEID_MASK 0x7f +#define CCN_HN_F_SAM_NODEID_DDR0 0x4 +#define CCN_HN_F_SAM_NODEID_DDR1 0xe + #define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000) #define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000) #define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000) diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c index 72ec1be..c686632 100644 --- a/drivers/ddr/fsl/main.c +++ b/drivers/ddr/fsl/main.c @@ -813,6 +813,7 @@ phys_size_t fsl_ddr_sdram(void) info.board_need_mem_reset = board_need_mem_reset; info.board_mem_reset = board_assert_mem_reset; info.board_mem_de_reset = board_deassert_mem_reset; + remove_unused_controllers(&info); return __fsl_ddr_sdram(&info); } diff --git a/drivers/ddr/fsl/util.c b/drivers/ddr/fsl/util.c index ce55aea..1a49b28 100644 --- a/drivers/ddr/fsl/util.c +++ b/drivers/ddr/fsl/util.c @@ -385,3 +385,43 @@ void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl, ddr_out32(ddrc_debug2_p[i], ddrc_debug2[i]); } #endif /* CONFIG_FSL_DDR_SYNC_REFRESH */ + +void remove_unused_controllers(fsl_ddr_info_t *info) +{ +#ifdef CONFIG_FSL_LSCH3 + int i; + u64 nodeid; + void *hnf_sam_ctrl = (void *)(CCI_HN_F_0_BASE + CCN_HN_F_SAM_CTL); + bool ddr0_used = false; + bool ddr1_used = false; + + for (i = 0; i < 8; i++) { + nodeid = in_le64(hnf_sam_ctrl) & CCN_HN_F_SAM_NODEID_MASK; + if (nodeid == CCN_HN_F_SAM_NODEID_DDR0) { + ddr0_used = true; + } else if (nodeid == CCN_HN_F_SAM_NODEID_DDR1) { + ddr1_used = true; + } else { + printf("Unknown nodeid in HN-F SAM control: 0x%llx\n", + nodeid); + } + hnf_sam_ctrl += (CCI_HN_F_1_BASE - CCI_HN_F_0_BASE); + } + if (!ddr0_used && !ddr1_used) { + printf("Invalid configuration in HN-F SAM control\n"); + return; + } + + if (!ddr0_used && info->first_ctrl == 0) { + info->first_ctrl = 1; + info->num_ctrls = 1; + debug("First DDR controller disabled\n"); + return; + } + + if (!ddr1_used && info->first_ctrl + info->num_ctrls > 1) { + info->num_ctrls = 1; + debug("Second DDR controller disabled\n"); + } +#endif +} diff --git a/include/fsl_ddr.h b/include/fsl_ddr.h index 1ac092b..9aaf6b3 100644 --- a/include/fsl_ddr.h +++ b/include/fsl_ddr.h @@ -131,6 +131,7 @@ void board_add_ram_info(int use_default); /* processor specific function */ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, unsigned int ctrl_num, int step); +void remove_unused_controllers(fsl_ddr_info_t *info); /* board specific function */ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, -- 1.7.9.5

1 1

[U-Boot] [Patch V4 0/7] add LS1043AQDS platform support
by Gong Qianyu 30 Nov '15

30 Nov '15

Hi all, Here are the main changes for V4 patchset. LS1043ARDB MAINTAINERS has already been updated in U-Boot. So remove that patch in V4 patchset. - Update the code base. - Use #ifndef CONFIG_LS102XA instead of #ifdef CONFIG_FSL_LAYERSCAPE for PCIe patch. - Fix vid support for LS1043AQDS. - Remove RAW_TIMING definition for DDR3. - Remove LS1043AQDS_MDIO_10GC related code because LS1043AQDS board has no phy for it. [Patch V4 1/7] pci/layerscape: add support for LS1043A PCIe LUT [Patch V4 2/7] armv8/fsl-layerscape: Remove reference to gdata [Patch V4 3/7] armv8/ls1043ardb: dts: add dtb support [Patch V4 4/7] armv8/ls1043aqds: add LS1043AQDS board support [Patch V4 5/7] armv8/ls1043aqds: dts: add dtb support [Patch V4 6/7] armv8/ls1043ardb: add DSPI support [Patch V4 7/7] armv8/ls1043ardb: add USB support

2 14

[U-Boot] [PATCH 2/2][v2] armv8: ls2085a: Add support of LS2085A SoC
by Prabhakar Kushwaha 30 Nov '15

30 Nov '15

Freescale's LS2085A is a another personality of LS2080A SoC with support of AIOP and DP-DDR. This Patch adds support of LS2085A Personality. Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava(a)freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- Changes for v2: Rebased on LS1043 patch set arch/arm/cpu/armv8/fsl-layerscape/Makefile | 8 ++++++-- arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c | 5 +++++ arch/arm/cpu/armv8/fsl-layerscape/soc.c | 2 +- arch/arm/cpu/armv8/fsl-layerscape/spl.c | 4 ++-- arch/arm/include/asm/arch-fsl-layerscape/config.h | 8 +++++++- arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 4 +++- arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h | 2 +- configs/ls2080a_emu_defconfig | 2 +- configs/ls2080a_simu_defconfig | 2 +- configs/ls2080aqds_defconfig | 2 +- configs/ls2080aqds_nand_defconfig | 2 +- configs/ls2080ardb_defconfig | 2 +- configs/ls2080ardb_nand_defconfig | 2 +- configs/{ls2080a_emu_defconfig => ls2085a_emu_defconfig} | 2 +- configs/{ls2080a_simu_defconfig => ls2085a_simu_defconfig} | 2 +- configs/{ls2080aqds_defconfig => ls2085aqds_defconfig} | 2 +- configs/{ls2080aqds_nand_defconfig => ls2085aqds_nand_defconfig} | 2 +- configs/{ls2080ardb_defconfig => ls2085ardb_defconfig} | 2 +- configs/{ls2080ardb_nand_defconfig => ls2085ardb_nand_defconfig} | 2 +- drivers/ddr/fsl/fsl_ddr_gen4.c | 4 ++-- drivers/net/ldpaa_eth/Makefile | 1 + drivers/pci/pcie_layerscape.c | 2 +- include/configs/ls2080a_common.h | 9 +++++++-- include/configs/ls2080a_emu.h | 7 +++++++ include/configs/ls2080a_simu.h | 7 +++++++ include/linux/usb/xhci-fsl.h | 2 +- 26 files changed, 63 insertions(+), 26 deletions(-) copy configs/{ls2080a_emu_defconfig => ls2085a_emu_defconfig} (87%) copy configs/{ls2080a_simu_defconfig => ls2085a_simu_defconfig} (90%) copy configs/{ls2080aqds_defconfig => ls2085aqds_defconfig} (86%) copy configs/{ls2080aqds_nand_defconfig => ls2085aqds_nand_defconfig} (73%) copy configs/{ls2080ardb_defconfig => ls2085ardb_defconfig} (86%) copy configs/{ls2080ardb_nand_defconfig => ls2085ardb_nand_defconfig} (73%) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index 1beb426..cce7405 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -23,8 +23,12 @@ endif ifneq ($(CONFIG_LS2080A),) obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o -else +endif + +ifneq ($(CONFIG_LS2085A),) +obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o +endif + ifneq ($(CONFIG_LS1043A),) obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o endif -endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c index ea3114c..8ef4f1c 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c @@ -28,7 +28,12 @@ static struct serdes_config serdes1_cfg_tbl[] = { SGMII1 } }, {0x26, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, XFI2, XFI1 } }, {0x28, {SGMII8, SGMII7, SGMII6, SGMII5, XFI4, XFI3, XFI2, XFI1 } }, +#ifdef CONFIG_LS2080A + {0x2A, {NONE, NONE, NONE, XFI5, XFI4, XFI3, XFI2, XFI1 } }, +#endif +#ifdef CONFIG_LS2085A {0x2A, {XFI8, XFI7, XFI6, XFI5, XFI4, XFI3, XFI2, XFI1 } }, +#endif {0x2B, {SGMII8, SGMII7, SGMII6, SGMII5, XAUI1, XAUI1, XAUI1, XAUI1 } }, {0x32, {XAUI2, XAUI2, XAUI2, XAUI2, XAUI1, XAUI1, XAUI1, XAUI1 } }, {0x33, {PCIE2, PCIE2, PCIE2, PCIE2, QSGMII_C, QSGMII_D, QSGMII_A, diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 54c75e2..188dc7a 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -13,7 +13,7 @@ DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_LS2080A +#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) #ifdef CONFIG_SYS_FSL_ERRATUM_A009635 #define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val" diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c index a3410af..3dae228 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -48,7 +48,7 @@ void board_init_f(ulong dummy) gd = &gdata; /* Clear global data */ memset((void *)gd, 0, sizeof(gd_t)); -#ifdef CONFIG_LS2080A +#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) arch_cpu_init(); #endif #ifdef CONFIG_FSL_IFC @@ -56,7 +56,7 @@ void board_init_f(ulong dummy) #endif board_early_init_f(); timer_init(); -#ifdef CONFIG_LS2080A +#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) env_init(); #endif get_clocks(); diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 1b700b3..9133425 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -17,10 +17,16 @@ #define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */ #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 -#if defined(CONFIG_LS2080A) +#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) #define CONFIG_MAX_CPUS 16 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 +#ifdef CONFIG_LS2080A #define CONFIG_NUM_DDR_CONTROLLERS 2 +#endif +#ifdef CONFIG_LS2085A +#define CONFIG_NUM_DDR_CONTROLLERS 3 +#define CONFIG_SYS_FSL_HAS_DP_DDR +#endif #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } #define SRDS_MAX_LANES 8 #define CONFIG_SYS_FSL_SRDS_1 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index 5a91dcb..2c93589 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -11,8 +11,10 @@ static struct cpu_type cpu_type_list[] = { #ifdef CONFIG_LS2080A CPU_TYPE_ENTRY(LS2080, LS2080, 8), #endif +#ifdef CONFIG_LS2085A CPU_TYPE_ENTRY(LS2085, LS2085, 8), CPU_TYPE_ENTRY(LS2045, LS2045, 4), +#endif CPU_TYPE_ENTRY(LS1043, LS1043, 4), }; @@ -182,7 +184,7 @@ static const struct sys_mmu_table final_mmu_table[] = { CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, -#ifdef CONFIG_LS2080A +#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h index 4787eec..d1fbde7 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h @@ -9,7 +9,7 @@ #include <config.h> -#if defined(CONFIG_LS2080A) +#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) enum srds_prtcl { NONE = 0, PCIE1, diff --git a/configs/ls2080a_emu_defconfig b/configs/ls2080a_emu_defconfig index ebdde04..0ab2528 100644 --- a/configs/ls2080a_emu_defconfig +++ b/configs/ls2080a_emu_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_TARGET_LS2080A_EMU=y -CONFIG_SYS_EXTRA_OPTIONS="EMU,SYS_FSL_DDR4" +CONFIG_SYS_EXTRA_OPTIONS="EMU,SYS_FSL_DDR4, LS2080A" # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_IMLS is not set # CONFIG_CMD_XIMG is not set diff --git a/configs/ls2080a_simu_defconfig b/configs/ls2080a_simu_defconfig index eb8000b..fb62962 100644 --- a/configs/ls2080a_simu_defconfig +++ b/configs/ls2080a_simu_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_TARGET_LS2080A_SIMU=y -CONFIG_SYS_EXTRA_OPTIONS="SIMU" +CONFIG_SYS_EXTRA_OPTIONS="SIMU, LS2080A" # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_IMLS is not set # CONFIG_CMD_XIMG is not set diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig index afba06b..8523dc5 100644 --- a/configs/ls2080aqds_defconfig +++ b/configs/ls2080aqds_defconfig @@ -4,7 +4,7 @@ CONFIG_TARGET_LS2080AQDS=y CONFIG_DM_SPI=y CONFIG_DM_SPI_FLASH=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds" -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A" # CONFIG_CMD_SETEXPR is not set CONFIG_OF_CONTROL=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig index 40cf883..e8e9697 100644 --- a/configs/ls2080aqds_nand_defconfig +++ b/configs/ls2080aqds_nand_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS2080AQDS=y CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND" +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, LS2080A" # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y CONFIG_NETDEVICES=y diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig index 301cd7f..35b570c 100644 --- a/configs/ls2080ardb_defconfig +++ b/configs/ls2080ardb_defconfig @@ -4,7 +4,7 @@ CONFIG_TARGET_LS2080ARDB=y CONFIG_DM_SPI=y CONFIG_DM_SPI_FLASH=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb" -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A" # CONFIG_CMD_SETEXPR is not set CONFIG_OF_CONTROL=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig index 658c9ff..dc6692f 100644 --- a/configs/ls2080ardb_nand_defconfig +++ b/configs/ls2080ardb_nand_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS2080ARDB=y CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND" +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, LS2080A" # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y CONFIG_NETDEVICES=y diff --git a/configs/ls2080a_emu_defconfig b/configs/ls2085a_emu_defconfig similarity index 87% copy from configs/ls2080a_emu_defconfig copy to configs/ls2085a_emu_defconfig index ebdde04..5f5fba9 100644 --- a/configs/ls2080a_emu_defconfig +++ b/configs/ls2085a_emu_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_TARGET_LS2080A_EMU=y -CONFIG_SYS_EXTRA_OPTIONS="EMU,SYS_FSL_DDR4" +CONFIG_SYS_EXTRA_OPTIONS="EMU,SYS_FSL_DDR4, LS2085A" # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_IMLS is not set # CONFIG_CMD_XIMG is not set diff --git a/configs/ls2080a_simu_defconfig b/configs/ls2085a_simu_defconfig similarity index 90% copy from configs/ls2080a_simu_defconfig copy to configs/ls2085a_simu_defconfig index eb8000b..d3867e5 100644 --- a/configs/ls2080a_simu_defconfig +++ b/configs/ls2085a_simu_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_TARGET_LS2080A_SIMU=y -CONFIG_SYS_EXTRA_OPTIONS="SIMU" +CONFIG_SYS_EXTRA_OPTIONS="SIMU, LS2085A" # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_IMLS is not set # CONFIG_CMD_XIMG is not set diff --git a/configs/ls2080aqds_defconfig b/configs/ls2085aqds_defconfig similarity index 86% copy from configs/ls2080aqds_defconfig copy to configs/ls2085aqds_defconfig index afba06b..b09d704 100644 --- a/configs/ls2080aqds_defconfig +++ b/configs/ls2085aqds_defconfig @@ -4,7 +4,7 @@ CONFIG_TARGET_LS2080AQDS=y CONFIG_DM_SPI=y CONFIG_DM_SPI_FLASH=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds" -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2085A" # CONFIG_CMD_SETEXPR is not set CONFIG_OF_CONTROL=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2085aqds_nand_defconfig similarity index 73% copy from configs/ls2080aqds_nand_defconfig copy to configs/ls2085aqds_nand_defconfig index 40cf883..918bec2 100644 --- a/configs/ls2080aqds_nand_defconfig +++ b/configs/ls2085aqds_nand_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS2080AQDS=y CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND" +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND,LS2085A" # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y CONFIG_NETDEVICES=y diff --git a/configs/ls2080ardb_defconfig b/configs/ls2085ardb_defconfig similarity index 86% copy from configs/ls2080ardb_defconfig copy to configs/ls2085ardb_defconfig index 301cd7f..561c412 100644 --- a/configs/ls2080ardb_defconfig +++ b/configs/ls2085ardb_defconfig @@ -4,7 +4,7 @@ CONFIG_TARGET_LS2080ARDB=y CONFIG_DM_SPI=y CONFIG_DM_SPI_FLASH=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb" -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2085A" # CONFIG_CMD_SETEXPR is not set CONFIG_OF_CONTROL=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2085ardb_nand_defconfig similarity index 73% copy from configs/ls2080ardb_nand_defconfig copy to configs/ls2085ardb_nand_defconfig index 658c9ff..fd070f9 100644 --- a/configs/ls2080ardb_nand_defconfig +++ b/configs/ls2085ardb_nand_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS2080ARDB=y CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND" +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND,LS2085A" # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y CONFIG_NETDEVICES=y diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c index eefe709..7881a20 100644 --- a/drivers/ddr/fsl/fsl_ddr_gen4.c +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c @@ -107,14 +107,14 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, goto step2; #ifdef CONFIG_SYS_FSL_ERRATUM_A008336 -#ifdef CONFIG_LS2080A +#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) /* A008336 only applies to general DDR controllers */ if ((ctrl_num == 0) || (ctrl_num == 1)) #endif ddr_out32(eddrtqcr1, 0x63b30002); #endif #ifdef CONFIG_SYS_FSL_ERRATUM_A008514 -#ifdef CONFIG_LS2080A +#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) /* A008514 only applies to DP-DDR controler */ if (ctrl_num == 2) #endif diff --git a/drivers/net/ldpaa_eth/Makefile b/drivers/net/ldpaa_eth/Makefile index 5587aa6..74c4916 100644 --- a/drivers/net/ldpaa_eth/Makefile +++ b/drivers/net/ldpaa_eth/Makefile @@ -7,3 +7,4 @@ obj-y += ldpaa_wriop.o obj-y += ldpaa_eth.o obj-$(CONFIG_LS2080A) += ls2080a.o +obj-$(CONFIG_LS2085A) += ls2080a.o diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c index 8af6531..c1e3627 100644 --- a/drivers/pci/pcie_layerscape.c +++ b/drivers/pci/pcie_layerscape.c @@ -665,7 +665,7 @@ void ft_pci_setup(void *blob, bd_t *bd) } #endif -#ifdef CONFIG_LS2080A +#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) void pcie_set_available_streamids(void *blob, const char *pcie_path, u32 *stream_ids, int count) diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index de542c2..e3f51f7 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -11,7 +11,6 @@ #define CONFIG_REMAKE_ELF #define CONFIG_FSL_LAYERSCAPE #define CONFIG_FSL_LSCH3 -#define CONFIG_LS2080A #define CONFIG_MP #define CONFIG_GICV3 #define CONFIG_FSL_TZPC_BP147 @@ -185,7 +184,7 @@ unsigned long long get_qixis_addr(void); #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 -#ifndef CONFIG_LS2080A +#ifdef CONFIG_LS2085A #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000 #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000 #endif @@ -209,7 +208,13 @@ unsigned long long get_qixis_addr(void); #define CONFIG_PCIE3 /* PCIE controler 3 */ #define CONFIG_PCIE4 /* PCIE controler 4 */ #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ +#ifdef CONFIG_LS2080A #define FSL_PCIE_COMPAT "fsl,ls2080a-pcie" +#endif + +#ifdef CONFIG_LS2085A +#define FSL_PCIE_COMPAT "fsl,ls2085a-pcie" +#endif #define CONFIG_SYS_PCI_64BIT diff --git a/include/configs/ls2080a_emu.h b/include/configs/ls2080a_emu.h index 6400f4f..4a7ba24 100644 --- a/include/configs/ls2080a_emu.h +++ b/include/configs/ls2080a_emu.h @@ -9,8 +9,15 @@ #include "ls2080a_common.h" +#ifdef CONFIG_LS2080A #define CONFIG_IDENT_STRING " LS2080A-EMU" #define CONFIG_BOOTP_VCI_STRING "U-boot.LS2080A-EMU" +#endif + +#ifdef CONFIG_LS2085A +#define CONFIG_IDENT_STRING " LS2085A-EMU" +#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2085A-EMU" +#endif #define CONFIG_SYS_CLK_FREQ 100000000 #define CONFIG_DDR_CLK_FREQ 133333333 diff --git a/include/configs/ls2080a_simu.h b/include/configs/ls2080a_simu.h index 666df80..876ee30 100644 --- a/include/configs/ls2080a_simu.h +++ b/include/configs/ls2080a_simu.h @@ -9,8 +9,15 @@ #include "ls2080a_common.h" +#ifdef CONFIG_LS2080A #define CONFIG_IDENT_STRING " LS2080A-SIMU" #define CONFIG_BOOTP_VCI_STRING "U-boot.LS2080A-SIMU" +#endif + +#ifdef CONFIG_LS2085A +#define CONFIG_IDENT_STRING " LS2085A-SIMU" +#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2085A-SIMU" +#endif #define CONFIG_SYS_CLK_FREQ 100000000 #define CONFIG_DDR_CLK_FREQ 133333333 diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h index 80b7718..f665bf1 100644 --- a/include/linux/usb/xhci-fsl.h +++ b/include/linux/usb/xhci-fsl.h @@ -54,7 +54,7 @@ struct fsl_xhci { #if defined(CONFIG_LS102XA) #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS102XA_XHCI_USB1_ADDR #define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0 -#elif defined(CONFIG_LS2080A) +#elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS2080A_XHCI_USB1_ADDR #define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS2080A_XHCI_USB2_ADDR #endif -- 1.9.1

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