October 2015 - U-Boot

[U-Boot] [PATCH 0/6] x86: pci: Various bug fixes/enhancements
by Bin Meng 18 Oct '15

18 Oct '15

This series contains various bug fixes/enhancements to x86 pci related VGA card support, as a result of attempting to support booting SeaBIOS. Bin Meng (6): pci: Set PCI_COMMAND_IO bit for VGA device video: vesa_fb: Fix wrong return value check of pci_find_class() dm: pci: Fix pci_last_busno() to return the real last bus no dm: pci: Enable VGA address forwarding on bridges x86: ivybridge: Remove the dead codes that programs pci bridge x86: Allow disabling IGD on Intel Queensbay arch/x86/cpu/ivybridge/bd82x6x.c | 32 ----------------------- arch/x86/cpu/queensbay/Kconfig | 8 ++++++ arch/x86/cpu/queensbay/tnc.c | 19 ++++++++++++++ arch/x86/include/asm/arch-queensbay/tnc.h | 5 ++++ drivers/pci/pci-uclass.c | 43 ++++++++++++++----------------- drivers/pci/pci_auto.c | 6 +++++ drivers/video/vesa_fb.c | 2 +- include/configs/crownbay.h | 1 + 8 files changed, 59 insertions(+), 57 deletions(-) -- 1.8.2.1

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[U-Boot] [PATCH 0/5] sbc8641d: misc fixes and generic board enablement
by Paul Gortmaker 18 Oct '15

18 Oct '15

The sbc8641d is not really a state of the art board anymore, but it does have the distinctive feature of being one of the relatively few SMP powerpc boards around. Combined with its small form factor, it remains a useful testing platform. So here we enable the generic board support so that it can remain in tree. One note worthy of mention is that the same commit that breaks[1] the sbc8548 board [commit 294b91a58171 ("Set up stdio earlier when using driver model")] also breaks this board in the identical way (hangs at "Net:" line during bootup). So the baseline for run time testing was one commit prior to that commit that introduced the regressions. The fixes are all board specific and a branch off 294b91a58171~ will merge seamlessly to master, or they can be applied to master; whenever the regressions of 294b91a58171 are resolved then things will work again on the tip of tree. [1] https://www.marc.info/?l=u-boot&m=142655649417364&w=3 Paul Gortmaker (5): sbc8641d: enable command line editing sbc8641d: increase malloc pool size to a sane default sbc8641d: set proper environment sector size. sbc8641d: add basic flash setup instructions to README file sbc8641d: enable and test CONFIG_SYS_GENERIC_BOARD board/sbc8641d/README | 21 +++++++++++++++++++++ include/configs/sbc8641d.h | 7 +++++-- 2 files changed, 26 insertions(+), 2 deletions(-) -- 2.1.0

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[U-Boot] [PATCH 00/10] x86: Early debug enhancements
by Simon Glass 18 Oct '15

18 Oct '15

This series adds a few more features to the debug UART, making it possible to use it even when the board needs to perform additional init for the UART to work. The debug UART is anabled on link. Some minor PCI tidy-ups are also included. Link currently does not boot due to lack of early malloc() memory. For now just increase the size. Simon Glass (10): x86: chromebook_link: Expand early malloc() memory malloc_simple: Add debug() information dm: pci: Tidy up auto-config error handling dm: pci: Correct a few debug() statements dm: pci: Adjust pci_find_and_bind_driver() to return -EPERM debug_uart: Adjust the declaration of debug_uart_init() debug_uart: Support board-specific UART initialisation debug_uart: Add an option to announce the debug UART x86: Init the debug UART if enabled x86: chromebook_link: Enable the debug UART arch/x86/cpu/ivybridge/cpu.c | 7 ++++++ arch/x86/cpu/start.S | 3 +++ common/malloc_simple.c | 4 ++++ configs/chromebook_link_defconfig | 11 ++++++--- drivers/pci/pci-uclass.c | 50 ++++++++++++++++++++++++++------------- drivers/serial/Kconfig | 21 ++++++++++++++++ drivers/serial/ns16550.c | 2 +- drivers/serial/serial_efi.c | 2 +- drivers/serial/serial_s5p.c | 2 +- include/debug_uart.h | 30 +++++++++++++++++++++-- lib/efi/efi_stub.c | 2 +- 11 files changed, 108 insertions(+), 26 deletions(-) -- 2.6.0.rc0.131.gf624c3d

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[U-Boot] [PATCH v4 8/8] Revert "ARM: zynq: disable CONFIG_SYS_MALLOC_F to fix MMC boot"
by Simon Glass 18 Oct '15

18 Oct '15

This reverts commit 321f86e18d6aae9f7b7ba3ef1eb0cec769481874. The original bug has been fixed. Signed-off-by: Simon Glass <sjg(a)chromium.org> Tested-on: Zedboard and ZC706 board Tested-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> Tested-on: zc702 Tested-by: Michal Simek <michal.simek(a)xilinx.com> --- Changes in v4: - Fully revert the commit (some changes were lost in v3) Changes in v3: - Rebase to master Changes in v2: None configs/zynq_microzed_defconfig | 1 - configs/zynq_zc702_defconfig | 1 - configs/zynq_zc706_defconfig | 1 - configs/zynq_zc70x_defconfig | 1 - configs/zynq_zc770_xm010_defconfig | 1 - configs/zynq_zc770_xm011_defconfig | 1 - configs/zynq_zc770_xm012_defconfig | 1 - configs/zynq_zc770_xm013_defconfig | 1 - configs/zynq_zed_defconfig | 1 - configs/zynq_zybo_defconfig | 1 - 10 files changed, 10 deletions(-) diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig index a6757ac..e9c3209 100644 --- a/configs/zynq_microzed_defconfig +++ b/configs/zynq_microzed_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_ZYNQ=y -# CONFIG_SYS_MALLOC_F is not set CONFIG_TARGET_ZYNQ_MICROZED=y CONFIG_DEFAULT_DEVICE_TREE="zynq-microzed" CONFIG_SPL=y diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig index 8a388f3..0abb7a8 100644 --- a/configs/zynq_zc702_defconfig +++ b/configs/zynq_zc702_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_ZYNQ=y -# CONFIG_SYS_MALLOC_F is not set CONFIG_DEFAULT_DEVICE_TREE="zynq-zc702" CONFIG_SPL=y CONFIG_FIT=y diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig index f1009ee..d67f507 100644 --- a/configs/zynq_zc706_defconfig +++ b/configs/zynq_zc706_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_ZYNQ=y -# CONFIG_SYS_MALLOC_F is not set CONFIG_TARGET_ZYNQ_ZC706=y CONFIG_DEFAULT_DEVICE_TREE="zynq-zc706" CONFIG_SPL=y diff --git a/configs/zynq_zc70x_defconfig b/configs/zynq_zc70x_defconfig index 6465040..37c249f 100644 --- a/configs/zynq_zc70x_defconfig +++ b/configs/zynq_zc70x_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_ZYNQ=y -# CONFIG_SYS_MALLOC_F is not set CONFIG_TARGET_ZYNQ_ZC70X=y CONFIG_DEFAULT_DEVICE_TREE="zynq-zc702" CONFIG_SPL=y diff --git a/configs/zynq_zc770_xm010_defconfig b/configs/zynq_zc770_xm010_defconfig index cafbb09..0e826bb 100644 --- a/configs/zynq_zc770_xm010_defconfig +++ b/configs/zynq_zc770_xm010_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_ZYNQ=y -# CONFIG_SYS_MALLOC_F is not set CONFIG_TARGET_ZYNQ_ZC770=y CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm010" CONFIG_SPL=y diff --git a/configs/zynq_zc770_xm011_defconfig b/configs/zynq_zc770_xm011_defconfig index e6e1c30..46d043b 100644 --- a/configs/zynq_zc770_xm011_defconfig +++ b/configs/zynq_zc770_xm011_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_ZYNQ=y -# CONFIG_SYS_MALLOC_F is not set CONFIG_TARGET_ZYNQ_ZC770=y CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm011" CONFIG_SPL=y diff --git a/configs/zynq_zc770_xm012_defconfig b/configs/zynq_zc770_xm012_defconfig index 9a44009..34d479f 100644 --- a/configs/zynq_zc770_xm012_defconfig +++ b/configs/zynq_zc770_xm012_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_ZYNQ=y -# CONFIG_SYS_MALLOC_F is not set CONFIG_TARGET_ZYNQ_ZC770=y CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm012" CONFIG_SPL=y diff --git a/configs/zynq_zc770_xm013_defconfig b/configs/zynq_zc770_xm013_defconfig index 95e32a5..c59599f 100644 --- a/configs/zynq_zc770_xm013_defconfig +++ b/configs/zynq_zc770_xm013_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_ZYNQ=y -# CONFIG_SYS_MALLOC_F is not set CONFIG_TARGET_ZYNQ_ZC770=y CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm013" CONFIG_SPL=y diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig index 43520d0..886b4a5 100644 --- a/configs/zynq_zed_defconfig +++ b/configs/zynq_zed_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_ZYNQ=y -# CONFIG_SYS_MALLOC_F is not set CONFIG_TARGET_ZYNQ_ZED=y CONFIG_DEFAULT_DEVICE_TREE="zynq-zed" CONFIG_SPL=y diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig index 46379e5..77b9409 100644 --- a/configs/zynq_zybo_defconfig +++ b/configs/zynq_zybo_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_ZYNQ=y -# CONFIG_SYS_MALLOC_F is not set CONFIG_TARGET_ZYNQ_ZYBO=y CONFIG_DEFAULT_DEVICE_TREE="zynq-zybo" CONFIG_SPL=y -- 2.6.0.rc2.230.g3dd15c0

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[U-Boot] [PATCH v5 1/5] lib, fdt: Adding fdtdec_get_uint function
by Chin Liang See 17 Oct '15

17 Oct '15

Adding fdtdec_get_uint function which is the unsigned version for fdtdec_get_int Signed-off-by: Chin Liang See <clsee(a)altera.com> Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> Cc: Dinh Nguyen <dinh.linux(a)gmail.com> Cc: Marek Vasut <marex(a)denx.de> Cc: Stefan Roese <sr(a)denx.de> Cc: Vikas Manocha <vikas.manocha(a)st.com> Cc: Jagannadh Teki <jteki(a)openedev.com> Cc: Pavel Machek <pavel(a)denx.de> Cc: Heiko Schocher <hs(a)denx.de> --- Changes for v5 - shuffling the patches - fixed the commit message Changes for v4 - Drop idea on enabling fdt_support in SPL build --- include/fdtdec.h | 13 +++++++++++++ lib/fdtdec_common.c | 18 ++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/include/fdtdec.h b/include/fdtdec.h index 2de6dda..d51e643 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -490,6 +490,19 @@ s32 fdtdec_get_int(const void *blob, int node, const char *prop_name, s32 default_val); /** + * Unsigned version of fdtdec_get_int. The property must have at least + * 4 bytes of data. The value of the first cell is returned. + * + * @param blob FDT blob + * @param node node to examine + * @param prop_name name of property to find + * @param default_val default value to return if the property is not found + * @return unsigned integer value, if found, or default_val if not + */ +unsigned int fdtdec_get_uint(const void *blob, int node, const char *prop_name, + unsigned int default_val); + +/** * Get a variable-sized number from a property * * This reads a number from one or more cells. diff --git a/lib/fdtdec_common.c b/lib/fdtdec_common.c index 757931a..63b704a 100644 --- a/lib/fdtdec_common.c +++ b/lib/fdtdec_common.c @@ -36,3 +36,21 @@ int fdtdec_get_int(const void *blob, int node, const char *prop_name, debug("(not found)\n"); return default_val; } + +unsigned int fdtdec_get_uint(const void *blob, int node, const char *prop_name, + unsigned int default_val) +{ + const int *cell; + int len; + + debug("%s: %s: ", __func__, prop_name); + cell = fdt_getprop(blob, node, prop_name, &len); + if (cell && len >= sizeof(unsigned int)) { + unsigned int val = fdt32_to_cpu(cell[0]); + + debug("%#x (%d)\n", val, val); + return val; + } + debug("(not found)\n"); + return default_val; +} -- 2.2.0

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[U-Boot] [PATCH v2 0/7] ARM: sunxi: Introduce CHIP support
by Maxime Ripard 17 Oct '15

17 Oct '15

Hi, Here is a serie introducing the support for the Allwinner R8 and the Nextthing's CHIP. The only missing parts for now are the display on the composite output and the NAND support that will come in due time. Everything else should work just fine, including the USB gadget and host support. Let me know what you think, Maxime Changes from v1: - Rebased on top of current sunxi next branch - Added regulators voltage - Synced the DTS with what has been accepted in the kernel - Added CONFIG_MMC rework Maxime Ripard (7): fastboot: Implement OEM format only when we have MMC support mmc: Add generic Kconfig option sunxi: board: Only try to use the MMC related functions if enabled sunxi: Use Kconfig CONFIG_MMC sun5i: Sync the DTSI with the kernel axp209: Sync the DTSI with the kernel sunxi: Add CHIP support arch/arm/cpu/armv7/sunxi/board.c | 6 +- arch/arm/dts/Makefile | 3 +- arch/arm/dts/axp209.dtsi | 5 + arch/arm/dts/sun5i-a10s.dtsi | 47 +++++++-- arch/arm/dts/sun5i-a13.dtsi | 28 ++++- arch/arm/dts/sun5i-r8-chip.dts | 214 +++++++++++++++++++++++++++++++++++++++ arch/arm/dts/sun5i-r8.dtsi | 59 +++++++++++ arch/arm/dts/sun5i.dtsi | 22 ++++ board/sunxi/Kconfig | 4 + configs/CHIP_defconfig | 14 +++ drivers/mmc/Kconfig | 6 ++ drivers/usb/gadget/f_fastboot.c | 2 +- include/configs/sunxi-common.h | 8 +- 13 files changed, 402 insertions(+), 16 deletions(-) create mode 100644 arch/arm/dts/sun5i-r8-chip.dts create mode 100644 arch/arm/dts/sun5i-r8.dtsi create mode 100644 configs/CHIP_defconfig -- 2.5.3

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[U-Boot] [PATCH v4 5/5] lib, fdt: Adding fdtdec_get_u32 function
by Chin Liang See 17 Oct '15

17 Oct '15

>From 3b86e60182b87a96f2e5e2236df7a877c9a8c468 Mon Sep 17 00:00:00 2001 From: Chin Liang See <clsee(a)altera.com> Date: Thu, 15 Oct 2015 14:04:39 +0800 Subject: [PATCH v4 5/5] lib, fdt: Adding fdtdec_get_u32 function Adding fdtdec_get_u32 function which is the unsigned version for fdtdec_get_int Signed-off-by: Chin Liang See <clsee(a)altera.com> Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> Cc: Dinh Nguyen <dinh.linux(a)gmail.com> Cc: Marek Vasut <marex(a)denx.de> Cc: Stefan Roese <sr(a)denx.de> Cc: Vikas Manocha <vikas.manocha(a)st.com> Cc: Jagannadh Teki <jteki(a)openedev.com> Cc: Pavel Machek <pavel(a)denx.de> Cc: Heiko Schocher <hs(a)denx.de> --- Changes for v4 - Drop idea on enabling fdt_support in SPL build --- include/fdtdec.h | 13 +++++++++++++ lib/fdtdec_common.c | 18 ++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/include/fdtdec.h b/include/fdtdec.h index 2de6dda..d51e643 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -490,6 +490,19 @@ s32 fdtdec_get_int(const void *blob, int node, const char *prop_name, s32 default_val); /** + * Unsigned version of fdtdec_get_int. The property must have at least + * 4 bytes of data. The value of the first cell is returned. + * + * @param blob FDT blob + * @param node node to examine + * @param prop_name name of property to find + * @param default_val default value to return if the property is not found + * @return unsigned integer value, if found, or default_val if not + */ +unsigned int fdtdec_get_uint(const void *blob, int node, const char *prop_name, + unsigned int default_val); + +/** * Get a variable-sized number from a property * * This reads a number from one or more cells. diff --git a/lib/fdtdec_common.c b/lib/fdtdec_common.c index 757931a..63b704a 100644 --- a/lib/fdtdec_common.c +++ b/lib/fdtdec_common.c @@ -36,3 +36,21 @@ int fdtdec_get_int(const void *blob, int node, const char *prop_name, debug("(not found)\n"); return default_val; } + +unsigned int fdtdec_get_uint(const void *blob, int node, const char *prop_name, + unsigned int default_val) +{ + const int *cell; + int len; + + debug("%s: %s: ", __func__, prop_name); + cell = fdt_getprop(blob, node, prop_name, &len); + if (cell && len >= sizeof(unsigned int)) { + unsigned int val = fdt32_to_cpu(cell[0]); + + debug("%#x (%d)\n", val, val); + return val; + } + debug("(not found)\n"); + return default_val; +} -- 2.2.0

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[U-Boot] [PATCH v5 5/5] arm: dts: socfpga: Increase the spi-max-frequency for QSPI flash
by Chin Liang See 17 Oct '15

17 Oct '15

With a working QSPI calibration, the SCLK can now run up to 100MHz Signed-off-by: Chin Liang See <clsee(a)altera.com> Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> Cc: Dinh Nguyen <dinh.linux(a)gmail.com> Cc: Marek Vasut <marex(a)denx.de> Cc: Stefan Roese <sr(a)denx.de> Cc: Vikas Manocha <vikas.manocha(a)st.com> Cc: Jagannadh Teki <jteki(a)openedev.com> Cc: Pavel Machek <pavel(a)denx.de> Reviewed-by: Marek Vasut <marex(a)denx.de> Acked-by: Marek Vasut <marex(a)denx.de> Reviewed-by: Jagan Teki <jteki(a)openedev.com> --- Changes for v5 - shuffling the patches Changes for v4 - no changes Changes for v3 - no changes Changes for v2 - no changes --- arch/arm/dts/socfpga_cyclone5_socdk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts b/arch/arm/dts/socfpga_cyclone5_socdk.dts index 5465609..9eb5a22 100644 --- a/arch/arm/dts/socfpga_cyclone5_socdk.dts +++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts @@ -89,7 +89,7 @@ #size-cells = <1>; compatible = "n25q00"; reg = <0>; /* chip select */ - spi-max-frequency = <50000000>; + spi-max-frequency = <100000000>; m25p,fast-read; page-size = <256>; block-size = <16>; /* 2^16, 64KB */ -- 2.2.0

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[U-Boot] [PATCH v5 3/5] spi: cadence_qspi: Fix fdt read of spi-max-frequency
by Chin Liang See 17 Oct '15

17 Oct '15

Fix the fdt read for spi-max-frequency as it's contained in the child node. Current state of code is always returning default value. Signed-off-by: Chin Liang See <clsee(a)altera.com> Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> Cc: Dinh Nguyen <dinh.linux(a)gmail.com> Cc: Marek Vasut <marex(a)denx.de> Cc: Stefan Roese <sr(a)denx.de> Cc: Vikas Manocha <vikas.manocha(a)st.com> Cc: Jagannadh Teki <jteki(a)openedev.com> Cc: Pavel Machek <pavel(a)denx.de> Acked-by: Marek Vasut <marex(a)denx.de> Acked-by: Pavel Machek <pavel(a)denx.de> --- Changes for v5 - shuffling the patches Changes for v4 - use the newly created fdtdec_get_uint Changes for v3 - Use of fdt_getprop_u32_default_node instead casting Changes for v2 - Add unsigned casting for plat->max_hz --- drivers/spi/cadence_qspi.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index c5a4276..5756178 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -295,10 +295,6 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus) plat->regbase = (void *)data[0]; plat->ahbbase = (void *)data[2]; - /* Use 500KHz as a suitable default */ - plat->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", - 500000); - /* All other paramters are embedded in the child node */ subnode = fdt_first_subnode(blob, node); if (subnode < 0) { @@ -306,6 +302,10 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus) return -ENODEV; } + /* Use 500 KHz as a suitable default */ + plat->max_hz = fdtdec_get_uint(blob, subnode, "spi-max-frequency", + 500000); + /* Read other parameters from DT */ plat->page_size = fdtdec_get_int(blob, subnode, "page-size", 256); plat->block_size = fdtdec_get_int(blob, subnode, "block-size", 16); -- 2.2.0

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[U-Boot] [PATCH v5 2/5] spi: cadence_qspi: Ensure spi_calibration is run when sclk change
by Chin Liang See 17 Oct '15

17 Oct '15

Ensuring spi_calibration is run when there is a change of sclk frequency. This will ensure the qspi flash access works for high sclk frequency Signed-off-by: Chin Liang See <clsee(a)altera.com> Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> Cc: Dinh Nguyen <dinh.linux(a)gmail.com> Cc: Marek Vasut <marex(a)denx.de> Cc: Stefan Roese <sr(a)denx.de> Cc: Vikas Manocha <vikas.manocha(a)st.com> Cc: Jagannadh Teki <jteki(a)openedev.com> Cc: Pavel Machek <pavel(a)denx.de> Acked-by: Marek Vasut <marex(a)denx.de> Reviewed-by: Jagan Teki <jteki(a)openedev.com> --- Changes for v5 - shuffling the patches Changes for v4 - shift the checking for requested SCLK to the caller Changes for v3 - no changes Changes for v2 - remove frequency set before calibration - introducing previous_hz to store requested frequency - prevent calibration run when request same frequency --- drivers/spi/cadence_qspi.c | 22 +++++++++++++--------- drivers/spi/cadence_qspi.h | 1 + 2 files changed, 14 insertions(+), 9 deletions(-) diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 34a0f46..c5a4276 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -37,9 +37,8 @@ static int cadence_spi_write_speed(struct udevice *bus, uint hz) } /* Calibration sequence to determine the read data capture delay register */ -static int spi_calibration(struct udevice *bus) +static int spi_calibration(struct udevice *bus, uint hz) { - struct cadence_spi_platdata *plat = bus->platdata; struct cadence_spi_priv *priv = dev_get_priv(bus); void *base = priv->regbase; u8 opcode_rdid = 0x9F; @@ -64,7 +63,7 @@ static int spi_calibration(struct udevice *bus) } /* use back the intended clock and find low range */ - cadence_spi_write_speed(bus, plat->max_hz); + cadence_spi_write_speed(bus, hz); for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) { /* Disable QSPI */ cadence_qspi_apb_controller_disable(base); @@ -111,7 +110,7 @@ static int spi_calibration(struct udevice *bus) (range_hi + range_lo) / 2, range_lo, range_hi); /* just to ensure we do once only when speed or chip select change */ - priv->qspi_calibrated_hz = plat->max_hz; + priv->qspi_calibrated_hz = hz; priv->qspi_calibrated_cs = spi_chip_select(bus); return 0; @@ -126,14 +125,19 @@ static int cadence_spi_set_speed(struct udevice *bus, uint hz) /* Disable QSPI */ cadence_qspi_apb_controller_disable(priv->regbase); - cadence_spi_write_speed(bus, hz); - - /* Calibration required for different SCLK speed or chip select */ - if (priv->qspi_calibrated_hz != plat->max_hz || + /* + * Calibration required for different current SCLK speed, requested + * SCLK speed or chip select + */ + if (priv->previous_hz != hz || + priv->qspi_calibrated_hz != hz || priv->qspi_calibrated_cs != spi_chip_select(bus)) { - err = spi_calibration(bus); + err = spi_calibration(bus, hz); if (err) return err; + + /* prevent calibration run when same as previous request */ + priv->previous_hz = hz; } /* Enable QSPI */ diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index 98e57aa..2912e36 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -38,6 +38,7 @@ struct cadence_spi_priv { int qspi_is_init; unsigned int qspi_calibrated_hz; unsigned int qspi_calibrated_cs; + unsigned int previous_hz; }; /* Functions call declaration */ -- 2.2.0

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