October 2015 - U-Boot

[U-Boot] [PATCH v2] Tegra: T210: Add QSPI driver
by Tom Warren 19 Oct '15

19 Oct '15

This is the normal Tegra SPI driver modified to work with the QSPI controller in Tegra210. It does not do 2x/4x transfers or any other QSPI protocol. Author: Yen Lin <yelin(a)nvidia.com> Signed-off-by: Yen Lin <yelin(a)nvidia.com> Signed-off-by: Tom Warren <twarren(a)nvidia.com> --- Changes in v2: - Drop defconfig and pinmux files, this is a driver-only patch. - When pinmux tables have been updated for P2371/P2571, another - patch will be sent to enable the QSPI driver on those boards. drivers/spi/Kconfig | 5 + drivers/spi/Makefile | 1 + drivers/spi/tegra210_qspi.c | 411 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 417 insertions(+) create mode 100644 drivers/spi/tegra210_qspi.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 8e04fce..168f31d 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -115,6 +115,11 @@ config TEGRA20_SLINK be used to access the SPI NOR flash on platforms embedding this nVidia Tegra20/Tegra30 IP cores. +config TEGRA210_QSPI + bool "nVidia Tegra210 QSPI driver" + help + Enable the Tegra Quad-SPI (QSPI) driver for T210. + config XILINX_SPI bool "Xilinx SPI driver" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index de241be..209a41e 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -46,6 +46,7 @@ obj-$(CONFIG_SH_QSPI) += sh_qspi.o obj-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o obj-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o obj-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o +obj-$(CONFIG_TEGRA210_QSPI) += tegra210_qspi.o obj-$(CONFIG_TI_QSPI) += ti_qspi.o obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o obj-$(CONFIG_ZYNQ_SPI) += zynq_spi.o diff --git a/drivers/spi/tegra210_qspi.c b/drivers/spi/tegra210_qspi.c new file mode 100644 index 0000000..876034d --- /dev/null +++ b/drivers/spi/tegra210_qspi.c @@ -0,0 +1,411 @@ +/* + * NVIDIA Tegra210 QSPI controller driver + * (C) Copyright 2015 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch-tegra/clk_rst.h> +#include <spi.h> +#include <fdtdec.h> +#include "tegra_spi.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* COMMAND1 */ +#define QSPI_CMD1_GO (1 << 31) +#define QSPI_CMD1_M_S (1 << 30) +#define QSPI_CMD1_MODE_MASK 0x3 +#define QSPI_CMD1_MODE_SHIFT 28 +#define QSPI_CMD1_CS_SEL_MASK 0x3 +#define QSPI_CMD1_CS_SEL_SHIFT 26 +#define QSPI_CMD1_CS_POL_INACTIVE0 (1 << 22) +#define QSPI_CMD1_CS_SW_HW (1 << 21) +#define QSPI_CMD1_CS_SW_VAL (1 << 20) +#define QSPI_CMD1_IDLE_SDA_MASK 0x3 +#define QSPI_CMD1_IDLE_SDA_SHIFT 18 +#define QSPI_CMD1_BIDIR (1 << 17) +#define QSPI_CMD1_LSBI_FE (1 << 16) +#define QSPI_CMD1_LSBY_FE (1 << 15) +#define QSPI_CMD1_BOTH_EN_BIT (1 << 14) +#define QSPI_CMD1_BOTH_EN_BYTE (1 << 13) +#define QSPI_CMD1_RX_EN (1 << 12) +#define QSPI_CMD1_TX_EN (1 << 11) +#define QSPI_CMD1_PACKED (1 << 5) +#define QSPI_CMD1_BITLEN_MASK 0x1F +#define QSPI_CMD1_BITLEN_SHIFT 0 + +/* COMMAND2 */ +#define QSPI_CMD2_TX_CLK_TAP_DELAY (1 << 6) +#define QSPI_CMD2_TX_CLK_TAP_DELAY_MASK (0x3F << 6) +#define QSPI_CMD2_RX_CLK_TAP_DELAY (1 << 0) +#define QSPI_CMD2_RX_CLK_TAP_DELAY_MASK (0x3F << 0) + +/* TRANSFER STATUS */ +#define QSPI_XFER_STS_RDY (1 << 30) + +/* FIFO STATUS */ +#define QSPI_FIFO_STS_CS_INACTIVE (1 << 31) +#define QSPI_FIFO_STS_FRAME_END (1 << 30) +#define QSPI_FIFO_STS_RX_FIFO_FLUSH (1 << 15) +#define QSPI_FIFO_STS_TX_FIFO_FLUSH (1 << 14) +#define QSPI_FIFO_STS_ERR (1 << 8) +#define QSPI_FIFO_STS_TX_FIFO_OVF (1 << 7) +#define QSPI_FIFO_STS_TX_FIFO_UNR (1 << 6) +#define QSPI_FIFO_STS_RX_FIFO_OVF (1 << 5) +#define QSPI_FIFO_STS_RX_FIFO_UNR (1 << 4) +#define QSPI_FIFO_STS_TX_FIFO_FULL (1 << 3) +#define QSPI_FIFO_STS_TX_FIFO_EMPTY (1 << 2) +#define QSPI_FIFO_STS_RX_FIFO_FULL (1 << 1) +#define QSPI_FIFO_STS_RX_FIFO_EMPTY (1 << 0) + +#define QSPI_TIMEOUT 1000 + +struct qspi_regs { + u32 command1; /* 000:QSPI_COMMAND1 register */ + u32 command2; /* 004:QSPI_COMMAND2 register */ + u32 timing1; /* 008:QSPI_CS_TIM1 register */ + u32 timing2; /* 00c:QSPI_CS_TIM2 register */ + u32 xfer_status;/* 010:QSPI_TRANS_STATUS register */ + u32 fifo_status;/* 014:QSPI_FIFO_STATUS register */ + u32 tx_data; /* 018:QSPI_TX_DATA register */ + u32 rx_data; /* 01c:QSPI_RX_DATA register */ + u32 dma_ctl; /* 020:QSPI_DMA_CTL register */ + u32 dma_blk; /* 024:QSPI_DMA_BLK register */ + u32 rsvd[56]; /* 028-107 reserved */ + u32 tx_fifo; /* 108:QSPI_FIFO1 register */ + u32 rsvd2[31]; /* 10c-187 reserved */ + u32 rx_fifo; /* 188:QSPI_FIFO2 register */ + u32 spare_ctl; /* 18c:QSPI_SPARE_CTRL register */ +}; + +struct tegra210_qspi_priv { + struct qspi_regs *regs; + unsigned int freq; + unsigned int mode; + int periph_id; + int valid; + int last_transaction_us; +}; + +static int tegra210_qspi_ofdata_to_platdata(struct udevice *bus) +{ + struct tegra_spi_platdata *plat = bus->platdata; + const void *blob = gd->fdt_blob; + int node = bus->of_offset; + + plat->base = dev_get_addr(bus); + plat->periph_id = clock_decode_periph_id(blob, node); + + if (plat->periph_id == PERIPH_ID_NONE) { + debug("%s: could not decode periph id %d\n", __func__, + plat->periph_id); + return -FDT_ERR_NOTFOUND; + } + + /* Use 500KHz as a suitable default */ + plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", + 500000); + plat->deactivate_delay_us = fdtdec_get_int(blob, node, + "spi-deactivate-delay", 0); + debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n", + __func__, plat->base, plat->periph_id, plat->frequency, + plat->deactivate_delay_us); + + return 0; +} + +static int tegra210_qspi_probe(struct udevice *bus) +{ + struct tegra_spi_platdata *plat = dev_get_platdata(bus); + struct tegra210_qspi_priv *priv = dev_get_priv(bus); + + priv->regs = (struct qspi_regs *)plat->base; + + priv->last_transaction_us = timer_get_us(); + priv->freq = plat->frequency; + priv->periph_id = plat->periph_id; + + return 0; +} + +static int tegra210_qspi_claim_bus(struct udevice *bus) +{ + struct tegra210_qspi_priv *priv = dev_get_priv(bus); + struct qspi_regs *regs = priv->regs; + + /* Change SPI clock to correct frequency, PLLP_OUT0 source */ + clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq); + + /* Clear stale status here */ + setbits_le32(&regs->fifo_status, + QSPI_FIFO_STS_ERR | + QSPI_FIFO_STS_TX_FIFO_OVF | + QSPI_FIFO_STS_TX_FIFO_UNR | + QSPI_FIFO_STS_RX_FIFO_OVF | + QSPI_FIFO_STS_RX_FIFO_UNR | + QSPI_FIFO_STS_TX_FIFO_FULL | + QSPI_FIFO_STS_TX_FIFO_EMPTY | + QSPI_FIFO_STS_RX_FIFO_FULL | + QSPI_FIFO_STS_RX_FIFO_EMPTY); + debug("%s: FIFO STATUS = %08x\n", __func__, readl(&regs->fifo_status)); + + /* Set master mode and sw controlled CS */ + setbits_le32(&regs->command1, QSPI_CMD1_M_S | QSPI_CMD1_CS_SW_HW | + (priv->mode << QSPI_CMD1_MODE_SHIFT)); + debug("%s: COMMAND1 = %08x\n", __func__, readl(&regs->command1)); + + return 0; +} + +/** + * Activate the CS by driving it LOW + * + * @param slave Pointer to spi_slave to which controller has to + * communicate with + */ +static void spi_cs_activate(struct udevice *dev) +{ + struct udevice *bus = dev->parent; + struct tegra_spi_platdata *pdata = dev_get_platdata(bus); + struct tegra210_qspi_priv *priv = dev_get_priv(bus); + + /* If it's too soon to do another transaction, wait */ + if (pdata->deactivate_delay_us && + priv->last_transaction_us) { + ulong delay_us; /* The delay completed so far */ + delay_us = timer_get_us() - priv->last_transaction_us; + if (delay_us < pdata->deactivate_delay_us) + udelay(pdata->deactivate_delay_us - delay_us); + } + + clrbits_le32(&priv->regs->command1, QSPI_CMD1_CS_SW_VAL); +} + +/** + * Deactivate the CS by driving it HIGH + * + * @param slave Pointer to spi_slave to which controller has to + * communicate with + */ +static void spi_cs_deactivate(struct udevice *dev) +{ + struct udevice *bus = dev->parent; + struct tegra_spi_platdata *pdata = dev_get_platdata(bus); + struct tegra210_qspi_priv *priv = dev_get_priv(bus); + + setbits_le32(&priv->regs->command1, QSPI_CMD1_CS_SW_VAL); + + /* Remember time of this transaction so we can honour the bus delay */ + if (pdata->deactivate_delay_us) + priv->last_transaction_us = timer_get_us(); + + debug("Deactivate CS, bus '%s'\n", bus->name); +} + +static int tegra210_qspi_xfer(struct udevice *dev, unsigned int bitlen, + const void *data_out, void *data_in, + unsigned long flags) +{ + struct udevice *bus = dev->parent; + struct tegra210_qspi_priv *priv = dev_get_priv(bus); + struct qspi_regs *regs = priv->regs; + u32 reg, tmpdout, tmpdin = 0; + const u8 *dout = data_out; + u8 *din = data_in; + int num_bytes; + int ret; + + debug("%s: slave %u:%u dout %p din %p bitlen %u\n", + __func__, bus->seq, spi_chip_select(dev), dout, din, bitlen); + if (bitlen % 8) + return -1; + num_bytes = bitlen / 8; + + ret = 0; + + /* clear all error status bits */ + reg = readl(&regs->fifo_status); + writel(reg, &regs->fifo_status); + + /* flush RX/TX FIFOs */ + setbits_le32(&regs->fifo_status, + (QSPI_FIFO_STS_RX_FIFO_FLUSH | + QSPI_FIFO_STS_TX_FIFO_FLUSH)); + while ((readl(&regs->fifo_status) & + (QSPI_FIFO_STS_RX_FIFO_FLUSH | + QSPI_FIFO_STS_TX_FIFO_FLUSH))) + ; + + /* + * Notes: + * 1. don't set LSBY_FE, so no need to swap bytes from/to TX/RX FIFOs; + * 2. don't set RX_EN and TX_EN yet. + * (SW needs to make sure that while programming the blk_size, + * tx_en and rx_en bits must be zero) + * [TODO] I (Yen Lin) have problems when both RX/TX EN bits are set + * i.e., both dout and din are not NULL. + */ + clrsetbits_le32(&regs->command1, + (QSPI_CMD1_LSBI_FE | QSPI_CMD1_LSBY_FE | + QSPI_CMD1_RX_EN | QSPI_CMD1_TX_EN), + (spi_chip_select(dev) << QSPI_CMD1_CS_SEL_SHIFT)); + + /* set xfer size to 1 block (32 bits) */ + writel(0, &regs->dma_blk); + + if (flags & SPI_XFER_BEGIN) + spi_cs_activate(dev); + + /* handle data in 32-bit chunks */ + while (num_bytes > 0) { + int bytes; + int tm; + + tmpdout = 0; + bytes = (num_bytes > 4) ? 4 : num_bytes; + + if (dout != NULL) { + memcpy((void *)&tmpdout, (void *)dout, bytes); + dout += bytes; + num_bytes -= bytes; + writel(tmpdout, &regs->tx_fifo); + setbits_le32(&regs->command1, QSPI_CMD1_TX_EN); + } + + if (din != NULL) + setbits_le32(&regs->command1, QSPI_CMD1_RX_EN); + + /* clear ready bit */ + setbits_le32(&regs->xfer_status, QSPI_XFER_STS_RDY); + + clrsetbits_le32(&regs->command1, + QSPI_CMD1_BITLEN_MASK << QSPI_CMD1_BITLEN_SHIFT, + (bytes * 8 - 1) << QSPI_CMD1_BITLEN_SHIFT); + /* Need to stabilize other reg bit before GO bit set */ + udelay(2); + setbits_le32(&regs->command1, QSPI_CMD1_GO); + udelay(1); + + /* + * Wait for SPI transmit FIFO to empty, or to time out. + * The RX FIFO status will be read and cleared last + */ + for (tm = 0; tm < QSPI_TIMEOUT; ++tm) { + u32 fifo_status, xfer_status; + + xfer_status = readl(&regs->xfer_status); + if (!(xfer_status & QSPI_XFER_STS_RDY)) + continue; + + fifo_status = readl(&regs->fifo_status); + if (fifo_status & QSPI_FIFO_STS_ERR) { + debug("%s: got a fifo error: ", __func__); + if (fifo_status & QSPI_FIFO_STS_TX_FIFO_OVF) + debug("tx FIFO overflow "); + if (fifo_status & QSPI_FIFO_STS_TX_FIFO_UNR) + debug("tx FIFO underrun "); + if (fifo_status & QSPI_FIFO_STS_RX_FIFO_OVF) + debug("rx FIFO overflow "); + if (fifo_status & QSPI_FIFO_STS_RX_FIFO_UNR) + debug("rx FIFO underrun "); + if (fifo_status & QSPI_FIFO_STS_TX_FIFO_FULL) + debug("tx FIFO full "); + if (fifo_status & QSPI_FIFO_STS_TX_FIFO_EMPTY) + debug("tx FIFO empty "); + if (fifo_status & QSPI_FIFO_STS_RX_FIFO_FULL) + debug("rx FIFO full "); + if (fifo_status & QSPI_FIFO_STS_RX_FIFO_EMPTY) + debug("rx FIFO empty "); + debug("\n"); + break; + } + + if (!(fifo_status & QSPI_FIFO_STS_RX_FIFO_EMPTY)) { + tmpdin = readl(&regs->rx_fifo); + if (din != NULL) { + memcpy(din, &tmpdin, bytes); + din += bytes; + num_bytes -= bytes; + } + } + break; + } + + if (tm >= QSPI_TIMEOUT) + ret = tm; + + /* clear ACK RDY, etc. bits */ + writel(readl(&regs->fifo_status), &regs->fifo_status); + } + + if (flags & SPI_XFER_END) + spi_cs_deactivate(dev); + + debug("%s: transfer ended. Value=%08x, fifo_status = %08x\n", + __func__, tmpdin, readl(&regs->fifo_status)); + + if (ret) { + printf("%s: timeout during SPI transfer, tm %d\n", + __func__, ret); + return -1; + } + + return ret; +} + +static int tegra210_qspi_set_speed(struct udevice *bus, uint speed) +{ + struct tegra_spi_platdata *plat = bus->platdata; + struct tegra210_qspi_priv *priv = dev_get_priv(bus); + + if (speed > plat->frequency) + speed = plat->frequency; + priv->freq = speed; + debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq); + + return 0; +} + +static int tegra210_qspi_set_mode(struct udevice *bus, uint mode) +{ + struct tegra210_qspi_priv *priv = dev_get_priv(bus); + + priv->mode = mode; + debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode); + + return 0; +} + +static const struct dm_spi_ops tegra210_qspi_ops = { + .claim_bus = tegra210_qspi_claim_bus, + .xfer = tegra210_qspi_xfer, + .set_speed = tegra210_qspi_set_speed, + .set_mode = tegra210_qspi_set_mode, + /* + * cs_info is not needed, since we require all chip selects to be + * in the device tree explicitly + */ +}; + +static const struct udevice_id tegra210_qspi_ids[] = { + { .compatible = "nvidia,tegra210-qspi" }, + { } +}; + +U_BOOT_DRIVER(tegra210_qspi) = { + .name = "tegra210-qspi", + .id = UCLASS_SPI, + .of_match = tegra210_qspi_ids, + .ops = &tegra210_qspi_ops, + .ofdata_to_platdata = tegra210_qspi_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata), + .priv_auto_alloc_size = sizeof(struct tegra210_qspi_priv), + .per_child_auto_alloc_size = sizeof(struct spi_slave), + .probe = tegra210_qspi_probe, +}; -- 1.8.2.1.610.g562af5b

3 2

[U-Boot] [PATCH] arm: add support for semihosting for ARMv7M targets
by Vadzim Dambrouski 19 Oct '15

19 Oct '15

It is possible to enable CONFIG_SEMIHOSTING for STM32F429 target, but it would result in compile error. This patch adds support for semihosting for STM32F429 or any other ARMv7M target. Tested on STM32F429-DISCOVERY board. Signed-off-by: Vadzim Dambrouski <pftbest(a)gmail.com> --- arch/arm/lib/semihosting.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/lib/semihosting.c b/arch/arm/lib/semihosting.c index c3e964e..6541cb4 100644 --- a/arch/arm/lib/semihosting.c +++ b/arch/arm/lib/semihosting.c @@ -31,6 +31,8 @@ static noinline long smh_trap(unsigned int sysnum, void *addr) register long result asm("r0"); #if defined(CONFIG_ARM64) asm volatile ("hlt #0xf000" : "=r" (result) : "0"(sysnum), "r"(addr)); +#elif defined(CONFIG_CPU_V7M) + asm volatile ("bkpt #0xAB" : "=r" (result) : "0"(sysnum), "r"(addr)); #else /* Note - untested placeholder */ asm volatile ("svc #0x123456" : "=r" (result) : "0"(sysnum), "r"(addr)); @@ -90,7 +92,7 @@ static long smh_read(long fd, void *memp, size_t len) size_t len; } read; - debug("%s: fd %ld, memp %p, len %lu\n", __func__, fd, memp, len); + debug("%s: fd %ld, memp %p, len %lu\n", __func__, fd, memp, (ulong)len); read.fd = fd; read.memp = memp; @@ -105,7 +107,7 @@ static long smh_read(long fd, void *memp, size_t len) * with an error message. */ printf("%s: ERROR ret %ld, fd %ld, len %lu memp %p\n", - __func__, ret, fd, len, memp); + __func__, ret, fd, (ulong)len, memp); return -1; } -- 2.6.1

4 6

[U-Boot] [PATCH 1/3] x86: pci: Add PCI IDs for Wildcat Point
by George McCollister 19 Oct '15

19 Oct '15

Signed-off-by: George McCollister <george.mccollister(a)gmail.com> --- include/pci_ids.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/pci_ids.h b/include/pci_ids.h index 49f7d7d..17a01a0 100644 --- a/include/pci_ids.h +++ b/include/pci_ids.h @@ -3022,6 +3022,8 @@ #define PCI_DEVICE_ID_INTEL_IXP2800 0x9004 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_AHCI 0x9c03 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LPC 0x9c45 +#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_AHCI 0x9c83 +#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LPC 0x9cc3 #define PCI_DEVICE_ID_INTEL_S21152BB 0xb152 #define PCI_VENDOR_ID_SCALEMP 0x8686 -- 2.5.0

4 16

[U-Boot] [PATCH 1/3] ARM: relocate: fix hang when CONFIG_ARMV7_SECURE_BASE
by Frank Li 19 Oct '15

19 Oct '15

When added above configuration, iram fix up plus relocate offset may locate in invalidate space. Write back fix up value will cause data abort. Add address check, skip psci code. Signed-off-by: Frank Li <Frank.Li(a)freescale.com> --- arch/arm/lib/relocate.S | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/lib/relocate.S b/arch/arm/lib/relocate.S index 475d503..6795a1b 100644 --- a/arch/arm/lib/relocate.S +++ b/arch/arm/lib/relocate.S @@ -99,6 +99,10 @@ fixloop: cmp r1, #23 /* relative fixup? */ bne fixnext + ldr r1, =__image_copy_start + cmp r0, r1 + blo fixnext + /* relative fix: increase location by offset */ add r0, r0, r4 ldr r1, [r0] -- 2.5.2

4 10

[U-Boot] [ELCE2015] Question about schedule
by Lukasz Majewski 19 Oct '15

19 Oct '15

Hi Tom, Is there any schedule for our ELCE2015 u-boot mini summit [1]? To be more precise - are know times when we will deliver our presentations? [1] - http://www.denx.de/wiki/U-Boot/SummitELCE2015 -- Best regards, Lukasz Majewski Samsung R&D Institute Poland (SRPOL) | Linux Platform Group

4 7

[U-Boot] [PATCH 1/2] dm: implement a Timer uclass
by Thomas Chou 19 Oct '15

19 Oct '15

Implement a Timer uclass to work with lib/time.c. Signed-off-by: Thomas Chou <thomas(a)wytron.com.tw> --- common/board_r.c | 2 +- drivers/Kconfig | 2 ++ drivers/Makefile | 1 + drivers/timer/Kconfig | 9 ++++++++ drivers/timer/Makefile | 7 ++++++ drivers/timer/timer-uclass.c | 35 ++++++++++++++++++++++++++++++ drivers/timer/timer.c | 51 ++++++++++++++++++++++++++++++++++++++++++++ include/dm/uclass-id.h | 1 + include/timer.h | 36 +++++++++++++++++++++++++++++++ 9 files changed, 143 insertions(+), 1 deletion(-) create mode 100644 drivers/timer/Kconfig create mode 100644 drivers/timer/Makefile create mode 100644 drivers/timer/timer-uclass.c create mode 100644 drivers/timer/timer.c create mode 100644 include/timer.h diff --git a/common/board_r.c b/common/board_r.c index f8c1baa..2d8ad11 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -829,7 +829,7 @@ init_fnc_t init_sequence_r[] = { initr_enable_interrupts, #endif #if defined(CONFIG_X86) || defined(CONFIG_MICROBLAZE) || defined(CONFIG_AVR32) \ - || defined(CONFIG_M68K) + || defined(CONFIG_M68K) || defined(CONFIG_DM_TIMER) timer_init, /* initialize timer */ #endif #if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT) diff --git a/drivers/Kconfig b/drivers/Kconfig index 63c92c5..f9496f7 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -56,6 +56,8 @@ source "drivers/spi/Kconfig" source "drivers/thermal/Kconfig" +source "drivers/timer/Kconfig" + source "drivers/tpm/Kconfig" source "drivers/usb/Kconfig" diff --git a/drivers/Makefile b/drivers/Makefile index 9d0a595..692da78 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -48,6 +48,7 @@ obj-y += pcmcia/ obj-y += dfu/ obj-y += rtc/ obj-y += sound/ +obj-y += timer/ obj-y += tpm/ obj-y += twserial/ obj-y += video/ diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig new file mode 100644 index 0000000..97014f3 --- /dev/null +++ b/drivers/timer/Kconfig @@ -0,0 +1,9 @@ +menu "Timer Support" + +config DM_TIMER + bool "Enable Driver Model for Timer drivers" + depends on DM + help + Enable driver model for Timer access. + +endmenu diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile new file mode 100644 index 0000000..58acd7c --- /dev/null +++ b/drivers/timer/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2015 Thomas Chou <thomas(a)wytron.com.tw> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_DM_TIMER) += timer-uclass.o timer.o diff --git a/drivers/timer/timer-uclass.c b/drivers/timer/timer-uclass.c new file mode 100644 index 0000000..1f088bf --- /dev/null +++ b/drivers/timer/timer-uclass.c @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2015 Thomas Chou <thomas(a)wytron.com.tw> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <timer.h> + +int timer_get_count(struct udevice *dev, unsigned long *count) +{ + const struct dm_timer_ops *ops = device_get_ops(dev); + + if (!ops->get_count) + return -ENOSYS; + + return ops->get_count(dev, count); +} + +int timer_get_rate(struct udevice *dev, unsigned long *rate) +{ + const struct dm_timer_ops *ops = device_get_ops(dev); + + if (!ops->get_rate) + return -ENOSYS; + + return ops->get_rate(dev, rate); +} + +UCLASS_DRIVER(timer) = { + .id = UCLASS_TIMER, + .name = "timer", +}; diff --git a/drivers/timer/timer.c b/drivers/timer/timer.c new file mode 100644 index 0000000..648fd06 --- /dev/null +++ b/drivers/timer/timer.c @@ -0,0 +1,51 @@ +/* + * Copyright (C) 2015 Thomas Chou <thomas(a)wytron.com.tw> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <timer.h> + +DECLARE_GLOBAL_DATA_PTR; + +unsigned long notrace get_tbclk(void) +{ + struct udevice *dev; + unsigned long rate; + + uclass_first_device(UCLASS_TIMER, &dev); + if (!dev) + return 100000000; /* 100MHz, fail-safe */ + + timer_get_rate(dev, &rate); + + return rate; +} + +unsigned long notrace timer_read_counter(void) +{ + struct udevice *dev; + unsigned long count; + + uclass_first_device(UCLASS_TIMER, &dev); + if (!dev) + return 0; /* 0, fail-safe */ + + timer_get_count(dev, &count); + + return count; +} + +int timer_init(void) +{ + struct udevice *dev; + + uclass_first_device(UCLASS_TIMER, &dev); + if (!dev) + return -ENODEV; + + return 0; +} diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index 1eeec74..aff34a4 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -56,6 +56,7 @@ enum uclass_id { UCLASS_SPI_GENERIC, /* Generic SPI flash target */ UCLASS_SYSCON, /* System configuration device */ UCLASS_THERMAL, /* Thermal sensor */ + UCLASS_TIMER, /* Timer device */ UCLASS_TPM, /* Trusted Platform Module TIS interface */ UCLASS_USB, /* USB bus */ UCLASS_USB_DEV_GENERIC, /* USB generic device */ diff --git a/include/timer.h b/include/timer.h new file mode 100644 index 0000000..5d71612 --- /dev/null +++ b/include/timer.h @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2015 Thomas Chou <thomas(a)wytron.com.tw> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DM_TIMER_H_ +#define _DM_TIMER_H_ + +int timer_get_count(struct udevice *dev, unsigned long *count); +int timer_get_rate(struct udevice *dev, unsigned long *rate); + +/* + * struct dm_timer_ops - Driver model Timer operations + * + * The uclass interface is implemented by all Timer devices which use + * driver model. + */ +struct dm_timer_ops { + /* + * Get the current timer count + * + * @dev: The Timer device + * @count: pointer that returns the currnet timer count + */ + int (*get_count)(struct udevice *dev, unsigned long *count); + /* + * Get the timer clock rate + * + * @dev: The Timer device + * @rate: pointer that returns the timer clock rate + */ + int (*get_rate)(struct udevice *dev, unsigned long *rate); +}; + +#endif /* _DM_TIMER_H_ */ -- 2.1.4

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[U-Boot] [PATCH v2 0/2] vexpress64: Juno: Add support for PCIe on Juno
by Liviu Dudau 19 Oct '15

19 Oct '15

Hello, This patchset enables PCIe for ARM's Juno boards and configures the host bridge's address translation block. This enables the Linux kernel to boot on Juno r1 using just a device tree and the generic host bridge driver. No support has been added at this phase for the SATA or Ethernet devices present on the PCIe bus. Changelog: - v2: Split XpressRICH3 code into pcie.c file and introduce vexpress64_pcie_init() that can be called from board_init(). Suggested by Linus Walleij. - v2: Set up the XpressRICH3 bridge class code to a valid value to correct the incorrect reset value. - v1: Original submission http://lists.denx.de/pipermail/u-boot/2015-October/229669.html Liviu Dudau (2): vexpress64: Juno: Declare all 8GB of RAM and make them visible to the kernel. vexpress64: Juno: Add initialisation code for Juno R1 PCIe host bridge. board/armltd/vexpress64/Makefile | 2 +- board/armltd/vexpress64/pcie.c | 196 +++++++++++++++++++++++++++++++++++ board/armltd/vexpress64/pcie.h | 13 +++ board/armltd/vexpress64/vexpress64.c | 10 ++ include/configs/vexpress_aemv8a.h | 4 +- 5 files changed, 223 insertions(+), 2 deletions(-) create mode 100644 board/armltd/vexpress64/pcie.c create mode 100644 board/armltd/vexpress64/pcie.h -- 2.6.0

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[U-Boot] [PATCH v2 1/2] arm: add support for semihosting for ARMv7M targets
by Vadzim Dambrouski 19 Oct '15

19 Oct '15

It is possible to enable CONFIG_SEMIHOSTING for STM32F429 target, but it would result in compile error. This patch adds support for semihosting for STM32F429 or any other ARMv7M target. Tested on STM32F429-DISCOVERY board. Signed-off-by: Vadzim Dambrouski <pftbest(a)gmail.com> --- arch/arm/lib/semihosting.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/lib/semihosting.c b/arch/arm/lib/semihosting.c index c3e964e..ed5e8e4 100644 --- a/arch/arm/lib/semihosting.c +++ b/arch/arm/lib/semihosting.c @@ -31,6 +31,8 @@ static noinline long smh_trap(unsigned int sysnum, void *addr) register long result asm("r0"); #if defined(CONFIG_ARM64) asm volatile ("hlt #0xf000" : "=r" (result) : "0"(sysnum), "r"(addr)); +#elif defined(CONFIG_CPU_V7M) + asm volatile ("bkpt #0xAB" : "=r" (result) : "0"(sysnum), "r"(addr)); #else /* Note - untested placeholder */ asm volatile ("svc #0x123456" : "=r" (result) : "0"(sysnum), "r"(addr)); -- 2.6.1

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[U-Boot] [PATCH] RFC: dm: Add proposed timeline and guide for porting serial drivers
by Simon Glass 19 Oct '15

19 Oct '15

Add a README with a brief guide to porting serial drivers over to use driver model. Add a timeline also. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- I intend to cc the final patch to all U-Boot maintainers using something like this: (for f in $(find . -name MAINTAINERS); do grep ^M: $f; done) | \ awk '{$1=""; print "Series-cc:" $0}' |sort | uniq This is about 229 email address, of which 217 seem to be different people. doc/driver-model/serial-howto.txt | 58 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 doc/driver-model/serial-howto.txt diff --git a/doc/driver-model/serial-howto.txt b/doc/driver-model/serial-howto.txt new file mode 100644 index 0000000..76a75da --- /dev/null +++ b/doc/driver-model/serial-howto.txt @@ -0,0 +1,58 @@ +How to port a serial driver to driver model +=========================================== + +About 16 of 33 serial drivers have been converted as at September 2015. It +is time for maintainers to start converting over the remaining serial drivers: + + altera_jtag_uart.c + altera_uart.c + arm_dcc.c + lpc32xx_hsuart.c + mcfuart.c + mxs_auart.c + opencores_yanu.c + serial_bfin.c + serial_imx.c + serial_lpuart.c + serial_max3100.c + serial_pxa.c + serial_s3c24x0.c + serial_sa1100.c + serial_stm32.c + serial_xuartlite.c + usbtty.c + +You should complete this by Christmas 2015. + +Here is a suggested approach for converting your serial driver over to driver +model. Please feel free to update this file with your ideas and suggestions. + +- #ifdef out all your own serial driver code (#ifndef CONFIG_DM_SERIAL) +- Define CONFIG_DM_SERIAL for your board, vendor or architecture +- If the board does not already use driver model, you need CONFIG_DM also +- Your board should then build, but will not boot since there will be no serial + driver +- Add the U_BOOT_DRIVER piece at the end (e.g. copy serial_s5p.c for example) +- Add a private struct for the driver data - avoid using static variables +- Implement each of the driver methods, perhaps by calling your old methods +- You may need to adjust the function parameters so that the old and new + implementations can share most of the existing code +- If you convert all existing users of the driver, remove the pre-driver-model + code + +In terms of patches a conversion series typically has these patches: +- clean up / prepare the driver for conversion +- add driver model code +- convert at least one existing board to use driver model serial +- (if no boards remain that don't use driver model) remove the old code + +This may be a good time to move your board to use device tree also. Mostly +this involves these steps: + +- define CONFIG_OF_CONTROL and CONFIG_OF_SEPARATE +- add your device tree files to arch/<arch>/dts +- update the Makefile there +- Add stdout-path to your /chosen device tree node if it is not already there +- build and get u-boot-dtb.bin so you can test it +- Your drivers can now use device tree +- For device tree in SPL, define CONFIG_SPL_OF_CONTROL -- 2.5.0.457.gab17608

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[U-Boot] [PATCH] nios2: convert dma mapping to use dm cpu data
by Thomas Chou 19 Oct '15

19 Oct '15

Convert dma mapping to use dm cpu data. Signed-off-by: Thomas Chou <thomas(a)wytron.com.tw> --- arch/nios2/include/asm/dma-mapping.h | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/arch/nios2/include/asm/dma-mapping.h b/arch/nios2/include/asm/dma-mapping.h index 1350e3b..403166b 100644 --- a/arch/nios2/include/asm/dma-mapping.h +++ b/arch/nios2/include/asm/dma-mapping.h @@ -1,23 +1,24 @@ #ifndef __ASM_NIOS2_DMA_MAPPING_H #define __ASM_NIOS2_DMA_MAPPING_H -/* dma_alloc_coherent() return cache-line aligned allocation which is mapped +/* + * dma_alloc_coherent() return cache-line aligned allocation which is mapped * to uncached io region. - * - * IO_REGION_BASE should be defined in board config header file - * 0x80000000 for nommu, 0xe0000000 for mmu */ static inline void *dma_alloc_coherent(size_t len, unsigned long *handle) { - void *addr = malloc(len + CONFIG_SYS_DCACHELINE_SIZE); + DECLARE_GLOBAL_DATA_PTR; + unsigned long addr = + (unsigned long)malloc(len + gd->arch.dcache_line_size); + if (!addr) return 0; - flush_dcache((unsigned long)addr, len + CONFIG_SYS_DCACHELINE_SIZE); - *handle = ((unsigned long)addr + - (CONFIG_SYS_DCACHELINE_SIZE - 1)) & - ~(CONFIG_SYS_DCACHELINE_SIZE - 1) & ~(IO_REGION_BASE); - return (void *)(*handle | IO_REGION_BASE); + flush_dcache(addr, len + gd->arch.dcache_line_size); + *handle = (addr + gd->arch.dcache_line_size - 1) & + ~(gd->arch.dcache_line_size - 1) & ~gd->arch.io_region_base; + + return (void *)(*handle | gd->arch.io_region_base); } #endif /* __ASM_NIOS2_DMA_MAPPING_H */ -- 2.1.4

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