October 2015 - U-Boot

[U-Boot] [PATCH v4 1/5] spi: cadence_qspi: Ensure spi_calibration is run when sclk change
by Chin Liang See 17 Oct '15

17 Oct '15

>From f22064087684b04d6d6ff105a4766a0902d361a8 Mon Sep 17 00:00:00 2001 From: Chin Liang See <clsee(a)altera.com> Date: Thu, 15 Oct 2015 13:56:45 +0800 Subject: [PATCH 1/5] spi: cadence_qspi: Ensure spi_calibration is run when sclk change Ensuring spi_calibration is run when there is a change of sclk frequency. This will ensure the qspi flash access works for high sclk frequency Signed-off-by: Chin Liang See <clsee(a)altera.com> Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> Cc: Dinh Nguyen <dinh.linux(a)gmail.com> Cc: Marek Vasut <marex(a)denx.de> Cc: Stefan Roese <sr(a)denx.de> Cc: Vikas Manocha <vikas.manocha(a)st.com> Cc: Jagannadh Teki <jteki(a)openedev.com> Cc: Pavel Machek <pavel(a)denx.de> Acked-by: Marek Vasut <marex(a)denx.de> Reviewed-by: Jagan Teki <jteki(a)openedev.com> --- Changes for v4 - shift the checking for requested SCLK to the caller Changes for v3 - no changes Changes for v2 - remove frequency set before calibration - introducing previous_hz to store requested frequency - prevent calibration run when request same frequency --- drivers/spi/cadence_qspi.c | 22 +++++++++++++--------- drivers/spi/cadence_qspi.h | 1 + 2 files changed, 14 insertions(+), 9 deletions(-) diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 34a0f46..c5a4276 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -37,9 +37,8 @@ static int cadence_spi_write_speed(struct udevice *bus, uint hz) } /* Calibration sequence to determine the read data capture delay register */ -static int spi_calibration(struct udevice *bus) +static int spi_calibration(struct udevice *bus, uint hz) { - struct cadence_spi_platdata *plat = bus->platdata; struct cadence_spi_priv *priv = dev_get_priv(bus); void *base = priv->regbase; u8 opcode_rdid = 0x9F; @@ -64,7 +63,7 @@ static int spi_calibration(struct udevice *bus) } /* use back the intended clock and find low range */ - cadence_spi_write_speed(bus, plat->max_hz); + cadence_spi_write_speed(bus, hz); for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) { /* Disable QSPI */ cadence_qspi_apb_controller_disable(base); @@ -111,7 +110,7 @@ static int spi_calibration(struct udevice *bus) (range_hi + range_lo) / 2, range_lo, range_hi); /* just to ensure we do once only when speed or chip select change */ - priv->qspi_calibrated_hz = plat->max_hz; + priv->qspi_calibrated_hz = hz; priv->qspi_calibrated_cs = spi_chip_select(bus); return 0; @@ -126,14 +125,19 @@ static int cadence_spi_set_speed(struct udevice *bus, uint hz) /* Disable QSPI */ cadence_qspi_apb_controller_disable(priv->regbase); - cadence_spi_write_speed(bus, hz); - - /* Calibration required for different SCLK speed or chip select */ - if (priv->qspi_calibrated_hz != plat->max_hz || + /* + * Calibration required for different current SCLK speed, requested + * SCLK speed or chip select + */ + if (priv->previous_hz != hz || + priv->qspi_calibrated_hz != hz || priv->qspi_calibrated_cs != spi_chip_select(bus)) { - err = spi_calibration(bus); + err = spi_calibration(bus, hz); if (err) return err; + + /* prevent calibration run when same as previous request */ + priv->previous_hz = hz; } /* Enable QSPI */ diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index 98e57aa..2912e36 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -38,6 +38,7 @@ struct cadence_spi_priv { int qspi_is_init; unsigned int qspi_calibrated_hz; unsigned int qspi_calibrated_cs; + unsigned int previous_hz; }; /* Functions call declaration */ -- 2.2.0

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[U-Boot] [PATCH v4 2/5] spi: cadence_qspi: Fix fdt read of spi-max-frequency
by Chin Liang See 17 Oct '15

17 Oct '15

>From 4a91b5a380e7d3178d4378df79224442c79278bb Mon Sep 17 00:00:00 2001 From: Chin Liang See <clsee(a)altera.com> Date: Fri, 16 Oct 2015 16:35:10 +0800 Subject: [PATCH v4 2/5] spi: cadence_qspi: Fix fdt read of spi-max-frequency Fix the fdt read for spi-max-frequency as it's contained in the child node. Current state of code is always returning default value. Signed-off-by: Chin Liang See <clsee(a)altera.com> Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> Cc: Dinh Nguyen <dinh.linux(a)gmail.com> Cc: Marek Vasut <marex(a)denx.de> Cc: Stefan Roese <sr(a)denx.de> Cc: Vikas Manocha <vikas.manocha(a)st.com> Cc: Jagannadh Teki <jteki(a)openedev.com> Cc: Pavel Machek <pavel(a)denx.de> Acked-by: Marek Vasut <marex(a)denx.de> Acked-by: Pavel Machek <pavel(a)denx.de> --- Changes for v4 - use the newly created fdtdec_get_uint Changes for v3 - Use of fdt_getprop_u32_default_node instead casting Changes for v2 - Add unsigned casting for plat->max_hz --- drivers/spi/cadence_qspi.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index c5a4276..5756178 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -295,10 +295,6 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus) plat->regbase = (void *)data[0]; plat->ahbbase = (void *)data[2]; - /* Use 500KHz as a suitable default */ - plat->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", - 500000); - /* All other paramters are embedded in the child node */ subnode = fdt_first_subnode(blob, node); if (subnode < 0) { @@ -306,6 +302,10 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus) return -ENODEV; } + /* Use 500 KHz as a suitable default */ + plat->max_hz = fdtdec_get_uint(blob, subnode, "spi-max-frequency", + 500000); + /* Read other parameters from DT */ plat->page_size = fdtdec_get_int(blob, subnode, "page-size", 256); plat->block_size = fdtdec_get_int(blob, subnode, "block-size", 16); -- 2.2.0

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[U-Boot] [PATCH] nios2: convert cache flush to use dm cpu data
by Thomas Chou 17 Oct '15

17 Oct '15

Convert cache flush to use dm cpu data. The cacheflush.c of Linux nios2 arch is copied to arch/nios2/lib/cache.c to replace the cache.S. The cache related functions in cpu.c is moved to cache.c. Both flush_dcache() and flush_icache() are replaced and removed. The flush_dcache_all() now flush icache too, which is the same as what is done in Linux nios2 arch. Signed-off-by: Thomas Chou <thomas(a)wytron.com.tw> --- arch/nios2/cpu/cpu.c | 15 -------- arch/nios2/include/asm/cache.h | 13 ++----- arch/nios2/lib/bootm.c | 6 +-- arch/nios2/lib/cache.S | 68 ---------------------------------- arch/nios2/lib/cache.c | 84 ++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 88 insertions(+), 98 deletions(-) delete mode 100644 arch/nios2/lib/cache.S create mode 100644 arch/nios2/lib/cache.c diff --git a/arch/nios2/cpu/cpu.c b/arch/nios2/cpu/cpu.c index 5403c0d..8607c95 100644 --- a/arch/nios2/cpu/cpu.c +++ b/arch/nios2/cpu/cpu.c @@ -29,21 +29,6 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } -int dcache_status(void) -{ - return 1; -} - -void dcache_enable(void) -{ - flush_dcache(CONFIG_SYS_DCACHE_SIZE, CONFIG_SYS_DCACHELINE_SIZE); -} - -void dcache_disable(void) -{ - flush_dcache(CONFIG_SYS_DCACHE_SIZE, CONFIG_SYS_DCACHELINE_SIZE); -} - /* * COPY EXCEPTION TRAMPOLINE -- copy the tramp to the * exception address. Define CONFIG_ROM_STUBS to prevent diff --git a/arch/nios2/include/asm/cache.h b/arch/nios2/include/asm/cache.h index 9b87c9f..dde43cd 100644 --- a/arch/nios2/include/asm/cache.h +++ b/arch/nios2/include/asm/cache.h @@ -8,18 +8,11 @@ #ifndef __ASM_NIOS2_CACHE_H_ #define __ASM_NIOS2_CACHE_H_ -extern void flush_dcache (unsigned long start, unsigned long size); -extern void flush_icache (unsigned long start, unsigned long size); - /* - * Valid L1 data cache line sizes for the NIOS2 architecture are 4, 16, and 32 - * bytes. If the board configuration has not specified one we default to the - * largest of these values for alignment of DMA buffers. + * Valid L1 data cache line sizes for the NIOS2 architecture are 4, + * 16, and 32 bytes. We default to the largest of these values for + * alignment of DMA buffers. */ -#ifdef CONFIG_SYS_CACHELINE_SIZE -#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE -#else #define ARCH_DMA_MINALIGN 32 -#endif #endif /* __ASM_NIOS2_CACHE_H_ */ diff --git a/arch/nios2/lib/bootm.c b/arch/nios2/lib/bootm.c index c730a3f..4e5c269 100644 --- a/arch/nios2/lib/bootm.c +++ b/arch/nios2/lib/bootm.c @@ -6,9 +6,6 @@ */ #include <common.h> -#include <command.h> -#include <asm/byteorder.h> -#include <asm/cache.h> #define NIOS_MAGIC 0x534f494e /* enable command line and initrd passing */ @@ -40,8 +37,7 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima /* flushes data and instruction caches before calling the kernel */ disable_interrupts(); - flush_dcache((ulong)kernel, CONFIG_SYS_DCACHE_SIZE); - flush_icache((ulong)kernel, CONFIG_SYS_ICACHE_SIZE); + flush_dcache_all(); debug("bootargs=%s @ 0x%lx\n", commandline, (ulong)&commandline); debug("initrd=0x%lx-0x%lx\n", (ulong)initrd_start, (ulong)initrd_end); diff --git a/arch/nios2/lib/cache.S b/arch/nios2/lib/cache.S deleted file mode 100644 index 683f005..0000000 --- a/arch/nios2/lib/cache.S +++ /dev/null @@ -1,68 +0,0 @@ -/* - * (C) Copyright 2004, Psyent Corporation <www.psyent.com> - * Scott McNutt <smcnutt(a)psyent.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> - - .text - - .global flush_dcache - -flush_dcache: - add r5, r5, r4 - movhi r8, %hi(CONFIG_SYS_DCACHELINE_SIZE) - ori r8, r8, %lo(CONFIG_SYS_DCACHELINE_SIZE) -0: flushd 0(r4) - add r4, r4, r8 - bltu r4, r5, 0b - ret - - - .global flush_icache - -flush_icache: - add r5, r5, r4 - movhi r8, %hi(CONFIG_SYS_ICACHELINE_SIZE) - ori r8, r8, %lo(CONFIG_SYS_ICACHELINE_SIZE) -1: flushi r4 - add r4, r4, r8 - bltu r4, r5, 1b - ret - - .global flush_dcache_range - -flush_dcache_range: - movhi r8, %hi(CONFIG_SYS_DCACHELINE_SIZE) - ori r8, r8, %lo(CONFIG_SYS_DCACHELINE_SIZE) -0: flushd 0(r4) - add r4, r4, r8 - bltu r4, r5, 0b - ret - - .global flush_cache - -flush_cache: - add r5, r5, r4 - mov r9, r4 - mov r10, r5 - - movhi r8, %hi(CONFIG_SYS_DCACHELINE_SIZE) - ori r8, r8, %lo(CONFIG_SYS_DCACHELINE_SIZE) -0: flushd 0(r4) - add r4, r4, r8 - bltu r4, r5, 0b - - mov r4, r9 - mov r5, r10 - movhi r8, %hi(CONFIG_SYS_ICACHELINE_SIZE) - ori r8, r8, %lo(CONFIG_SYS_ICACHELINE_SIZE) -1: flushi r4 - add r4, r4, r8 - bltu r4, r5, 1b - - sync - flushp - ret diff --git a/arch/nios2/lib/cache.c b/arch/nios2/lib/cache.c new file mode 100644 index 0000000..6f26d8d --- /dev/null +++ b/arch/nios2/lib/cache.c @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2015 Thomas Chou <thomas(a)wytron.com.tw> + * Copyright (C) 2009, Wind River Systems Inc + * Implemented by fredrik.markstrom(a)gmail.com and ivarholmqvist(a)gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/cache.h> + +DECLARE_GLOBAL_DATA_PTR; + +static void __flush_dcache_all(unsigned long start, unsigned long end) +{ + unsigned long addr; + + start &= ~(gd->arch.dcache_line_size - 1); + end += (gd->arch.dcache_line_size - 1); + end &= ~(gd->arch.dcache_line_size - 1); + + if (end > start + gd->arch.dcache_size) + end = start + gd->arch.dcache_size; + + for (addr = start; addr < end; addr += gd->arch.dcache_line_size) { + __asm__ __volatile__ (" flushd 0(%0)\n" + : /* Outputs */ + : /* Inputs */ "r"(addr) + /* : No clobber */); + } +} + +static void __flush_icache(unsigned long start, unsigned long end) +{ + unsigned long addr; + + start &= ~(gd->arch.icache_line_size - 1); + end += (gd->arch.icache_line_size - 1); + end &= ~(gd->arch.icache_line_size - 1); + + if (end > start + gd->arch.icache_size) + end = start + gd->arch.icache_size; + + for (addr = start; addr < end; addr += gd->arch.icache_line_size) { + __asm__ __volatile__ (" flushi %0\n" + : /* Outputs */ + : /* Inputs */ "r"(addr) + /* : No clobber */); + } + __asm__ __volatile(" flushp\n"); +} + +void flush_dcache_all(void) +{ + __flush_dcache_all(0, gd->arch.dcache_size); + __flush_icache(0, gd->arch.icache_size); +} + +void flush_dcache_range(unsigned long start, unsigned long end) +{ + __flush_dcache_all(start, end); +} + +void flush_cache(unsigned long start, unsigned long size) +{ + __flush_dcache_all(start, start + size); + __flush_icache(start, start + size); +} + +/* nios2 data cache is always enabled */ +int dcache_status(void) +{ + return 1; +} + +void dcache_enable(void) +{ + flush_dcache_all(); +} + +void dcache_disable(void) +{ + flush_dcache_all(); +} -- 2.1.4

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[U-Boot] [PULL] u-boot-socfpga/master
by Marek Vasut 17 Oct '15

17 Oct '15

The following changes since commit 1275456d31cc130738775dca19b0a2ab1374cfbd: Merge branch 'master' of git://git.denx.de/u-boot-arm (2015-10-15 17:45:39 -0400) are available in the git repository at: git://git.denx.de/u-boot-socfpga.git for you to fetch changes up to 3790a8c66266de6361c8be1544d244f8adb71fb9: arm: dts: socfpga: add "u-boot,dm-pre-reloc" to socfpga_cyclone5_socdk dts (2015-10-17 01:47:31 +0200) ---------------------------------------------------------------- Dinh Nguyen (2): arm: socfpga: enable data/inst prefetch and shared override in the L2 arm: dts: socfpga: add "u-boot,dm-pre-reloc" to socfpga_cyclone5_socdk dts arch/arm/dts/socfpga_cyclone5_socdk.dts | 3 +++ arch/arm/include/asm/pl310.h | 2 ++ arch/arm/mach-socfpga/misc.c | 12 ++++++++++++ 3 files changed, 17 insertions(+)

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[U-Boot] [PATCH] vf610twr: Fix typo in DRAM init
by Anthony Felice 17 Oct '15

17 Oct '15

This commit fixes a typo in vf610twr DRAM init that was causing a hang in U-Boot for the Vybrid Tower. This typo was introduced in commit 3f353cecc (vf610: refactor DDRMC code). Signed-off-by: Anthony Felice <tony.felice(a)timesys.com> --- board/freescale/vf610twr/vf610twr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/freescale/vf610twr/vf610twr.c b/board/freescale/vf610twr/vf610twr.c index a78e9e6..fa0075c 100644 --- a/board/freescale/vf610twr/vf610twr.c +++ b/board/freescale/vf610twr/vf610twr.c @@ -108,7 +108,7 @@ int dram_init(void) .trcd_int = 6, .tras_lockout = 0, .tdal = 12, - .bstlen = 0, + .bstlen = 3, .tdll = 512, .trp_ab = 6, .tref = 3120, -- 1.9.1

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[U-Boot] please pull u-boot-samsung master
by Minkyu Kang 17 Oct '15

17 Oct '15

Dear Tom, The following changes since commit f861f51c4673d35908e4e330a86c81d7d909b51c: ls102xa: Fix reset hang (2015-10-12 12:56:32 -0400) are available in the git repository at: http://git.denx.de/u-boot-samsung for you to fetch changes up to 2308ea7c6fe003f699f4648d4ac3bb030fdc64d0: exynos: more debug and cleanup in do_sdhci_init() (2015-10-13 20:22:28 +0900) ---------------------------------------------------------------- Guillaume GARDET (2): odroid: replace 'fatload' with 'load' to be able to use EXT* partitions odroid: Add boot script (boot.scr) support Tobias Jakobi (4): exynos: Properly zero initialize host in s5p_sdhci_init() exynos: Fix passing of errors in exynos_mmc_init() exynos: be more verbose in process_nodes() exynos: more debug and cleanup in do_sdhci_init() drivers/mmc/s5p_sdhci.c | 50 +++++++++++++++++++++++++++------------------- include/configs/odroid.h | 16 +++++++++++---- 2 files changed, 42 insertions(+), 24 deletions(-) -- Thanks, Minkyu Kang.

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[U-Boot] Pull request (again): u-boot-arm/master
by Albert ARIBAUD 17 Oct '15

17 Oct '15

Hello, The following changes since commit 1275456d31cc130738775dca19b0a2ab1374cfbd: Merge branch 'master' of git://git.denx.de/u-boot-arm (2015-10-15 17:45:39 -0400) are available in the git repository at: git://git.denx.de/u-boot-arm master for you to fetch changes up to 53fd4b8c22bbdf4598f87e701e9a6c6ee50172ff: arm: mmu: Add missing volatile for reading SCTLR register (2015-10-16 07:55:51 +0200) ---------------------------------------------------------------- Alison Wang (1): arm: mmu: Add missing volatile for reading SCTLR register arch/arm/include/asm/system.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) Amicalement, -- Albert.

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[U-Boot] [PATCHv2] arm: socfpga: enable data/inst prefetch and shared override in the L2
by dinguyen＠opensource.altera.com 17 Oct '15

17 Oct '15

From: Dinh Nguyen <dinguyen(a)opensource.altera.com> Update the L2 AUX CTRL settings for the SoCFPGA. Enabling D and I prefetch bits helps improve SDRAM performance on the platform. Also, we need to enable bit 22 of the L2. By not having bit 22 set in the PL310 Auxiliary Control register (shared attribute override enable) has the side effect of transforming Normal Shared Non-cacheable reads into Cacheable no-allocate reads. Coherent DMA buffers in Linux always have a Cacheable alias via the kernel linear mapping and the processor can speculatively load cache lines into the PL310 controller. With bit 22 cleared, Non-cacheable reads would unexpectedly hit such cache lines leading to buffer corruption. Signed-off-by: Dinh Nguyen <dinguyen(a)opensource.altera.com> --- v2: s/PL310_/L310_ --- arch/arm/include/asm/pl310.h | 2 ++ arch/arm/mach-socfpga/misc.c | 12 ++++++++++++ 2 files changed, 14 insertions(+) diff --git a/arch/arm/include/asm/pl310.h b/arch/arm/include/asm/pl310.h index de7650e..d588f94 100644 --- a/arch/arm/include/asm/pl310.h +++ b/arch/arm/include/asm/pl310.h @@ -17,6 +17,8 @@ #define L2X0_CTRL_EN 1 #define L310_SHARED_ATT_OVERRIDE_ENABLE (1 << 22) +#define L310_AUX_CTRL_DATA_PREFETCH_MASK (1 << 28) +#define L310_AUX_CTRL_INST_PREFETCH_MASK (1 << 29) struct pl310_regs { u32 pl310_cache_id; diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 0940cc5..bbd31ef 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -52,6 +52,18 @@ void enable_caches(void) #endif } +void v7_outer_cache_enable(void) +{ + /* disable the L2 cache */ + writel(0, &pl310->pl310_ctrl); + + /* enable BRESP, instruction and data prefetch, full line of zeroes */ + setbits_le32(&pl310->pl310_aux_ctrl, + L310_AUX_CTRL_DATA_PREFETCH_MASK | + L310_AUX_CTRL_INST_PREFETCH_MASK | + L310_SHARED_ATT_OVERRIDE_ENABLE); +} + /* * DesignWare Ethernet initialization */ -- 2.4.5

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[U-Boot] [PATCH] arm: dts: socfpga: add "u-boot, dm-pre-reloc" to socfpga_cyclone5_socdk dts
by dinguyen＠opensource.altera.com 17 Oct '15

17 Oct '15

From: Dinh Nguyen <dinguyen(a)opensource.altera.com> We need "u-boot,dm-pre-reloc" in the socfpga_cyclone5_socdk.dts file in order for the SPL to use SD/MMC. Signed-off-by: Dinh Nguyen <dinguyen(a)opensource.altera.com> --- arch/arm/dts/socfpga_cyclone5_socdk.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts b/arch/arm/dts/socfpga_cyclone5_socdk.dts index 9650eb0..5465609 100644 --- a/arch/arm/dts/socfpga_cyclone5_socdk.dts +++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts @@ -69,6 +69,9 @@ }; &mmc0 { + status = "okay"; + u-boot,dm-pre-reloc; + cd-gpios = <&portb 18 0>; vmmc-supply = <&regulator_3_3v>; vqmmc-supply = <&regulator_3_3v>; -- 2.4.5

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[U-Boot] [PATCH v7 1/4] include: Add log2 and fls64 header files
by Fabio Estevam 16 Oct '15

16 Oct '15

From: Fabio Estevam <fabio.estevam(a)freescale.com> Use the log2 and fls64 header files from the kernel. Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- Changes since v6: - Newly introduced in this series include/asm-generic/bitops/fls64.h | 36 +++++++ include/linux/bitops.h | 9 ++ include/linux/log2.h | 208 +++++++++++++++++++++++++++++++++++++ 3 files changed, 253 insertions(+) create mode 100644 include/asm-generic/bitops/fls64.h create mode 100644 include/linux/log2.h diff --git a/include/asm-generic/bitops/fls64.h b/include/asm-generic/bitops/fls64.h new file mode 100644 index 0000000..86d403f --- /dev/null +++ b/include/asm-generic/bitops/fls64.h @@ -0,0 +1,36 @@ +#ifndef _ASM_GENERIC_BITOPS_FLS64_H_ +#define _ASM_GENERIC_BITOPS_FLS64_H_ + +#include <asm/types.h> + +/** + * fls64 - find last set bit in a 64-bit word + * @x: the word to search + * + * This is defined in a similar way as the libc and compiler builtin + * ffsll, but returns the position of the most significant set bit. + * + * fls64(value) returns 0 if value is 0 or the position of the last + * set bit if value is nonzero. The last (most significant) bit is + * at position 64. + */ +#if BITS_PER_LONG == 32 +static inline int fls64(__u64 x) +{ + __u32 h = x >> 32; + if (h) + return fls(h) + 32; + return fls(x); +} +#elif BITS_PER_LONG == 64 +static inline int fls64(__u64 x) +{ + if (x == 0) + return 0; + return __fls(x) + 1; +} +#else +#error BITS_PER_LONG not 32 or 64 +#endif + +#endif /* _ASM_GENERIC_BITOPS_FLS64_H_ */ diff --git a/include/linux/bitops.h b/include/linux/bitops.h index 7d30ace..647733f 100644 --- a/include/linux/bitops.h +++ b/include/linux/bitops.h @@ -129,6 +129,15 @@ static inline unsigned int generic_hweight8(unsigned int w) # define fls generic_fls #endif +#include <asm-generic/bitops/fls64.h> + +static inline unsigned fls_long(unsigned long l) +{ + if (sizeof(l) == 4) + return fls(l); + return fls64(l); +} + /** * __set_bit - Set a bit in memory * @nr: the bit to set diff --git a/include/linux/log2.h b/include/linux/log2.h new file mode 100644 index 0000000..fd7ff3d --- /dev/null +++ b/include/linux/log2.h @@ -0,0 +1,208 @@ +/* Integer base 2 logarithm calculation + * + * Copyright (C) 2006 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells(a)redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#ifndef _LINUX_LOG2_H +#define _LINUX_LOG2_H + +#include <linux/types.h> +#include <linux/bitops.h> + +/* + * deal with unrepresentable constant logarithms + */ +extern __attribute__((const, noreturn)) +int ____ilog2_NaN(void); + +/* + * non-constant log of base 2 calculators + * - the arch may override these in asm/bitops.h if they can be implemented + * more efficiently than using fls() and fls64() + * - the arch is not required to handle n==0 if implementing the fallback + */ +#ifndef CONFIG_ARCH_HAS_ILOG2_U32 +static inline __attribute__((const)) +int __ilog2_u32(u32 n) +{ + return fls(n) - 1; +} +#endif + +#ifndef CONFIG_ARCH_HAS_ILOG2_U64 +static inline __attribute__((const)) +int __ilog2_u64(u64 n) +{ + return fls64(n) - 1; +} +#endif + +/* + * Determine whether some value is a power of two, where zero is + * *not* considered a power of two. + */ + +static inline __attribute__((const)) +bool is_power_of_2(unsigned long n) +{ + return (n != 0 && ((n & (n - 1)) == 0)); +} + +/* + * round up to nearest power of two + */ +static inline __attribute__((const)) +unsigned long __roundup_pow_of_two(unsigned long n) +{ + return 1UL << fls_long(n - 1); +} + +/* + * round down to nearest power of two + */ +static inline __attribute__((const)) +unsigned long __rounddown_pow_of_two(unsigned long n) +{ + return 1UL << (fls_long(n) - 1); +} + +/** + * ilog2 - log of base 2 of 32-bit or a 64-bit unsigned value + * @n - parameter + * + * constant-capable log of base 2 calculation + * - this can be used to initialise global variables from constant data, hence + * the massive ternary operator construction + * + * selects the appropriately-sized optimised version depending on sizeof(n) + */ +#define ilog2(n) \ +( \ + __builtin_constant_p(n) ? ( \ + (n) < 1 ? ____ilog2_NaN() : \ + (n) & (1ULL << 63) ? 63 : \ + (n) & (1ULL << 62) ? 62 : \ + (n) & (1ULL << 61) ? 61 : \ + (n) & (1ULL << 60) ? 60 : \ + (n) & (1ULL << 59) ? 59 : \ + (n) & (1ULL << 58) ? 58 : \ + (n) & (1ULL << 57) ? 57 : \ + (n) & (1ULL << 56) ? 56 : \ + (n) & (1ULL << 55) ? 55 : \ + (n) & (1ULL << 54) ? 54 : \ + (n) & (1ULL << 53) ? 53 : \ + (n) & (1ULL << 52) ? 52 : \ + (n) & (1ULL << 51) ? 51 : \ + (n) & (1ULL << 50) ? 50 : \ + (n) & (1ULL << 49) ? 49 : \ + (n) & (1ULL << 48) ? 48 : \ + (n) & (1ULL << 47) ? 47 : \ + (n) & (1ULL << 46) ? 46 : \ + (n) & (1ULL << 45) ? 45 : \ + (n) & (1ULL << 44) ? 44 : \ + (n) & (1ULL << 43) ? 43 : \ + (n) & (1ULL << 42) ? 42 : \ + (n) & (1ULL << 41) ? 41 : \ + (n) & (1ULL << 40) ? 40 : \ + (n) & (1ULL << 39) ? 39 : \ + (n) & (1ULL << 38) ? 38 : \ + (n) & (1ULL << 37) ? 37 : \ + (n) & (1ULL << 36) ? 36 : \ + (n) & (1ULL << 35) ? 35 : \ + (n) & (1ULL << 34) ? 34 : \ + (n) & (1ULL << 33) ? 33 : \ + (n) & (1ULL << 32) ? 32 : \ + (n) & (1ULL << 31) ? 31 : \ + (n) & (1ULL << 30) ? 30 : \ + (n) & (1ULL << 29) ? 29 : \ + (n) & (1ULL << 28) ? 28 : \ + (n) & (1ULL << 27) ? 27 : \ + (n) & (1ULL << 26) ? 26 : \ + (n) & (1ULL << 25) ? 25 : \ + (n) & (1ULL << 24) ? 24 : \ + (n) & (1ULL << 23) ? 23 : \ + (n) & (1ULL << 22) ? 22 : \ + (n) & (1ULL << 21) ? 21 : \ + (n) & (1ULL << 20) ? 20 : \ + (n) & (1ULL << 19) ? 19 : \ + (n) & (1ULL << 18) ? 18 : \ + (n) & (1ULL << 17) ? 17 : \ + (n) & (1ULL << 16) ? 16 : \ + (n) & (1ULL << 15) ? 15 : \ + (n) & (1ULL << 14) ? 14 : \ + (n) & (1ULL << 13) ? 13 : \ + (n) & (1ULL << 12) ? 12 : \ + (n) & (1ULL << 11) ? 11 : \ + (n) & (1ULL << 10) ? 10 : \ + (n) & (1ULL << 9) ? 9 : \ + (n) & (1ULL << 8) ? 8 : \ + (n) & (1ULL << 7) ? 7 : \ + (n) & (1ULL << 6) ? 6 : \ + (n) & (1ULL << 5) ? 5 : \ + (n) & (1ULL << 4) ? 4 : \ + (n) & (1ULL << 3) ? 3 : \ + (n) & (1ULL << 2) ? 2 : \ + (n) & (1ULL << 1) ? 1 : \ + (n) & (1ULL << 0) ? 0 : \ + ____ilog2_NaN() \ + ) : \ + (sizeof(n) <= 4) ? \ + __ilog2_u32(n) : \ + __ilog2_u64(n) \ + ) + +/** + * roundup_pow_of_two - round the given value up to nearest power of two + * @n - parameter + * + * round the given value up to the nearest power of two + * - the result is undefined when n == 0 + * - this can be used to initialise global variables from constant data + */ +#define roundup_pow_of_two(n) \ +( \ + __builtin_constant_p(n) ? ( \ + (n == 1) ? 1 : \ + (1UL << (ilog2((n) - 1) + 1)) \ + ) : \ + __roundup_pow_of_two(n) \ + ) + +/** + * rounddown_pow_of_two - round the given value down to nearest power of two + * @n - parameter + * + * round the given value down to the nearest power of two + * - the result is undefined when n == 0 + * - this can be used to initialise global variables from constant data + */ +#define rounddown_pow_of_two(n) \ +( \ + __builtin_constant_p(n) ? ( \ + (1UL << ilog2(n))) : \ + __rounddown_pow_of_two(n) \ + ) + +/** + * order_base_2 - calculate the (rounded up) base 2 order of the argument + * @n: parameter + * + * The first few values calculated by this routine: + * ob2(0) = 0 + * ob2(1) = 0 + * ob2(2) = 1 + * ob2(3) = 2 + * ob2(4) = 2 + * ob2(5) = 3 + * ... and so on. + */ + +#define order_base_2(n) ilog2(roundup_pow_of_two(n)) + +#endif /* _LINUX_LOG2_H */ -- 1.9.1

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