January 2015 - U-Boot

[U-Boot] [PATCH 1/2] sunxi: video: Make pwm polarity configurable
by Hans de Goede 23 Jan '15

23 Jan '15

It turns out that there are some panels where the pwm input is not active low, so make it configurable. Signed-off-by: Hans de Goede <hdegoede(a)redhat.com> --- board/sunxi/Kconfig | 7 +++++++ drivers/video/sunxi_display.c | 17 +++++++++++------ 2 files changed, 18 insertions(+), 6 deletions(-) diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index 0e3c207..738b55e 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -319,6 +319,13 @@ config VIDEO_LCD_BL_PWM Set the backlight pwm pin for the LCD panel. This takes a string in the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. +config VIDEO_LCD_BL_PWM_ACTIVE_LOW + bool "LCD panel backlight pwm is inverted" + depends on VIDEO + default y + ---help--- + Set this if the backlight pwm output is active low. + # Note only one of these may be selected at a time! But hidden choices are # not supported by Kconfig diff --git a/drivers/video/sunxi_display.c b/drivers/video/sunxi_display.c index 5077111..af728b5 100644 --- a/drivers/video/sunxi_display.c +++ b/drivers/video/sunxi_display.c @@ -23,6 +23,14 @@ #include "hitachi_tx18d42vm_lcd.h" #include "ssd2828.h" +#ifdef CONFIG_VIDEO_LCD_BL_PWM_ACTIVE_LOW +#define PWM_ON 0 +#define PWM_OFF 1 +#else +#define PWM_ON 1 +#define PWM_OFF 0 +#endif + DECLARE_GLOBAL_DATA_PTR; enum sunxi_monitor { @@ -598,8 +606,7 @@ static void sunxi_lcdc_panel_enable(void) pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_PWM); if (pin != -1) { gpio_request(pin, "lcd_backlight_pwm"); - /* backlight pwm is inverted, set to 1 to disable backlight */ - gpio_direction_output(pin, 1); + gpio_direction_output(pin, PWM_OFF); } /* Give the backlight some time to turn off and power up the panel. */ @@ -626,10 +633,8 @@ static void sunxi_lcdc_backlight_enable(void) gpio_direction_output(pin, 1); pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_PWM); - if (pin != -1) { - /* backlight pwm is inverted, set to 0 to enable backlight */ - gpio_direction_output(pin, 0); - } + if (pin != -1) + gpio_direction_output(pin, PWM_ON); } static int sunxi_lcdc_get_clk_delay(const struct ctfb_res_modes *mode) -- 2.1.0

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[U-Boot] [PATCH] sunxi: video: Add support for Hitachi tx18d42vm LVDS LCD panels
by Hans de Goede 23 Jan '15

23 Jan '15

Add support for Hitachi tx18d42vm LVDS LCD panels, these panels have a lcd controller which needs to be initialized over SPI, once that is done they work like a regular LVDS panel. Signed-off-by: Hans de Goede <hdegoede(a)redhat.com> --- board/sunxi/Kconfig | 7 +++++++ drivers/video/sunxi_display.c | 5 +++++ 2 files changed, 12 insertions(+) diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index f1501d4..8ac3d42 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -354,6 +354,13 @@ config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828 ---help--- 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0 +config VIDEO_LCD_PANEL_HITACHI_TX18D42VM + bool "Hitachi tx18d42vm LCD panel" + select VIDEO_LCD_HITACHI_TX18D42VM + select VIDEO_LCD_IF_LVDS + ---help--- + 7.85" 1024x768 Hitachi tx18d42vm LCD panel support + endchoice diff --git a/drivers/video/sunxi_display.c b/drivers/video/sunxi_display.c index a6e3778..5077111 100644 --- a/drivers/video/sunxi_display.c +++ b/drivers/video/sunxi_display.c @@ -20,6 +20,7 @@ #include <fdt_support.h> #include <video_fb.h> #include "videomodes.h" +#include "hitachi_tx18d42vm_lcd.h" #include "ssd2828.h" DECLARE_GLOBAL_DATA_PTR; @@ -1004,6 +1005,10 @@ static void sunxi_mode_set(const struct ctfb_res_modes *mode, break; case sunxi_monitor_lcd: sunxi_lcdc_panel_enable(); + if (IS_ENABLED(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM)) { + mdelay(50); /* Wait for lcd controller power on */ + hitachi_tx18d42vm_init(); + } sunxi_composer_mode_set(mode, address); sunxi_lcdc_tcon0_mode_set(mode); sunxi_composer_enable(); -- 2.1.0

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[U-Boot] removing bit reversing for SCFG in immap_ls102xa.h
by Sinan Akman 23 Jan '15

23 Jan '15

Hi Alison I was just testing out ls1021atwr board with NOR boot using rcw_1000.bin. I noticed that Ethernet is not working. In ls1021atwr.c we have : out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125); In your earlier commit c207ff612903389f8b32e377fe32be43e6efd8f7 you removed the bit reversing around this but those defines are not in big-endian. By setting bit reversing before those lines as before makes Ethernet working. Could you please take a look at this. Should we reverse your commit since we are accessing SCFG registers directly in the board specific files ? Regards Sinan Akman

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[U-Boot] [PATCH v4 00/18] Support for eMMC partitioning and related fixes
by Diego Santa Cruz 23 Jan '15

23 Jan '15

I have the need to hardware partition eMMC devices from U-Boot along with setting enhanced and reliable write attributes. This series of patches adds this support to U-Boot via a new mmc API, a few new members of struct mmc and a new mmc sub-command. It also features several fixes to the eMMC hardware partition support. I have tested this with Micron eMMC 4.41 parts and it is working as expected. This version resyncs to u-boot.git master d8bec60c1b0de7770f9b56ad092ab9be801d99af as some recent mmc changes conflicted with these patches, in particular the DDR mode support. Diego Santa Cruz (18): mmc: show hardware partition sizes in mmcinfo output mmc: extend mmcinfo to show enhanced partition attribute mmc: make eMMC general purpose partition numbering match spec mmc: skip mmcinfo partition info processing for eMMC < 4.41 mmc: incomplete test to switch to high-capacity group size definitions mmc: computation of eMMC GP partition size was missing 512 KiB factor mmc: read the size of eMMC enhanced user data area mmc: display size and start of eMMC enhanced user data area in mmcinfo mmc: fix erase_grp_size computation with high-capacity size definition mmc: read the high capacity WP group size for eMMC mmc: show the erase group size and HC WP group size in mmcinfo output mmc: eMMC partitioning data is not effective till partitioning completed mmc: the ext_csd data may be used during init even if reading failed mmc: add API to do eMMC hardware partitioning mmc: add mmc hwpartition sub-command to do eMMC hardware partitioning mmc: extend the mmc hardware partitioning API with write reliability mmc: extend the mmc hwpartition sub-command to change write reliability mmc: extend mmcinfo output to show partition write reliability settings common/cmd_mmc.c | 207 ++++++++++++++++++++++++++++++++++++++- drivers/mmc/mmc.c | 288 +++++++++++++++++++++++++++++++++++++++++++++++++----- include/mmc.h | 45 ++++++++- 3 files changed, 515 insertions(+), 25 deletions(-) -- 2.2.1

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[U-Boot] [PATCH 0/5] Add support for G2C1 mx28 board (which has no battery)
by Graeme Russ 23 Jan '15

23 Jan '15

This series adds support for booting mx28 based boards which do not include a battery as per Freescale application note AN4199 Patch 2 (which implements booting without a battery) is based on a patch submitted to the Freescale community forums by Damien Gotfroi (Cc'd) The patch series adds the following functionality (in oreder of implementation) - Debug output for mxs SPL (define DEBUG and CONFIG_SPL_SERIAL_SUPPORT in order to enable) - Ability to boot mx28 boards without a battery as per AN4199 (define CONFIG_SYS_MXS_VDD5V_ONLY to enable) - A tight loop (with 'Waiting for JTAG user') at the completion of SPL init if booting with the bootmode jumpers set to JTAG - Move the PLL power-up to a more logical location and properly initialise and check for PLL lock - Finally, add the G2C1 board Graeme Russ (5): Add debug output to mx29 SPL source files Enable booting of mx28 without battery Add 'Wait for JTAG user' if booted in JTAG mode Move PLL power-up from power init to memory init Add support for ReachTech G2C1 board arch/arm/Kconfig | 13 + arch/arm/cpu/arm926ejs/mxs/spl_boot.c | 7 + arch/arm/cpu/arm926ejs/mxs/spl_lradc_init.c | 13 +- arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c | 49 +++ arch/arm/cpu/arm926ejs/mxs/spl_power_init.c | 287 ++++++++++++++++-- board/reachtech/g2c1/Kconfig | 15 + board/reachtech/g2c1/MAINTAINERS | 9 + board/reachtech/g2c1/Makefile | 12 + board/reachtech/g2c1/README | 58 ++++ board/reachtech/g2c1/g2c1.c | 79 +++++ board/reachtech/g2c1/spl_boot.c | 452 ++++++++++++++++++++++++++++ configs/g2c1_defconfig | 3 + doc/README.mxs | 10 + include/configs/g2c1.h | 303 +++++++++++++++++++ 14 files changed, 1281 insertions(+), 29 deletions(-) create mode 100644 board/reachtech/g2c1/Kconfig create mode 100644 board/reachtech/g2c1/MAINTAINERS create mode 100644 board/reachtech/g2c1/Makefile create mode 100644 board/reachtech/g2c1/README create mode 100644 board/reachtech/g2c1/g2c1.c create mode 100644 board/reachtech/g2c1/spl_boot.c create mode 100644 configs/g2c1_defconfig create mode 100644 include/configs/g2c1.h -- 1.9.3

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[U-Boot] Using __func__ and __LINE__ in debug outputs
by Graeme Russ 23 Jan '15

23 Jan '15

Hi All, What is the general consensus on using __func__ and __LINE__ in debug outputs? My personal opinion is that distinct statements that can be grep'd are better for a couple of reasons: - It keeps the debug statements shorter - If your running a slightly older version of U-Boot, the line numbers (and possibly even the function names) may not match the current version of the source code Regardless of whether we should use __func__ and __LINE__, greping for __func__ yields 1,837 hits with inconsistent usage. Should we not simply have a #define which tells debug() to output the function and line number in a consistent manner? Regards, Graeme

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[U-Boot] [PATCH v4 06/11] arch/powerpc: Initialize VSC9953 L2 Switch
by Codrin Ciubotariu 23 Jan '15

23 Jan '15

This patch initializes VSC9953 L2 Switch for boards that have CONFIG_VSC9953 defined in their config file. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu(a)freescale.com> --- Changes for v2: - added patch description; Changes for v3: - Removed "Change-id" line from comment; Changes for v4: - removed define CONFIG_VSC9953 from SoC config header; - patch title and comment changed to reflect the new change; arch/powerpc/cpu/mpc8xxx/cpu.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index 2d28eb2..c92589f 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -15,6 +15,7 @@ #include <netdev.h> #include <asm/cache.h> #include <asm/io.h> +#include <vsc9953.h> DECLARE_GLOBAL_DATA_PTR; @@ -271,5 +272,9 @@ int cpu_eth_init(bd_t *bis) #ifdef CONFIG_FMAN_ENET fm_standard_init(bis); #endif + +#ifdef CONFIG_VSC9953 + vsc9953_init(bis); +#endif return 0; } -- 1.7.11.7

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[U-Boot] [PATCH v3 00/11] Add driver for VSC9953 Ethernet Switch
by Codrin Ciubotariu 23 Jan '15

23 Jan '15

This patches add support for VSC9953, a Vitesse L2 Switch IP which is integrated in the T1040/T1020 Freescale SoCs. About Device: ============= The Seville Gigabit Ethernet switch core contains eight 10/100/1000 Mbps Ethernet ports and two 10/100/1000/2500 Mbps ports. It provides a rich set of Ethernet switching features such as advanced TCAM-based VLAN and QoS processing as well as security processing using a TCAM. Switch interfaces: - 8 Gigabit switch ports (ports 0 to 7) are external and are connected to external PHYs - 2 switch ports (ports 8 and 9) of 2.5 G are connected (fixed links) to FMan ports (FM1@DTSEC1 and FM1@DTSEC2) Commands Overview: ============= Commands supported - enable/disable a port - check a port's link speed, duplexity and status. Commands syntax ethsw port <port_nr> enable|disable - enable/disable an l2 switch port ethsw port <port_nr> show - show an l2 switch port's configuration port_nr=0..9; use "all" for all ports => ethsw port all show Port Status Link Speed Duplex 0 enabled down 10 half 1 enabled down 10 half 2 enabled down 10 half 3 enabled up 1000 full 4 disabled down - half 5 disabled down - half 6 disabled down - half 7 disabled down - half 8 enabled up 2500 full 9 enabled up 2500 full => Changes for v2: - split the bug fix from the implementation of SerDes protocols of L2 Switch ports patch; - added debug messages if MDIO reads or writes timeout; - added debug messages when reset of VSC9953 switch fails; - replaced Copyright and license to the generic one; - added patch descriptions; Changes for v3: - replaced the arrays type from 'int' to 'u8' int the fix for mapping of Freescale SerDes protocols; - removed "Change-id" lines from almost all the patches; Codrin Ciubotariu (11): net/fm: Fix error when FMAN MAC has no PHY arch/powerpc: Fix mapping of Freescale SerDes protocols arch/powerpc: Add SGMII support for the L2 Switch ports net/fm: Enable FMAN ports if l2switch ports are connected over SGMII net/vsc9953: Add driver for Vitesse VSC9953 L2 Switch IP arch/powerpc: Enable VSC9953 driver on T1040 and T1020 board/T1040qds: Fix lane-to-slot mapping for SerDes protocol 0x89 board/T1040qds: T1040 FMAN ports FM1@DTSEC1 and FM1@DTSEC2 have no PHYs board/T104xrdb: T1040 FMAN ports FM1@DTSEC1 and FM1@DTSEC2 have no PHYs board/T1040qds: Add VSC9953 support for T1040qds board board/T1040rdb: Add VSC9953 support for T1040rdb board arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c | 73 ++-- arch/powerpc/cpu/mpc85xx/t1040_serdes.c | 8 +- arch/powerpc/cpu/mpc8xxx/cpu.c | 5 + arch/powerpc/include/asm/config_mpc85xx.h | 3 + arch/powerpc/include/asm/fsl_serdes.h | 7 + board/freescale/t1040qds/eth.c | 93 +++++ board/freescale/t104xrdb/eth.c | 59 ++- doc/README.t1040-l2switch | 49 +++ drivers/net/Makefile | 1 + drivers/net/fm/eth.c | 30 +- drivers/net/fm/t1040.c | 3 +- drivers/net/vsc9953.c | 497 +++++++++++++++++++++++++ include/configs/T1040QDS.h | 4 + include/configs/T104xRDB.h | 6 + include/vsc9953.h | 402 ++++++++++++++++++++ 15 files changed, 1191 insertions(+), 49 deletions(-) create mode 100644 doc/README.t1040-l2switch create mode 100644 drivers/net/vsc9953.c create mode 100644 include/vsc9953.h -- 1.7.11.7

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[U-Boot] [PATCH] phylib: add support for aquantia PHYs
by shh.xie＠gmail.com 23 Jan '15

23 Jan '15

From: Shaohui Xie <Shaohui.Xie(a)freescale.com> This patch supports AQ1202, AQ2104, AQR105 PHY. Signed-off-by: Shaohui Xie <Shaohui.Xie(a)freescale.com> --- drivers/net/phy/Makefile | 1 + drivers/net/phy/aquantia.c | 156 +++++++++++++++++++++++++++++++++++++++++++++ drivers/net/phy/phy.c | 3 + include/phy.h | 1 + 4 files changed, 161 insertions(+) create mode 100644 drivers/net/phy/aquantia.c diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index 9556536..87d5c9c 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_MV88E6352_SWITCH) += mv88e6352.o obj-$(CONFIG_PHYLIB) += phy.o obj-$(CONFIG_PHYLIB_10G) += generic_10g.o +obj-$(CONFIG_PHY_AQUANTIA) += aquantia.o obj-$(CONFIG_PHY_ATHEROS) += atheros.o obj-$(CONFIG_PHY_BROADCOM) += broadcom.o obj-$(CONFIG_PHY_DAVICOM) += davicom.o diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c new file mode 100644 index 0000000..ef4da4e --- /dev/null +++ b/drivers/net/phy/aquantia.c @@ -0,0 +1,156 @@ +/* + * Aquantia PHY drivers + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Copyright 2014 Freescale Semiconductor, Inc. + */ +#include <config.h> +#include <common.h> +#include <phy.h> + +#ifndef CONFIG_PHYLIB_10G +#error The Aquantia PHY needs 10G support +#endif + +#define AQUNTIA_10G_CTL 0x20 +#define AQUNTIA_VENDOR_P1 0xc400 + +#define AQUNTIA_SPEED_LSB_MASK 0x2000 +#define AQUNTIA_SPEED_MSB_MASK 0x40 + +int aquantia_config(struct phy_device *phydev) +{ + u32 val = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR); + + if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { + /* 1000BASE-T mode */ + phydev->advertising = SUPPORTED_1000baseT_Full; + phydev->supported = phydev->advertising; + + val = (val & ~AQUNTIA_SPEED_LSB_MASK) | AQUNTIA_SPEED_MSB_MASK; + phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val); + } else if (phydev->interface == PHY_INTERFACE_MODE_XGMII) { + /* 10GBASE-T mode */ + phydev->advertising = SUPPORTED_10000baseT_Full; + phydev->supported = phydev->advertising; + + if (!(val & AQUNTIA_SPEED_LSB_MASK) || + !(val & AQUNTIA_SPEED_MSB_MASK)) + phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, + AQUNTIA_SPEED_LSB_MASK | + AQUNTIA_SPEED_MSB_MASK); + } else if (phydev->interface == PHY_INTERFACE_MODE_SGMII_2500) { + /* 2.5GBASE-T mode */ + phydev->advertising = SUPPORTED_1000baseT_Full; + phydev->supported = phydev->advertising; + + phy_write(phydev, MDIO_MMD_AN, AQUNTIA_10G_CTL, 1); + phy_write(phydev, MDIO_MMD_AN, AQUNTIA_VENDOR_P1, 0x9440); + } else if (phydev->interface == PHY_INTERFACE_MODE_MII) { + /* 100BASE-TX mode */ + phydev->advertising = SUPPORTED_100baseT_Full; + phydev->supported = phydev->advertising; + + val = (val & ~AQUNTIA_SPEED_MSB_MASK) | AQUNTIA_SPEED_LSB_MASK; + phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val); + } + return 0; +} + +int aquantia_startup(struct phy_device *phydev) +{ + u32 reg, speed; + int i = 0; + + phydev->duplex = DUPLEX_FULL; + + /* if the AN is still in progress, wait till timeout. */ + phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1); + reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1); + if (!(reg & MDIO_AN_STAT1_COMPLETE)) { + printf("%s Waiting for PHY auto negotiation to complete", + phydev->dev->name); + do { + udelay(1000); + reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1); + if ((i++ % 500) == 0) + printf("."); + } while (!(reg & MDIO_AN_STAT1_COMPLETE) && + i < (4 * PHY_ANEG_TIMEOUT)); + + if (i > PHY_ANEG_TIMEOUT) + printf(" TIMEOUT !\n"); + } + + /* Read twice because link state is latched and a + * read moves the current state into the register */ + phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1); + reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1); + if (reg < 0 || !(reg & MDIO_STAT1_LSTATUS)) + phydev->link = 0; + else + phydev->link = 1; + + speed = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR); + if (speed & AQUNTIA_SPEED_MSB_MASK) { + if (speed & AQUNTIA_SPEED_LSB_MASK) + phydev->speed = SPEED_10000; + else + phydev->speed = SPEED_1000; + } else { + if (speed & AQUNTIA_SPEED_LSB_MASK) + phydev->speed = SPEED_100; + else + phydev->speed = SPEED_10; + } + + return 0; +} + +struct phy_driver aq1202_driver = { + .name = "Aquantia AQ1202", + .uid = 0x3a1b445, + .mask = 0xfffffff0, + .features = PHY_10G_FEATURES, + .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS| + MDIO_MMD_PHYXS | MDIO_MMD_AN | + MDIO_MMD_VEND1), + .config = &aquantia_config, + .startup = &aquantia_startup, + .shutdown = &gen10g_shutdown, +}; + +struct phy_driver aq2104_driver = { + .name = "Aquantia AQ2104", + .uid = 0x3a1b460, + .mask = 0xfffffff0, + .features = PHY_10G_FEATURES, + .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS| + MDIO_MMD_PHYXS | MDIO_MMD_AN | + MDIO_MMD_VEND1), + .config = &aquantia_config, + .startup = &aquantia_startup, + .shutdown = &gen10g_shutdown, +}; + +struct phy_driver aqr105_driver = { + .name = "Aquantia AQR105", + .uid = 0x3a1b4a2, + .mask = 0xfffffff0, + .features = PHY_10G_FEATURES, + .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS| + MDIO_MMD_PHYXS | MDIO_MMD_AN | + MDIO_MMD_VEND1), + .config = &aquantia_config, + .startup = &aquantia_startup, + .shutdown = &gen10g_shutdown, +}; +int phy_aquantia_init(void) +{ + phy_register(&aq1202_driver); + phy_register(&aq2104_driver); + phy_register(&aqr105_driver); + + return 0; +} diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index 1d6c14f..7b75f85 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -442,6 +442,9 @@ static LIST_HEAD(phy_drivers); int phy_init(void) { +#ifdef CONFIG_PHY_AQUANTIA + phy_aquantia_init(); +#endif #ifdef CONFIG_PHY_ATHEROS phy_atheros_init(); #endif diff --git a/include/phy.h b/include/phy.h index 2fcc328..c84a441 100644 --- a/include/phy.h +++ b/include/phy.h @@ -221,6 +221,7 @@ int gen10g_startup(struct phy_device *phydev); int gen10g_shutdown(struct phy_device *phydev); int gen10g_discover_mmds(struct phy_device *phydev); +int phy_aquantia_init(void); int phy_atheros_init(void); int phy_broadcom_init(void); int phy_davicom_init(void); -- 2.1.0.27.g96db324

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[U-Boot] [PATCH] mpc85xx: clean up the old deep sleep framework
by Tang Yuantian 23 Jan '15

23 Jan '15

All the boards that support deep sleep feature are converted to deep sleep generic board interface. The old interface which support non-generic board is not used anymore. So clean it up. Signed-off-by: Tang Yuantian <Yuantian.Tang(a)freescale.com> --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 10 +--------- arch/powerpc/lib/board.c | 21 --------------------- 2 files changed, 1 insertion(+), 30 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 85d32fc..4cf8853 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -424,7 +424,6 @@ void fsl_erratum_a007212_workaround(void) ulong cpu_init_f(void) { - ulong flag = 0; extern void m8560_cpm_reset (void); #if defined(CONFIG_SYS_DCSRBAR_PHYS) || \ (defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET)) @@ -499,18 +498,11 @@ ulong cpu_init_f(void) in_be32(&gur->dcsrcr); #endif -#ifdef CONFIG_SYS_DCSRBAR_PHYS -#ifdef CONFIG_DEEP_SLEEP - /* disable the console if boot from deep sleep */ - if (in_be32(&gur->scrtsr[0]) & (1 << 3)) - flag = GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; -#endif -#endif #ifdef CONFIG_SYS_FSL_ERRATUM_A007212 fsl_erratum_a007212_workaround(); #endif - return flag; + return 0; } /* Implement a dummy function for those platforms w/o SERDES */ diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c index e6d5355..91645d3 100644 --- a/arch/powerpc/lib/board.c +++ b/arch/powerpc/lib/board.c @@ -346,13 +346,6 @@ void board_init_f(ulong bootflag) #ifdef CONFIG_PRAM ulong reg; #endif -#ifdef CONFIG_DEEP_SLEEP - const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - struct ccsr_scfg *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG; - u32 start_addr; - typedef void (*func_t)(void); - func_t kernel_resume; -#endif /* Pointer is writable since we allocated a register for it */ gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); @@ -372,20 +365,6 @@ void board_init_f(ulong bootflag) if ((*init_fnc_ptr) () != 0) hang(); -#ifdef CONFIG_DEEP_SLEEP - /* Jump to kernel in deep sleep case */ - if (in_be32(&gur->scrtsr[0]) & (1 << 3)) { - l2cache_init(); -#if defined(CONFIG_RAMBOOT_PBL) - disable_cpc_sram(); -#endif - enable_cpc(); - start_addr = in_be32(&scfg->sparecr[1]); - kernel_resume = (func_t)start_addr; - kernel_resume(); - } -#endif - #ifdef CONFIG_POST post_bootmode_init(); post_run(NULL, POST_ROM | post_bootmode_get(NULL)); -- 2.1.0.27.g96db324

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