January 2015 - U-Boot

[U-Boot] [PATCH] mpc85xx/t1040qds: convert deep sleep to generic board interface
by Tang Yuantian 23 Jan '15

23 Jan '15

A new deep sleep interface is introduced to support generic board structure. Converts it to use new interface. Signed-off-by: Tang Yuantian <Yuantian.Tang(a)freescale.com> --- board/freescale/t1040qds/ddr.c | 19 +++++++++++++++++++ board/freescale/t1040qds/t1040qds.c | 23 +++++++++++------------ include/configs/T1040QDS.h | 3 +++ 3 files changed, 33 insertions(+), 12 deletions(-) diff --git a/board/freescale/t1040qds/ddr.c b/board/freescale/t1040qds/ddr.c index 43f952f..8240240 100644 --- a/board/freescale/t1040qds/ddr.c +++ b/board/freescale/t1040qds/ddr.c @@ -11,6 +11,7 @@ #include <fsl_ddr_sdram.h> #include <fsl_ddr_dimm_params.h> #include <asm/fsl_law.h> +#include <asm/mpc85xx_gpio.h> #include "ddr.h" DECLARE_GLOBAL_DATA_PTR; @@ -100,6 +101,19 @@ found: #endif } +#if defined(CONFIG_DEEP_SLEEP) +void board_mem_sleep_setup(void) +{ + void __iomem *qixis_base = (void *)QIXIS_BASE; + + /* does not provide HW signals for power management */ + clrbits_8(qixis_base + 0x21, 0x2); + /* Disable MCKE isolation */ + gpio_set_value(2, 0); + udelay(1); +} +#endif + phys_size_t initdram(int board_type) { phys_size_t dram_size; @@ -112,5 +126,10 @@ phys_size_t initdram(int board_type) dram_size *= 0x100000; puts(" DDR: "); + +#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD) + fsl_dp_resume(); +#endif + return dram_size; } diff --git a/board/freescale/t1040qds/t1040qds.c b/board/freescale/t1040qds/t1040qds.c index 13285be..eaca57f 100644 --- a/board/freescale/t1040qds/t1040qds.c +++ b/board/freescale/t1040qds/t1040qds.c @@ -19,8 +19,8 @@ #include <asm/fsl_liodn.h> #include <fm_eth.h> #include <hwconfig.h> -#include <asm/mpc85xx_gpio.h> +#include "../common/sleep.h" #include "../common/qixis.h" #include "t1040qds.h" #include "t1040qds_qixis.h" @@ -115,6 +115,16 @@ static void qe_board_setup(void) } } +int board_early_init_f(void) +{ +#if defined(CONFIG_DEEP_SLEEP) + if (is_warm_boot()) + fsl_dp_disable_console(); +#endif + + return 0; +} + int board_early_init_r(void) { #ifdef CONFIG_SYS_FLASH_BASE @@ -281,14 +291,3 @@ int board_need_mem_reset(void) { return 1; } - -#ifdef CONFIG_DEEP_SLEEP -void board_mem_sleep_setup(void) -{ - /* does not provide HW signals for power management */ - QIXIS_WRITE(pwr_ctl[1], (QIXIS_READ(pwr_ctl[1]) & ~0x2)); - /* Disable MCKE isolation */ - gpio_set_value(2, 0); - udelay(1); -} -#endif diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index b70bdfe..5ebc870 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -47,7 +47,10 @@ /* support deep sleep */ #define CONFIG_DEEP_SLEEP +#if defined(CONFIG_DEEP_SLEEP) #define CONFIG_SILENT_CONSOLE +#define CONFIG_BOARD_EARLY_INIT_F +#endif #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0xeff40000 -- 2.1.0.27.g96db324

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[U-Boot] [PATCH] mpc85xx/t102xqds: convert deep sleep to generic board interface
by Tang Yuantian 23 Jan '15

23 Jan '15

A new deep sleep interface is introduced to support generic board structure. Converts it to use new interface. Signed-off-by: Tang Yuantian <Yuantian.Tang(a)freescale.com> --- board/freescale/t102xqds/ddr.c | 19 +++++++++++++++++++ board/freescale/t102xqds/t102xqds.c | 23 +++++++++++------------ include/configs/T102xQDS.h | 3 +++ 3 files changed, 33 insertions(+), 12 deletions(-) diff --git a/board/freescale/t102xqds/ddr.c b/board/freescale/t102xqds/ddr.c index 46fc64e..2d4d10f 100644 --- a/board/freescale/t102xqds/ddr.c +++ b/board/freescale/t102xqds/ddr.c @@ -11,6 +11,7 @@ #include <fsl_ddr_sdram.h> #include <fsl_ddr_dimm_params.h> #include <asm/fsl_law.h> +#include <asm/mpc85xx_gpio.h> DECLARE_GLOBAL_DATA_PTR; @@ -152,6 +153,19 @@ found: #endif } +#if defined(CONFIG_DEEP_SLEEP) +void board_mem_sleep_setup(void) +{ + void __iomem *qixis_base = (void *)QIXIS_BASE; + + /* does not provide HW signals for power management */ + clrbits_8(qixis_base + 0x21, 0x2); + /* Disable MCKE isolation */ + gpio_set_value(2, 0); + udelay(1); +} +#endif + phys_size_t initdram(int board_type) { phys_size_t dram_size; @@ -166,5 +180,10 @@ phys_size_t initdram(int board_type) /* DDR has been initialised by first stage boot loader */ dram_size = fsl_ddr_sdram_size(); #endif + +#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD) + fsl_dp_resume(); +#endif + return dram_size; } diff --git a/board/freescale/t102xqds/t102xqds.c b/board/freescale/t102xqds/t102xqds.c index f3141b5..708afca 100644 --- a/board/freescale/t102xqds/t102xqds.c +++ b/board/freescale/t102xqds/t102xqds.c @@ -19,10 +19,10 @@ #include <asm/fsl_liodn.h> #include <fm_eth.h> #include <hwconfig.h> -#include <asm/mpc85xx_gpio.h> #include "../common/qixis.h" #include "t102xqds.h" #include "t102xqds_qixis.h" +#include "../common/sleep.h" DECLARE_GLOBAL_DATA_PTR; @@ -242,6 +242,16 @@ void board_retimer_ds125df111_init(void) i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1); } +int board_early_init_f(void) +{ +#if defined(CONFIG_DEEP_SLEEP) + if (is_warm_boot()) + fsl_dp_disable_console(); +#endif + + return 0; +} + int board_early_init_r(void) { #ifdef CONFIG_SYS_FLASH_BASE @@ -395,14 +405,3 @@ void qixis_dump_switch(void) printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1])); } } - -#ifdef CONFIG_DEEP_SLEEP -void board_mem_sleep_setup(void) -{ - /* does not provide HW signals for power management */ - QIXIS_WRITE(pwr_ctl[1], (QIXIS_READ(pwr_ctl[1]) & ~0x2)); - /* Disable MCKE isolation */ - gpio_set_value(2, 0); - udelay(1); -} -#endif diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h index c2bdbb9..3f02ced 100644 --- a/include/configs/T102xQDS.h +++ b/include/configs/T102xQDS.h @@ -35,7 +35,10 @@ #define CONFIG_ENV_OVERWRITE #define CONFIG_DEEP_SLEEP +#if defined(CONFIG_DEEP_SLEEP) #define CONFIG_SILENT_CONSOLE +#define CONFIG_BOARD_EARLY_INIT_F +#endif #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg -- 2.1.0.27.g96db324

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[U-Boot] [PATCH] powerpc/t1024rdb: Add support for T1024RDB-PB
by Shengzhou Liu 23 Jan '15

23 Jan '15

T1024RDB-PB board adds 2.5G SGMII support with AQR105 PHY. rcw_0x095 is used for 10G XFI + 3x PCIex1 rcw_0x135 is used for 2.5G SGMII + 2x PCIex1 Signed-off-by: Shengzhou Liu <Shengzhou.Liu(a)freescale.com> --- based on u-boot-fsl-qoriq.git, master branch board/freescale/t102xrdb/cpld.h | 4 ++++ board/freescale/t102xrdb/eth_t102xrdb.c | 30 +++++++++++++++++++++++++++--- board/freescale/t102xrdb/t102xrdb.c | 31 ++++++++++++++++++++++++++++++- include/configs/T102xRDB.h | 2 ++ 4 files changed, 63 insertions(+), 4 deletions(-) diff --git a/board/freescale/t102xrdb/cpld.h b/board/freescale/t102xrdb/cpld.h index 5a3100f..db50f81 100644 --- a/board/freescale/t102xrdb/cpld.h +++ b/board/freescale/t102xrdb/cpld.h @@ -43,3 +43,7 @@ void cpld_write(unsigned int reg, u8 value); #define CPLD_LBMAP_RESET 0xFF #define CPLD_LBMAP_SHIFT 0x03 #define CPLD_BOOT_SEL 0x80 + +#define CPLD_PCIE_SGMII_MUX 0x80 +#define CPLD_OVERRIDE_BOOT_EN 0x01 +#define CPLD_OVERRIDE_MUX_EN 0x02 /* PCIE/2.5G-SGMII mux override enable */ diff --git a/board/freescale/t102xrdb/eth_t102xrdb.c b/board/freescale/t102xrdb/eth_t102xrdb.c index 2e400c4..f611ff0 100644 --- a/board/freescale/t102xrdb/eth_t102xrdb.c +++ b/board/freescale/t102xrdb/eth_t102xrdb.c @@ -21,6 +21,7 @@ #include <phy.h> #include <asm/fsl_dtsec.h> #include <asm/fsl_serdes.h> +#include "../common/fman.h" int board_eth_init(bd_t *bis) { @@ -51,15 +52,22 @@ int board_eth_init(bd_t *bis) /* Register the 10G MDIO bus */ fm_memac_mdio_init(bis, &tgec_mdio_info); - /* Set the two on-board RGMII PHY address */ - fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR); + /* Set the on-board RGMII PHY address */ fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR); switch (srds_s1) { case 0x95: - /* 10G XFI with Aquantia PHY */ + /* set the on-board RGMII2 PHY */ + fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR); + + /* set 10G XFI with Aquantia AQR105 PHY */ fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); break; + case 0x77: + case 0x135: + /* set the on-board 2.5G SGMII AQR105 PHY */ + fm_info_set_phy_address(FM1_DTSEC3, SGMII_PHY1_ADDR); + break; default: printf("SerDes protocol 0x%x is not supported on T102xRDB\n", srds_s1); @@ -73,6 +81,10 @@ int board_eth_init(bd_t *bis) dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); fm_info_set_mdio(i, dev); break; + case PHY_INTERFACE_MODE_SGMII_2500: + dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); + fm_info_set_mdio(i, dev); + break; default: break; } @@ -95,6 +107,18 @@ int board_eth_init(bd_t *bis) return pci_eth_init(bis); } +void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, + enum fm_port port, int offset) +{ + if ((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) && + (port == FM1_DTSEC3)) { + fdt_set_phy_handle(fdt, compat, addr, "sg_2500_aqr105_phy4"); + fdt_setprop(fdt, offset, "phy-connection-type", + "sgmii-2500", 10); + fdt_status_disabled_by_alias(fdt, "xg_aqr105_phy3"); + } +} + void fdt_fixup_board_enet(void *fdt) { } diff --git a/board/freescale/t102xrdb/t102xrdb.c b/board/freescale/t102xrdb/t102xrdb.c index f5c438d..9676577 100644 --- a/board/freescale/t102xrdb/t102xrdb.c +++ b/board/freescale/t102xrdb/t102xrdb.c @@ -27,6 +27,11 @@ int checkboard(void) { struct cpu_type *cpu = gd->arch.cpu; static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"}; + ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 srds_s1; + + srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL; + srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; printf("Board: %sRDB, ", cpu->name); printf("Board rev: 0x%02x CPLD ver: 0x%02x, boot from ", @@ -50,11 +55,34 @@ int checkboard(void) #endif puts("SERDES Reference Clocks:\n"); - printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]); + if (srds_s1 == 0x95) + printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]); + else + printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[0], freq[0]); return 0; } +static void board_mux_lane(void) +{ + ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 srds_prtcl_s1; + u8 reg = CPLD_READ(misc_ctl_status); + + srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS1_PRTCL; + srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; + + if (srds_prtcl_s1 == 0x95) { + /* Route Lane B to PCIE */ + CPLD_WRITE(misc_ctl_status, reg & ~CPLD_PCIE_SGMII_MUX); + } else { + /* Route Lane B to SGMII */ + CPLD_WRITE(misc_ctl_status, reg | CPLD_PCIE_SGMII_MUX); + } + CPLD_WRITE(boot_override, CPLD_OVERRIDE_MUX_EN); +} + int board_early_init_r(void) { #ifdef CONFIG_SYS_FLASH_BASE @@ -86,6 +114,7 @@ int board_early_init_r(void) #ifdef CONFIG_SYS_DPAA_QBMAN setup_portals(); #endif + board_mux_lane(); return 0; } diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 6f1fcd6..9e71836 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -743,8 +743,10 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_FMAN_ENET #define CONFIG_PHYLIB_10G #define CONFIG_PHY_REALTEK +#define CONFIG_PHY_AQUANTIA #define RGMII_PHY1_ADDR 0x2 #define RGMII_PHY2_ADDR 0x6 +#define SGMII_PHY1_ADDR 0x2 #define FM1_10GEC1_PHY_ADDR 0x1 #endif -- 1.8.0

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[U-Boot] [PATCH] mpc85xx/t102xrdb: convert deep sleep to generic board interface
by Tang Yuantian 23 Jan '15

23 Jan '15

A new deep sleep interface is introduced to support generic board structure. Converts it to use new interface. Besides, added SPI/SD/NAND boot deep sleep support. Signed-off-by: Tang Yuantian <Yuantian.Tang(a)freescale.com> --- board/freescale/t102xrdb/ddr.c | 19 +++++++++++++++++++ board/freescale/t102xrdb/spl.c | 7 +++++++ board/freescale/t102xrdb/t102xrdb.c | 23 +++++++++++------------ include/configs/T102xRDB.h | 21 ++++++++++++--------- 4 files changed, 49 insertions(+), 21 deletions(-) diff --git a/board/freescale/t102xrdb/ddr.c b/board/freescale/t102xrdb/ddr.c index a20330b..a2a8f4c 100644 --- a/board/freescale/t102xrdb/ddr.c +++ b/board/freescale/t102xrdb/ddr.c @@ -11,6 +11,7 @@ #include <fsl_ddr_sdram.h> #include <fsl_ddr_dimm_params.h> #include <asm/fsl_law.h> +#include <asm/mpc85xx_gpio.h> DECLARE_GLOBAL_DATA_PTR; @@ -136,6 +137,19 @@ found: #endif } +#if defined(CONFIG_DEEP_SLEEP) +void board_mem_sleep_setup(void) +{ + void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE; + + /* does not provide HW signals for power management */ + clrbits_8(cpld_base + 0x17, 0x40); + /* Disable MCKE isolation */ + gpio_set_value(2, 0); + udelay(1); +} +#endif + phys_size_t initdram(int board_type) { phys_size_t dram_size; @@ -150,5 +164,10 @@ phys_size_t initdram(int board_type) /* DDR has been initialised by first stage boot loader */ dram_size = fsl_ddr_sdram_size(); #endif + +#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD) + fsl_dp_resume(); +#endif + return dram_size; } diff --git a/board/freescale/t102xrdb/spl.c b/board/freescale/t102xrdb/spl.c index dd2dec4..1a3a996 100644 --- a/board/freescale/t102xrdb/spl.c +++ b/board/freescale/t102xrdb/spl.c @@ -11,6 +11,7 @@ #include <mmc.h> #include <fsl_esdhc.h> #include <spi_flash.h> +#include "../common/sleep.h" DECLARE_GLOBAL_DATA_PTR; @@ -42,6 +43,12 @@ void board_init_f(ulong bootflag) console_init_f(); +#ifdef CONFIG_DEEP_SLEEP + /* disable the console if boot from deep sleep */ + if (is_warm_boot()) + fsl_dp_disable_console(); +#endif + /* initialize selected port with appropriate baud rate */ sys_clk = get_board_sys_clk(); plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; diff --git a/board/freescale/t102xrdb/t102xrdb.c b/board/freescale/t102xrdb/t102xrdb.c index f5c438d..96457cf 100644 --- a/board/freescale/t102xrdb/t102xrdb.c +++ b/board/freescale/t102xrdb/t102xrdb.c @@ -16,10 +16,10 @@ #include <asm/fsl_serdes.h> #include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> -#include <asm/mpc85xx_gpio.h> #include <fm_eth.h> #include "t102xrdb.h" #include "cpld.h" +#include "../common/sleep.h" DECLARE_GLOBAL_DATA_PTR; @@ -55,6 +55,16 @@ int checkboard(void) return 0; } +int board_early_init_f(void) +{ +#if defined(CONFIG_DEEP_SLEEP) + if (is_warm_boot()) + fsl_dp_disable_console(); +#endif + + return 0; +} + int board_early_init_r(void) { #ifdef CONFIG_SYS_FLASH_BASE @@ -131,14 +141,3 @@ int ft_board_setup(void *blob, bd_t *bd) return 0; } - -#ifdef CONFIG_DEEP_SLEEP -void board_mem_sleep_setup(void) -{ - /* does not provide HW signals for power management */ - CPLD_WRITE(misc_ctl_status, (CPLD_READ(misc_ctl_status) & ~0x40)); - /* Disable MCKE isolation */ - gpio_set_value(2, 0); - udelay(1); -} -#endif diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 82b669b..e6222f3 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -36,7 +36,10 @@ /* support deep sleep */ #define CONFIG_DEEP_SLEEP +#if defined(CONFIG_DEEP_SLEEP) #define CONFIG_SILENT_CONSOLE +#define CONFIG_BOARD_EARLY_INIT_F +#endif #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg @@ -51,7 +54,7 @@ #define CONFIG_SPL_I2C_SUPPORT #define CONFIG_SPL_DRIVERS_MISC_SUPPORT #define CONFIG_FSL_LAW /* Use common FSL init code */ -#define CONFIG_SYS_TEXT_BASE 0x00201000 +#define CONFIG_SYS_TEXT_BASE 0x30001000 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 #define CONFIG_SPL_PAD_TO 0x40000 #define CONFIG_SPL_MAX_SIZE 0x28000 @@ -67,21 +70,21 @@ #ifdef CONFIG_NAND #define CONFIG_SPL_NAND_SUPPORT #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 -#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 +#define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 +#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" #define CONFIG_SPL_NAND_BOOT #endif #ifdef CONFIG_SPIFLASH -#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC +#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC #define CONFIG_SPL_SPI_SUPPORT #define CONFIG_SPL_SPI_FLASH_SUPPORT #define CONFIG_SPL_SPI_FLASH_MINIMAL #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" #ifndef CONFIG_SPL_BUILD @@ -91,12 +94,12 @@ #endif #ifdef CONFIG_SDCARD -#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC +#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC #define CONFIG_SPL_MMC_SUPPORT #define CONFIG_SPL_MMC_MINIMAL #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) -#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) +#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) +#define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" #ifndef CONFIG_SPL_BUILD -- 2.1.0.27.g96db324

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[U-Boot] [PATCH] t1024qds: add missing T1024QDS_defconfig
by Shengzhou Liu 23 Jan '15

23 Jan '15

Add missing T1024QDS_defconfig for NOR boot on T1024QDS. Signed-off-by: Shengzhou Liu <Shengzhou.Liu(a)freescale.com> --- configs/T1024QDS_defconfig | 4 ++++ 1 file changed, 4 insertions(+) create mode 100644 configs/T1024QDS_defconfig diff --git a/configs/T1024QDS_defconfig b/configs/T1024QDS_defconfig new file mode 100644 index 0000000..94a76ba --- /dev/null +++ b/configs/T1024QDS_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T102XQDS=y -- 1.8.0

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[U-Boot] [PATCH v2] powerpc/t1024: add serdes protocol 0x40 and 0x5f
by Shengzhou Liu 23 Jan '15

23 Jan '15

Add serdes protocol 0x40 and 0x5f. Signed-off-by: Shengzhou Liu <Shengzhou.Liu(a)freescale.com> --- v2: fix a typo. arch/powerpc/cpu/mpc85xx/t1024_serdes.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/powerpc/cpu/mpc85xx/t1024_serdes.c b/arch/powerpc/cpu/mpc85xx/t1024_serdes.c index 7dc8385..2ba314a 100644 --- a/arch/powerpc/cpu/mpc85xx/t1024_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/t1024_serdes.c @@ -11,6 +11,7 @@ static u8 serdes_cfg_tbl[][4] = { + [0x40] = {PCIE1, PCIE1, PCIE1, PCIE1}, [0xD5] = {QSGMII_FM1_A, PCIE3, PCIE2, PCIE1}, [0xD6] = {QSGMII_FM1_A, PCIE3, PCIE2, SATA1}, [0x95] = {XFI_FM1_MAC1, PCIE3, PCIE2, PCIE1}, @@ -20,6 +21,7 @@ static u8 serdes_cfg_tbl[][4] = { [0x56] = {PCIE1, PCIE3, PCIE2, SATA1}, [0x5A] = {PCIE1, PCIE3, SGMII_FM1_DTSEC2, SATA1}, [0x5B] = {PCIE1, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC1}, + [0x5F] = {PCIE1, PCIE3, SGMII_2500_FM1_DTSEC2, SGMII_2500_FM1_DTSEC1}, [0x6A] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC2, SATA1}, [0x6B] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC1}, [0x6F] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_2500_FM1_DTSEC2, -- 1.8.0

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[U-Boot] [PATCH] powerpc: SECURE BOOT- Add secure boot target for T1042RDB
by Gaurav Rana 23 Jan '15

23 Jan '15

Secure boot target is added for T1042RDB platform. Signed-off-by: Gaurav Rana <gaurav.rana(a)freescale.com> --- board/freescale/t104xrdb/MAINTAINERS | 1 + configs/T1042RDB_SECURE_BOOT_defconfig | 4 ++++ 2 files changed, 5 insertions(+) create mode 100644 configs/T1042RDB_SECURE_BOOT_defconfig diff --git a/board/freescale/t104xrdb/MAINTAINERS b/board/freescale/t104xrdb/MAINTAINERS index b61e1c0..13d9be9 100644 --- a/board/freescale/t104xrdb/MAINTAINERS +++ b/board/freescale/t104xrdb/MAINTAINERS @@ -21,3 +21,4 @@ T1040RDB_SECURE_BOOT BOARD M: Aneesh Bansal <aneesh.bansal(a)freescale.com> S: Maintained F: configs/T1040RDB_SECURE_BOOT_defconfig +F: configs/T1042RDB_SECURE_BOOT_defconfig diff --git a/configs/T1042RDB_SECURE_BOOT_defconfig b/configs/T1042RDB_SECURE_BOOT_defconfig new file mode 100644 index 0000000..c8dd5c2 --- /dev/null +++ b/configs/T1042RDB_SECURE_BOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,SECURE_BOOT,T1042RDB" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T104XRDB=y -- 1.8.1.4

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[U-Boot] [PATCH] powerpc/913x: Add config flag for bootdelay
by Harninder Rai 23 Jan '15

23 Jan '15

Signed-off-by: Harninder Rai <harninder.rai(a)freescale.com> --- include/configs/BSC9131RDB.h | 1 + include/configs/BSC9132QDS.h | 1 + 2 files changed, 2 insertions(+), 0 deletions(-) diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h index adb8146..6f1022e 100644 --- a/include/configs/BSC9131RDB.h +++ b/include/configs/BSC9131RDB.h @@ -430,6 +430,7 @@ extern unsigned long get_sdram_size(void); #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ #define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTDELAY 10 /* -1 disable auto-boot */ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h index 2722a32..66ca461 100644 --- a/include/configs/BSC9132QDS.h +++ b/include/configs/BSC9132QDS.h @@ -672,6 +672,7 @@ combinations. this should be removed later #define CONFIG_UBOOTPATH "u-boot.bin" #define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTDELAY 10 /* -1 disable auto-boot */ #ifdef CONFIG_SDCARD #define CONFIG_DEF_HWCONFIG "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" -- 1.7.6.GIT

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[U-Boot] [PATCH] powerpc/mpc85xx: Define PBI Flash Base for C29XPCIE Secure Boot
by Aneesh Bansal 23 Jan '15

23 Jan '15

CONFIG_SYS_PBI_FLASH_BASE is defined for Secure Boot on C29X Signed-off-by: Aneesh Bansal <aneesh.bansal(a)freescale.com> --- arch/powerpc/include/asm/fsl_secure_boot.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 14c6fc3..b4c0c99 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -12,6 +12,8 @@ #define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000 #elif defined(CONFIG_BSC9132QDS) #define CONFIG_SYS_PBI_FLASH_BASE 0xc8000000 +#elif defined(CONFIG_C29XPCIE) +#define CONFIG_SYS_PBI_FLASH_BASE 0xcc000000 #else #define CONFIG_SYS_PBI_FLASH_BASE 0xce000000 #endif -- 1.8.1.4

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[U-Boot] [PATCH] b4860: Correct LIODN assignment for PCIe
by Laurentiu Tudor 23 Jan '15

23 Jan '15

For B4 the LIODN register for PCIe is in PCIe address space and not in GUTs Signed-off-by: Poonam Aggrwal <poonam.aggrwal(a)freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi(a)freescale.com> Signed-off-by: Shaveta Leekha <shaveta(a)freescale.com> Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor(a)freescale.com> Reviewed-by: Zang Tiefei <tie-fei.zang(a)freescale.com> Reviewed-by: Yusong Sun <yorksun(a)freescale.com> --- arch/powerpc/cpu/mpc85xx/b4860_ids.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/cpu/mpc85xx/b4860_ids.c b/arch/powerpc/cpu/mpc85xx/b4860_ids.c index 598f7bd..fd7f5fa 100644 --- a/arch/powerpc/cpu/mpc85xx/b4860_ids.c +++ b/arch/powerpc/cpu/mpc85xx/b4860_ids.c @@ -57,7 +57,7 @@ struct liodn_id_table liodn_tbl[] = { SET_USB_LIODN(1, "fsl-usb2-dr", 553), - SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148), + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148), SET_DMA_LIODN(1, "fsl,elo3-dma", 147), SET_DMA_LIODN(2, "fsl,elo3-dma", 227), -- 1.8.3.1

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