January 2015 - U-Boot

[U-Boot] [PATCH] arm: ls102xa: Update snoop settings for CCI-400
by Alison Wang 24 Jan '15

24 Jan '15

CAAM is connected to CCI-400 S0 slave interface. Disable snooping for S0 will cause CAAM self test failure. This patch is to enable snooping for S0 slave interface. These CCI-400 operations are moved to board_early_init_f() to be initialized earlier. For S4 slave interface, issuing of snoop requests and DVM message requests are enabled. Signed-off-by: Alison Wang <alison.wang(a)freescale.com> --- arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 ++ board/freescale/ls1021aqds/ls1021aqds.c | 21 ++++++++++++------- board/freescale/ls1021atwr/ls1021atwr.c | 25 ++++++++++++++--------- 3 files changed, 31 insertions(+), 17 deletions(-) diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 697d4ca..7287969 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -456,6 +456,8 @@ struct ccsr_ddr { #define CCI400_CTRLORD_TERM_BARRIER 0x00000008 #define CCI400_CTRLORD_EN_BARRIER 0 #define CCI400_SHAORD_NON_SHAREABLE 0x00000002 +#define CCI400_DVM_MESSAGE_REQ_EN 0x00000002 +#define CCI400_SNOOP_REQ_EN 0x00000001 /* CCI-400 registers */ struct ccsr_cci400 { diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index f08e54f..93a8028 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -188,6 +188,20 @@ int board_early_init_f(void) out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); #endif + /* + * Enable snoop requests and DVM message requests for + * Slave insterface S4 (A7 core cluster) + */ + out_le32(&cci->slave[4].snoop_ctrl, + CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); + + /* + * Set CCI-400 Slave interface S1, S2 Shareable Override Register + * All transactions are treated as non-shareable + */ + out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); + out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); + /* Workaround for the issue that DDR could not respond to * barrier transaction which is generated by executing DSB/ISB * instruction. Set CCI-400 control override register to @@ -474,13 +488,6 @@ int board_init(void) /* Set CCI-400 control override register to * enable barrier transaction */ out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); - /* - * Set CCI-400 Slave interface S0, S1, S2 Shareable Override Register - * All transactions are treated as non-shareable - */ - out_le32(&cci->slave[0].sha_ord, CCI400_SHAORD_NON_SHAREABLE); - out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); - out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index 8ab229d..c8e8bd8 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -263,6 +263,7 @@ int config_serdes_mux(void) int board_early_init_f(void) { struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; + struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; #ifdef CONFIG_TSEC_ENET out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); @@ -281,6 +282,20 @@ int board_early_init_f(void) out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); #endif + /* + * Enable snoop requests and DVM message requests for + * Slave insterface S4 (A7 core cluster) + */ + out_le32(&cci->slave[4].snoop_ctrl, + CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); + + /* + * Set CCI-400 Slave interface S1, S2 Shareable Override Register + * All transactions are treated as non-shareable + */ + out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); + out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); + return 0; } @@ -408,16 +423,6 @@ struct smmu_stream_id dev_stream_id[] = { int board_init(void) { - struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; - - /* - * Set CCI-400 Slave interface S0, S1, S2 Shareable Override Register - * All transactions are treated as non-shareable - */ - out_le32(&cci->slave[0].sha_ord, CCI400_SHAORD_NON_SHAREABLE); - out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); - out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); - #ifndef CONFIG_SYS_FSL_NO_SERDES fsl_serdes_init(); #ifndef CONFIG_QSPI_BOOT -- 2.1.0.27.g96db324

3 3

[U-Boot] [PATCH] ls102xa: dcu: Add platform support for DCU on LS1021AQDS board
by Xiubo Li 24 Jan '15

24 Jan '15

This patch adds the CH7301 HDMI options and the common configuration for DCU on LS1021AQDS board. Signed-off-by: Xiubo Li <Li.Xiubo(a)freescale.com> Signed-off-by: Alison Wang <alison.wang(a)freescale.com> Cc: Jason Jin <Jason.Jin(a)freescale.com> --- board/freescale/ls1021aqds/Makefile | 1 + board/freescale/ls1021aqds/dcu.c | 92 +++++++++++++++++++++++++++ board/freescale/ls1021aqds/ls1021aqds.c | 4 ++ board/freescale/ls1021aqds/ls1021aqds_qixis.h | 2 + include/configs/ls1021aqds.h | 20 ++++++ 5 files changed, 119 insertions(+) create mode 100644 board/freescale/ls1021aqds/dcu.c diff --git a/board/freescale/ls1021aqds/Makefile b/board/freescale/ls1021aqds/Makefile index 3b6903c..ab02344 100644 --- a/board/freescale/ls1021aqds/Makefile +++ b/board/freescale/ls1021aqds/Makefile @@ -7,3 +7,4 @@ obj-y += ls1021aqds.o obj-y += ddr.o obj-y += eth.o +obj-$(CONFIG_FSL_DCU_FB) += dcu.o diff --git a/board/freescale/ls1021aqds/dcu.c b/board/freescale/ls1021aqds/dcu.c new file mode 100644 index 0000000..90f5bc0 --- /dev/null +++ b/board/freescale/ls1021aqds/dcu.c @@ -0,0 +1,92 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * FSL DCU Framebuffer driver + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/io.h> +#include <common.h> +#include <fsl_dcu_fb.h> +#include <i2c.h> +#include "div64.h" +#include "../common/diu_ch7301.h" +#include "ls1021aqds_qixis.h" + +DECLARE_GLOBAL_DATA_PTR; + +static int select_i2c_ch_pca9547(u8 ch) +{ + int ret; + + ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); + if (ret) { + puts("PCA: failed to select proper channel\n"); + return ret; + } + + return 0; +} + +unsigned int dcu_set_pixel_clock(unsigned int pixclock) +{ + unsigned long long div; + + div = (unsigned long long)(gd->bus_clk / 1000); + div *= (unsigned long long)pixclock; + do_div(div, 1000000000); + + return div; +} + +int platform_dcu_init(unsigned int xres, unsigned int yres, + const char *port, + struct fb_videomode *dcu_fb_videomode) +{ + const char *name; + unsigned int pixel_format; + int ret; + u8 ch; + + /* Mux I2C3+I2C4 as HSYNC+VSYNC */ + ret = i2c_read(CONFIG_SYS_I2C_QIXIS_ADDR, QIXIS_DCU_BRDCFG5, + 1, &ch, 1); + if (ret) { + printf("Error: failed to read I2C @%02x\n", + CONFIG_SYS_I2C_QIXIS_ADDR); + return ret; + } + ch &= 0x1F; + ch |= 0xA0; + ret = i2c_write(CONFIG_SYS_I2C_QIXIS_ADDR, QIXIS_DCU_BRDCFG5, + 1, &ch, 1); + if (ret) { + printf("Error: failed to write I2C @%02x\n", + CONFIG_SYS_I2C_QIXIS_ADDR); + return ret; + } + + if (strncmp(port, "hdmi", 4) == 0) { + unsigned long pixval; + + name = "HDMI"; + + pixval = 1000000000 / dcu_fb_videomode->pixclock; + pixval *= 1000; + + i2c_set_bus_num(CONFIG_SYS_I2C_DVI_BUS_NUM); + select_i2c_ch_pca9547(I2C_MUX_CH_CH7301); + diu_set_dvi_encoder(pixval); + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + } else { + return 0; + } + + printf("DCU: Switching to %s monitor @ %ux%u\n", name, xres, yres); + + pixel_format = 32; + fsl_dcu_init(xres, yres, pixel_format); + + return 0; +} diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index 2bc029c..738b71e 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -194,6 +194,10 @@ int board_early_init_f(void) out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); #endif +#ifdef CONFIG_FSL_DCU_FB + out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN); +#endif + /* * Enable snoop requests and DVM message requests for * Slave insterface S4 (A7 core cluster) diff --git a/board/freescale/ls1021aqds/ls1021aqds_qixis.h b/board/freescale/ls1021aqds/ls1021aqds_qixis.h index 09b3be2..8e482eb 100644 --- a/board/freescale/ls1021aqds/ls1021aqds_qixis.h +++ b/board/freescale/ls1021aqds/ls1021aqds_qixis.h @@ -32,4 +32,6 @@ #define QIXIS_SRDS1CLK_100 0x0 +#define QIXIS_DCU_BRDCFG5 0x55 + #endif diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 5e2c0c3..2ea1134 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -402,6 +402,7 @@ unsigned long get_board_ddr_clk(void); */ #define I2C_MUX_PCA_ADDR_PRI 0x77 #define I2C_MUX_CH_DEFAULT 0x8 +#define I2C_MUX_CH_CH7301 0xC /* * MMC @@ -468,6 +469,25 @@ unsigned long get_board_ddr_clk(void); #endif /* + * Video + */ +#define CONFIG_FSL_DCU_FB + +#ifdef CONFIG_FSL_DCU_FB +#define CONFIG_VIDEO +#define CONFIG_CMD_BMP +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO + +#define CONFIG_FSL_DIU_CH7301 +#define CONFIG_SYS_I2C_DVI_BUS_NUM 0 +#define CONFIG_SYS_I2C_QIXIS_ADDR 0x66 +#define CONFIG_SYS_I2C_DVI_ADDR 0x75 +#endif + +/* * eTSEC */ #define CONFIG_TSEC_ENET -- 2.1.0.27.g96db324

2 1

[U-Boot] [PATCH] crypto/fsl: Add fixup for crypto node
by Ruchika Gupta 24 Jan '15

24 Jan '15

Era property is added in the crypto node in device tree. Move the code to do so from arch/powerpc/mpc8xxx/fdt.c to drivers/sec/sec.c so that it can be used across arm and powerpc platforms having crypto node. Signed-off-by: Ruchika Gupta <ruchika.gupta(a)freescale.com> --- arch/arm/cpu/armv7/ls102xa/fdt.c | 17 ++++ arch/powerpc/cpu/mpc8xxx/fdt.c | 170 ----------------------------------- arch/powerpc/include/asm/config.h | 1 + drivers/crypto/fsl/Makefile | 1 + drivers/crypto/fsl/sec.c | 184 ++++++++++++++++++++++++++++++++++++++ 5 files changed, 203 insertions(+), 170 deletions(-) create mode 100644 drivers/crypto/fsl/sec.c diff --git a/arch/arm/cpu/armv7/ls102xa/fdt.c b/arch/arm/cpu/armv7/ls102xa/fdt.c index 989780d..0fda694 100644 --- a/arch/arm/cpu/armv7/ls102xa/fdt.c +++ b/arch/arm/cpu/armv7/ls102xa/fdt.c @@ -15,6 +15,8 @@ #include <fsl_esdhc.h> #endif #include <tsec.h> +#include <asm/arch/immap_ls102xa.h> +#include <fsl_sec.h> DECLARE_GLOBAL_DATA_PTR; @@ -77,9 +79,24 @@ void ft_cpu_setup(void *blob, bd_t *bd) int off; int val; const char *sysclk_path; + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + unsigned int svr; + svr = in_be32(&gur->svr); unsigned long busclk = get_bus_freq(0); + /* delete crypto node if not on an E-processor */ + if (!IS_E_PROCESSOR(svr)) + fdt_fixup_crypto_node(blob, 0); +#if CONFIG_SYS_FSL_SEC_COMPAT >= 4 + else { + ccsr_sec_t __iomem *sec; + + sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR; + fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms)); + } +#endif + fdt_fixup_ethernet(blob); off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c index 1c63f93..9cc1676 100644 --- a/arch/powerpc/cpu/mpc8xxx/fdt.c +++ b/arch/powerpc/cpu/mpc8xxx/fdt.c @@ -73,176 +73,6 @@ void ft_fixup_num_cores(void *blob) { } #endif /* defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) */ -/* - * update crypto node properties to a specified revision of the SEC - * called with sec_rev == 0 if not on an E processor - */ -#if CONFIG_SYS_FSL_SEC_COMPAT == 2 /* SEC 2.x/3.x */ -void fdt_fixup_crypto_node(void *blob, int sec_rev) -{ - static const struct sec_rev_prop { - u32 sec_rev; - u32 num_channels; - u32 channel_fifo_len; - u32 exec_units_mask; - u32 descriptor_types_mask; - } sec_rev_prop_list [] = { - { 0x0200, 4, 24, 0x07e, 0x01010ebf }, /* SEC 2.0 */ - { 0x0201, 4, 24, 0x0fe, 0x012b0ebf }, /* SEC 2.1 */ - { 0x0202, 1, 24, 0x04c, 0x0122003f }, /* SEC 2.2 */ - { 0x0204, 4, 24, 0x07e, 0x012b0ebf }, /* SEC 2.4 */ - { 0x0300, 4, 24, 0x9fe, 0x03ab0ebf }, /* SEC 3.0 */ - { 0x0301, 4, 24, 0xbfe, 0x03ab0ebf }, /* SEC 3.1 */ - { 0x0303, 4, 24, 0x97c, 0x03a30abf }, /* SEC 3.3 */ - }; - static char compat_strlist[ARRAY_SIZE(sec_rev_prop_list) * - sizeof("fsl,secX.Y")]; - int crypto_node, sec_idx, err; - char *p; - u32 val; - - /* locate crypto node based on lowest common compatible */ - crypto_node = fdt_node_offset_by_compatible(blob, -1, "fsl,sec2.0"); - if (crypto_node == -FDT_ERR_NOTFOUND) - return; - - /* delete it if not on an E-processor */ - if (crypto_node > 0 && !sec_rev) { - fdt_del_node(blob, crypto_node); - return; - } - - /* else we got called for possible uprev */ - for (sec_idx = 0; sec_idx < ARRAY_SIZE(sec_rev_prop_list); sec_idx++) - if (sec_rev_prop_list[sec_idx].sec_rev == sec_rev) - break; - - if (sec_idx == ARRAY_SIZE(sec_rev_prop_list)) { - puts("warning: unknown SEC revision number\n"); - return; - } - - val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].num_channels); - err = fdt_setprop(blob, crypto_node, "fsl,num-channels", &val, 4); - if (err < 0) - printf("WARNING: could not set crypto property: %s\n", - fdt_strerror(err)); - - val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].descriptor_types_mask); - err = fdt_setprop(blob, crypto_node, "fsl,descriptor-types-mask", &val, 4); - if (err < 0) - printf("WARNING: could not set crypto property: %s\n", - fdt_strerror(err)); - - val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].exec_units_mask); - err = fdt_setprop(blob, crypto_node, "fsl,exec-units-mask", &val, 4); - if (err < 0) - printf("WARNING: could not set crypto property: %s\n", - fdt_strerror(err)); - - val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].channel_fifo_len); - err = fdt_setprop(blob, crypto_node, "fsl,channel-fifo-len", &val, 4); - if (err < 0) - printf("WARNING: could not set crypto property: %s\n", - fdt_strerror(err)); - - val = 0; - while (sec_idx >= 0) { - p = compat_strlist + val; - val += sprintf(p, "fsl,sec%d.%d", - (sec_rev_prop_list[sec_idx].sec_rev & 0xff00) >> 8, - sec_rev_prop_list[sec_idx].sec_rev & 0x00ff) + 1; - sec_idx--; - } - err = fdt_setprop(blob, crypto_node, "compatible", &compat_strlist, val); - if (err < 0) - printf("WARNING: could not set crypto property: %s\n", - fdt_strerror(err)); -} -#elif CONFIG_SYS_FSL_SEC_COMPAT >= 4 /* SEC4 */ -static u8 caam_get_era(void) -{ - static const struct { - u16 ip_id; - u8 maj_rev; - u8 era; - } caam_eras[] = { - {0x0A10, 1, 1}, - {0x0A10, 2, 2}, - {0x0A12, 1, 3}, - {0x0A14, 1, 3}, - {0x0A14, 2, 4}, - {0x0A16, 1, 4}, - {0x0A10, 3, 4}, - {0x0A11, 1, 4}, - {0x0A18, 1, 4}, - {0x0A11, 2, 5}, - {0x0A12, 2, 5}, - {0x0A13, 1, 5}, - {0x0A1C, 1, 5} - }; - - ccsr_sec_t __iomem *sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR; - u32 secvid_ms = sec_in32(&sec->secvid_ms); - u32 ccbvid = sec_in32(&sec->ccbvid); - u16 ip_id = (secvid_ms & SEC_SECVID_MS_IPID_MASK) >> - SEC_SECVID_MS_IPID_SHIFT; - u8 maj_rev = (secvid_ms & SEC_SECVID_MS_MAJ_REV_MASK) >> - SEC_SECVID_MS_MAJ_REV_SHIFT; - u8 era = (ccbvid & SEC_CCBVID_ERA_MASK) >> SEC_CCBVID_ERA_SHIFT; - - int i; - - if (era) /* This is '0' prior to CAAM ERA-6 */ - return era; - - for (i = 0; i < ARRAY_SIZE(caam_eras); i++) - if (caam_eras[i].ip_id == ip_id && - caam_eras[i].maj_rev == maj_rev) - return caam_eras[i].era; - - return 0; -} - -static void fdt_fixup_crypto_era(void *blob, u32 era) -{ - int err; - int crypto_node; - - crypto_node = fdt_path_offset(blob, "crypto"); - if (crypto_node < 0) { - printf("WARNING: Missing crypto node\n"); - return; - } - - err = fdt_setprop(blob, crypto_node, "fsl,sec-era", &era, - sizeof(era)); - if (err < 0) { - printf("ERROR: could not set fsl,sec-era property: %s\n", - fdt_strerror(err)); - } -} - -void fdt_fixup_crypto_node(void *blob, int sec_rev) -{ - u8 era; - - if (!sec_rev) { - fdt_del_node_and_alias(blob, "crypto"); - return; - } - - /* Add SEC ERA information in compatible */ - era = caam_get_era(); - if (era) { - fdt_fixup_crypto_era(blob, era); - } else { - printf("WARNING: Unable to get ERA for CAAM rev: %d\n", - sec_rev); - } -} -#endif - int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc) { return fdt_setprop_string(blob, offset, "phy-connection-type", diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h index 423a6fb..65496d0 100644 --- a/arch/powerpc/include/asm/config.h +++ b/arch/powerpc/include/asm/config.h @@ -75,6 +75,7 @@ * SEC (crypto unit) major compatible version determination */ #if defined(CONFIG_MPC83xx) +#define CONFIG_SYS_FSL_SEC_BE #define CONFIG_SYS_FSL_SEC_COMPAT 2 #endif diff --git a/drivers/crypto/fsl/Makefile b/drivers/crypto/fsl/Makefile index cb13d2e..067d0a9 100644 --- a/drivers/crypto/fsl/Makefile +++ b/drivers/crypto/fsl/Makefile @@ -6,5 +6,6 @@ # Version 2 as published by the Free Software Foundation. # +obj-y += sec.o obj-$(CONFIG_FSL_CAAM) += jr.o fsl_hash.o jobdesc.o error.o obj-$(CONFIG_CMD_BLOB) += fsl_blob.o diff --git a/drivers/crypto/fsl/sec.c b/drivers/crypto/fsl/sec.c new file mode 100644 index 0000000..443ee96 --- /dev/null +++ b/drivers/crypto/fsl/sec.c @@ -0,0 +1,184 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <libfdt.h> +#include <fdt_support.h> +#if CONFIG_SYS_FSL_SEC_COMPAT == 2 || CONFIG_SYS_FSL_SEC_COMPAT >= 4 +#include <fsl_sec.h> +#endif + +/* + * update crypto node properties to a specified revision of the SEC + * called with sec_rev == 0 if not on an E processor + */ +#if CONFIG_SYS_FSL_SEC_COMPAT == 2 /* SEC 2.x/3.x */ +void fdt_fixup_crypto_node(void *blob, int sec_rev) +{ + static const struct sec_rev_prop { + u32 sec_rev; + u32 num_channels; + u32 channel_fifo_len; + u32 exec_units_mask; + u32 descriptor_types_mask; + } sec_rev_prop_list[] = { + { 0x0200, 4, 24, 0x07e, 0x01010ebf }, /* SEC 2.0 */ + { 0x0201, 4, 24, 0x0fe, 0x012b0ebf }, /* SEC 2.1 */ + { 0x0202, 1, 24, 0x04c, 0x0122003f }, /* SEC 2.2 */ + { 0x0204, 4, 24, 0x07e, 0x012b0ebf }, /* SEC 2.4 */ + { 0x0300, 4, 24, 0x9fe, 0x03ab0ebf }, /* SEC 3.0 */ + { 0x0301, 4, 24, 0xbfe, 0x03ab0ebf }, /* SEC 3.1 */ + { 0x0303, 4, 24, 0x97c, 0x03a30abf }, /* SEC 3.3 */ + }; + static char compat_strlist[ARRAY_SIZE(sec_rev_prop_list) * + sizeof("fsl,secX.Y")]; + int crypto_node, sec_idx, err; + char *p; + u32 val; + + /* locate crypto node based on lowest common compatible */ + crypto_node = fdt_node_offset_by_compatible(blob, -1, "fsl,sec2.0"); + if (crypto_node == -FDT_ERR_NOTFOUND) + return; + + /* delete it if not on an E-processor */ + if (crypto_node > 0 && !sec_rev) { + fdt_del_node(blob, crypto_node); + return; + } + + /* else we got called for possible uprev */ + for (sec_idx = 0; sec_idx < ARRAY_SIZE(sec_rev_prop_list); sec_idx++) + if (sec_rev_prop_list[sec_idx].sec_rev == sec_rev) + break; + + if (sec_idx == ARRAY_SIZE(sec_rev_prop_list)) { + puts("warning: unknown SEC revision number\n"); + return; + } + + val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].num_channels); + err = fdt_setprop(blob, crypto_node, "fsl,num-channels", &val, 4); + if (err < 0) + printf("WARNING: could not set crypto property: %s\n", + fdt_strerror(err)); + + val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].descriptor_types_mask); + err = fdt_setprop(blob, crypto_node, "fsl,descriptor-types-mask", + &val, 4); + if (err < 0) + printf("WARNING: could not set crypto property: %s\n", + fdt_strerror(err)); + + val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].exec_units_mask); + err = fdt_setprop(blob, crypto_node, "fsl,exec-units-mask", &val, 4); + if (err < 0) + printf("WARNING: could not set crypto property: %s\n", + fdt_strerror(err)); + + val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].channel_fifo_len); + err = fdt_setprop(blob, crypto_node, "fsl,channel-fifo-len", &val, 4); + if (err < 0) + printf("WARNING: could not set crypto property: %s\n", + fdt_strerror(err)); + + val = 0; + while (sec_idx >= 0) { + p = compat_strlist + val; + val += sprintf(p, "fsl,sec%d.%d", + (sec_rev_prop_list[sec_idx].sec_rev & 0xff00) >> 8, + sec_rev_prop_list[sec_idx].sec_rev & 0x00ff) + 1; + sec_idx--; + } + err = fdt_setprop(blob, crypto_node, "compatible", &compat_strlist, + val); + if (err < 0) + printf("WARNING: could not set crypto property: %s\n", + fdt_strerror(err)); +} +#elif CONFIG_SYS_FSL_SEC_COMPAT >= 4 /* SEC4 */ +static u8 caam_get_era(void) +{ + static const struct { + u16 ip_id; + u8 maj_rev; + u8 era; + } caam_eras[] = { + {0x0A10, 1, 1}, + {0x0A10, 2, 2}, + {0x0A12, 1, 3}, + {0x0A14, 1, 3}, + {0x0A14, 2, 4}, + {0x0A16, 1, 4}, + {0x0A10, 3, 4}, + {0x0A11, 1, 4}, + {0x0A18, 1, 4}, + {0x0A11, 2, 5}, + {0x0A12, 2, 5}, + {0x0A13, 1, 5}, + {0x0A1C, 1, 5} + }; + + ccsr_sec_t __iomem *sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR; + u32 secvid_ms = sec_in32(&sec->secvid_ms); + u32 ccbvid = sec_in32(&sec->ccbvid); + u16 ip_id = (secvid_ms & SEC_SECVID_MS_IPID_MASK) >> + SEC_SECVID_MS_IPID_SHIFT; + u8 maj_rev = (secvid_ms & SEC_SECVID_MS_MAJ_REV_MASK) >> + SEC_SECVID_MS_MAJ_REV_SHIFT; + u8 era = (ccbvid & SEC_CCBVID_ERA_MASK) >> SEC_CCBVID_ERA_SHIFT; + + int i; + + if (era) /* This is '0' prior to CAAM ERA-6 */ + return era; + + for (i = 0; i < ARRAY_SIZE(caam_eras); i++) + if (caam_eras[i].ip_id == ip_id && + caam_eras[i].maj_rev == maj_rev) + return caam_eras[i].era; + + return 0; +} + +static void fdt_fixup_crypto_era(void *blob, u32 era) +{ + int err; + int crypto_node; + + crypto_node = fdt_path_offset(blob, "crypto"); + if (crypto_node < 0) { + printf("WARNING: Missing crypto node\n"); + return; + } + + err = fdt_setprop(blob, crypto_node, "fsl,sec-era", &era, + sizeof(era)); + if (err < 0) { + printf("ERROR: could not set fsl,sec-era property: %s\n", + fdt_strerror(err)); + } +} + +void fdt_fixup_crypto_node(void *blob, int sec_rev) +{ + u8 era; + + if (!sec_rev) { + fdt_del_node_and_alias(blob, "crypto"); + return; + } + + /* Add SEC ERA information in compatible */ + era = caam_get_era(); + if (era) { + fdt_fixup_crypto_era(blob, era); + } else { + printf("WARNING: Unable to get ERA for CAAM rev: %d\n", + sec_rev); + } +} +#endif -- 1.8.1.4

2 1

[U-Boot] [PATCH 1/2] arm: ls102xa: Add dummy gpio.h to enable CONFIG_OF_CONTROL
by Ruchika Gupta 24 Jan '15

24 Jan '15

If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled. It includes <asm/gpio.h> and then <asm/gpio.h> includes <asm/arch/gpio.h>. As a result, all the SoCs that enable CONFIG_OF_CONTROL must have <asm/arch/gpio.h> even if they do not support GPIO. The right fix would be to split the lib/fdtdec.c to remove dependency on GPIO.This commit adds a dummy <asm/arch/gpio.h> to support OF_CONTROL for LS102x platform. This dummy header will be removed after FDT-GPIO stuff is fixed correctly. Signed-off-by: Ruchika Gupta <ruchika.gupta(a)freescale.com> --- arch/arm/include/asm/arch-ls102xa/gpio.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 arch/arm/include/asm/arch-ls102xa/gpio.h diff --git a/arch/arm/include/asm/arch-ls102xa/gpio.h b/arch/arm/include/asm/arch-ls102xa/gpio.h new file mode 100644 index 0000000..b704436 --- /dev/null +++ b/arch/arm/include/asm/arch-ls102xa/gpio.h @@ -0,0 +1,15 @@ +/* + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * Dummy header file to enable CONFIG_OF_CONTROL. + * If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled. + * It includes <asm/arch/gpio.h> via <asm/gpio.h>, so those SoCs that enable + * OF_CONTROL must have arch/gpio.h. + */ + +#ifndef __ASM_ARCH_LS102XA_GPIO_H_ +#define __ASM_ARCH_LS102XA_GPIO_H_ + +#endif -- 1.8.1.4

4 3

[U-Boot] [RFC PATCH] dm:spi:fsl_qspi add DM support
by Peng Fan 24 Jan '15

24 Jan '15

Hi Simon ,Jagan This patch is based on git://git.denx.de/u-boot-spi.git master branch, since some fsl_qspi's new feature is still in this git repo and have not been merged to mainline. I saw Simon sent out a new patch that remove the per_child_auto_alloc_size from the platforms' driver code and move it to spi uclass driver. In this patch I do not remove it, since this is a RFC version, and Jagan's spi git repo still has it. I can remove it in formal version if needed. Please take your time to review and comment this patch. Thanks. This patch adds DM support for fsl_qspi driver, the DM part needs device tree support. Partial of the original driver code is reused, such as the AHB part, the LUT initialization and etc. The driver now supports new DM and original driver by define "CONFIG_DM_SPI". Until device tree is integrated, the original part can be discarded. The driver code file is now as following: " Common code that needs both by DM or original driver code. #if defined(CONFIG_DM_SPI) DM part #else Original driver code #endif " In DM part, some reconstruction is done. A fsl_qspi_runcmd is included to simplify the code, but not the original qspi_op_xxxxs. fsl_qspi_get_seqid is included to get seqid, but not hardcoded in original qspi_op_xxxxs. Signed-off-by: Peng Fan <Peng.Fan(a)freescale.com> --- drivers/spi/fsl_qspi.c | 420 +++++++++++++++++++++++++++++++++++++++++++++++-- drivers/spi/fsl_qspi.h | 1 + 2 files changed, 405 insertions(+), 16 deletions(-) diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index 5e0b069..ee151b3 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -13,6 +13,13 @@ #include <linux/sizes.h> #include "fsl_qspi.h" +#ifdef CONFIG_DM_SPI +#include <dm.h> +#include <fdtdec.h> +#include <asm/errno.h> +#include <spi_flash.h> +#endif + #define RX_BUFFER_SIZE 0x80 #ifdef CONFIG_MX6SX #define TX_BUFFER_SIZE 0x200 @@ -71,27 +78,41 @@ #define qspi_write32 out_be32 #endif -static unsigned long spi_bases[] = { - QSPI0_BASE_ADDR, -#ifdef CONFIG_MX6SX - QSPI1_BASE_ADDR, -#endif -}; +#ifdef CONFIG_DM_SPI +DECLARE_GLOBAL_DATA_PTR; +#define QUADSPI_AHBMAP_BANK_MAXSIZE SZ_64M -static unsigned long amba_bases[] = { - QSPI0_AMBA_BASE, -#ifdef CONFIG_MX6SX - QSPI1_AMBA_BASE, -#endif +struct fsl_qspi_platdata { + u32 max_hz; + u32 reg_base; + u32 amba_base; + u32 flash_num; }; struct fsl_qspi { + u32 reg_base; + u32 amba_base; + size_t cmd_len; + u8 cmd_buf[32]; + size_t data_len; + int qspi_is_init; + size_t flash_size; + u32 bank_memmap_phy[4]; + int cs; + u32 sf_addr; + int flash_num; + u8 cur_seqid; + u32 freq; +}; +#else +struct fsl_qspi { struct spi_slave slave; unsigned long reg_base; unsigned long amba_base; u32 sf_addr; u8 cur_seqid; }; +#endif /* QSPI support swapping the flash read/write data * in hardware for LS102xA, but not for VF610 */ @@ -104,11 +125,6 @@ static inline u32 qspi_endian_xchg(u32 data) #endif } -static inline struct fsl_qspi *to_qspi_spi(struct spi_slave *slave) -{ - return container_of(slave, struct fsl_qspi, slave); -} - static void qspi_set_lut(struct fsl_qspi *qspi) { struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base; @@ -367,6 +383,377 @@ static void qspi_init_ahb_read(struct fsl_qspi_regs *regs) } #endif +#ifdef CONFIG_DM_SPI +/* Get the SEQID for the command */ +static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd) +{ + switch (cmd) { + case QSPI_CMD_FAST_READ: + case QSPI_CMD_FAST_READ_4B: + return SEQID_FAST_READ; + case QSPI_CMD_WREN: + return SEQID_WREN; + case QSPI_CMD_RDSR: + return SEQID_RDSR; + case QSPI_CMD_SE: + return SEQID_SE; + case QSPI_CMD_PP: + case QSPI_CMD_PP_4B: + return SEQID_PP; + case QSPI_CMD_RDID: + return SEQID_RDID; + case QSPI_CMD_BE_4K: + return SEQID_BE_4K; +#ifdef CONFIG_SPI_FLASH_BAR + case QSPI_CMD_BRRD: + return SEQID_BRRD; + case QSPI_CMD_BRWR: + return SEQID_BRWR; + case QSPI_CMD_RDEAR: + return SEQID_RDEAR; + case QSPI_CMD_WREAR: + return SEQID_WREAR; +#endif + default: + break; + } + return -1; +} + +/* Read out the data from the QUADSPI_RBDR buffer registers. */ +static void fsl_qspi_ip_read(struct fsl_qspi *q, int len, u8 *rxbuf) +{ + struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)q->reg_base; + u32 tmp; + int i = 0; + + while (len > 0) { + tmp = qspi_read32(&regs->rbdr[i]); + tmp = qspi_endian_xchg(tmp); + + if (len >= 4) { + memcpy(rxbuf, &tmp, 4); + rxbuf += 4; + } else { + memcpy(rxbuf, &tmp, len); + break; + } + + len -= 4; + i++; + } +} + +/* Write data to the QUADSPI_TBDR buffer registers. */ +static void fsl_qspi_write_data(struct fsl_qspi *q, int len, u8 *txbuf) +{ + struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)q->reg_base; + u32 tmp; + u32 t1, t2; + int j; + + tmp = qspi_read32(&regs->mcr); + qspi_write32(&regs->mcr, tmp | QSPI_MCR_CLR_RXF_MASK | + QSPI_MCR_CLR_TXF_MASK); + + /* fill the TX data to the FIFO */ + t2 = len % 4; + t1 = len >> 2; /* 4 Bytes aligned */ + + for (j = 0; j < t1; j++) { + memcpy(&tmp, txbuf, 4); + tmp = qspi_endian_xchg(tmp); + qspi_write32(&regs->tbdr, tmp); + txbuf += 4; + } + + if (t2) { + tmp = 0; + memcpy(&tmp, txbuf, t2); + tmp = qspi_endian_xchg(tmp); + qspi_write32(&regs->tbdr, tmp); + } +} + +static int fsl_qspi_runcmd(struct fsl_qspi *q, u8 cmd, int len) +{ + struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)q->reg_base; + int seqid; + u32 reg; + + /* Wait previous cmd completed */ + while (qspi_read32(&regs->sr) & QSPI_SR_BUSY_MASK) + ; + + /* save the reg */ + reg = qspi_read32(&regs->mcr); + + qspi_write32(&regs->sfar, q->amba_base + q->sf_addr); + qspi_write32(&regs->rbct, QSPI_RBCT_WMRK_MASK | QSPI_RBCT_RXBRD_USEIPS); + qspi_write32(&regs->mcr, reg | QSPI_MCR_CLR_RXF_MASK); + + /* trigger the LUT now */ + seqid = fsl_qspi_get_seqid(q, cmd); + qspi_write32(&regs->ipcr, (seqid << QSPI_IPCR_SEQID_SHIFT) | len); + + /* Wait until completed */ + while (qspi_read32(&regs->sr) & QSPI_SR_BUSY_MASK) + ; + + /* restore the MCR */ + qspi_write32(&regs->mcr, reg); + +#ifdef CONFIG_SYS_FSL_QSPI_AHB + /* After switch BANK, AHB buffer should also be invalid. */ + if ((QSPI_CMD_SE == cmd) || (QSPI_CMD_PP == cmd) || + (QSPI_CMD_BE_4K == cmd) || (QSPI_CMD_WREAR == cmd) || + (QSPI_CMD_BRWR == cmd)) + qspi_ahb_invalid(q); +#endif + return 0; +} + +int fsl_qspi_init(struct fsl_qspi *qspi) +{ + struct fsl_qspi_regs *regs; + u32 smpr_val; + + regs = (struct fsl_qspi_regs *)qspi->reg_base; + + qspi_write32(&regs->mcr, QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK); + + smpr_val = qspi_read32(&regs->smpr); + qspi_write32(&regs->smpr, smpr_val & ~(QSPI_SMPR_FSDLY_MASK | + QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK)); + qspi_write32(&regs->mcr, QSPI_MCR_RESERVED_MASK); + + /* flash size is still using macro definition. */ + if (qspi->flash_num == 2) { + qspi_write32(&regs->sfa1ad, qspi->amba_base + + FSL_QSPI_FLASH_SIZE); + qspi_write32(&regs->sfa2ad, qspi->amba_base + + FSL_QSPI_FLASH_SIZE); + qspi_write32(&regs->sfb1ad, qspi->amba_base + + FSL_QSPI_FLASH_SIZE * 2); + qspi_write32(&regs->sfb2ad, qspi->amba_base + + FSL_QSPI_FLASH_SIZE * 2); + } else if (qspi->flash_num == 4) { + qspi_write32(&regs->sfa1ad, qspi->amba_base + + FSL_QSPI_FLASH_SIZE); + qspi_write32(&regs->sfa2ad, qspi->amba_base + + FSL_QSPI_FLASH_SIZE * 2); + qspi_write32(&regs->sfb1ad, qspi->amba_base + + FSL_QSPI_FLASH_SIZE * 3); + qspi_write32(&regs->sfb2ad, qspi->amba_base + + FSL_QSPI_FLASH_SIZE * 4); + } else { + qspi_write32(&regs->sfa1ad, qspi->amba_base + + FSL_QSPI_FLASH_SIZE); + qspi_write32(&regs->sfa2ad, qspi->amba_base + + FSL_QSPI_FLASH_SIZE); + qspi_write32(&regs->sfb1ad, qspi->amba_base + + FSL_QSPI_FLASH_SIZE); + qspi_write32(&regs->sfb2ad, qspi->amba_base + + FSL_QSPI_FLASH_SIZE); + } + + qspi_set_lut(qspi); + + smpr_val = qspi_read32(&regs->smpr); + smpr_val &= ~QSPI_SMPR_DDRSMP_MASK; + qspi_write32(&regs->smpr, smpr_val); + qspi_write32(&regs->mcr, QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); + +#ifdef CONFIG_SYS_FSL_QSPI_AHB + qspi_init_ahb_read(regs); +#endif + return 0; +} + +static int fsl_qspi_probe(struct udevice *bus) +{ + struct fsl_qspi_platdata *plat = bus->platdata; + struct fsl_qspi *priv = dev_get_priv(bus); + + priv->reg_base = plat->reg_base; + priv->amba_base = plat->amba_base; + priv->flash_num = plat->flash_num; + + if (!priv->qspi_is_init) { + /* Initialization */ + fsl_qspi_init(priv); + priv->qspi_is_init = 1; + } + + return 0; +} + +static int fsl_qspi_child_pre_probe(struct udevice *dev) +{ + struct udevice *bus = dev_get_parent(dev); + struct fsl_qspi *priv = dev_get_priv(bus); + struct spi_slave *slave = dev_get_parentdata(dev); + int cs = spi_chip_select(dev); + + slave->max_write_size = TX_BUFFER_SIZE; + + priv->cs = cs; + priv->amba_base = priv->bank_memmap_phy[priv->cs]; + + return 0; +} + +static int fsl_qspi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct udevice *bus = dev->parent; + struct fsl_qspi *q = dev_get_priv(bus); + u32 len = DIV_ROUND_UP(bitlen, 8); + int ret = 0; + u8 *buf; + static u32 addr; + static u8 opcode; + + if (!opcode && (flags & SPI_XFER_BEGIN)) { + /* CMD PHASE */ + buf = (u8 *)dout; + opcode = buf[0]; + if (len > 1) { + addr = buf[1] << 16 | buf[2] << 8 | buf[3]; + q->sf_addr = addr; + } + + /* Only transfer CMD */ + if (flags & SPI_XFER_END) + ret = fsl_qspi_runcmd(q, opcode, 0); + + } else if (opcode) { + /* Data phase */ + if (din) { + /* read*/ + buf = (u8 *)din; +#ifdef CONFIG_SYS_FSL_QSPI_AHB + if (QSPI_CMD_FAST_READ == opcode) { + qspi_ahb_read(q, buf, len); + } else { + ret = fsl_qspi_runcmd(q, opcode, len); + if (!ret) + fsl_qspi_ip_read(q, len, buf); + } +#else + ret = fsl_qspi_runcmd(q, opcode, len); + if (!ret) + fsl_qspi_ip_read(q, len, buf); +#endif + } else if (dout) { + /* Write data, First prepare data */ + buf = (u8 *)dout; + fsl_qspi_write_data(q, len, buf); + /* Run page program cmd */ + ret = fsl_qspi_runcmd(q, opcode, len); + } + } + + if (ret || (flags & SPI_XFER_END)) { + opcode = 0; + addr = 0; + } + + return ret; +} + +static int fsl_qspi_ofdata_to_platdata(struct udevice *bus) +{ + struct fsl_qspi_platdata *plat = bus->platdata; + const void *blob = gd->fdt_blob; + int node = bus->of_offset; + int subnode, flash_num = 0; + u32 data[4]; + int ret; + + ret = fdtdec_get_int_array(blob, node, "reg", data, ARRAY_SIZE(data)); + if (ret) { + printf("Error: can't get base addresses (ret = %d)!\n", ret); + return -ENODEV; + } + + /* Count flash numbers */ + fdt_for_each_subnode(blob, subnode, node) + ++flash_num; + + if (flash_num == 0) { + printf("Error: Missing flashes!\n"); + return -ENODEV; + } + + plat->reg_base = data[0]; + plat->amba_base = data[2]; + plat->flash_num = flash_num; + + plat->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", + 50000000); + + debug("%s: reg_base=0x%x amba_base=0x%x max-frequency=%d\n", + __func__, plat->reg_base, plat->amba_base, plat->max_hz); + + return 0; +} + +static int fsl_qspi_set_speed(struct udevice *bus, u32 speed) +{ + return 0; +} + +static int fsl_qspi_set_mode(struct udevice *bus, u32 mode) +{ + return 0; +} + +static const struct dm_spi_ops fsl_qspi_ops = { + .xfer = fsl_qspi_xfer, + .set_speed = fsl_qspi_set_speed, + .set_mode = fsl_qspi_set_mode, +}; + +static const struct udevice_id fsl_qspi_ids[] = { + { .compatible = "fsl,vf610-qspi" }, + { .compatible = "fsl,imx6sx-qspi" }, + { } +}; + +U_BOOT_DRIVER(fsl_qspi) = { + .name = "fsl_qspi", + .id = UCLASS_SPI, + .of_match = fsl_qspi_ids, + .ops = &fsl_qspi_ops, + .ofdata_to_platdata = fsl_qspi_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct fsl_qspi_platdata), + .priv_auto_alloc_size = sizeof(struct fsl_qspi), + .per_child_auto_alloc_size = sizeof(struct spi_slave), + .probe = fsl_qspi_probe, + .child_pre_probe = fsl_qspi_child_pre_probe, +}; + +#else +static unsigned long spi_bases[] = { + QSPI0_BASE_ADDR, +#ifdef CONFIG_MX6SX + QSPI1_BASE_ADDR, +#endif +}; + +static unsigned long amba_bases[] = { + QSPI0_AMBA_BASE, +#ifdef CONFIG_MX6SX + QSPI1_AMBA_BASE, +#endif +}; + +static inline struct fsl_qspi *to_qspi_spi(struct spi_slave *slave) +{ + return container_of(slave, struct fsl_qspi, slave); +} + void spi_init() { /* do nothing */ @@ -782,3 +1169,4 @@ void spi_release_bus(struct spi_slave *slave) { /* Nothing to do */ } +#endif diff --git a/drivers/spi/fsl_qspi.h b/drivers/spi/fsl_qspi.h index 6cb3610..ef4d4b5 100644 --- a/drivers/spi/fsl_qspi.h +++ b/drivers/spi/fsl_qspi.h @@ -104,6 +104,7 @@ struct fsl_qspi_regs { #define QSPI_RBCT_RXBRD_SHIFT 8 #define QSPI_RBCT_RXBRD_USEIPS (1 << QSPI_RBCT_RXBRD_SHIFT) +#define QSPI_RBCT_WMRK_MASK 0x1F #define QSPI_SR_BUSY_SHIFT 0 #define QSPI_SR_BUSY_MASK (1 << QSPI_SR_BUSY_SHIFT) -- 1.8.4

4 4

[U-Boot] [PATCH v1] ls102xa: etsec: Select ge0_clk125 for eTSEC clock muxing as default
by Alison Wang 24 Jan '15

24 Jan '15

This patch reverts to use ge0_clk125 for eTSEC clock muxing. For SAI and CAN which are pin multiplexed with RGMII1 in EC1 of RCW, ge2_clk125 will be used via hwconfig. Signed-off-by: Bhupesh Sharma <bhupesh.sharma(a)freescale.com> Signed-off-by: Alison Wang <alison.wang(a)freescale.com> --- arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 ++ board/freescale/ls1021aqds/ls1021aqds.c | 35 ++++++++++++++++++++++- 2 files changed, 36 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 697d4ca..afdccdc 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -105,6 +105,8 @@ struct ccsr_gur { #define SCFG_ETSECDMAMCR_LE_BD_FR 0xf8001a0f #define SCFG_ETSECCMCR_GE2_CLK125 0x04000000 +#define SCFG_ETSECCMCR_GE0_CLK125 0x00000000 +#define SCFG_ETSECCMCR_GE1_CLK125 0x08000000 #define SCFG_PIXCLKCR_PXCKEN 0x80000000 #define SCFG_QSPI_CLKSEL 0xc0100000 diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index f08e54f..f4a5dda 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -48,6 +48,12 @@ enum { MUX_TYPE_SD_PC_SG_SG, }; +enum { + GE0_CLK125, + GE2_CLK125, + GE1_CLK125, +}; + int checkboard(void) { #ifndef CONFIG_QSPI_BOOT @@ -177,7 +183,6 @@ int board_early_init_f(void) #ifdef CONFIG_TSEC_ENET out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); - out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125); #endif #ifdef CONFIG_FSL_IFC @@ -244,6 +249,32 @@ void board_init_f(ulong dummy) } #endif +void config_etseccm_source(int etsec_gtx_125_mux) +{ + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; + + switch (etsec_gtx_125_mux) { + case GE0_CLK125: + out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE0_CLK125); + debug("etseccm set to GE0_CLK125\n"); + break; + + case GE2_CLK125: + out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125); + debug("etseccm set to GE2_CLK125\n"); + break; + + case GE1_CLK125: + out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE1_CLK125); + debug("etseccm set to GE1_CLK125\n"); + break; + + default: + printf("Error! trying to set etseccm to invalid value\n"); + break; + } +} + int config_board_mux(int ctrl_type) { u8 reg12, reg14; @@ -253,6 +284,7 @@ int config_board_mux(int ctrl_type) switch (ctrl_type) { case MUX_TYPE_CAN: + config_etseccm_source(GE2_CLK125); reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN); break; case MUX_TYPE_IIC2: @@ -262,6 +294,7 @@ int config_board_mux(int ctrl_type) reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII); break; case MUX_TYPE_SAI: + config_etseccm_source(GE2_CLK125); reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI); break; case MUX_TYPE_SDHC: -- 2.1.0.27.g96db324

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[U-Boot] [PATCH v2 0/26] dm: Add additional bus functionality
by Simon Glass 24 Jan '15

24 Jan '15

The current bus implementation is simple but leaves some things to drivers which are better handled in the uclass. At present uclasses cannot provide a common way of dealing with children (i.e. devices on the bus), so we have duplication in the drivers. The same code is repeated in each driver when it would be better to put it in the uclass. Secondly, we don't have the concept of per-child platform data for devices on the bus. Instead the per-child data can only exist when the child is actually probed. This is not really suitable. Examples of things we want to know before a child is probed are: - chip address (for I2C) - chip select (for SPI) - device address (for PCI) These things are static and do not change when the device is probed and removed. In some cases (such as SPI mode and maximum speed), the data may be copied to run-time data when the device is probed. It may then be changed while the driver is active, but the original platform data is never changed by drivers once it is set up. To address these issues, additional functions are added: - per-child platform data, which can be defined by the uclass and (if necessary) overriden by the bus driver. This allows the bus's uclass to provide some consistency here - per-child post-bind and pre-probe methods in the uclass. These allow the bus uclass to set up the per-child platform data, and also to do any last-minute adjustments before the child is probed. With these changes, some code can be removed from the existing I2C and SPI drivers and this has been done as part of this series. With this series I2C and SPI are tested on: - jetson-tk1 (Tegra 124) - beaver (Tegra 30) - seaboard (Tegra 20, I2C only) - trimslice (Tegra 20, SPI only) - snow (Exynos 5250) - pit (Exynos 5420, note I2C probe is previously broken) - link (x86) - sandbox Note: Some of these changes were previously included in the DM PCI RFC. This series is available at u-boot-dm/i2c-working. Changes in v2: - Add a TODO to remove struct dm_spi_bus - Add additional comments to spi.h - Add new patch to provide an offset length parameter where needed - Add patches to tidy up cros_ec using new I2C/SPI features - Copy max_hz and mode from platdata to spi_slave when probing - Drop RFC prefix since this series has been properly tested now - Tidy up soft_spi driver also - Update commit message to describe immuatable platform data - Update the spi-howto docs Simon Glass (26): dm: i2c: Provide an offset length parameter where needed dm: Don't run tests if U-Boot cannot be built dm: core: Improve comments for uclass_first/next_device() dm: core: Set device tree node for root device dm: core: Tidy up error handling in device_bind() dm: core: Allocate platform data when binding a device dm: core: Allow parents to have platform data for their children dm: core: Allow uclasses to specific the platdata for a device's children dm: core: Add a post_bind method for parents dm: core: Add a function to get a device's uclass ID dm: core: Add a flag to control sequence numbering dm: core: Allow uclasses to specific the private data for a device's children dm: spi: Move the per-child data size to the uclass dm: core: Allow the uclass to set up a device's child after binding dm: sandbox: sf: Tidy up the error handling in sandbox_sf_probe() dm: core: Allow uclass to set up a device's child before it is probed dm: spi: Set up the spi_slave device pointer in child_pre_probe() dm: spi: Move slave details to child platdata dm: i2c: Move slave details to child platdata dm: tegra: Drop unused COMPAT features for I2C, SPI dm: exynos: Drop unused COMPAT features for SPI dm: core: Ignore disabled devices when binding dm: cros_ec: Don't require protocol 3 support dm: cros_ec: Move cros_ec_i2c over to driver model dm: cros_ec_spi: Remove old pre-driver-model code dm: Update documentation for new bus features arch/arm/cpu/tegra20-common/pmu.c | 2 +- board/avionic-design/common/tamonten-ng.c | 2 +- board/nvidia/cardhu/cardhu.c | 4 +- board/nvidia/dalmore/dalmore.c | 4 +- board/nvidia/whistler/whistler.c | 4 +- board/toradex/apalis_t30/apalis_t30.c | 2 +- common/cmd_i2c.c | 2 +- doc/driver-model/README.txt | 91 +++++------ doc/driver-model/spi-howto.txt | 40 ++++- drivers/core/device-remove.c | 16 +- drivers/core/device.c | 119 ++++++++++---- drivers/core/root.c | 8 + drivers/core/uclass.c | 34 +++- drivers/i2c/i2c-uclass-compat.c | 2 +- drivers/i2c/i2c-uclass.c | 68 ++++---- drivers/i2c/i2c-uniphier-f.c | 12 -- drivers/i2c/i2c-uniphier.c | 12 -- drivers/i2c/s3c24x0_i2c.c | 12 -- drivers/i2c/sandbox_i2c.c | 30 +--- drivers/i2c/tegra_i2c.c | 18 --- drivers/misc/cros_ec.c | 10 +- drivers/misc/cros_ec_i2c.c | 107 +++++-------- drivers/misc/cros_ec_spi.c | 70 +-------- drivers/mtd/spi/sandbox.c | 12 +- drivers/mtd/spi/sf_probe.c | 3 +- drivers/power/as3722.c | 2 +- drivers/serial/serial-uclass.c | 1 + drivers/spi/cadence_qspi.c | 1 - drivers/spi/designware_spi.c | 1 - drivers/spi/exynos_spi.c | 1 - drivers/spi/sandbox_spi.c | 1 - drivers/spi/soft_spi.c | 10 -- drivers/spi/spi-uclass.c | 95 ++++++++---- drivers/spi/tegra114_spi.c | 1 - drivers/spi/tegra20_sflash.c | 1 - drivers/spi/tegra20_slink.c | 1 - include/configs/snow.h | 5 + include/dm/device.h | 29 ++++ include/dm/test.h | 3 + include/dm/uclass-internal.h | 11 ++ include/dm/uclass.h | 21 +++ include/fdtdec.h | 7 - include/i2c.h | 12 +- include/spi.h | 42 +++-- lib/fdtdec.c | 7 - test/dm/bus.c | 250 +++++++++++++++++++++++++++++- test/dm/core.c | 11 ++ test/dm/i2c.c | 10 +- test/dm/spi.c | 6 +- test/dm/test-dm.sh | 9 +- test/dm/test-fdt.c | 20 ++- test/dm/test.dts | 16 ++ 52 files changed, 812 insertions(+), 446 deletions(-) -- 2.2.0.rc0.207.ga3a616c

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[U-Boot] U-Boot on Sparc leon3
by Florian Praden 24 Jan '15

24 Jan '15

Hi, I'm trying to build u-boot for a new gaisler board (gr-pci-xc5v-LX110T). I have some trouble with the leon3/start.S and the linking process so I tried to build u-boot from a fresh clean GIT source with the board on board/gaisler/gr_xc3s_1500 which should be supported. And I'm having the same linking problem. I have already tried the u-boot 1.3.3 which is working on my board (booting, but the flash is not supported). The linking problem is the following: On version v2013.04: * In the relocation loop, the start.S define 2 variables which is set during the link: ============= /* un relocated start address of monitor */ #define TEXT_START _text /* un relocated end address of monitor */ #define DATA_END __init_end reloc: set TEXT_START,%g2 set DATA_END,%g3 set CONFIG_SYS_RELOC_MONITOR_BASE,%g4 reloc_loop: ============= * compiling this start.S give the following relocation record ============= RELOCATION RECORDS FOR [.text]: OFFSET TYPE VALUE 0000009c R_SPARC_WDISP30 cpu_init_f 000000a4 R_SPARC_HI22 _text 000000a8 R_SPARC_LO10 _text 000000ac R_SPARC_HI22 __init_end 000000b0 R_SPARC_LO10 __init_end ============= with the following assembly code: ============= 000000a4 <reloc>: a4: 05 00 00 00 sethi %hi(0), %g2 a8: 84 10 a0 00 mov %g2, %g2 ! 0 <_hardreset> ac: 07 00 00 00 sethi %hi(0), %g3 b0: 86 10 e0 00 mov %g3, %g3 ! 0 <_hardreset> b4: 09 10 fe 38 sethi %hi(0x43f8e000), %g4 000000b8 <reloc_loop>: ============= For now, everythings is normal. After the linking process, I've the following elf: ============= 000010a4 <reloc>: 10a4: 05 00 00 03 sethi %hi(0xc00), %g2 10a8: 84 10 a1 3c or %g2, 0x13c, %g2 ! d3c <MINFRAME+0xce0> 10ac: 07 00 00 03 sethi %hi(0xc00), %g3 10b0: 86 10 e1 30 or %g3, 0x130, %g3 ! d30 <MINFRAME+0xcd4> 10b4: 09 10 fe 38 sethi %hi(0x43f8e000), %g4 ============= And the associated .map: ============= .text 0x0000000000000000 0x2d2b8 0x0000000000000000 _load_addr = . 0x0000000000000000 _text = . [...] .data.init *(.data.init) 0x0000000000030000 . = ALIGN (0x1000) 0x0000000000030000 __init_end = . 0x0000000000030000 __bss_start = . ============= And the others symbol in this start.S are not defined correctly either. On the v2013.01 version, I've the same intermediate file but the following u-boot elf: ============= 000010a4 <reloc>: 10a4: 05 00 00 00 sethi %hi(0), %g2 10a8: 84 10 a0 00 mov %g2, %g2 ! 0 <_load_addr> 10ac: 07 00 00 c0 sethi %hi(0x30000), %g3 10b0: 86 10 e0 00 mov %g3, %g3 ! 30000 <__bss_start> 10b4: 09 10 fe 38 sethi %hi(0x43f8e000), %g4 ============= Which is what I expected. On IRC, Marex give me the advice to check with git bisect and find the commit which (I think) break the linking process. And It found this one: ============================= eb33809f70e3d3a2c1fba043e56cca8fccedbe0c is the first bad commit commit eb33809f70e3d3a2c1fba043e56cca8fccedbe0c Author: Simon Glass <sjg(a)chromium.org> Date: Tue Mar 5 14:40:03 2013 +0000 sparc: Fix out-of-tree building It isn't clear why the sparc cpu Makefile has its own compile line, but it does not work correctly with an out-of-tree build. Removing it fixes this problem. Perhaps it does not introduce others. Signed-off-by: Simon Glass <sjg(a)chromium.org> :040000 040000 39dc0c7a3ff2feadaddeda1b7938502f30f2ed76 7e77469d3aa8550d3f712470d45ef73e46b217b8 M arch bisect run success ============================ Which corresponds to remove the specific makefile for sparc. So what did i do wrong or misunderstund about the compiling u-boot process? Why removing specific compile process for sparc? Best, -- Florian.

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[U-Boot] [PATCH v4 0/3] pmic:pfuze support buck regulator mode switch
by Peng Fan 24 Jan '15

24 Jan '15

Hi, Przemyslaw There is a few return value comments that from Fabio, I correct them and send out v4 version. Others are same to the v1 version patch set. If this patch set is fine, please give you Acked-by. Sorry for the troubles. This patch set is to support buck regulator can working in different switching modes. To improve system efficiency the buck regulators can operate in different switching modes. patch 1/3 is to add related bit definitions and registers. patch 2/3 is to implement the switching mode init function. patch 3/3 is to add related mode init function in board code. mx6slevk board is not included in this patch set, since power and i2c interface are not implemented for it. Future patch will cover this to add PAD setting, power_init_board and etc. Peng Fan (3): pmic:pfuz100 add switch mode and more registers pmic:pfuze implement pmic_mode_init imx:mx6 set normal APS and standby PFM mode board/freescale/common/pfuze.c | 36 ++++++++++++++++++ board/freescale/common/pfuze.h | 1 + board/freescale/mx6qsabreauto/mx6qsabreauto.c | 6 +++ board/freescale/mx6sabresd/mx6sabresd.c | 6 ++- board/freescale/mx6sxsabresd/mx6sxsabresd.c | 6 ++- include/power/pfuze100_pmic.h | 53 +++++++++++++++++++++++++++ 6 files changed, 106 insertions(+), 2 deletions(-) -- 1.8.4

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[U-Boot] x86 FSP - delayed SDRAM init?
by Simon Glass 24 Jan '15

24 Jan '15

Hi Bin, In the Baytrail FSP docs I see a note about the HOB passing back the 'Boot Loader Temporary Memory Data HOB'. This seems to be a copy of the entire temporary memory space. I wonder if we could recover struct global_data from this? If so, then we could move the fsp_init stuff to dram_init(), perhaps? But perhaps this is a feature of only this FSP? Regards, Simon

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