June 2014 - U-Boot

Re: [U-Boot] U-Boot Digest, Vol 73, Issue 47
by luca.luminari＠spesonline.com 27 Jun '14

27 Jun '14

Grazie per il tuo messaggio. Sono fuori azienda con accesso limitato alle mail fino al 3 Luglio. Thank you for your message I am out of office and will be back on Thursday the third of July.

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Re: [U-Boot] U-Boot Digest, Vol 73, Issue 46
by luca.luminari＠spesonline.com 27 Jun '14

27 Jun '14

Grazie per il tuo messaggio. Sono fuori azienda con accesso limitato alle mail fino al 3 Luglio. Thank you for your message I am out of office and will be back on Thursday the third of July.

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[U-Boot] [RFC PATCH 0/3] Implement "fastboot flash" for eMMC
by Steve Rae 27 Jun '14

27 Jun '14

This series implements the "fastboot flash" command for eMMC devices. It supports both raw and sparse images. NOTES: - the support for the "fastboot flash" command is enabled with CONFIG_FASTBOOT_FLASH - the support for eMMC is enabled with CONFIG_FASTBOOT_FLASH_MMC_DEV - (future) the support for NAND would be enabled with CONFIG_FASTBOOT_FLASH_NAND(???) - thus the proposal is to place the code in common/fb_mmc.c and (future) common/fb_nand.c(???), however, this may not be the appropriate location.... This has been tested on ARMv7. This is a WIP -- and I would appreciate some comments/advice... Thanks, Steve Steve Rae (3): usb/gadget: fastboot: add sparse image definitions usb/gadget: fastboot: add eMMC support for flash command usb/gadget: fastboot: add support for flash command README | 10 +++ common/Makefile | 5 ++ common/fb_mmc.c | 144 ++++++++++++++++++++++++++++++++++++++++ doc/README.android-fastboot | 5 +- drivers/usb/gadget/f_fastboot.c | 31 +++++++++ include/fb_mmc.h | 8 +++ include/sparse_format.h | 58 ++++++++++++++++ 7 files changed, 259 insertions(+), 2 deletions(-) create mode 100644 common/fb_mmc.c create mode 100644 include/fb_mmc.h create mode 100644 include/sparse_format.h -- 1.8.5

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[U-Boot] [PATCH] powerpc/t4240qds: fix offset of serdes when checking its' reference clock
by shh.xie＠gmail.com 27 Jun '14

27 Jun '14

From: Shaohui Xie <Shaohui.Xie(a)freescale.com> T4240 has 4 serdes, each serdes has 4k memory space, two PLLs. We use PLL1CR0 to check the serdes reference clock. Signed-off-by: Shaohui Xie <Shaohui.Xie(a)freescale.com> --- arch/powerpc/include/asm/immap_85xx.h | 6 ++++++ board/freescale/t4qds/t4240qds.c | 10 ++++++---- 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 8258ab3..dfb370e 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -2905,6 +2905,8 @@ struct ccsr_sfp_regs { #endif #define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000 #define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000 +#define CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET 0xEC000 +#define CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET 0xED000 #define CONFIG_SYS_FSL_CPC_OFFSET 0x10000 #define CONFIG_SYS_FSL_SCFG_OFFSET 0xFC000 #define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x100000 @@ -3090,6 +3092,10 @@ struct ccsr_sfp_regs { (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET) #define CONFIG_SYS_FSL_CORENET_SERDES2_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET) +#define CONFIG_SYS_FSL_CORENET_SERDES3_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET) +#define CONFIG_SYS_FSL_CORENET_SERDES4_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET) #define CONFIG_SYS_MPC85xx_USB1_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_OFFSET) #define CONFIG_SYS_MPC85xx_USB2_ADDR \ diff --git a/board/freescale/t4qds/t4240qds.c b/board/freescale/t4qds/t4240qds.c index fe1bc7f..cbe62c1 100644 --- a/board/freescale/t4qds/t4240qds.c +++ b/board/freescale/t4qds/t4240qds.c @@ -638,9 +638,10 @@ unsigned long get_board_ddr_clk(void) int misc_init_r(void) { u8 sw; - serdes_corenet_t *srds_regs = - (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + void *srds_base = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + serdes_corenet_t *srds_regs; u32 actual[MAX_SERDES]; + u32 pllcr0, expected; unsigned int i; sw = QIXIS_READ(brdcfg[2]); @@ -663,8 +664,9 @@ int misc_init_r(void) } for (i = 0; i < MAX_SERDES; i++) { - u32 pllcr0 = srds_regs->bank[i].pllcr0; - u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; + srds_regs = srds_base + i * 0x1000; + pllcr0 = srds_regs->bank[0].pllcr0; + expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; if (expected != actual[i]) { printf("Warning: SERDES%u expects reference clock %sMHz, but actual is %sMHz\n", i + 1, serdes_clock_to_string(expected), -- 1.8.0

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[U-Boot] [PATCH] driver/ddr: Fix DDR register timing_cfg_8
by York Sun 26 Jun '14

26 Jun '14

The field wrtord_bg should add 2 clocks if on the fly chop is enabled, according to DDR controller manual for DDR4. Signed-off-by: York Sun <yorksun(a)freescale.com> --- drivers/ddr/fsl/ctrl_regs.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index dcf6287..04e4178 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -1857,6 +1857,9 @@ static void set_timing_cfg_8(fsl_ddr_cfg_regs_t *ddr, acttoact_bg = picos_to_mclk(common_dimm->trrdl_ps); wrtord_bg = max(4, picos_to_mclk(7500)); + if (popts->otf_burst_chop_en) + wrtord_bg += 2; + pre_all_rec = 0; ddr->timing_cfg_8 = (0 -- 1.7.9.5

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[U-Boot] Why spi flash probe runs twice ?
by Heshsham Abdul Basit 26 Jun '14

26 Jun '14

Hi, This is a section of the log from u-boot running on Avnet Microzed board: [Thu Jun 26 17:40:53.656 2014] [Thu Jun 26 17:40:53.656 2014] [Thu Jun 26 17:40:53.656 2014] U-Boot 2013.07 (Jun 26 2014 - 17:34:41) [Thu Jun 26 17:40:53.656 2014] [Thu Jun 26 17:40:53.656 2014] 1 GiB [Thu Jun 26 17:40:53.671 2014] SF: Detected S25FL129P_64K/S25FL128S_64K with page size 64 KiB, total 16 MiB [Thu Jun 26 17:40:53.703 2014] *** Warning - bad CRC, using default environment [Thu Jun 26 17:40:53.703 2014] [Thu Jun 26 17:40:53.703 2014] In: serial [Thu Jun 26 17:40:53.703 2014] Out: serial [Thu Jun 26 17:40:53.703 2014] Err: serial [Thu Jun 26 17:40:53.703 2014] U-BOOT for suheb_24 [Thu Jun 26 17:40:53.703 2014] [Thu Jun 26 17:40:53.703 2014] [Thu Jun 26 17:40:53.703 2014] SF: Detected S25FL129P_64K/S25FL128S_64K with page size 64 KiB, total 16 MiB [Thu Jun 26 17:40:54.453 2014] SF: 5242880 bytes @ 0x520000 Read: OK [Thu Jun 26 17:40:54.453 2014] Description: PetaLinux Kernel [Thu Jun 26 17:40:54.453 2014] 0x010000f0 [Thu Jun 26 17:40:54.453 2014] 4620145 Bytes = 4.4 MiB [Thu Jun 26 17:40:54.453 2014] Description: Flattened Device Tree blob [Thu Jun 26 17:40:54.453 2014] 0x01468114 [Thu Jun 26 17:40:54.453 2014] 9766 Bytes = 9.5 KiB [Thu Jun 26 17:40:54.453 2014] Hash algo: crc32 [Thu Jun 26 17:40:54.453 2014] Hash value: 9a94aca8 [Thu Jun 26 17:40:54.453 2014] Hash algo: sha1 [Thu Jun 26 17:40:54.453 2014] Hash value: 97b81e3014decb706ff19e61e1227dace97d4232 [Thu Jun 26 17:40:54.453 2014] crc32+ sha1+ Uncompressing Kernel Image ... OK . . . I noticed that the following lines are coming twice: SF: Detected S25FL129P_64K/S25FL128S_64K with page size 64 KiB, total 16 MiB This corresponds to the function spi_flash_probe from drivers/mtd/spi/spi_flash.c I need to know: 1- Why it is probed twice? 2- The name and location of the file from where it is called (twice). 3- The second time it is being probed it is conciderably slow, why it is so? Thanks and regards, Abdul Basit

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[U-Boot] [PATCH V2 00/10] peach_pit: Add support for FIMD, DP and parade chip
by Ajay Kumar 26 Jun '14

26 Jun '14

Patchset V1: https://www.mail-archive.com/u-boot@lists.denx.de/msg140596.html Patch 6 is TEST_ONLY since Simon will be sending it as a part of device model changes. Patch 10 is TEST_ONLY and it adds support for cros-ec on peach_pit. Simon will be sending a proper patchset for the same. Changes from V1: [PATCH V2 3/10] : Don't mix cpu_is and proid_isas per Minkyu's suggestion. Also, incorporate Simon's suggestion of not using else. [PATCH V2 4/10] : For FIMD SYSMMU DT, use same compatible string as kernel. [TEST_ONLY V2 6/10]: Make this patch TEST_ONLY Ajay Kumar (9): [PATCH V2 1/10] exynos_fb: Remove usage of static defines [PATCH V2 2/10] arm: exynos: Add RPLL for Exynos5420 [PATCH V2 3/10] arm: exynos: Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 [PATCH V2 4/10] video: exynos_fimd: Add framework to disable FIMD sysmmu [TEST_ONLY V2 6/10] ARM: exynos: Add missing declaration for gpio_direction_input [PATCH V2 7/10] exynos5420: add callbacks needed for exynos_fb driver [PATCH V2 8/10] ARM: exynos: peach_pit: Add DT nodes for fimd and parade bridge chip [PATCH V2 9/10] CONFIGS: peach_pit: Enable display for peach_pit board [TEST_ONLY V2 10/10] Pit WIP Vadim Bendebury (1): [PATCH V2 5/10] video: Add driver for Parade PS8625 dP to LVDS bridge arch/arm/cpu/armv7/exynos/clock.c | 83 +++++++++- arch/arm/cpu/armv7/exynos/clock_init.h | 3 + arch/arm/cpu/armv7/exynos/clock_init_exynos5.c | 13 ++ arch/arm/cpu/armv7/exynos/exynos5_setup.h | 2 +- arch/arm/dts/exynos5420-peach-pit.dts | 30 ++++ arch/arm/dts/exynos54xx.dtsi | 10 ++ arch/arm/include/asm/arch-exynos/clk.h | 1 + arch/arm/include/asm/arch-exynos/gpio.h | 1 + arch/arm/include/asm/arch-exynos/system.h | 4 + board/samsung/common/board.c | 15 ++ board/samsung/smdk5420/smdk5420.c | 129 ++++++--------- doc/device-tree-bindings/video/exynos-fb.txt | 6 + drivers/misc/cros_ec_spi.c | 4 +- drivers/power/pmic/Makefile | 3 +- drivers/power/pmic/pmic_tps65090_ec.c | 212 ++++++++++++++++++++++++ drivers/spi/exynos_spi.c | 9 +- drivers/spi/spi.c | 2 + drivers/video/Makefile | 1 + drivers/video/exynos_fb.c | 17 +- drivers/video/exynos_fimd.c | 43 +++++ drivers/video/parade.c | 220 +++++++++++++++++++++++++ include/configs/exynos5-dt.h | 2 +- include/configs/exynos5250-dt.h | 2 - include/configs/peach-pit.h | 12 ++ include/configs/s5pc210_universal.h | 3 - include/configs/trats.h | 3 - include/configs/trats2.h | 3 - include/fdtdec.h | 2 + include/power/tps65090_pmic.h | 6 + lib/fdtdec.c | 2 + 30 files changed, 724 insertions(+), 119 deletions(-) create mode 100644 drivers/power/pmic/pmic_tps65090_ec.c create mode 100644 drivers/video/parade.c -- 1.8.1.2

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[U-Boot] [PATCH] mx25pdk: Remove CONFIG_SYS_GENERIC_BOARD
by Fabio Estevam 26 Jun '14

26 Jun '14

From: Fabio Estevam <fabio.estevam(a)freescale.com> With CONFIG_SYS_GENERIC_BOARD the board hangs after issuing a 'save' command. Remove CONFIG_SYS_GENERIC_BOARD until this issue can be fixed properly. Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- Stefano, I will not have time to debug this prior to 2014.07 version. It would be better if this patch could be applied so that mx25pdk keeps working in 2014.07. I can then investigate and provide a proper fix after 2014.07 is out. include/configs/mx25pdk.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/configs/mx25pdk.h b/include/configs/mx25pdk.h index cfaf6ca..aff2419 100644 --- a/include/configs/mx25pdk.h +++ b/include/configs/mx25pdk.h @@ -26,8 +26,6 @@ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG -#define CONFIG_SYS_GENERIC_BOARD - #define CONFIG_MACH_TYPE MACH_TYPE_MX25_3DS /* Size of malloc() pool */ -- 1.8.3.2

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[U-Boot] [PATCH] Add Epson RX8581 RTC support
by Johannes Thumshirn 26 Jun '14

26 Jun '14

Signed-off-by: Johannes Thumshirn <johannes.thumshirn(a)men.de> --- drivers/rtc/Makefile | 1 + drivers/rtc/rx8581.c | 180 +++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 181 insertions(+) create mode 100644 drivers/rtc/rx8581.c diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index d5a2725..1502166 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -48,5 +48,6 @@ obj-$(CONFIG_RTC_RS5C372A) += rs5c372.o obj-$(CONFIG_RTC_RTC4543) += rtc4543.o obj-$(CONFIG_RTC_RV3029) += rv3029.o obj-$(CONFIG_RTC_RX8025) += rx8025.o +obj-$(CONFIG_RTC_RX8581) += rx8581.o obj-$(CONFIG_RTC_S3C24X0) += s3c24x0_rtc.o obj-$(CONFIG_RTC_X1205) += x1205.o diff --git a/drivers/rtc/rx8581.c b/drivers/rtc/rx8581.c new file mode 100644 index 0000000..71466d6 --- /dev/null +++ b/drivers/rtc/rx8581.c @@ -0,0 +1,180 @@ + /* + * (C) Copyright 2011 + * Ralf Truebenbach <ralf.truebenbach(a)men.de>, MEN Mikro Elektronik GmbH + * + * Based on: pcf8563.c + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Date & Time support for Epson RX8581 RTC + */ + +/* #define DEBUG */ + +#include <common.h> +#include <command.h> +#include <rtc.h> +#include <i2c.h> + +#if defined(CONFIG_CMD_DATE) + +static uchar rtc_read(uchar reg); +static void rtc_write(uchar reg, uchar val); + +/* registers */ +#define RX8581_SEC 0x00 +#define RX8581_MIN 0x01 +#define RX8581_HOUR 0x02 +#define RX8581_WEEK 0x03 +#define RX8581_DAY 0x04 +#define RX8581_MONTH 0x05 +#define RX8581_YEAR 0x06 +#define RX8581_FLAG 0x0E +#define RX8581_CONTROL 0x0F + +/* masks */ +#define RX8581_SEC_MSK 0x7f +#define RX8581_MIN_MSK 0x7f +#define RX8581_HOUR_MSK 0x3f +#define RX8581_WEEK_MSK 0x7f +#define RX8581_DAY_MSK 0x3f +#define RX8581_MONTH_MSK 0x1f + +/* bits */ +#define RX8581_FLAG_VLF 0x02 + +#define RX8581_CONTROL_STOP 0x02 +#define RX8581_CONTROL_RESET 0x01 + +/* ------------------------------------------------------------------------- */ + +int rtc_get(struct rtc_time *tmp) +{ + int rel = 0; + uchar sec, min, hour, day, week, month, year, flag; + + sec = rtc_read(RX8581_SEC); + min = rtc_read(RX8581_MIN); + hour = rtc_read(RX8581_HOUR); + week = rtc_read(RX8581_WEEK); + day = rtc_read(RX8581_DAY); + month = rtc_read(RX8581_MONTH); + year = rtc_read(RX8581_YEAR); + flag = rtc_read(RX8581_FLAG); + + debug("Get RTC YEAR: 0x%02x MONTH: 0x%02x DAY: 0x%02x WEEK: 0x%02x ", + year, month, day, week); + debug("HOUR: 0x%02x MIN: 0x%02x SEC: 0x%02x Flag: 0x%02x\n", + hour, min, sec, flag); + debug("Alarms: MIN: 0x%02x HOUR: 0x%02x WEEK/DAY: 0x%02x\n", + rtc_read(0x08), rtc_read(0x09), rtc_read(0x0A)); + + if (flag & RX8581_FLAG_VLF) { + puts("## Warning: RTC Low Voltage - date/time not reliable\n"); + rel = -1; + } + + tmp->tm_sec = bcd2bin(sec & RX8581_SEC_MSK); + tmp->tm_min = bcd2bin(min & RX8581_MIN_MSK); + tmp->tm_hour = bcd2bin(hour & RX8581_HOUR_MSK); + tmp->tm_mday = bcd2bin(day & RX8581_DAY_MSK); + tmp->tm_mon = bcd2bin(month & RX8581_MONTH_MSK); + tmp->tm_year = bcd2bin(year) + (bcd2bin(year) >= 70 ? 1900 : 2000); + tmp->tm_wday = __ilog2(week & RX8581_WEEK_MSK); + tmp->tm_yday = 0; + tmp->tm_isdst = 0; + + debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + + return rel; +} + +int rtc_set(struct rtc_time *tmp) +{ + uchar reg; + + debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + + if (tmp->tm_year < 1970 || tmp->tm_year > 2069) + puts("## Warning: year should be between 1970 and 2069!\n"); + + /* stop */ + reg = rtc_read(RX8581_CONTROL); + rtc_write(RX8581_CONTROL, reg | RX8581_CONTROL_STOP); + + /* write data */ + rtc_write(RX8581_SEC, bin2bcd(tmp->tm_sec)); + rtc_write(RX8581_MIN, bin2bcd(tmp->tm_min)); + rtc_write(RX8581_HOUR, bin2bcd(tmp->tm_hour)); + rtc_write(RX8581_WEEK, bin2bcd(0x1 << tmp->tm_wday)); + rtc_write(RX8581_DAY, bin2bcd(tmp->tm_mday)); + rtc_write(RX8581_MONTH, bin2bcd(tmp->tm_mon)); + rtc_write(RX8581_YEAR, bin2bcd(tmp->tm_year % 100)); + + /* clear VLF */ + reg = rtc_read(RX8581_FLAG); + rtc_write(RX8581_FLAG, reg & ~RX8581_FLAG_VLF); + + /* restart */ + reg = rtc_read(RX8581_CONTROL); + rtc_write(RX8581_CONTROL, reg & ~RX8581_CONTROL_STOP); + + return 0; +} + +void rtc_reset(void) +{ + struct rtc_time tmp; + + /* reset device */ + rtc_write(0x0F, 0x03); + rtc_write(0x0F, 0x00); + + /* reset time */ + tmp.tm_year = 1970; + tmp.tm_mon = 1; + tmp.tm_mday = 1; + tmp.tm_hour = 0; + tmp.tm_min = 0; + tmp.tm_sec = 0; + + rtc_set(&tmp); +} + +/* ------------------------------------------------------------------------- */ + +static uchar rtc_read(uchar reg) +{ + return i2c_reg_read(CONFIG_SYS_I2C_RTC_ADDR, reg); +} + +static void rtc_write(uchar reg, uchar val) +{ + i2c_reg_write(CONFIG_SYS_I2C_RTC_ADDR, reg, val); +} + +#endif -- 1.9.1

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[U-Boot] [PATCH] powerpc/ifc: fix invalid CSn FTIM2.TCH setting
by shh.xie＠gmail.com 26 Jun '14

26 Jun '14

From: Shaohui Xie <Shaohui.Xie(a)freescale.com> On some platforms, CSn FTIM2.TCH is set to zero which is invalid, an invalid hold time makes DUT timing variances, whether it works or not on luck. Signed-off-by: Shaohui Xie <Shaohui.Xie(a)freescale.com> --- based on 'next' of git://git.denx.de/u-boot-mpc85xx.git. include/configs/B4860QDS.h | 2 +- include/configs/BSC9132QDS.h | 2 +- include/configs/C29XPCIE.h | 2 +- include/configs/P1010RDB.h | 2 +- include/configs/T104xRDB.h | 2 +- include/configs/T208xRDB.h | 2 +- include/configs/T4240QDS.h | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index 1af9ba6..43c9df0 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -340,7 +340,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ FTIM1_GPCM_TRAD(0x1f)) #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ - FTIM2_GPCM_TCH(0x0) | \ + FTIM2_GPCM_TCH(0x8) | \ FTIM2_GPCM_TWP(0x1f)) #define CONFIG_SYS_CS3_FTIM3 0x0 diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h index 7bb5d33..49c16af 100644 --- a/include/configs/BSC9132QDS.h +++ b/include/configs/BSC9132QDS.h @@ -354,7 +354,7 @@ combinations. this should be removed later #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ FTIM1_GPCM_TRAD(0x1f)) #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ - FTIM2_GPCM_TCH(0x0) | \ + FTIM2_GPCM_TCH(0x8) | \ FTIM2_GPCM_TWP(0x1f)) #define CONFIG_SYS_CS2_FTIM3 0x0 #endif diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index 9e12fac..0dd1560 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -319,7 +319,7 @@ #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ FTIM1_GPCM_TRAD(0x1f)) #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ - FTIM2_GPCM_TCH(0x0) | \ + FTIM2_GPCM_TCH(0x8) | \ FTIM2_GPCM_TWP(0x1f)) #define CONFIG_SYS_CS2_FTIM3 0x0 diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index d612a8b..50529bf 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -537,7 +537,7 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ FTIM1_GPCM_TRAD(0x1f)) #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ - FTIM2_GPCM_TCH(0x0) | \ + FTIM2_GPCM_TCH(0x8) | \ FTIM2_GPCM_TWP(0x1f)) #define CONFIG_SYS_CS3_FTIM3 0x0 diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 8d6c51b..40bfc60 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -286,7 +286,7 @@ #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ FTIM1_GPCM_TRAD(0x1f)) #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ - FTIM2_GPCM_TCH(0x0) | \ + FTIM2_GPCM_TCH(0x8) | \ FTIM2_GPCM_TWP(0x1f)) #define CONFIG_SYS_CS2_FTIM3 0x0 diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 3a1c49c..5d10ad2 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -283,7 +283,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ FTIM1_GPCM_TRAD(0x1f)) #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ - FTIM2_GPCM_TCH(0x0) | \ + FTIM2_GPCM_TCH(0x8) | \ FTIM2_GPCM_TWP(0x1f)) #define CONFIG_SYS_CS2_FTIM3 0x0 diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h index a770dd0..efdb68b 100644 --- a/include/configs/T4240QDS.h +++ b/include/configs/T4240QDS.h @@ -237,7 +237,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ FTIM1_GPCM_TRAD(0x3f)) #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ - FTIM2_GPCM_TCH(0x0) | \ + FTIM2_GPCM_TCH(0x8) | \ FTIM2_GPCM_TWP(0x1f)) #define CONFIG_SYS_CS3_FTIM3 0x0 -- 1.8.0

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