April 2014 - U-Boot

[U-Boot] [PATCHv2 00/10] mmc: code cleanup and support DDR mode
by Jaehoon Chung 02 Apr '14

02 Apr '14

If card and host are supported DDR mode, then it can be used the DDR mode. This patch-set has dependency about beomho's patch-set. (Based-on u-boot-samsung repository) http://patchwork.ozlabs.org/patch/331986/ http://patchwork.ozlabs.org/patch/331987/ http://patchwork.ozlabs.org/patch/331989/ http://patchwork.ozlabs.org/patch/331988/ It's result for loading image. sdhci controller ->5260488 bytes read in 259 ms (19.4 MiB/s) dwmmc controller without DDR mode -> 5260488 bytes read in 202 ms (24.8 MiB/s) dwmmc controller with DDR mode -> 5260488 bytes read in 118 ms (42.5 MiB/s) Download the 400M image with lthor. sdhci controller -> 59.4sec (Avg 6.95 MB/s) dwmmc controller without DDR mode -> 61.6sec (Avg 6.72MB/s) dwmmc controller with DDR mode -> 60.4sec (Avg 6.85MB/s) Jaehoon Chung (10): mmc: s5p_sdhci: add the s5p_sdhci_core_init function ARM: exynos: board: change the mmc/sd init sequence ARM: exynos: clock: modify the set_mmc_clk for exynos4 mmc: exynos_dw_mmc: restore the property into host mmc: remove the unnecessary define and fix the wrong bit control mmc: support the DDR mode for eMMC mmc: dw_mmc: support the DDR mode ARM: dts: exnyos: enable dw-mmc controller mmc: exynos_dw_mmc: enable the DDR mode ARM: exynos4: enable the dwmmc configuration arch/arm/cpu/armv7/exynos/clock.c | 16 ++- arch/arm/dts/exynos4412-trats2.dts | 6 +- arch/arm/include/asm/arch-exynos/clk.h | 5 + board/samsung/common/board.c | 13 +- drivers/mmc/dw_mmc.c | 10 +- drivers/mmc/exynos_dw_mmc.c | 221 ++++++++++++++++++++------------ drivers/mmc/mmc.c | 16 ++- drivers/mmc/s5p_sdhci.c | 42 +++--- include/configs/exynos4-dt.h | 3 + include/dwmmc.h | 5 + include/mmc.h | 25 ++-- 11 files changed, 225 insertions(+), 137 deletions(-) -- 1.7.9.5

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[U-Boot] [PATCH] mmc: fsl_esdhc: add controller reset in case of data related errors too
by Andrew Gabbasov 02 Apr '14

02 Apr '14

The controller reset is performed now if command error occurs. This commit adds the reset for the case of data related errors too. Signed-off-by: Andrew Gabbasov <andrew_gabbasov(a)mentor.com> --- drivers/mmc/fsl_esdhc.c | 63 +++++++++++++++++++++++++++-------------------- 1 file changed, 36 insertions(+), 27 deletions(-) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index f4d3132..dfb1cc3 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -265,6 +265,7 @@ static void check_and_invalidate_dcache_range static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) { + int err = 0; uint xfertyp; uint irqstat; struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; @@ -296,8 +297,6 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) /* Set up for a data transfer if we have one */ if (data) { - int err; - err = esdhc_setup_data(mmc, data); if(err) return err; @@ -325,27 +324,15 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) irqstat = esdhc_read32(&regs->irqstat); - /* Reset CMD and DATA portions on error */ - if (irqstat & (CMD_ERR | IRQSTAT_CTOE)) { - esdhc_write32(&regs->sysctl, esdhc_read32(&regs->sysctl) | - SYSCTL_RSTC); - while (esdhc_read32(&regs->sysctl) & SYSCTL_RSTC) - ; - - if (data) { - esdhc_write32(&regs->sysctl, - esdhc_read32(&regs->sysctl) | - SYSCTL_RSTD); - while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD)) - ; - } + if (irqstat & CMD_ERR) { + err = COMM_ERR; + goto out; } - if (irqstat & CMD_ERR) - return COMM_ERR; - - if (irqstat & IRQSTAT_CTOE) - return TIMEOUT; + if (irqstat & IRQSTAT_CTOE) { + err = TIMEOUT; + goto out; + } /* Workaround for ESDHC errata ENGcm03648 */ if (!data && (cmd->resp_type & MMC_RSP_BUSY)) { @@ -360,7 +347,8 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) if (timeout <= 0) { printf("Timeout waiting for DAT0 to go high!\n"); - return TIMEOUT; + err = TIMEOUT; + goto out; } } @@ -387,20 +375,41 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) do { irqstat = esdhc_read32(&regs->irqstat); - if (irqstat & IRQSTAT_DTOE) - return TIMEOUT; + if (irqstat & IRQSTAT_DTOE) { + err = TIMEOUT; + goto out; + } - if (irqstat & DATA_ERR) - return COMM_ERR; + if (irqstat & DATA_ERR) { + err = COMM_ERR; + goto out; + } } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE); #endif if (data->flags & MMC_DATA_READ) check_and_invalidate_dcache_range(cmd, data); } +out: + /* Reset CMD and DATA portions on error */ + if (err) { + esdhc_write32(&regs->sysctl, esdhc_read32(&regs->sysctl) | + SYSCTL_RSTC); + while (esdhc_read32(&regs->sysctl) & SYSCTL_RSTC) + ; + + if (data) { + esdhc_write32(&regs->sysctl, + esdhc_read32(&regs->sysctl) | + SYSCTL_RSTD); + while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD)) + ; + } + } + esdhc_write32(&regs->irqstat, -1); - return 0; + return err; } static void set_sysctl(struct mmc *mmc, uint clock) -- 1.7.10.4

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[U-Boot] [PATCH] mmc: fsl_esdhc: fix calculation of timeout for data transactions
by Andrew Gabbasov 02 Apr '14

02 Apr '14

Calculation of the timeout value should be based on actual clock value, written to controller registers. Since mmc->tran_speed is either the maximum allowed speed, or the preliminary value, that is be not yet set to registers, the actual timeout, taken by the controller, based on its clock settings, may be much longer than expected, based on mmc->tran_speed value. In particular it happens at early initialization stage, when typical value of mmc->tran_speed is 20MHz or 26MHz, while actual clock setting, configured in the controller, is 400kHz. It's more correct to use mmc->clock value for timeout calculation instead. Signed-off-by: Andrew Gabbasov <andrew_gabbasov(a)mentor.com> --- drivers/mmc/fsl_esdhc.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 7b146a3..f4d3132 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -221,16 +221,16 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) * 2)Timeout period should be minimum 0.250sec as per SD Card spec * So, Number of SD Clock cycles for 0.25sec should be minimum * (SD Clock/sec * 0.25 sec) SD Clock cycles - * = (mmc->tran_speed * 1/4) SD Clock cycles + * = (mmc->clock * 1/4) SD Clock cycles * As 1) >= 2) - * => (2^(timeout+13)) >= mmc->tran_speed * 1/4 + * => (2^(timeout+13)) >= mmc->clock * 1/4 * Taking log2 both the sides - * => timeout + 13 >= log2(mmc->tran_speed/4) + * => timeout + 13 >= log2(mmc->clock/4) * Rounding up to next power of 2 - * => timeout + 13 = log2(mmc->tran_speed/4) + 1 - * => timeout + 13 = fls(mmc->tran_speed/4) + * => timeout + 13 = log2(mmc->clock/4) + 1 + * => timeout + 13 = fls(mmc->clock/4) */ - timeout = fls(mmc->tran_speed/4); + timeout = fls(mmc->clock/4); timeout -= 13; if (timeout > 14) -- 1.7.10.4

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[U-Boot] [PATCH 1/2] arm: mxs: Properly set GD pointer in SPL
by Marek Vasut 02 Apr '14

02 Apr '14

Set the GD pointer in the SPL to a defined symbol so various functions from U-Boot can be used without adverse side effects. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Stefano Babic <sbabic(a)denx.de> --- arch/arm/cpu/arm926ejs/mxs/spl_boot.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c index 68c30af..87b63c1 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c @@ -13,9 +13,13 @@ #include <asm/arch/imx-regs.h> #include <asm/arch/sys_proto.h> #include <asm/gpio.h> +#include <linux/compiler.h> #include "mxs_init.h" +DECLARE_GLOBAL_DATA_PTR; +gd_t gdata __section(".data"); + /* * This delay function is intended to be used only in early stage of boot, where * clock are not set up yet. The timer used here is reset on every boot and @@ -109,6 +113,7 @@ void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr, struct mxs_spl_data *data = (struct mxs_spl_data *) ((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf); uint8_t bootmode = mxs_get_bootmode_index(); + gd = &gdata; mxs_iomux_setup_multiple_pads(iomux_setup, iomux_size); mxs_power_init(); -- 1.8.5.2

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[U-Boot] NAND SPL on imx6
by Andy Ng 02 Apr '14

02 Apr '14

Dear colleagues, Has anyone tried to build NAND SPL support on imx6. Does it work? Best regards, Andy

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[U-Boot] [PATCH 1/6] arm: rmobile: Coordinate the common part of the header file of r8a7790 and r8a7791
by Nobuhiro Iwamatsu 02 Apr '14

02 Apr '14

Header files of R8A7790 and R8A7791 have common part of many. This coordinates as rcar-base.h. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj(a)renesas.com> --- arch/arm/include/asm/arch-rmobile/r8a7790.h | 607 +----------------------- arch/arm/include/asm/arch-rmobile/r8a7791.h | 624 +------------------------ arch/arm/include/asm/arch-rmobile/rcar-base.h | 633 ++++++++++++++++++++++++++ 3 files changed, 640 insertions(+), 1224 deletions(-) create mode 100644 arch/arm/include/asm/arch-rmobile/rcar-base.h diff --git a/arch/arm/include/asm/arch-rmobile/r8a7790.h b/arch/arm/include/asm/arch-rmobile/r8a7790.h index d9ea71f..bd210d0 100644 --- a/arch/arm/include/asm/arch-rmobile/r8a7790.h +++ b/arch/arm/include/asm/arch-rmobile/r8a7790.h @@ -1,615 +1,14 @@ /* * arch/arm/include/asm/arch-rmobile/r8a7790.h * - * Copyright (C) 2013 Renesas Electronics Corporation + * Copyright (C) 2013,2014 Renesas Electronics Corporation * * SPDX-License-Identifier: GPL-2.0 - */ +*/ #ifndef __ASM_ARCH_R8A7790_H #define __ASM_ARCH_R8A7790_H -/* - * R8A7790 I/O Addresses - */ -#define RWDT_BASE 0xE6020000 -#define SWDT_BASE 0xE6030000 -#define LBSC_BASE 0xFEC00200 -#define DBSC3_0_BASE 0xE6790000 -#define DBSC3_1_BASE 0xE67A0000 -#define TMU_BASE 0xE61E0000 -#define GPIO5_BASE 0xE6055000 -#define SH_QSPI_BASE 0xE6B10000 - -#define S3C_BASE 0xE6784000 -#define S3C_INT_BASE 0xE6784A00 -#define S3C_MEDIA_BASE 0xE6784B00 - -#define S3C_QOS_DCACHE_BASE 0xE6784BDC -#define S3C_QOS_CCI0_BASE 0xE6784C00 -#define S3C_QOS_CCI1_BASE 0xE6784C24 -#define S3C_QOS_MXI_BASE 0xE6784C48 -#define S3C_QOS_AXI_BASE 0xE6784C6C - -#define DBSC3_0_QOS_R0_BASE 0xE6791000 -#define DBSC3_0_QOS_R1_BASE 0xE6791100 -#define DBSC3_0_QOS_R2_BASE 0xE6791200 -#define DBSC3_0_QOS_R3_BASE 0xE6791300 -#define DBSC3_0_QOS_R4_BASE 0xE6791400 -#define DBSC3_0_QOS_R5_BASE 0xE6791500 -#define DBSC3_0_QOS_R6_BASE 0xE6791600 -#define DBSC3_0_QOS_R7_BASE 0xE6791700 -#define DBSC3_0_QOS_R8_BASE 0xE6791800 -#define DBSC3_0_QOS_R9_BASE 0xE6791900 -#define DBSC3_0_QOS_R10_BASE 0xE6791A00 -#define DBSC3_0_QOS_R11_BASE 0xE6791B00 -#define DBSC3_0_QOS_R12_BASE 0xE6791C00 -#define DBSC3_0_QOS_R13_BASE 0xE6791D00 -#define DBSC3_0_QOS_R14_BASE 0xE6791E00 -#define DBSC3_0_QOS_R15_BASE 0xE6791F00 -#define DBSC3_0_QOS_W0_BASE 0xE6792000 -#define DBSC3_0_QOS_W1_BASE 0xE6792100 -#define DBSC3_0_QOS_W2_BASE 0xE6792200 -#define DBSC3_0_QOS_W3_BASE 0xE6792300 -#define DBSC3_0_QOS_W4_BASE 0xE6792400 -#define DBSC3_0_QOS_W5_BASE 0xE6792500 -#define DBSC3_0_QOS_W6_BASE 0xE6792600 -#define DBSC3_0_QOS_W7_BASE 0xE6792700 -#define DBSC3_0_QOS_W8_BASE 0xE6792800 -#define DBSC3_0_QOS_W9_BASE 0xE6792900 -#define DBSC3_0_QOS_W10_BASE 0xE6792A00 -#define DBSC3_0_QOS_W11_BASE 0xE6792B00 -#define DBSC3_0_QOS_W12_BASE 0xE6792C00 -#define DBSC3_0_QOS_W13_BASE 0xE6792D00 -#define DBSC3_0_QOS_W14_BASE 0xE6792E00 -#define DBSC3_0_QOS_W15_BASE 0xE6792F00 - -#define DBSC3_0_DBADJ2 0xE67900C8 - -#define CCI_400_MAXOT_1 0xF0091110 -#define CCI_400_MAXOT_2 0xF0092110 -#define CCI_400_QOSCNTL_1 0xF009110C -#define CCI_400_QOSCNTL_2 0xF009210C - -#define MXI_BASE 0xFE960000 -#define MXI_QOS_BASE 0xFE960300 - -#define SYS_AXI_SYX64TO128_BASE 0xFF800300 -#define SYS_AXI_AVB_BASE 0xFF800340 -#define SYS_AXI_G2D_BASE 0xFF800540 -#define SYS_AXI_IMP0_BASE 0xFF800580 -#define SYS_AXI_IMP1_BASE 0xFF8005C0 -#define SYS_AXI_IMUX0_BASE 0xFF800600 -#define SYS_AXI_IMUX1_BASE 0xFF800640 -#define SYS_AXI_IMUX2_BASE 0xFF800680 -#define SYS_AXI_LBS_BASE 0xFF8006C0 -#define SYS_AXI_MMUDS_BASE 0xFF800700 -#define SYS_AXI_MMUM_BASE 0xFF800740 -#define SYS_AXI_MMUR_BASE 0xFF800780 -#define SYS_AXI_MMUS0_BASE 0xFF8007C0 -#define SYS_AXI_MMUS1_BASE 0xFF800800 -#define SYS_AXI_MTSB0_BASE 0xFF800880 -#define SYS_AXI_MTSB1_BASE 0xFF8008C0 -#define SYS_AXI_PCI_BASE 0xFF800900 -#define SYS_AXI_RTX_BASE 0xFF800940 -#define SYS_AXI_SDS0_BASE 0xFF800A80 -#define SYS_AXI_SDS1_BASE 0xFF800AC0 -#define SYS_AXI_USB20_BASE 0xFF800C00 -#define SYS_AXI_USB21_BASE 0xFF800C40 -#define SYS_AXI_USB22_BASE 0xFF800C80 -#define SYS_AXI_USB30_BASE 0xFF800CC0 - -#define RT_AXI_SHX_BASE 0xFF810100 -#define RT_AXI_RDS_BASE 0xFF8101C0 -#define RT_AXI_RTX64TO128_BASE 0xFF810200 -#define RT_AXI_STPRO_BASE 0xFF810240 - -#define MP_AXI_ADSP_BASE 0xFF820100 -#define MP_AXI_ASDS0_BASE 0xFF8201C0 -#define MP_AXI_ASDS1_BASE 0xFF820200 -#define MP_AXI_MLP_BASE 0xFF820240 -#define MP_AXI_MMUMP_BASE 0xFF820280 -#define MP_AXI_SPU_BASE 0xFF8202C0 -#define MP_AXI_SPUC_BASE 0xFF820300 - -#define SYS_AXI256_AXI128TO256_BASE 0xFF860100 -#define SYS_AXI256_SYX_BASE 0xFF860140 -#define SYS_AXI256_MPX_BASE 0xFF860180 -#define SYS_AXI256_MXI_BASE 0xFF8601C0 - -#define CCI_AXI_MMUS0_BASE 0xFF880100 -#define CCI_AXI_SYX2_BASE 0xFF880140 -#define CCI_AXI_MMUR_BASE 0xFF880180 -#define CCI_AXI_MMUDS_BASE 0xFF8801C0 -#define CCI_AXI_MMUM_BASE 0xFF880200 -#define CCI_AXI_MXI_BASE 0xFF880240 -#define CCI_AXI_MMUS1_BASE 0xFF880280 -#define CCI_AXI_MMUMP_BASE 0xFF8802C0 - -#define MEDIA_AXI_JPR_BASE 0xFE964100 -#define MEDIA_AXI_JPW_BASE 0xFE966100 -#define MEDIA_AXI_GCU0R_BASE 0xFE964140 -#define MEDIA_AXI_GCU0W_BASE 0xFE966140 -#define MEDIA_AXI_GCU1R_BASE 0xFE964180 -#define MEDIA_AXI_GCU1W_BASE 0xFE966180 -#define MEDIA_AXI_TDMR_BASE 0xFE964500 -#define MEDIA_AXI_TDMW_BASE 0xFE966500 -#define MEDIA_AXI_VSP0CR_BASE 0xFE964540 -#define MEDIA_AXI_VSP0CW_BASE 0xFE966540 -#define MEDIA_AXI_VSP1CR_BASE 0xFE964580 -#define MEDIA_AXI_VSP1CW_BASE 0xFE966580 -#define MEDIA_AXI_VSPDU0CR_BASE 0xFE9645C0 -#define MEDIA_AXI_VSPDU0CW_BASE 0xFE9665C0 -#define MEDIA_AXI_VSPDU1CR_BASE 0xFE964600 -#define MEDIA_AXI_VSPDU1CW_BASE 0xFE966600 -#define MEDIA_AXI_VIN0W_BASE 0xFE966900 -#define MEDIA_AXI_VSP0R_BASE 0xFE964D00 -#define MEDIA_AXI_VSP0W_BASE 0xFE966D00 -#define MEDIA_AXI_FDP0R_BASE 0xFE964D40 -#define MEDIA_AXI_FDP0W_BASE 0xFE966D40 -#define MEDIA_AXI_IMSR_BASE 0xFE964D80 -#define MEDIA_AXI_IMSW_BASE 0xFE966D80 -#define MEDIA_AXI_VSP1R_BASE 0xFE965100 -#define MEDIA_AXI_VSP1W_BASE 0xFE967100 -#define MEDIA_AXI_FDP1R_BASE 0xFE965140 -#define MEDIA_AXI_FDP1W_BASE 0xFE967140 -#define MEDIA_AXI_IMRR_BASE 0xFE965180 -#define MEDIA_AXI_IMRW_BASE 0xFE967180 -#define MEDIA_AXI_FDP2R_BASE 0xFE9651C0 -#define MEDIA_AXI_FDP2W_BASE 0xFE966DC0 -#define MEDIA_AXI_VSPD0R_BASE 0xFE965500 -#define MEDIA_AXI_VSPD0W_BASE 0xFE967500 -#define MEDIA_AXI_VSPD1R_BASE 0xFE965540 -#define MEDIA_AXI_VSPD1W_BASE 0xFE967540 -#define MEDIA_AXI_DU0R_BASE 0xFE965580 -#define MEDIA_AXI_DU0W_BASE 0xFE967580 -#define MEDIA_AXI_DU1R_BASE 0xFE9655C0 -#define MEDIA_AXI_DU1W_BASE 0xFE9675C0 -#define MEDIA_AXI_VCP0CR_BASE 0xFE965900 -#define MEDIA_AXI_VCP0CW_BASE 0xFE967900 -#define MEDIA_AXI_VCP0VR_BASE 0xFE965940 -#define MEDIA_AXI_VCP0VW_BASE 0xFE967940 -#define MEDIA_AXI_VPC0R_BASE 0xFE965980 -#define MEDIA_AXI_VCP1CR_BASE 0xFE965D00 -#define MEDIA_AXI_VCP1CW_BASE 0xFE967D00 -#define MEDIA_AXI_VCP1VR_BASE 0xFE965D40 -#define MEDIA_AXI_VCP1VW_BASE 0xFE967D40 -#define MEDIA_AXI_VPC1R_BASE 0xFE965D80 - -#define SYS_AXI_AVBDMSCR 0xFF802000 -#define SYS_AXI_SYX2DMSCR 0xFF802004 -#define SYS_AXI_CC50DMSCR 0xFF802008 -#define SYS_AXI_CC51DMSCR 0xFF80200C -#define SYS_AXI_CCIDMSCR 0xFF802010 -#define SYS_AXI_CSDMSCR 0xFF802014 -#define SYS_AXI_DDMDMSCR 0xFF802018 -#define SYS_AXI_ETHDMSCR 0xFF80201C -#define SYS_AXI_G2DDMSCR 0xFF802020 -#define SYS_AXI_IMP0DMSCR 0xFF802024 -#define SYS_AXI_IMP1DMSCR 0xFF802028 -#define SYS_AXI_LBSDMSCR 0xFF80202C -#define SYS_AXI_MMUDSDMSCR 0xFF802030 -#define SYS_AXI_MMUMXDMSCR 0xFF802034 -#define SYS_AXI_MMURDDMSCR 0xFF802038 -#define SYS_AXI_MMUS0DMSCR 0xFF80203C -#define SYS_AXI_MMUS1DMSCR 0xFF802040 -#define SYS_AXI_MPXDMSCR 0xFF802044 -#define SYS_AXI_MTSB0DMSCR 0xFF802048 -#define SYS_AXI_MTSB1DMSCR 0xFF80204C -#define SYS_AXI_PCIDMSCR 0xFF802050 -#define SYS_AXI_RTXDMSCR 0xFF802054 -#define SYS_AXI_SAT0DMSCR 0xFF802058 -#define SYS_AXI_SAT1DMSCR 0xFF80205C -#define SYS_AXI_SDM0DMSCR 0xFF802060 -#define SYS_AXI_SDM1DMSCR 0xFF802064 -#define SYS_AXI_SDS0DMSCR 0xFF802068 -#define SYS_AXI_SDS1DMSCR 0xFF80206C -#define SYS_AXI_ETRABDMSCR 0xFF802070 -#define SYS_AXI_ETRKFDMSCR 0xFF802074 -#define SYS_AXI_UDM0DMSCR 0xFF802078 -#define SYS_AXI_UDM1DMSCR 0xFF80207C -#define SYS_AXI_USB20DMSCR 0xFF802080 -#define SYS_AXI_USB21DMSCR 0xFF802084 -#define SYS_AXI_USB22DMSCR 0xFF802088 -#define SYS_AXI_USB30DMSCR 0xFF80208C -#define SYS_AXI_X128TO64SLVDMSCR 0xFF802100 -#define SYS_AXI_X64TO128SLVDMSCR 0xFF802104 -#define SYS_AXI_AVBSLVDMSCR 0xFF802108 -#define SYS_AXI_SYX2SLVDMSCR 0xFF80210C -#define SYS_AXI_ETHSLVDMSCR 0xFF802110 -#define SYS_AXI_GICSLVDMSCR 0xFF802114 -#define SYS_AXI_IMPSLVDMSCR 0xFF802118 -#define SYS_AXI_IMX0SLVDMSCR 0xFF80211C -#define SYS_AXI_IMX1SLVDMSCR 0xFF802120 -#define SYS_AXI_IMX2SLVDMSCR 0xFF802124 -#define SYS_AXI_LBSSLVDMSCR 0xFF802128 -#define SYS_AXI_MMC0SLVDMSCR 0xFF80212C -#define SYS_AXI_MMC1SLVDMSCR 0xFF802130 -#define SYS_AXI_MPXSLVDMSCR 0xFF802134 -#define SYS_AXI_MTSB0SLVDMSCR 0xFF802138 -#define SYS_AXI_MTSB1SLVDMSCR 0xFF80213C -#define SYS_AXI_MXTSLVDMSCR 0xFF802140 -#define SYS_AXI_PCISLVDMSCR 0xFF802144 -#define SYS_AXI_SYAPBSLVDMSCR 0xFF802148 -#define SYS_AXI_QSAPBSLVDMSCR 0xFF80214C -#define SYS_AXI_RTXSLVDMSCR 0xFF802150 -#define SYS_AXI_SAT0SLVDMSCR 0xFF802168 -#define SYS_AXI_SAT1SLVDMSCR 0xFF80216C -#define SYS_AXI_SDAP0SLVDMSCR 0xFF802170 -#define SYS_AXI_SDAP1SLVDMSCR 0xFF802174 -#define SYS_AXI_SDAP2SLVDMSCR 0xFF802178 -#define SYS_AXI_SDAP3SLVDMSCR 0xFF80217C -#define SYS_AXI_SGXSLVDMSCR 0xFF802180 -#define SYS_AXI_STBSLVDMSCR 0xFF802188 -#define SYS_AXI_STMSLVDMSCR 0xFF80218C -#define SYS_AXI_TSPL0SLVDMSCR 0xFF802194 -#define SYS_AXI_TSPL1SLVDMSCR 0xFF802198 -#define SYS_AXI_TSPL2SLVDMSCR 0xFF80219C -#define SYS_AXI_USB20SLVDMSCR 0xFF8021A0 -#define SYS_AXI_USB21SLVDMSCR 0xFF8021A4 -#define SYS_AXI_USB22SLVDMSCR 0xFF8021A8 -#define SYS_AXI_USB30SLVDMSCR 0xFF8021AC - -#define RT_AXI_CBMDMSCR 0xFF812000 -#define RT_AXI_DBDMSCR 0xFF812004 -#define RT_AXI_RDMDMSCR 0xFF812008 -#define RT_AXI_RDSDMSCR 0xFF81200C -#define RT_AXI_STRDMSCR 0xFF812010 -#define RT_AXI_SY2RTDMSCR 0xFF812014 -#define RT_AXI_CBSSLVDMSCR 0xFF812100 -#define RT_AXI_DBSSLVDMSCR 0xFF812104 -#define RT_AXI_RTAP1SLVDMSCR 0xFF812108 -#define RT_AXI_RTAP2SLVDMSCR 0xFF81210C -#define RT_AXI_RTAP3SLVDMSCR 0xFF812110 -#define RT_AXI_RT2SYSLVDMSCR 0xFF812114 -#define RT_AXI_A128TO64SLVDMSCR 0xFF812118 -#define RT_AXI_A64TO128SLVDMSCR 0xFF81211C -#define RT_AXI_A64TO128CSLVDMSCR 0xFF812120 -#define RT_AXI_UTLBRSLVDMSCR 0xFF812128 - -#define MP_AXI_ADSPDMSCR 0xFF822000 -#define MP_AXI_ASDM0DMSCR 0xFF822004 -#define MP_AXI_ASDM1DMSCR 0xFF822008 -#define MP_AXI_ASDS0DMSCR 0xFF82200C -#define MP_AXI_ASDS1DMSCR 0xFF822010 -#define MP_AXI_MLPDMSCR 0xFF822014 -#define MP_AXI_MMUMPDMSCR 0xFF822018 -#define MP_AXI_SPUDMSCR 0xFF82201C -#define MP_AXI_SPUCDMSCR 0xFF822020 -#define MP_AXI_SY2MPDMSCR 0xFF822024 -#define MP_AXI_ADSPSLVDMSCR 0xFF822100 -#define MP_AXI_MLMSLVDMSCR 0xFF822104 -#define MP_AXI_MPAP4SLVDMSCR 0xFF822108 -#define MP_AXI_MPAP5SLVDMSCR 0xFF82210C -#define MP_AXI_MPAP6SLVDMSCR 0xFF822110 -#define MP_AXI_MPAP7SLVDMSCR 0xFF822114 -#define MP_AXI_MP2SYSLVDMSCR 0xFF822118 -#define MP_AXI_MP2SY2SLVDMSCR 0xFF82211C -#define MP_AXI_MPXAPSLVDMSCR 0xFF822124 -#define MP_AXI_SPUSLVDMSCR 0xFF822128 -#define MP_AXI_UTLBMPSLVDMSCR 0xFF82212C - -#define ADM_AXI_ASDM0DMSCR 0xFF842000 -#define ADM_AXI_ASDM1DMSCR 0xFF842004 -#define ADM_AXI_MPAP1SLVDMSCR 0xFF842104 -#define ADM_AXI_MPAP2SLVDMSCR 0xFF842108 -#define ADM_AXI_MPAP3SLVDMSCR 0xFF84210C - -#define DM_AXI_RDMDMSCR 0xFF852000 -#define DM_AXI_SDM0DMSCR 0xFF852004 -#define DM_AXI_SDM1DMSCR 0xFF852008 -#define DM_AXI_MMAP0SLVDMSCR 0xFF852100 -#define DM_AXI_MMAP1SLVDMSCR 0xFF852104 -#define DM_AXI_QSPAPSLVDMSCR 0xFF852108 -#define DM_AXI_RAP4SLVDMSCR 0xFF85210C -#define DM_AXI_RAP5SLVDMSCR 0xFF852110 -#define DM_AXI_SAP4SLVDMSCR 0xFF852114 -#define DM_AXI_SAP5SLVDMSCR 0xFF852118 -#define DM_AXI_SAP6SLVDMSCR 0xFF85211C -#define DM_AXI_SAP65SLVDMSCR 0xFF852120 -#define DM_AXI_SDAP0SLVDMSCR 0xFF852124 -#define DM_AXI_SDAP1SLVDMSCR 0xFF852128 -#define DM_AXI_SDAP2SLVDMSCR 0xFF85212C -#define DM_AXI_SDAP3SLVDMSCR 0xFF852130 - -#define SYS_AXI256_SYXDMSCR 0xFF862000 -#define SYS_AXI256_MPXDMSCR 0xFF862004 -#define SYS_AXI256_MXIDMSCR 0xFF862008 -#define SYS_AXI256_X128TO256SLVDMSCR 0xFF862100 -#define SYS_AXI256_X256TO128SLVDMSCR 0xFF862104 -#define SYS_AXI256_SYXSLVDMSCR 0xFF862108 -#define SYS_AXI256_CCXSLVDMSCR 0xFF86210C -#define SYS_AXI256_S3CSLVDMSCR 0xFF862110 - -#define MXT_SYXDMSCR 0xFF872000 -#define MXT_CMM0SLVDMSCR 0xFF872100 -#define MXT_CMM1SLVDMSCR 0xFF872104 -#define MXT_CMM2SLVDMSCR 0xFF872108 -#define MXT_FDPSLVDMSCR 0xFF87210C -#define MXT_IMRSLVDMSCR 0xFF872110 -#define MXT_VINSLVDMSCR 0xFF872114 -#define MXT_VPC0SLVDMSCR 0xFF872118 -#define MXT_VPC1SLVDMSCR 0xFF87211C -#define MXT_VSP0SLVDMSCR 0xFF872120 -#define MXT_VSP1SLVDMSCR 0xFF872124 -#define MXT_VSPD0SLVDMSCR 0xFF872128 -#define MXT_VSPD1SLVDMSCR 0xFF87212C -#define MXT_MAP1SLVDMSCR 0xFF872130 -#define MXT_MAP2SLVDMSCR 0xFF872134 - -#define CCI_AXI_MMUS0DMSCR 0xFF882000 -#define CCI_AXI_SYX2DMSCR 0xFF882004 -#define CCI_AXI_MMURDMSCR 0xFF882008 -#define CCI_AXI_MMUDSDMSCR 0xFF88200C -#define CCI_AXI_MMUMDMSCR 0xFF882010 -#define CCI_AXI_MXIDMSCR 0xFF882014 -#define CCI_AXI_MMUS1DMSCR 0xFF882018 -#define CCI_AXI_MMUMPDMSCR 0xFF88201C -#define CCI_AXI_DVMDMSCR 0xFF882020 -#define CCI_AXI_CCISLVDMSCR 0xFF882100 - -#define CCI_AXI_IPMMUIDVMCR 0xFF880400 -#define CCI_AXI_IPMMURDVMCR 0xFF880404 -#define CCI_AXI_IPMMUS0DVMCR 0xFF880408 -#define CCI_AXI_IPMMUS1DVMCR 0xFF88040C -#define CCI_AXI_IPMMUMPDVMCR 0xFF880410 -#define CCI_AXI_IPMMUDSDVMCR 0xFF880414 -#define CCI_AXI_AX2ADDRMASK 0xFF88041C - -#ifndef __ASSEMBLY__ -#include <asm/types.h> - -/* RWDT */ -struct r8a7790_rwdt { - u32 rwtcnt; /* 0x00 */ - u32 rwtcsra; /* 0x04 */ - u16 rwtcsrb; /* 0x08 */ -}; - -/* SWDT */ -struct r8a7790_swdt { - u32 swtcnt; /* 0x00 */ - u32 swtcsra; /* 0x04 */ - u16 swtcsrb; /* 0x08 */ -}; - -/* LBSC */ -struct r8a7790_lbsc { - u32 cs0ctrl; - u32 cs1ctrl; - u32 ecs0ctrl; - u32 ecs1ctrl; - u32 ecs2ctrl; - u32 ecs3ctrl; - u32 ecs4ctrl; - u32 ecs5ctrl; - u32 dummy0[4]; /* 0x20 .. 0x2C */ - u32 cswcr0; - u32 cswcr1; - u32 ecswcr0; - u32 ecswcr1; - u32 ecswcr2; - u32 ecswcr3; - u32 ecswcr4; - u32 ecswcr5; - u32 exdmawcr0; - u32 exdmawcr1; - u32 exdmawcr2; - u32 dummy1[9]; /* 0x5C .. 0x7C */ - u32 cspwcr0; - u32 cspwcr1; - u32 ecspwcr0; - u32 ecspwcr1; - u32 ecspwcr2; - u32 ecspwcr3; - u32 ecspwcr4; - u32 ecspwcr5; - u32 exwtsync; - u32 dummy2[3]; /* 0xA4 .. 0xAC */ - u32 cs0bstctl; - u32 cs0btph; - u32 dummy3[2]; /* 0xB8 .. 0xBC */ - u32 cs1gdst; - u32 ecs0gdst; - u32 ecs1gdst; - u32 ecs2gdst; - u32 ecs3gdst; - u32 ecs4gdst; - u32 ecs5gdst; - u32 dummy4[5]; /* 0xDC .. 0xEC */ - u32 exdmaset0; - u32 exdmaset1; - u32 exdmaset2; - u32 dummy5[5]; /* 0xFC .. 0x10C */ - u32 exdmcr0; - u32 exdmcr1; - u32 exdmcr2; - u32 dummy6[5]; /* 0x11C .. 0x12C */ - u32 bcintsr; - u32 bcintcr; - u32 bcintmr; - u32 dummy7; /* 0x13C */ - u32 exbatlv; - u32 exwtsts; - u32 dummy8[14]; /* 0x148 .. 0x17C */ - u32 atacsctrl; - u32 dummy9[15]; /* 0x184 .. 0x1BC */ - u32 exbct; - u32 extct; -}; - -/* DBSC3 */ -struct r8a7790_dbsc3 { - u32 dummy0[3]; /* 0x00 .. 0x08 */ - u32 dbstate1; - u32 dbacen; - u32 dbrfen; - u32 dbcmd; - u32 dbwait; - u32 dbkind; - u32 dbconf0; - u32 dummy1[2]; /* 0x28 .. 0x2C */ - u32 dbphytype; - u32 dummy2[3]; /* 0x34 .. 0x3C */ - u32 dbtr0; - u32 dbtr1; - u32 dbtr2; - u32 dummy3; /* 0x4C */ - u32 dbtr3; - u32 dbtr4; - u32 dbtr5; - u32 dbtr6; - u32 dbtr7; - u32 dbtr8; - u32 dbtr9; - u32 dbtr10; - u32 dbtr11; - u32 dbtr12; - u32 dbtr13; - u32 dbtr14; - u32 dbtr15; - u32 dbtr16; - u32 dbtr17; - u32 dbtr18; - u32 dbtr19; - u32 dummy4[7]; /* 0x94 .. 0xAC */ - u32 dbbl; - u32 dummy5[3]; /* 0xB4 .. 0xBC */ - u32 dbadj0; - u32 dummy6; /* 0xC4 */ - u32 dbadj2; - u32 dummy7[5]; /* 0xCC .. 0xDC */ - u32 dbrfcnf0; - u32 dbrfcnf1; - u32 dbrfcnf2; - u32 dummy8[2]; /* 0xEC .. 0xF0 */ - u32 dbcalcnf; - u32 dbcaltr; - u32 dummy9; /* 0xFC */ - u32 dbrnk0; - u32 dummy10[31]; /* 0x104 .. 0x17C */ - u32 dbpdncnf; - u32 dummy11[47]; /* 0x184 ..0x23C */ - u32 dbdfistat; - u32 dbdficnt; - u32 dummy12[14]; /* 0x248 .. 0x27C */ - u32 dbpdlck; - u32 dummy13[3]; /* 0x284 .. 0x28C */ - u32 dbpdrga; - u32 dummy14[3]; /* 0x294 .. 0x29C */ - u32 dbpdrgd; - u32 dummy15[24]; /* 0x2A4 .. 0x300 */ - u32 dbbs0cnt1; - u32 dummy16[30]; /* 0x308 .. 0x37C */ - u32 dbwt0cnf0; - u32 dbwt0cnf1; - u32 dbwt0cnf2; - u32 dbwt0cnf3; - u32 dbwt0cnf4; -}; - -/* GPIO */ -struct r8a7790_gpio { - u32 iointsel; - u32 inoutsel; - u32 outdt; - u32 indt; - u32 intdt; - u32 intclr; - u32 intmsk; - u32 posneg; - u32 edglevel; - u32 filonoff; - u32 intmsks; - u32 mskclrs; - u32 outdtsel; - u32 outdth; - u32 outdtl; - u32 bothedge; -}; - -/* S3C(QoS) */ -struct r8a7790_s3c { - u32 s3cexcladdmsk; - u32 s3cexclidmsk; - u32 s3cadsplcr; - u32 s3cmaar; - u32 s3carcr11; - u32 s3crorr; - u32 s3cworr; - u32 s3carcr22; - u32 dummy1[2]; /* 0x20 .. 0x24 */ - u32 s3cmctr; - u32 dummy2; /* 0x2C */ - u32 cconf0; - u32 cconf1; - u32 cconf2; - u32 cconf3; -}; - -struct r8a7790_s3c_qos { - u32 s3cqos0; - u32 s3cqos1; - u32 s3cqos2; - u32 s3cqos3; - u32 s3cqos4; - u32 s3cqos5; - u32 s3cqos6; - u32 s3cqos7; - u32 s3cqos8; -}; - -/* DBSC(QoS) */ -struct r8a7790_dbsc3_qos { - u32 dblgcnt; - u32 dbtmval0; - u32 dbtmval1; - u32 dbtmval2; - u32 dbtmval3; - u32 dbrqctr; - u32 dbthres0; - u32 dbthres1; - u32 dbthres2; - u32 dummy0; /* 0x24 */ - u32 dblgqon; -}; - -/* MXI(QoS) */ -struct r8a7790_mxi { - u32 mxsaar0; - u32 mxsaar1; - u32 dummy0[7]; /* 0x08 .. 0x20 */ - u32 mxaxiracr; - u32 mxs3cracr; - u32 dummy1[2]; /* 0x2C .. 0x30 */ - u32 mxaxiwacr; - u32 mxs3cwacr; - u32 dummy2; /* 0x3C */ - u32 mxrtcr; - u32 mxwtcr; -}; - -struct r8a7790_mxi_qos { - u32 vspdu0; - u32 vspdu1; - u32 du0; - u32 du1; -}; - -/* AXI(QoS) */ -struct r8a7790_axi_qos { - u32 qosconf; - u32 qosctset0; - u32 qosctset1; - u32 qosctset2; - u32 qosctset3; - u32 qosreqctr; - u32 qosthres0; - u32 qosthres1; - u32 qosthres2; - u32 qosqon; -}; - -#endif +#include "rcar-base.h" #endif /* __ASM_ARCH_R8A7790_H */ diff --git a/arch/arm/include/asm/arch-rmobile/r8a7791.h b/arch/arm/include/asm/arch-rmobile/r8a7791.h index ff30180..7c8f19c 100644 --- a/arch/arm/include/asm/arch-rmobile/r8a7791.h +++ b/arch/arm/include/asm/arch-rmobile/r8a7791.h @@ -1,69 +1,18 @@ /* * arch/arm/include/asm/arch-rmobile/r8a7791.h * - * Copyright (C) 2013 Renesas Electronics Corporation + * Copyright (C) 2013,2014 Renesas Electronics Corporation * * SPDX-License-Identifier: GPL-2.0 - */ +*/ #ifndef __ASM_ARCH_R8A7791_H #define __ASM_ARCH_R8A7791_H +#include "rcar-base.h" /* - * R8A7791 I/O Addresses + * R-Car (R8A7791) I/O Addresses */ -#define RWDT_BASE 0xE6020000 -#define SWDT_BASE 0xE6030000 -#define LBSC_BASE 0xFEC00200 -#define DBSC3_0_BASE 0xE6790000 -#define DBSC3_1_BASE 0xE67A0000 -#define TMU_BASE 0xE61E0000 -#define GPIO5_BASE 0xE6055000 -#define SH_QSPI_BASE 0xE6B10000 - -#define S3C_BASE 0xE6784000 -#define S3C_INT_BASE 0xE6784A00 -#define S3C_MEDIA_BASE 0xE6784B00 - -#define S3C_QOS_DCACHE_BASE 0xE6784BDC -#define S3C_QOS_CCI0_BASE 0xE6784C00 -#define S3C_QOS_CCI1_BASE 0xE6784C24 -#define S3C_QOS_MXI_BASE 0xE6784C48 -#define S3C_QOS_AXI_BASE 0xE6784C6C - -#define DBSC3_0_QOS_R0_BASE 0xE6791000 -#define DBSC3_0_QOS_R1_BASE 0xE6791100 -#define DBSC3_0_QOS_R2_BASE 0xE6791200 -#define DBSC3_0_QOS_R3_BASE 0xE6791300 -#define DBSC3_0_QOS_R4_BASE 0xE6791400 -#define DBSC3_0_QOS_R5_BASE 0xE6791500 -#define DBSC3_0_QOS_R6_BASE 0xE6791600 -#define DBSC3_0_QOS_R7_BASE 0xE6791700 -#define DBSC3_0_QOS_R8_BASE 0xE6791800 -#define DBSC3_0_QOS_R9_BASE 0xE6791900 -#define DBSC3_0_QOS_R10_BASE 0xE6791A00 -#define DBSC3_0_QOS_R11_BASE 0xE6791B00 -#define DBSC3_0_QOS_R12_BASE 0xE6791C00 -#define DBSC3_0_QOS_R13_BASE 0xE6791D00 -#define DBSC3_0_QOS_R14_BASE 0xE6791E00 -#define DBSC3_0_QOS_R15_BASE 0xE6791F00 -#define DBSC3_0_QOS_W0_BASE 0xE6792000 -#define DBSC3_0_QOS_W1_BASE 0xE6792100 -#define DBSC3_0_QOS_W2_BASE 0xE6792200 -#define DBSC3_0_QOS_W3_BASE 0xE6792300 -#define DBSC3_0_QOS_W4_BASE 0xE6792400 -#define DBSC3_0_QOS_W5_BASE 0xE6792500 -#define DBSC3_0_QOS_W6_BASE 0xE6792600 -#define DBSC3_0_QOS_W7_BASE 0xE6792700 -#define DBSC3_0_QOS_W8_BASE 0xE6792800 -#define DBSC3_0_QOS_W9_BASE 0xE6792900 -#define DBSC3_0_QOS_W10_BASE 0xE6792A00 -#define DBSC3_0_QOS_W11_BASE 0xE6792B00 -#define DBSC3_0_QOS_W12_BASE 0xE6792C00 -#define DBSC3_0_QOS_W13_BASE 0xE6792D00 -#define DBSC3_0_QOS_W14_BASE 0xE6792E00 -#define DBSC3_0_QOS_W15_BASE 0xE6792F00 - #define DBSC3_1_QOS_R0_BASE 0xE67A1000 #define DBSC3_1_QOS_R1_BASE 0xE67A1100 #define DBSC3_1_QOS_R2_BASE 0xE67A1200 @@ -97,569 +46,4 @@ #define DBSC3_1_QOS_W14_BASE 0xE67A2E00 #define DBSC3_1_QOS_W15_BASE 0xE67A2F00 -#define DBSC3_0_DBADJ2 0xE67900C8 - -#define CCI_400_MAXOT_1 0xF0091110 -#define CCI_400_MAXOT_2 0xF0092110 -#define CCI_400_QOSCNTL_1 0xF009110C -#define CCI_400_QOSCNTL_2 0xF009210C - -#define MXI_BASE 0xFE960000 -#define MXI_QOS_BASE 0xFE960300 - -#define SYS_AXI_SYX64TO128_BASE 0xFF800300 -#define SYS_AXI_AVB_BASE 0xFF800340 -#define SYS_AXI_G2D_BASE 0xFF800540 -#define SYS_AXI_IMP0_BASE 0xFF800580 -#define SYS_AXI_IMP1_BASE 0xFF8005C0 -#define SYS_AXI_IMUX0_BASE 0xFF800600 -#define SYS_AXI_IMUX1_BASE 0xFF800640 -#define SYS_AXI_IMUX2_BASE 0xFF800680 -#define SYS_AXI_LBS_BASE 0xFF8006C0 -#define SYS_AXI_MMUDS_BASE 0xFF800700 -#define SYS_AXI_MMUM_BASE 0xFF800740 -#define SYS_AXI_MMUR_BASE 0xFF800780 -#define SYS_AXI_MMUS0_BASE 0xFF8007C0 -#define SYS_AXI_MMUS1_BASE 0xFF800800 -#define SYS_AXI_MTSB0_BASE 0xFF800880 -#define SYS_AXI_MTSB1_BASE 0xFF8008C0 -#define SYS_AXI_PCI_BASE 0xFF800900 -#define SYS_AXI_RTX_BASE 0xFF800940 -#define SYS_AXI_SDS0_BASE 0xFF800A80 -#define SYS_AXI_SDS1_BASE 0xFF800AC0 -#define SYS_AXI_USB20_BASE 0xFF800C00 -#define SYS_AXI_USB21_BASE 0xFF800C40 -#define SYS_AXI_USB22_BASE 0xFF800C80 -#define SYS_AXI_USB30_BASE 0xFF800CC0 -#define SYS_AXI_AX2M_BASE 0xFF800380 -#define SYS_AXI_CC50_BASE 0xFF8003C0 -#define SYS_AXI_CCI_BASE 0xFF800440 -#define SYS_AXI_CS_BASE 0xFF800480 -#define SYS_AXI_DDM_BASE 0xFF8004C0 -#define SYS_AXI_ETH_BASE 0xFF800500 -#define SYS_AXI_MPXM_BASE 0xFF800840 -#define SYS_AXI_SAT0_BASE 0xFF800980 -#define SYS_AXI_SAT1_BASE 0xFF8009C0 -#define SYS_AXI_SDM0_BASE 0xFF800A00 -#define SYS_AXI_SDM1_BASE 0xFF800A40 -#define SYS_AXI_TRAB_BASE 0xFF800B00 -#define SYS_AXI_UDM0_BASE 0xFF800B80 -#define SYS_AXI_UDM1_BASE 0xFF800BC0 - -#define RT_AXI_SHX_BASE 0xFF810100 -#define RT_AXI_DBG_BASE 0xFF810140 -#define RT_AXI_RDM_BASE 0xFF810180 -#define RT_AXI_RDS_BASE 0xFF8101C0 -#define RT_AXI_RTX64TO128_BASE 0xFF810200 -#define RT_AXI_STPRO_BASE 0xFF810240 -#define RT_AXI_SY2RT_BASE 0xFF810280 - -#define MP_AXI_ADSP_BASE 0xFF820100 -#define MP_AXI_ASDS0_BASE 0xFF8201C0 -#define MP_AXI_ASDS1_BASE 0xFF820200 -#define MP_AXI_MLP_BASE 0xFF820240 -#define MP_AXI_MMUMP_BASE 0xFF820280 -#define MP_AXI_SPU_BASE 0xFF8202C0 -#define MP_AXI_SPUC_BASE 0xFF820300 - -#define SYS_AXI256_AXI128TO256_BASE 0xFF860100 -#define SYS_AXI256_SYX_BASE 0xFF860140 -#define SYS_AXI256_MPX_BASE 0xFF860180 -#define SYS_AXI256_MXI_BASE 0xFF8601C0 - -#define CCI_AXI_MMUS0_BASE 0xFF880100 -#define CCI_AXI_SYX2_BASE 0xFF880140 -#define CCI_AXI_MMUR_BASE 0xFF880180 -#define CCI_AXI_MMUDS_BASE 0xFF8801C0 -#define CCI_AXI_MMUM_BASE 0xFF880200 -#define CCI_AXI_MXI_BASE 0xFF880240 -#define CCI_AXI_MMUS1_BASE 0xFF880280 -#define CCI_AXI_MMUMP_BASE 0xFF8802C0 - -#define MEDIA_AXI_MXR_BASE 0xFE960080 -#define MEDIA_AXI_MXW_BASE 0xFE9600C0 -#define MEDIA_AXI_JPR_BASE 0xFE964100 -#define MEDIA_AXI_JPW_BASE 0xFE966100 -#define MEDIA_AXI_GCU0R_BASE 0xFE964140 -#define MEDIA_AXI_GCU0W_BASE 0xFE966140 -#define MEDIA_AXI_GCU1R_BASE 0xFE964180 -#define MEDIA_AXI_GCU1W_BASE 0xFE966180 -#define MEDIA_AXI_TDMR_BASE 0xFE964500 -#define MEDIA_AXI_TDMW_BASE 0xFE966500 -#define MEDIA_AXI_VSP0CR_BASE 0xFE964540 -#define MEDIA_AXI_VSP0CW_BASE 0xFE966540 -#define MEDIA_AXI_VSP1CR_BASE 0xFE964580 -#define MEDIA_AXI_VSP1CW_BASE 0xFE966580 -#define MEDIA_AXI_VSPDU0CR_BASE 0xFE9645C0 -#define MEDIA_AXI_VSPDU0CW_BASE 0xFE9665C0 -#define MEDIA_AXI_VSPDU1CR_BASE 0xFE964600 -#define MEDIA_AXI_VSPDU1CW_BASE 0xFE966600 -#define MEDIA_AXI_VIN0W_BASE 0xFE966900 -#define MEDIA_AXI_VSP0R_BASE 0xFE964D00 -#define MEDIA_AXI_VSP0W_BASE 0xFE966D00 -#define MEDIA_AXI_FDP0R_BASE 0xFE964D40 -#define MEDIA_AXI_FDP0W_BASE 0xFE966D40 -#define MEDIA_AXI_IMSR_BASE 0xFE964D80 -#define MEDIA_AXI_IMSW_BASE 0xFE966D80 -#define MEDIA_AXI_VSP1R_BASE 0xFE965100 -#define MEDIA_AXI_VSP1W_BASE 0xFE967100 -#define MEDIA_AXI_FDP1R_BASE 0xFE965140 -#define MEDIA_AXI_FDP1W_BASE 0xFE967140 -#define MEDIA_AXI_IMRR_BASE 0xFE965180 -#define MEDIA_AXI_IMRW_BASE 0xFE967180 -#define MEDIA_AXI_FDP2R_BASE 0xFE9651C0 -#define MEDIA_AXI_FDP2W_BASE 0xFE966DC0 -#define MEDIA_AXI_VSPD0R_BASE 0xFE965500 -#define MEDIA_AXI_VSPD0W_BASE 0xFE967500 -#define MEDIA_AXI_VSPD1R_BASE 0xFE965540 -#define MEDIA_AXI_VSPD1W_BASE 0xFE967540 -#define MEDIA_AXI_DU0R_BASE 0xFE965580 -#define MEDIA_AXI_DU0W_BASE 0xFE967580 -#define MEDIA_AXI_DU1R_BASE 0xFE9655C0 -#define MEDIA_AXI_DU1W_BASE 0xFE9675C0 -#define MEDIA_AXI_VCP0CR_BASE 0xFE965900 -#define MEDIA_AXI_VCP0CW_BASE 0xFE967900 -#define MEDIA_AXI_VCP0VR_BASE 0xFE965940 -#define MEDIA_AXI_VCP0VW_BASE 0xFE967940 -#define MEDIA_AXI_VPC0R_BASE 0xFE965980 -#define MEDIA_AXI_VCP1CR_BASE 0xFE965D00 -#define MEDIA_AXI_VCP1CW_BASE 0xFE967D00 -#define MEDIA_AXI_VCP1VR_BASE 0xFE965D40 -#define MEDIA_AXI_VCP1VW_BASE 0xFE967D40 -#define MEDIA_AXI_VPC1R_BASE 0xFE965D80 - -#define SYS_AXI_AVBDMSCR 0xFF802000 -#define SYS_AXI_SYX2DMSCR 0xFF802004 -#define SYS_AXI_CC50DMSCR 0xFF802008 -#define SYS_AXI_CC51DMSCR 0xFF80200C -#define SYS_AXI_CCIDMSCR 0xFF802010 -#define SYS_AXI_CSDMSCR 0xFF802014 -#define SYS_AXI_DDMDMSCR 0xFF802018 -#define SYS_AXI_ETHDMSCR 0xFF80201C -#define SYS_AXI_G2DDMSCR 0xFF802020 -#define SYS_AXI_IMP0DMSCR 0xFF802024 -#define SYS_AXI_IMP1DMSCR 0xFF802028 -#define SYS_AXI_LBSDMSCR 0xFF80202C -#define SYS_AXI_MMUDSDMSCR 0xFF802030 -#define SYS_AXI_MMUMXDMSCR 0xFF802034 -#define SYS_AXI_MMURDDMSCR 0xFF802038 -#define SYS_AXI_MMUS0DMSCR 0xFF80203C -#define SYS_AXI_MMUS1DMSCR 0xFF802040 -#define SYS_AXI_MPXDMSCR 0xFF802044 -#define SYS_AXI_MTSB0DMSCR 0xFF802048 -#define SYS_AXI_MTSB1DMSCR 0xFF80204C -#define SYS_AXI_PCIDMSCR 0xFF802050 -#define SYS_AXI_RTXDMSCR 0xFF802054 -#define SYS_AXI_SAT0DMSCR 0xFF802058 -#define SYS_AXI_SAT1DMSCR 0xFF80205C -#define SYS_AXI_SDM0DMSCR 0xFF802060 -#define SYS_AXI_SDM1DMSCR 0xFF802064 -#define SYS_AXI_SDS0DMSCR 0xFF802068 -#define SYS_AXI_SDS1DMSCR 0xFF80206C -#define SYS_AXI_ETRABDMSCR 0xFF802070 -#define SYS_AXI_ETRKFDMSCR 0xFF802074 -#define SYS_AXI_UDM0DMSCR 0xFF802078 -#define SYS_AXI_UDM1DMSCR 0xFF80207C -#define SYS_AXI_USB20DMSCR 0xFF802080 -#define SYS_AXI_USB21DMSCR 0xFF802084 -#define SYS_AXI_USB22DMSCR 0xFF802088 -#define SYS_AXI_USB30DMSCR 0xFF80208C -#define SYS_AXI_X128TO64SLVDMSCR 0xFF802100 -#define SYS_AXI_X64TO128SLVDMSCR 0xFF802104 -#define SYS_AXI_AVBSLVDMSCR 0xFF802108 -#define SYS_AXI_SYX2SLVDMSCR 0xFF80210C -#define SYS_AXI_ETHSLVDMSCR 0xFF802110 -#define SYS_AXI_GICSLVDMSCR 0xFF802114 -#define SYS_AXI_IMPSLVDMSCR 0xFF802118 -#define SYS_AXI_IMX0SLVDMSCR 0xFF80211C -#define SYS_AXI_IMX1SLVDMSCR 0xFF802120 -#define SYS_AXI_IMX2SLVDMSCR 0xFF802124 -#define SYS_AXI_LBSSLVDMSCR 0xFF802128 -#define SYS_AXI_MMC0SLVDMSCR 0xFF80212C -#define SYS_AXI_MMC1SLVDMSCR 0xFF802130 -#define SYS_AXI_MPXSLVDMSCR 0xFF802134 -#define SYS_AXI_MTSB0SLVDMSCR 0xFF802138 -#define SYS_AXI_MTSB1SLVDMSCR 0xFF80213C -#define SYS_AXI_MXTSLVDMSCR 0xFF802140 -#define SYS_AXI_PCISLVDMSCR 0xFF802144 -#define SYS_AXI_SYAPBSLVDMSCR 0xFF802148 -#define SYS_AXI_QSAPBSLVDMSCR 0xFF80214C -#define SYS_AXI_RTXSLVDMSCR 0xFF802150 -#define SYS_AXI_SAT0SLVDMSCR 0xFF802168 -#define SYS_AXI_SAT1SLVDMSCR 0xFF80216C -#define SYS_AXI_SDAP0SLVDMSCR 0xFF802170 -#define SYS_AXI_SDAP1SLVDMSCR 0xFF802174 -#define SYS_AXI_SDAP2SLVDMSCR 0xFF802178 -#define SYS_AXI_SDAP3SLVDMSCR 0xFF80217C -#define SYS_AXI_SGXSLVDMSCR 0xFF802180 -#define SYS_AXI_STBSLVDMSCR 0xFF802188 -#define SYS_AXI_STMSLVDMSCR 0xFF80218C -#define SYS_AXI_TSPL0SLVDMSCR 0xFF802194 -#define SYS_AXI_TSPL1SLVDMSCR 0xFF802198 -#define SYS_AXI_TSPL2SLVDMSCR 0xFF80219C -#define SYS_AXI_USB20SLVDMSCR 0xFF8021A0 -#define SYS_AXI_USB21SLVDMSCR 0xFF8021A4 -#define SYS_AXI_USB22SLVDMSCR 0xFF8021A8 -#define SYS_AXI_USB30SLVDMSCR 0xFF8021AC - -#define RT_AXI_CBMDMSCR 0xFF812000 -#define RT_AXI_DBDMSCR 0xFF812004 -#define RT_AXI_RDMDMSCR 0xFF812008 -#define RT_AXI_RDSDMSCR 0xFF81200C -#define RT_AXI_STRDMSCR 0xFF812010 -#define RT_AXI_SY2RTDMSCR 0xFF812014 -#define RT_AXI_CBSSLVDMSCR 0xFF812100 -#define RT_AXI_DBSSLVDMSCR 0xFF812104 -#define RT_AXI_RTAP1SLVDMSCR 0xFF812108 -#define RT_AXI_RTAP2SLVDMSCR 0xFF81210C -#define RT_AXI_RTAP3SLVDMSCR 0xFF812110 -#define RT_AXI_RT2SYSLVDMSCR 0xFF812114 -#define RT_AXI_A128TO64SLVDMSCR 0xFF812118 -#define RT_AXI_A64TO128SLVDMSCR 0xFF81211C -#define RT_AXI_A64TO128CSLVDMSCR 0xFF812120 -#define RT_AXI_UTLBRSLVDMSCR 0xFF812128 - -#define MP_AXI_ADSPDMSCR 0xFF822000 -#define MP_AXI_ASDM0DMSCR 0xFF822004 -#define MP_AXI_ASDM1DMSCR 0xFF822008 -#define MP_AXI_ASDS0DMSCR 0xFF82200C -#define MP_AXI_ASDS1DMSCR 0xFF822010 -#define MP_AXI_MLPDMSCR 0xFF822014 -#define MP_AXI_MMUMPDMSCR 0xFF822018 -#define MP_AXI_SPUDMSCR 0xFF82201C -#define MP_AXI_SPUCDMSCR 0xFF822020 -#define MP_AXI_SY2MPDMSCR 0xFF822024 -#define MP_AXI_ADSPSLVDMSCR 0xFF822100 -#define MP_AXI_MLMSLVDMSCR 0xFF822104 -#define MP_AXI_MPAP4SLVDMSCR 0xFF822108 -#define MP_AXI_MPAP5SLVDMSCR 0xFF82210C -#define MP_AXI_MPAP6SLVDMSCR 0xFF822110 -#define MP_AXI_MPAP7SLVDMSCR 0xFF822114 -#define MP_AXI_MP2SYSLVDMSCR 0xFF822118 -#define MP_AXI_MP2SY2SLVDMSCR 0xFF82211C -#define MP_AXI_MPXAPSLVDMSCR 0xFF822124 -#define MP_AXI_SPUSLVDMSCR 0xFF822128 -#define MP_AXI_UTLBMPSLVDMSCR 0xFF82212C - -#define ADM_AXI_ASDM0DMSCR 0xFF842000 -#define ADM_AXI_ASDM1DMSCR 0xFF842004 -#define ADM_AXI_MPAP1SLVDMSCR 0xFF842104 -#define ADM_AXI_MPAP2SLVDMSCR 0xFF842108 -#define ADM_AXI_MPAP3SLVDMSCR 0xFF84210C - -#define DM_AXI_RDMDMSCR 0xFF852000 -#define DM_AXI_SDM0DMSCR 0xFF852004 -#define DM_AXI_SDM1DMSCR 0xFF852008 -#define DM_AXI_MMAP0SLVDMSCR 0xFF852100 -#define DM_AXI_MMAP1SLVDMSCR 0xFF852104 -#define DM_AXI_QSPAPSLVDMSCR 0xFF852108 -#define DM_AXI_RAP4SLVDMSCR 0xFF85210C -#define DM_AXI_RAP5SLVDMSCR 0xFF852110 -#define DM_AXI_SAP4SLVDMSCR 0xFF852114 -#define DM_AXI_SAP5SLVDMSCR 0xFF852118 -#define DM_AXI_SAP6SLVDMSCR 0xFF85211C -#define DM_AXI_SAP65SLVDMSCR 0xFF852120 -#define DM_AXI_SDAP0SLVDMSCR 0xFF852124 -#define DM_AXI_SDAP1SLVDMSCR 0xFF852128 -#define DM_AXI_SDAP2SLVDMSCR 0xFF85212C -#define DM_AXI_SDAP3SLVDMSCR 0xFF852130 - -#define SYS_AXI256_SYXDMSCR 0xFF862000 -#define SYS_AXI256_MPXDMSCR 0xFF862004 -#define SYS_AXI256_MXIDMSCR 0xFF862008 -#define SYS_AXI256_X128TO256SLVDMSCR 0xFF862100 -#define SYS_AXI256_X256TO128SLVDMSCR 0xFF862104 -#define SYS_AXI256_SYXSLVDMSCR 0xFF862108 -#define SYS_AXI256_CCXSLVDMSCR 0xFF86210C -#define SYS_AXI256_S3CSLVDMSCR 0xFF862110 - -#define MXT_SYXDMSCR 0xFF872000 -#define MXT_CMM0SLVDMSCR 0xFF872100 -#define MXT_CMM1SLVDMSCR 0xFF872104 -#define MXT_CMM2SLVDMSCR 0xFF872108 -#define MXT_FDPSLVDMSCR 0xFF87210C -#define MXT_IMRSLVDMSCR 0xFF872110 -#define MXT_VINSLVDMSCR 0xFF872114 -#define MXT_VPC0SLVDMSCR 0xFF872118 -#define MXT_VPC1SLVDMSCR 0xFF87211C -#define MXT_VSP0SLVDMSCR 0xFF872120 -#define MXT_VSP1SLVDMSCR 0xFF872124 -#define MXT_VSPD0SLVDMSCR 0xFF872128 -#define MXT_VSPD1SLVDMSCR 0xFF87212C -#define MXT_MAP1SLVDMSCR 0xFF872130 -#define MXT_MAP2SLVDMSCR 0xFF872134 - -#define CCI_AXI_MMUS0DMSCR 0xFF882000 -#define CCI_AXI_SYX2DMSCR 0xFF882004 -#define CCI_AXI_MMURDMSCR 0xFF882008 -#define CCI_AXI_MMUDSDMSCR 0xFF88200C -#define CCI_AXI_MMUMDMSCR 0xFF882010 -#define CCI_AXI_MXIDMSCR 0xFF882014 -#define CCI_AXI_MMUS1DMSCR 0xFF882018 -#define CCI_AXI_MMUMPDMSCR 0xFF88201C -#define CCI_AXI_DVMDMSCR 0xFF882020 -#define CCI_AXI_CCISLVDMSCR 0xFF882100 - -#define CCI_AXI_IPMMUIDVMCR 0xFF880400 -#define CCI_AXI_IPMMURDVMCR 0xFF880404 -#define CCI_AXI_IPMMUS0DVMCR 0xFF880408 -#define CCI_AXI_IPMMUS1DVMCR 0xFF88040C -#define CCI_AXI_IPMMUMPDVMCR 0xFF880410 -#define CCI_AXI_IPMMUDSDVMCR 0xFF880414 -#define CCI_AXI_AX2ADDRMASK 0xFF88041C - -#ifndef __ASSEMBLY__ -#include <asm/types.h> - -/* RWDT */ -struct r8a7791_rwdt { - u32 rwtcnt; /* 0x00 */ - u32 rwtcsra; /* 0x04 */ - u16 rwtcsrb; /* 0x08 */ -}; - -/* SWDT */ -struct r8a7791_swdt { - u32 swtcnt; /* 0x00 */ - u32 swtcsra; /* 0x04 */ - u16 swtcsrb; /* 0x08 */ -}; - -/* LBSC */ -struct r8a7791_lbsc { - u32 cs0ctrl; - u32 cs1ctrl; - u32 ecs0ctrl; - u32 ecs1ctrl; - u32 ecs2ctrl; - u32 ecs3ctrl; - u32 ecs4ctrl; - u32 ecs5ctrl; - u32 dummy0[4]; /* 0x20 .. 0x2C */ - u32 cswcr0; - u32 cswcr1; - u32 ecswcr0; - u32 ecswcr1; - u32 ecswcr2; - u32 ecswcr3; - u32 ecswcr4; - u32 ecswcr5; - u32 exdmawcr0; - u32 exdmawcr1; - u32 exdmawcr2; - u32 dummy1[9]; /* 0x5C .. 0x7C */ - u32 cspwcr0; - u32 cspwcr1; - u32 ecspwcr0; - u32 ecspwcr1; - u32 ecspwcr2; - u32 ecspwcr3; - u32 ecspwcr4; - u32 ecspwcr5; - u32 exwtsync; - u32 dummy2[3]; /* 0xA4 .. 0xAC */ - u32 cs0bstctl; - u32 cs0btph; - u32 dummy3[2]; /* 0xB8 .. 0xBC */ - u32 cs1gdst; - u32 ecs0gdst; - u32 ecs1gdst; - u32 ecs2gdst; - u32 ecs3gdst; - u32 ecs4gdst; - u32 ecs5gdst; - u32 dummy4[5]; /* 0xDC .. 0xEC */ - u32 exdmaset0; - u32 exdmaset1; - u32 exdmaset2; - u32 dummy5[5]; /* 0xFC .. 0x10C */ - u32 exdmcr0; - u32 exdmcr1; - u32 exdmcr2; - u32 dummy6[5]; /* 0x11C .. 0x12C */ - u32 bcintsr; - u32 bcintcr; - u32 bcintmr; - u32 dummy7; /* 0x13C */ - u32 exbatlv; - u32 exwtsts; - u32 dummy8[14]; /* 0x148 .. 0x17C */ - u32 atacsctrl; - u32 dummy9[15]; /* 0x184 .. 0x1BC */ - u32 exbct; - u32 extct; -}; - -/* DBSC3 */ -struct r8a7791_dbsc3 { - u32 dummy0[3]; /* 0x00 .. 0x08 */ - u32 dbstate1; - u32 dbacen; - u32 dbrfen; - u32 dbcmd; - u32 dbwait; - u32 dbkind; - u32 dbconf0; - u32 dummy1[2]; /* 0x28 .. 0x2C */ - u32 dbphytype; - u32 dummy2[3]; /* 0x34 .. 0x3C */ - u32 dbtr0; - u32 dbtr1; - u32 dbtr2; - u32 dummy3; /* 0x4C */ - u32 dbtr3; - u32 dbtr4; - u32 dbtr5; - u32 dbtr6; - u32 dbtr7; - u32 dbtr8; - u32 dbtr9; - u32 dbtr10; - u32 dbtr11; - u32 dbtr12; - u32 dbtr13; - u32 dbtr14; - u32 dbtr15; - u32 dbtr16; - u32 dbtr17; - u32 dbtr18; - u32 dbtr19; - u32 dummy4[7]; /* 0x94 .. 0xAC */ - u32 dbbl; - u32 dummy5[3]; /* 0xB4 .. 0xBC */ - u32 dbadj0; - u32 dummy6; /* 0xC4 */ - u32 dbadj2; - u32 dummy7[5]; /* 0xCC .. 0xDC */ - u32 dbrfcnf0; - u32 dbrfcnf1; - u32 dbrfcnf2; - u32 dummy8[2]; /* 0xEC .. 0xF0 */ - u32 dbcalcnf; - u32 dbcaltr; - u32 dummy9; /* 0xFC */ - u32 dbrnk0; - u32 dummy10[31]; /* 0x104 .. 0x17C */ - u32 dbpdncnf; - u32 dummy11[47]; /* 0x184 ..0x23C */ - u32 dbdfistat; - u32 dbdficnt; - u32 dummy12[14]; /* 0x248 .. 0x27C */ - u32 dbpdlck; - u32 dummy13[3]; /* 0x284 .. 0x28C */ - u32 dbpdrga; - u32 dummy14[3]; /* 0x294 .. 0x29C */ - u32 dbpdrgd; - u32 dummy15[24]; /* 0x2A4 .. 0x300 */ - u32 dbbs0cnt1; - u32 dummy16[30]; /* 0x308 .. 0x37C */ - u32 dbwt0cnf0; - u32 dbwt0cnf1; - u32 dbwt0cnf2; - u32 dbwt0cnf3; - u32 dbwt0cnf4; -}; - -/* GPIO */ -struct r8a7791_gpio { - u32 iointsel; - u32 inoutsel; - u32 outdt; - u32 indt; - u32 intdt; - u32 intclr; - u32 intmsk; - u32 posneg; - u32 edglevel; - u32 filonoff; - u32 intmsks; - u32 mskclrs; - u32 outdtsel; - u32 outdth; - u32 outdtl; - u32 bothedge; -}; - -/* S3C(QoS) */ -struct r8a7791_s3c { - u32 s3cexcladdmsk; - u32 s3cexclidmsk; - u32 s3cadsplcr; - u32 s3cmaar; - u32 dummy0; /* 0x10 */ - u32 s3crorr; - u32 s3cworr; - u32 s3carcr22; - u32 dummy1[2]; /* 0x20 .. 0x24 */ - u32 s3cmctr; - u32 dummy2; /* 0x2C */ - u32 cconf0; - u32 cconf1; - u32 cconf2; - u32 cconf3; -}; - -struct r8a7791_s3c_qos { - u32 s3cqos0; - u32 s3cqos1; - u32 s3cqos2; - u32 s3cqos3; - u32 s3cqos4; - u32 s3cqos5; - u32 s3cqos6; - u32 s3cqos7; - u32 s3cqos8; -}; - -/* DBSC(QoS) */ -struct r8a7791_dbsc3_qos { - u32 dblgcnt; - u32 dbtmval0; - u32 dbtmval1; - u32 dbtmval2; - u32 dbtmval3; - u32 dbrqctr; - u32 dbthres0; - u32 dbthres1; - u32 dbthres2; - u32 dummy0; /* 0x24 */ - u32 dblgqon; -}; - -/* MXI(QoS) */ -struct r8a7791_mxi { - u32 mxsaar0; - u32 mxsaar1; - u32 dummy0[8]; /* 0x08 .. 0x24 */ - u32 mxs3cracr; - u32 dummy1[3]; /* 0x2C .. 0x34 */ - u32 mxs3cwacr; - u32 dummy2; /* 0x3C */ - u32 mxrtcr; - u32 mxwtcr; -}; - -struct r8a7791_mxi_qos { - u32 vspdu0; - u32 vspdu1; - u32 du0; - u32 du1; -}; - -/* AXI(QoS) */ -struct r8a7791_axi_qos { - u32 qosconf; - u32 qosctset0; - u32 qosctset1; - u32 qosctset2; - u32 qosctset3; - u32 qosreqctr; - u32 qosthres0; - u32 qosthres1; - u32 qosthres2; - u32 qosqon; -}; - -#endif - #endif /* __ASM_ARCH_R8A7791_H */ diff --git a/arch/arm/include/asm/arch-rmobile/rcar-base.h b/arch/arm/include/asm/arch-rmobile/rcar-base.h new file mode 100644 index 0000000..67f227b --- /dev/null +++ b/arch/arm/include/asm/arch-rmobile/rcar-base.h @@ -0,0 +1,633 @@ +/* + * arch/arm/include/asm/arch-rmobile/rcar-base.h + * + * Copyright (C) 2013,2014 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 +*/ + +#ifndef __ASM_ARCH_RCAR_BASE_H +#define __ASM_ARCH_RCAR_BASE_H + +/* + * R-Car (R8A7790/R8A7791) I/O Addresses + */ +#define RWDT_BASE 0xE6020000 +#define SWDT_BASE 0xE6030000 +#define LBSC_BASE 0xFEC00200 +#define DBSC3_0_BASE 0xE6790000 +#define DBSC3_1_BASE 0xE67A0000 +#define TMU_BASE 0xE61E0000 +#define GPIO5_BASE 0xE6055000 +#define SH_QSPI_BASE 0xE6B10000 + +#define S3C_BASE 0xE6784000 +#define S3C_INT_BASE 0xE6784A00 +#define S3C_MEDIA_BASE 0xE6784B00 + +#define S3C_QOS_DCACHE_BASE 0xE6784BDC +#define S3C_QOS_CCI0_BASE 0xE6784C00 +#define S3C_QOS_CCI1_BASE 0xE6784C24 +#define S3C_QOS_MXI_BASE 0xE6784C48 +#define S3C_QOS_AXI_BASE 0xE6784C6C + +#define DBSC3_0_QOS_R0_BASE 0xE6791000 +#define DBSC3_0_QOS_R1_BASE 0xE6791100 +#define DBSC3_0_QOS_R2_BASE 0xE6791200 +#define DBSC3_0_QOS_R3_BASE 0xE6791300 +#define DBSC3_0_QOS_R4_BASE 0xE6791400 +#define DBSC3_0_QOS_R5_BASE 0xE6791500 +#define DBSC3_0_QOS_R6_BASE 0xE6791600 +#define DBSC3_0_QOS_R7_BASE 0xE6791700 +#define DBSC3_0_QOS_R8_BASE 0xE6791800 +#define DBSC3_0_QOS_R9_BASE 0xE6791900 +#define DBSC3_0_QOS_R10_BASE 0xE6791A00 +#define DBSC3_0_QOS_R11_BASE 0xE6791B00 +#define DBSC3_0_QOS_R12_BASE 0xE6791C00 +#define DBSC3_0_QOS_R13_BASE 0xE6791D00 +#define DBSC3_0_QOS_R14_BASE 0xE6791E00 +#define DBSC3_0_QOS_R15_BASE 0xE6791F00 +#define DBSC3_0_QOS_W0_BASE 0xE6792000 +#define DBSC3_0_QOS_W1_BASE 0xE6792100 +#define DBSC3_0_QOS_W2_BASE 0xE6792200 +#define DBSC3_0_QOS_W3_BASE 0xE6792300 +#define DBSC3_0_QOS_W4_BASE 0xE6792400 +#define DBSC3_0_QOS_W5_BASE 0xE6792500 +#define DBSC3_0_QOS_W6_BASE 0xE6792600 +#define DBSC3_0_QOS_W7_BASE 0xE6792700 +#define DBSC3_0_QOS_W8_BASE 0xE6792800 +#define DBSC3_0_QOS_W9_BASE 0xE6792900 +#define DBSC3_0_QOS_W10_BASE 0xE6792A00 +#define DBSC3_0_QOS_W11_BASE 0xE6792B00 +#define DBSC3_0_QOS_W12_BASE 0xE6792C00 +#define DBSC3_0_QOS_W13_BASE 0xE6792D00 +#define DBSC3_0_QOS_W14_BASE 0xE6792E00 +#define DBSC3_0_QOS_W15_BASE 0xE6792F00 +#define DBSC3_0_DBADJ2 0xE67900C8 + +#define CCI_400_MAXOT_1 0xF0091110 +#define CCI_400_MAXOT_2 0xF0092110 +#define CCI_400_QOSCNTL_1 0xF009110C +#define CCI_400_QOSCNTL_2 0xF009210C + +#define MXI_BASE 0xFE960000 +#define MXI_QOS_BASE 0xFE960300 + +#define SYS_AXI_SYX64TO128_BASE 0xFF800300 +#define SYS_AXI_AVB_BASE 0xFF800340 +#define SYS_AXI_G2D_BASE 0xFF800540 +#define SYS_AXI_IMP0_BASE 0xFF800580 +#define SYS_AXI_IMP1_BASE 0xFF8005C0 +#define SYS_AXI_IMUX0_BASE 0xFF800600 +#define SYS_AXI_IMUX1_BASE 0xFF800640 +#define SYS_AXI_IMUX2_BASE 0xFF800680 +#define SYS_AXI_LBS_BASE 0xFF8006C0 +#define SYS_AXI_MMUDS_BASE 0xFF800700 +#define SYS_AXI_MMUM_BASE 0xFF800740 +#define SYS_AXI_MMUR_BASE 0xFF800780 +#define SYS_AXI_MMUS0_BASE 0xFF8007C0 +#define SYS_AXI_MMUS1_BASE 0xFF800800 +#define SYS_AXI_MTSB0_BASE 0xFF800880 +#define SYS_AXI_MTSB1_BASE 0xFF8008C0 +#define SYS_AXI_PCI_BASE 0xFF800900 +#define SYS_AXI_RTX_BASE 0xFF800940 +#define SYS_AXI_SDS0_BASE 0xFF800A80 +#define SYS_AXI_SDS1_BASE 0xFF800AC0 +#define SYS_AXI_USB20_BASE 0xFF800C00 +#define SYS_AXI_USB21_BASE 0xFF800C40 +#define SYS_AXI_USB22_BASE 0xFF800C80 +#define SYS_AXI_USB30_BASE 0xFF800CC0 +#define SYS_AXI_AX2M_BASE 0xFF800380 +#define SYS_AXI_CC50_BASE 0xFF8003C0 +#define SYS_AXI_CCI_BASE 0xFF800440 +#define SYS_AXI_CS_BASE 0xFF800480 +#define SYS_AXI_DDM_BASE 0xFF8004C0 +#define SYS_AXI_ETH_BASE 0xFF800500 +#define SYS_AXI_MPXM_BASE 0xFF800840 +#define SYS_AXI_SAT0_BASE 0xFF800980 +#define SYS_AXI_SAT1_BASE 0xFF8009C0 +#define SYS_AXI_SDM0_BASE 0xFF800A00 +#define SYS_AXI_SDM1_BASE 0xFF800A40 +#define SYS_AXI_TRAB_BASE 0xFF800B00 +#define SYS_AXI_UDM0_BASE 0xFF800B80 +#define SYS_AXI_UDM1_BASE 0xFF800BC0 + +#define RT_AXI_SHX_BASE 0xFF810100 +#define RT_AXI_DBG_BASE 0xFF810140 /* R8A7791 only */ +#define RT_AXI_RDM_BASE 0xFF810180 /* R8A7791 only */ +#define RT_AXI_RDS_BASE 0xFF8101C0 +#define RT_AXI_RTX64TO128_BASE 0xFF810200 +#define RT_AXI_STPRO_BASE 0xFF810240 +#define RT_AXI_SY2RT_BASE 0xFF810280 /* R8A7791 only */ + +#define MP_AXI_ADSP_BASE 0xFF820100 +#define MP_AXI_ASDS0_BASE 0xFF8201C0 +#define MP_AXI_ASDS1_BASE 0xFF820200 +#define MP_AXI_MLP_BASE 0xFF820240 +#define MP_AXI_MMUMP_BASE 0xFF820280 +#define MP_AXI_SPU_BASE 0xFF8202C0 +#define MP_AXI_SPUC_BASE 0xFF820300 + +#define SYS_AXI256_AXI128TO256_BASE 0xFF860100 +#define SYS_AXI256_SYX_BASE 0xFF860140 +#define SYS_AXI256_MPX_BASE 0xFF860180 +#define SYS_AXI256_MXI_BASE 0xFF8601C0 + +#define CCI_AXI_MMUS0_BASE 0xFF880100 +#define CCI_AXI_SYX2_BASE 0xFF880140 +#define CCI_AXI_MMUR_BASE 0xFF880180 +#define CCI_AXI_MMUDS_BASE 0xFF8801C0 +#define CCI_AXI_MMUM_BASE 0xFF880200 +#define CCI_AXI_MXI_BASE 0xFF880240 +#define CCI_AXI_MMUS1_BASE 0xFF880280 +#define CCI_AXI_MMUMP_BASE 0xFF8802C0 + +#define MEDIA_AXI_MXR_BASE 0xFE960080 /* R8A7791 only */ +#define MEDIA_AXI_MXW_BASE 0xFE9600C0 /* R8A7791 only */ +#define MEDIA_AXI_JPR_BASE 0xFE964100 +#define MEDIA_AXI_JPW_BASE 0xFE966100 +#define MEDIA_AXI_GCU0R_BASE 0xFE964140 +#define MEDIA_AXI_GCU0W_BASE 0xFE966140 +#define MEDIA_AXI_GCU1R_BASE 0xFE964180 +#define MEDIA_AXI_GCU1W_BASE 0xFE966180 +#define MEDIA_AXI_TDMR_BASE 0xFE964500 +#define MEDIA_AXI_TDMW_BASE 0xFE966500 +#define MEDIA_AXI_VSP0CR_BASE 0xFE964540 +#define MEDIA_AXI_VSP0CW_BASE 0xFE966540 +#define MEDIA_AXI_VSP1CR_BASE 0xFE964580 +#define MEDIA_AXI_VSP1CW_BASE 0xFE966580 +#define MEDIA_AXI_VSPDU0CR_BASE 0xFE9645C0 +#define MEDIA_AXI_VSPDU0CW_BASE 0xFE9665C0 +#define MEDIA_AXI_VSPDU1CR_BASE 0xFE964600 +#define MEDIA_AXI_VSPDU1CW_BASE 0xFE966600 +#define MEDIA_AXI_VIN0W_BASE 0xFE966900 +#define MEDIA_AXI_VSP0R_BASE 0xFE964D00 +#define MEDIA_AXI_VSP0W_BASE 0xFE966D00 +#define MEDIA_AXI_FDP0R_BASE 0xFE964D40 +#define MEDIA_AXI_FDP0W_BASE 0xFE966D40 +#define MEDIA_AXI_IMSR_BASE 0xFE964D80 +#define MEDIA_AXI_IMSW_BASE 0xFE966D80 +#define MEDIA_AXI_VSP1R_BASE 0xFE965100 +#define MEDIA_AXI_VSP1W_BASE 0xFE967100 +#define MEDIA_AXI_FDP1R_BASE 0xFE965140 +#define MEDIA_AXI_FDP1W_BASE 0xFE967140 +#define MEDIA_AXI_IMRR_BASE 0xFE965180 +#define MEDIA_AXI_IMRW_BASE 0xFE967180 +#define MEDIA_AXI_FDP2R_BASE 0xFE9651C0 +#define MEDIA_AXI_FDP2W_BASE 0xFE966DC0 +#define MEDIA_AXI_VSPD0R_BASE 0xFE965500 +#define MEDIA_AXI_VSPD0W_BASE 0xFE967500 +#define MEDIA_AXI_VSPD1R_BASE 0xFE965540 +#define MEDIA_AXI_VSPD1W_BASE 0xFE967540 +#define MEDIA_AXI_DU0R_BASE 0xFE965580 +#define MEDIA_AXI_DU0W_BASE 0xFE967580 +#define MEDIA_AXI_DU1R_BASE 0xFE9655C0 +#define MEDIA_AXI_DU1W_BASE 0xFE9675C0 +#define MEDIA_AXI_VCP0CR_BASE 0xFE965900 +#define MEDIA_AXI_VCP0CW_BASE 0xFE967900 +#define MEDIA_AXI_VCP0VR_BASE 0xFE965940 +#define MEDIA_AXI_VCP0VW_BASE 0xFE967940 +#define MEDIA_AXI_VPC0R_BASE 0xFE965980 +#define MEDIA_AXI_VCP1CR_BASE 0xFE965D00 +#define MEDIA_AXI_VCP1CW_BASE 0xFE967D00 +#define MEDIA_AXI_VCP1VR_BASE 0xFE965D40 +#define MEDIA_AXI_VCP1VW_BASE 0xFE967D40 +#define MEDIA_AXI_VPC1R_BASE 0xFE965D80 + +#define SYS_AXI_AVBDMSCR 0xFF802000 +#define SYS_AXI_SYX2DMSCR 0xFF802004 +#define SYS_AXI_CC50DMSCR 0xFF802008 +#define SYS_AXI_CC51DMSCR 0xFF80200C +#define SYS_AXI_CCIDMSCR 0xFF802010 +#define SYS_AXI_CSDMSCR 0xFF802014 +#define SYS_AXI_DDMDMSCR 0xFF802018 +#define SYS_AXI_ETHDMSCR 0xFF80201C +#define SYS_AXI_G2DDMSCR 0xFF802020 +#define SYS_AXI_IMP0DMSCR 0xFF802024 +#define SYS_AXI_IMP1DMSCR 0xFF802028 +#define SYS_AXI_LBSDMSCR 0xFF80202C +#define SYS_AXI_MMUDSDMSCR 0xFF802030 +#define SYS_AXI_MMUMXDMSCR 0xFF802034 +#define SYS_AXI_MMURDDMSCR 0xFF802038 +#define SYS_AXI_MMUS0DMSCR 0xFF80203C +#define SYS_AXI_MMUS1DMSCR 0xFF802040 +#define SYS_AXI_MPXDMSCR 0xFF802044 +#define SYS_AXI_MTSB0DMSCR 0xFF802048 +#define SYS_AXI_MTSB1DMSCR 0xFF80204C +#define SYS_AXI_PCIDMSCR 0xFF802050 +#define SYS_AXI_RTXDMSCR 0xFF802054 +#define SYS_AXI_SAT0DMSCR 0xFF802058 +#define SYS_AXI_SAT1DMSCR 0xFF80205C +#define SYS_AXI_SDM0DMSCR 0xFF802060 +#define SYS_AXI_SDM1DMSCR 0xFF802064 +#define SYS_AXI_SDS0DMSCR 0xFF802068 +#define SYS_AXI_SDS1DMSCR 0xFF80206C +#define SYS_AXI_ETRABDMSCR 0xFF802070 +#define SYS_AXI_ETRKFDMSCR 0xFF802074 +#define SYS_AXI_UDM0DMSCR 0xFF802078 +#define SYS_AXI_UDM1DMSCR 0xFF80207C +#define SYS_AXI_USB20DMSCR 0xFF802080 +#define SYS_AXI_USB21DMSCR 0xFF802084 +#define SYS_AXI_USB22DMSCR 0xFF802088 +#define SYS_AXI_USB30DMSCR 0xFF80208C +#define SYS_AXI_X128TO64SLVDMSCR 0xFF802100 +#define SYS_AXI_X64TO128SLVDMSCR 0xFF802104 +#define SYS_AXI_AVBSLVDMSCR 0xFF802108 +#define SYS_AXI_SYX2SLVDMSCR 0xFF80210C +#define SYS_AXI_ETHSLVDMSCR 0xFF802110 +#define SYS_AXI_GICSLVDMSCR 0xFF802114 +#define SYS_AXI_IMPSLVDMSCR 0xFF802118 +#define SYS_AXI_IMX0SLVDMSCR 0xFF80211C +#define SYS_AXI_IMX1SLVDMSCR 0xFF802120 +#define SYS_AXI_IMX2SLVDMSCR 0xFF802124 +#define SYS_AXI_LBSSLVDMSCR 0xFF802128 +#define SYS_AXI_MMC0SLVDMSCR 0xFF80212C +#define SYS_AXI_MMC1SLVDMSCR 0xFF802130 +#define SYS_AXI_MPXSLVDMSCR 0xFF802134 +#define SYS_AXI_MTSB0SLVDMSCR 0xFF802138 +#define SYS_AXI_MTSB1SLVDMSCR 0xFF80213C +#define SYS_AXI_MXTSLVDMSCR 0xFF802140 +#define SYS_AXI_PCISLVDMSCR 0xFF802144 +#define SYS_AXI_SYAPBSLVDMSCR 0xFF802148 +#define SYS_AXI_QSAPBSLVDMSCR 0xFF80214C +#define SYS_AXI_RTXSLVDMSCR 0xFF802150 +#define SYS_AXI_SAT0SLVDMSCR 0xFF802168 +#define SYS_AXI_SAT1SLVDMSCR 0xFF80216C +#define SYS_AXI_SDAP0SLVDMSCR 0xFF802170 +#define SYS_AXI_SDAP1SLVDMSCR 0xFF802174 +#define SYS_AXI_SDAP2SLVDMSCR 0xFF802178 +#define SYS_AXI_SDAP3SLVDMSCR 0xFF80217C +#define SYS_AXI_SGXSLVDMSCR 0xFF802180 +#define SYS_AXI_STBSLVDMSCR 0xFF802188 +#define SYS_AXI_STMSLVDMSCR 0xFF80218C +#define SYS_AXI_TSPL0SLVDMSCR 0xFF802194 +#define SYS_AXI_TSPL1SLVDMSCR 0xFF802198 +#define SYS_AXI_TSPL2SLVDMSCR 0xFF80219C +#define SYS_AXI_USB20SLVDMSCR 0xFF8021A0 +#define SYS_AXI_USB21SLVDMSCR 0xFF8021A4 +#define SYS_AXI_USB22SLVDMSCR 0xFF8021A8 +#define SYS_AXI_USB30SLVDMSCR 0xFF8021AC + +#define RT_AXI_CBMDMSCR 0xFF812000 +#define RT_AXI_DBDMSCR 0xFF812004 +#define RT_AXI_RDMDMSCR 0xFF812008 +#define RT_AXI_RDSDMSCR 0xFF81200C +#define RT_AXI_STRDMSCR 0xFF812010 +#define RT_AXI_SY2RTDMSCR 0xFF812014 +#define RT_AXI_CBSSLVDMSCR 0xFF812100 +#define RT_AXI_DBSSLVDMSCR 0xFF812104 +#define RT_AXI_RTAP1SLVDMSCR 0xFF812108 +#define RT_AXI_RTAP2SLVDMSCR 0xFF81210C +#define RT_AXI_RTAP3SLVDMSCR 0xFF812110 +#define RT_AXI_RT2SYSLVDMSCR 0xFF812114 +#define RT_AXI_A128TO64SLVDMSCR 0xFF812118 +#define RT_AXI_A64TO128SLVDMSCR 0xFF81211C +#define RT_AXI_A64TO128CSLVDMSCR 0xFF812120 +#define RT_AXI_UTLBRSLVDMSCR 0xFF812128 + +#define MP_AXI_ADSPDMSCR 0xFF822000 +#define MP_AXI_ASDM0DMSCR 0xFF822004 +#define MP_AXI_ASDM1DMSCR 0xFF822008 +#define MP_AXI_ASDS0DMSCR 0xFF82200C +#define MP_AXI_ASDS1DMSCR 0xFF822010 +#define MP_AXI_MLPDMSCR 0xFF822014 +#define MP_AXI_MMUMPDMSCR 0xFF822018 +#define MP_AXI_SPUDMSCR 0xFF82201C +#define MP_AXI_SPUCDMSCR 0xFF822020 +#define MP_AXI_SY2MPDMSCR 0xFF822024 +#define MP_AXI_ADSPSLVDMSCR 0xFF822100 +#define MP_AXI_MLMSLVDMSCR 0xFF822104 +#define MP_AXI_MPAP4SLVDMSCR 0xFF822108 +#define MP_AXI_MPAP5SLVDMSCR 0xFF82210C +#define MP_AXI_MPAP6SLVDMSCR 0xFF822110 +#define MP_AXI_MPAP7SLVDMSCR 0xFF822114 +#define MP_AXI_MP2SYSLVDMSCR 0xFF822118 +#define MP_AXI_MP2SY2SLVDMSCR 0xFF82211C +#define MP_AXI_MPXAPSLVDMSCR 0xFF822124 +#define MP_AXI_SPUSLVDMSCR 0xFF822128 +#define MP_AXI_UTLBMPSLVDMSCR 0xFF82212C + +#define ADM_AXI_ASDM0DMSCR 0xFF842000 +#define ADM_AXI_ASDM1DMSCR 0xFF842004 +#define ADM_AXI_MPAP1SLVDMSCR 0xFF842104 +#define ADM_AXI_MPAP2SLVDMSCR 0xFF842108 +#define ADM_AXI_MPAP3SLVDMSCR 0xFF84210C + +#define DM_AXI_RDMDMSCR 0xFF852000 +#define DM_AXI_SDM0DMSCR 0xFF852004 +#define DM_AXI_SDM1DMSCR 0xFF852008 +#define DM_AXI_MMAP0SLVDMSCR 0xFF852100 +#define DM_AXI_MMAP1SLVDMSCR 0xFF852104 +#define DM_AXI_QSPAPSLVDMSCR 0xFF852108 +#define DM_AXI_RAP4SLVDMSCR 0xFF85210C +#define DM_AXI_RAP5SLVDMSCR 0xFF852110 +#define DM_AXI_SAP4SLVDMSCR 0xFF852114 +#define DM_AXI_SAP5SLVDMSCR 0xFF852118 +#define DM_AXI_SAP6SLVDMSCR 0xFF85211C +#define DM_AXI_SAP65SLVDMSCR 0xFF852120 +#define DM_AXI_SDAP0SLVDMSCR 0xFF852124 +#define DM_AXI_SDAP1SLVDMSCR 0xFF852128 +#define DM_AXI_SDAP2SLVDMSCR 0xFF85212C +#define DM_AXI_SDAP3SLVDMSCR 0xFF852130 + +#define SYS_AXI256_SYXDMSCR 0xFF862000 +#define SYS_AXI256_MPXDMSCR 0xFF862004 +#define SYS_AXI256_MXIDMSCR 0xFF862008 +#define SYS_AXI256_X128TO256SLVDMSCR 0xFF862100 +#define SYS_AXI256_X256TO128SLVDMSCR 0xFF862104 +#define SYS_AXI256_SYXSLVDMSCR 0xFF862108 +#define SYS_AXI256_CCXSLVDMSCR 0xFF86210C +#define SYS_AXI256_S3CSLVDMSCR 0xFF862110 + +#define MXT_SYXDMSCR 0xFF872000 +#define MXT_CMM0SLVDMSCR 0xFF872100 +#define MXT_CMM1SLVDMSCR 0xFF872104 +#define MXT_CMM2SLVDMSCR 0xFF872108 +#define MXT_FDPSLVDMSCR 0xFF87210C +#define MXT_IMRSLVDMSCR 0xFF872110 +#define MXT_VINSLVDMSCR 0xFF872114 +#define MXT_VPC0SLVDMSCR 0xFF872118 +#define MXT_VPC1SLVDMSCR 0xFF87211C +#define MXT_VSP0SLVDMSCR 0xFF872120 +#define MXT_VSP1SLVDMSCR 0xFF872124 +#define MXT_VSPD0SLVDMSCR 0xFF872128 +#define MXT_VSPD1SLVDMSCR 0xFF87212C +#define MXT_MAP1SLVDMSCR 0xFF872130 +#define MXT_MAP2SLVDMSCR 0xFF872134 + +#define CCI_AXI_MMUS0DMSCR 0xFF882000 +#define CCI_AXI_SYX2DMSCR 0xFF882004 +#define CCI_AXI_MMURDMSCR 0xFF882008 +#define CCI_AXI_MMUDSDMSCR 0xFF88200C +#define CCI_AXI_MMUMDMSCR 0xFF882010 +#define CCI_AXI_MXIDMSCR 0xFF882014 +#define CCI_AXI_MMUS1DMSCR 0xFF882018 +#define CCI_AXI_MMUMPDMSCR 0xFF88201C +#define CCI_AXI_DVMDMSCR 0xFF882020 +#define CCI_AXI_CCISLVDMSCR 0xFF882100 + +#define CCI_AXI_IPMMUIDVMCR 0xFF880400 +#define CCI_AXI_IPMMURDVMCR 0xFF880404 +#define CCI_AXI_IPMMUS0DVMCR 0xFF880408 +#define CCI_AXI_IPMMUS1DVMCR 0xFF88040C +#define CCI_AXI_IPMMUMPDVMCR 0xFF880410 +#define CCI_AXI_IPMMUDSDVMCR 0xFF880414 +#define CCI_AXI_AX2ADDRMASK 0xFF88041C + +#ifndef __ASSEMBLY__ +#include <asm/types.h> + +/* RWDT */ +struct rcar_rwdt { + u32 rwtcnt; /* 0x00 */ + u32 rwtcsra; /* 0x04 */ + u16 rwtcsrb; /* 0x08 */ +}; + +/* SWDT */ +struct rcar_swdt { + u32 swtcnt; /* 0x00 */ + u32 swtcsra; /* 0x04 */ + u16 swtcsrb; /* 0x08 */ +}; + +/* LBSC */ +struct rcar_lbsc { + u32 cs0ctrl; + u32 cs1ctrl; + u32 ecs0ctrl; + u32 ecs1ctrl; + u32 ecs2ctrl; + u32 ecs3ctrl; + u32 ecs4ctrl; + u32 ecs5ctrl; + u32 dummy0[4]; /* 0x20 .. 0x2C */ + u32 cswcr0; + u32 cswcr1; + u32 ecswcr0; + u32 ecswcr1; + u32 ecswcr2; + u32 ecswcr3; + u32 ecswcr4; + u32 ecswcr5; + u32 exdmawcr0; + u32 exdmawcr1; + u32 exdmawcr2; + u32 dummy1[9]; /* 0x5C .. 0x7C */ + u32 cspwcr0; + u32 cspwcr1; + u32 ecspwcr0; + u32 ecspwcr1; + u32 ecspwcr2; + u32 ecspwcr3; + u32 ecspwcr4; + u32 ecspwcr5; + u32 exwtsync; + u32 dummy2[3]; /* 0xA4 .. 0xAC */ + u32 cs0bstctl; + u32 cs0btph; + u32 dummy3[2]; /* 0xB8 .. 0xBC */ + u32 cs1gdst; + u32 ecs0gdst; + u32 ecs1gdst; + u32 ecs2gdst; + u32 ecs3gdst; + u32 ecs4gdst; + u32 ecs5gdst; + u32 dummy4[5]; /* 0xDC .. 0xEC */ + u32 exdmaset0; + u32 exdmaset1; + u32 exdmaset2; + u32 dummy5[5]; /* 0xFC .. 0x10C */ + u32 exdmcr0; + u32 exdmcr1; + u32 exdmcr2; + u32 dummy6[5]; /* 0x11C .. 0x12C */ + u32 bcintsr; + u32 bcintcr; + u32 bcintmr; + u32 dummy7; /* 0x13C */ + u32 exbatlv; + u32 exwtsts; + u32 dummy8[14]; /* 0x148 .. 0x17C */ + u32 atacsctrl; + u32 dummy9[15]; /* 0x184 .. 0x1BC */ + u32 exbct; + u32 extct; +}; + +/* DBSC3 */ +struct rcar_dbsc3 { + u32 dummy0[3]; /* 0x00 .. 0x08 */ + u32 dbstate1; + u32 dbacen; + u32 dbrfen; + u32 dbcmd; + u32 dbwait; + u32 dbkind; + u32 dbconf0; + u32 dummy1[2]; /* 0x28 .. 0x2C */ + u32 dbphytype; + u32 dummy2[3]; /* 0x34 .. 0x3C */ + u32 dbtr0; + u32 dbtr1; + u32 dbtr2; + u32 dummy3; /* 0x4C */ + u32 dbtr3; + u32 dbtr4; + u32 dbtr5; + u32 dbtr6; + u32 dbtr7; + u32 dbtr8; + u32 dbtr9; + u32 dbtr10; + u32 dbtr11; + u32 dbtr12; + u32 dbtr13; + u32 dbtr14; + u32 dbtr15; + u32 dbtr16; + u32 dbtr17; + u32 dbtr18; + u32 dbtr19; + u32 dummy4[7]; /* 0x94 .. 0xAC */ + u32 dbbl; + u32 dummy5[3]; /* 0xB4 .. 0xBC */ + u32 dbadj0; + u32 dummy6; /* 0xC4 */ + u32 dbadj2; + u32 dummy7[5]; /* 0xCC .. 0xDC */ + u32 dbrfcnf0; + u32 dbrfcnf1; + u32 dbrfcnf2; + u32 dummy8[2]; /* 0xEC .. 0xF0 */ + u32 dbcalcnf; + u32 dbcaltr; + u32 dummy9; /* 0xFC */ + u32 dbrnk0; + u32 dummy10[31]; /* 0x104 .. 0x17C */ + u32 dbpdncnf; + u32 dummy11[47]; /* 0x184 ..0x23C */ + u32 dbdfistat; + u32 dbdficnt; + u32 dummy12[14]; /* 0x248 .. 0x27C */ + u32 dbpdlck; + u32 dummy13[3]; /* 0x284 .. 0x28C */ + u32 dbpdrga; + u32 dummy14[3]; /* 0x294 .. 0x29C */ + u32 dbpdrgd; + u32 dummy15[24]; /* 0x2A4 .. 0x300 */ + u32 dbbs0cnt1; + u32 dummy16[30]; /* 0x308 .. 0x37C */ + u32 dbwt0cnf0; + u32 dbwt0cnf1; + u32 dbwt0cnf2; + u32 dbwt0cnf3; + u32 dbwt0cnf4; +}; + +/* GPIO */ +struct rcar_gpio { + u32 iointsel; + u32 inoutsel; + u32 outdt; + u32 indt; + u32 intdt; + u32 intclr; + u32 intmsk; + u32 posneg; + u32 edglevel; + u32 filonoff; + u32 intmsks; + u32 mskclrs; + u32 outdtsel; + u32 outdth; + u32 outdtl; + u32 bothedge; +}; + +/* S3C(QoS) */ +struct rcar_s3c { + u32 s3cexcladdmsk; + u32 s3cexclidmsk; + u32 s3cadsplcr; + u32 s3cmaar; + u32 s3carcr11; /* R8a7790 only */ + u32 s3crorr; + u32 s3cworr; + u32 s3carcr22; + u32 dummy1[2]; /* 0x20 .. 0x24 */ + u32 s3cmctr; + u32 dummy2; /* 0x2C */ + u32 cconf0; + u32 cconf1; + u32 cconf2; + u32 cconf3; +}; + +struct rcar_s3c_qos { + u32 s3cqos0; + u32 s3cqos1; + u32 s3cqos2; + u32 s3cqos3; + u32 s3cqos4; + u32 s3cqos5; + u32 s3cqos6; + u32 s3cqos7; + u32 s3cqos8; +}; + +/* DBSC(QoS) */ +struct rcar_dbsc3_qos { + u32 dblgcnt; + u32 dbtmval0; + u32 dbtmval1; + u32 dbtmval2; + u32 dbtmval3; + u32 dbrqctr; + u32 dbthres0; + u32 dbthres1; + u32 dbthres2; + u32 dummy0; /* 0x24 */ + u32 dblgqon; +}; + +/* MXI(QoS) */ +struct rcar_mxi { + u32 mxsaar0; + u32 mxsaar1; + u32 dummy0[7]; /* 0x08 .. 0x20 */ + u32 mxaxiracr; /* R8a7790 only */ + u32 mxs3cracr; + u32 dummy1[2]; /* 0x2C .. 0x30 */ + u32 mxaxiwacr; /* R8a7790 only */ + u32 mxs3cwacr; + u32 dummy2; /* 0x3C */ + u32 mxrtcr; + u32 mxwtcr; +}; + +struct rcar_mxi_qos { + u32 vspdu0; + u32 vspdu1; + u32 du0; + u32 du1; +}; + +/* AXI(QoS) */ +struct rcar_axi_qos { + u32 qosconf; + u32 qosctset0; + u32 qosctset1; + u32 qosctset2; + u32 qosctset3; + u32 qosreqctr; + u32 qosthres0; + u32 qosthres1; + u32 qosthres2; + u32 qosqon; +}; + +#endif + +#endif /* __ASM_ARCH_RCAR_BASE_H */ -- 1.8.5

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[U-Boot] Please pull u-boot-ti/master
by Tom Rini 02 Apr '14

02 Apr '14

Hey, The following changes since commit ab6423cae0323e8db2c8fdd0a99138d93fde2137: Merge branch 'u-boot/master' into 'u-boot-arm/master' (2014-03-25 10:53:15 +0100) are available in the git repository at: git://git.denx.de/u-boot-ti.git master for you to fetch changes up to 96de041ed9d91f87e59a1bf55dfa35d5caec8b26: board: enable 32kHz RTC OSC at B&R boards (2014-03-31 11:19:41 -0400) ---------------------------------------------------------------- Hannes Petermaier (1): board: enable 32kHz RTC OSC at B&R boards include/configs/bur_am335x_common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- Tom

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[U-Boot] pull request for u-boot-tegra/master info ARM/master
by Tom Warren 02 Apr '14

02 Apr '14

Albert, Please pull u-boot-tegra/master into ARM/master. Thanks! ./MAKEALL -s tegra AOK, checkpatch.pl is clean, and ./MAKEALL -a arm only shows failures that were already present in ARM/master. The following changes since commit ab6423cae0323e8db2c8fdd0a99138d93fde2137: Merge branch 'u-boot/master' into 'u-boot-arm/master' (2014-03-25 10:53:15 +0100) are available in the git repository at: git://git.denx.de/u-boot-tegra master for you to fetch changes up to 352580870ca64b23a485a6b2ba6febc240b10904: ARM: tegra: make all I2C ports open-drain (2014-03-26 15:20:56 -0700) ---------------------------------------------------------------- Stephen Warren (1): ARM: tegra: make all I2C ports open-drain board/nvidia/dalmore/pinmux-config-dalmore.h | 16 ++++++++-------- board/nvidia/venice2/pinmux-config-venice2.h | 16 ++++++++-------- 2 files changed, 16 insertions(+), 16 deletions(-) Thanks!

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[U-Boot] [PATCH] drivers/ddr: Fix klockworks warnings
by York Sun 01 Apr '14

01 Apr '14

This is a possible out of bounds error, caught by Klockworks. Adding check before using as array index. Klockworks also gives warning when pre-compiling conditions should be used instead of runtime. Signed-off-by: York Sun <yorksun(a)freescale.com> --- drivers/ddr/fsl/ctrl_regs.c | 8 ++-- drivers/ddr/fsl/main.c | 6 +++ drivers/ddr/fsl/options.c | 108 +++++++++++++++++++++---------------------- 3 files changed, 64 insertions(+), 58 deletions(-) diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index d01eea0..78e82bb 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -507,8 +507,8 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr, wrrec_mclk = picos_to_mclk(common_dimm->twr_ps); acttoact_mclk = max(picos_to_mclk(common_dimm->trrds_ps), 4); wrtord_mclk = max(2, picos_to_mclk(2500)); - if (wrrec_mclk > 24) - printf("Error: WRREC doesn't support more than 24 clocks\n"); + if ((wrrec_mclk < 1) || (wrrec_mclk > 24)) + printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk); else wrrec_mclk = wrrec_table[wrrec_mclk - 1]; #else @@ -516,8 +516,8 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr, wrrec_mclk = picos_to_mclk(common_dimm->twr_ps); acttoact_mclk = picos_to_mclk(common_dimm->trrd_ps); wrtord_mclk = picos_to_mclk(common_dimm->twtr_ps); - if (wrrec_mclk > 16) - printf("Error: WRREC doesn't support more than 16 clocks\n"); + if ((wrrec_mclk < 1) || (wrrec_mclk > 16)) + printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk); else wrrec_mclk = wrrec_table[wrrec_mclk - 1]; #endif diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c index f95704f..5e001fc 100644 --- a/drivers/ddr/fsl/main.c +++ b/drivers/ddr/fsl/main.c @@ -220,6 +220,11 @@ const char * step_to_string(unsigned int step) { if ((1 << s) != step) return step_string_tbl[7]; + if (s >= ARRAY_SIZE(step_string_tbl)) { + printf("Error for the step in %s\n", __func__); + s = 0; + } + return step_string_tbl[s]; } @@ -520,6 +525,7 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, /* STEP 5: Assign addresses to chip selects */ check_interleaving_options(pinfo); total_mem = step_assign_addresses(pinfo, dbw_capacity_adjust); + debug("Total mem %llu assigned\n", total_mem); case STEP_COMPUTE_REGS: /* STEP 6: compute controller register values */ diff --git a/drivers/ddr/fsl/options.c b/drivers/ddr/fsl/options.c index bf0d1da..5986e1a 100644 --- a/drivers/ddr/fsl/options.c +++ b/drivers/ddr/fsl/options.c @@ -525,67 +525,66 @@ unsigned int populate_memctl_options(int all_dimms_registered, defined(CONFIG_SYS_FSL_DDR2) || \ defined(CONFIG_SYS_FSL_DDR4) /* Chip select options. */ - if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) { - switch (pdimm[0].n_ranks) { - case 1: - pdodt = single_S; - break; +#if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) + switch (pdimm[0].n_ranks) { + case 1: + pdodt = single_S; + break; + case 2: + pdodt = single_D; + break; + case 4: + pdodt = single_Q; + break; + } +#elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2) + switch (pdimm[0].n_ranks) { +#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE + case 4: + pdodt = single_Q; + if (pdimm[1].n_ranks) + printf("Error: Quad- and Dual-rank DIMMs cannot be used together\n"); + break; +#endif + case 2: + switch (pdimm[1].n_ranks) { case 2: - pdodt = single_D; + pdodt = dual_DD; break; - case 4: - pdodt = single_Q; + case 1: + pdodt = dual_DS; break; - } - } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) { - switch (pdimm[0].n_ranks) { -#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE - case 4: - pdodt = single_Q; - if (pdimm[1].n_ranks) - printf("Error: Quad- and Dual-rank DIMMs " - "cannot be used together\n"); + case 0: + pdodt = dual_D0; break; -#endif + } + break; + case 1: + switch (pdimm[1].n_ranks) { case 2: - switch (pdimm[1].n_ranks) { - case 2: - pdodt = dual_DD; - break; - case 1: - pdodt = dual_DS; - break; - case 0: - pdodt = dual_D0; - break; - } + pdodt = dual_SD; break; case 1: - switch (pdimm[1].n_ranks) { - case 2: - pdodt = dual_SD; - break; - case 1: - pdodt = dual_SS; - break; - case 0: - pdodt = dual_S0; - break; - } + pdodt = dual_SS; break; case 0: - switch (pdimm[1].n_ranks) { - case 2: - pdodt = dual_0D; - break; - case 1: - pdodt = dual_0S; - break; - } + pdodt = dual_S0; break; } + break; + case 0: + switch (pdimm[1].n_ranks) { + case 2: + pdodt = dual_0D; + break; + case 1: + pdodt = dual_0S; + break; + } + break; } -#endif +#endif /* CONFIG_DIMM_SLOTS_PER_CTLR */ +#endif /* CONFIG_SYS_FSL_DDR2, 3, 4 */ /* Pick chip-select local options. */ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { @@ -847,8 +846,7 @@ unsigned int populate_memctl_options(int all_dimms_registered, popts->memctl_interleaving_mode = FSL_DDR_256B_INTERLEAVING; popts->memctl_interleaving = 1; debug("256 Byte interleaving\n"); - goto done; -#endif +#else /* * test null first. if CONFIG_HWCONFIG is not defined * hwconfig_arg_cmp returns non-zero @@ -930,8 +928,9 @@ unsigned int populate_memctl_options(int all_dimms_registered, popts->memctl_interleaving = 0; printf("hwconfig has unrecognized parameter for ctlr_intlv.\n"); } +#endif /* CONFIG_SYS_FSL_DDR_INTLV_256B */ done: -#endif +#endif /* CONFIG_NUM_DDR_CONTROLLERS > 1 */ if ((hwconfig_sub_f("fsl_ddr", "bank_intlv", buf)) && (CONFIG_CHIP_SELECTS_PER_CTRL > 1)) { /* test null first. if CONFIG_HWCONFIG is not defined, @@ -1106,10 +1105,11 @@ void check_interleaving_options(fsl_ddr_info_t *pinfo) case FSL_DDR_PAGE_INTERLEAVING: case FSL_DDR_BANK_INTERLEAVING: case FSL_DDR_SUPERBANK_INTERLEAVING: - if (3 == CONFIG_NUM_DDR_CONTROLLERS) +#if (3 == CONFIG_NUM_DDR_CONTROLLERS) k = 2; - else +#else k = CONFIG_NUM_DDR_CONTROLLERS; +#endif break; case FSL_DDR_3WAY_1KB_INTERLEAVING: case FSL_DDR_3WAY_4KB_INTERLEAVING: -- 1.7.9.5

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[U-Boot] [PATCH v3 0/9] Add support for keystone2 SoC and K2HK EVM
by Murali Karicheri 01 Apr '14

01 Apr '14

Change history: v3 - Seperated network driver patches from the original series and and is now a different set as there are outstanding issues to be discussed and sorted out. Also the original series is ready for merge to upstream IMO. - Review comments incorporated. Following are the major comments addressed - Added KBUILD target for u-boot-spi.gph - Added bootup and flashing instructions in README - Cleaned up manually replacing #define <tab> with #define <space> - Cleaned up k2hk_evm.h include file to remove unnecessary options v2 - Review comments incorporated. Following are major comments addressed - split network driver to navigator driver + ethernet driver - replaced register base + offset implemenation with struct based register access implementation - Added Readme for NAND no subpage write option - re-use code for davinci i2c driver on keystone2 with updates - clock-k2hk.c merged to clock.c - currently keeping board specific getclk() command. See the thread for the rational. - Added update to davinci spi driver to re-use on keystone v1 - added separate patch for sorting tools/Makefile entries - reworked gpimage patch to allow more re-use across omapimage/gpimage - dropped patch related to ubifs file size - added keystone SoC and K2HK EVM support v0 - preparatory patch for keystone Murali Karicheri (6): tools: mkimage: add support for gpimage format NAND: DaVinci: allow forced disable of subpage writes i2c, davinci: move i2c_defs.h to the drivers/i2c directory k2hk: add support for k2hk SOC and EVM spi: davinci: add support for multiple bus and chip select k2hk-evm: add configuration for spi1 and spi2 support Vitaly Andrianov (3): fdt: call ft_board_setup_ex() at the end of image_setup_libfdt() arm: add support for arch timer i2c, davinci: add support for multiple i2c buses Makefile | 10 + README | 5 + arch/arm/cpu/armv7/keystone/Makefile | 17 + arch/arm/cpu/armv7/keystone/aemif.c | 71 ++++ arch/arm/cpu/armv7/keystone/clock.c | 318 ++++++++++++++++++ arch/arm/cpu/armv7/keystone/cmd_clock.c | 124 +++++++ arch/arm/cpu/armv7/keystone/cmd_mon.c | 131 ++++++++ arch/arm/cpu/armv7/keystone/ddr3.c | 69 ++++ arch/arm/cpu/armv7/keystone/init.c | 56 ++++ arch/arm/cpu/armv7/keystone/msmc.c | 68 ++++ arch/arm/cpu/armv7/keystone/psc.c | 238 ++++++++++++++ arch/arm/cpu/armv7/keystone/spl.c | 45 +++ arch/arm/include/asm/arch-davinci/i2c_defs.h | 71 +--- arch/arm/include/asm/arch-keystone/clock-k2hk.h | 109 +++++++ arch/arm/include/asm/arch-keystone/clock.h | 17 + arch/arm/include/asm/arch-keystone/clock_defs.h | 121 +++++++ arch/arm/include/asm/arch-keystone/emif_defs.h | 73 +++++ arch/arm/include/asm/arch-keystone/hardware-k2hk.h | 150 +++++++++ arch/arm/include/asm/arch-keystone/hardware.h | 175 ++++++++++ arch/arm/include/asm/arch-keystone/i2c_defs.h | 17 + arch/arm/include/asm/arch-keystone/nand_defs.h | 25 ++ arch/arm/include/asm/arch-keystone/psc_defs.h | 90 +++++ arch/arm/include/asm/arch-keystone/spl.h | 12 + arch/arm/lib/Makefile | 1 + arch/arm/lib/arch_timer.c | 58 ++++ board/ti/k2hk_evm/Makefile | 9 + board/ti/k2hk_evm/README | 122 +++++++ board/ti/k2hk_evm/board.c | 236 ++++++++++++++ board/ti/k2hk_evm/ddr3.c | 269 +++++++++++++++ boards.cfg | 1 + common/image-fdt.c | 5 + common/image.c | 1 + drivers/i2c/davinci_i2c.c | 344 ++++++++++++-------- drivers/i2c/davinci_i2c.h | 78 +++++ drivers/mtd/nand/davinci_nand.c | 3 + drivers/serial/ns16550.c | 8 + drivers/spi/davinci_spi.c | 60 +++- drivers/spi/davinci_spi.h | 33 ++ include/configs/k2hk_evm.h | 218 +++++++++++++ include/fdt_support.h | 1 + include/image.h | 1 + tools/Makefile | 2 + tools/gpheader.h | 40 +++ tools/gpimage-common.c | 80 +++++ tools/gpimage.c | 77 +++++ tools/imagetool.c | 2 + tools/imagetool.h | 1 + tools/omapimage.c | 104 +----- tools/omapimage.h | 5 - 49 files changed, 3467 insertions(+), 304 deletions(-) create mode 100644 arch/arm/cpu/armv7/keystone/Makefile create mode 100644 arch/arm/cpu/armv7/keystone/aemif.c create mode 100644 arch/arm/cpu/armv7/keystone/clock.c create mode 100644 arch/arm/cpu/armv7/keystone/cmd_clock.c create mode 100644 arch/arm/cpu/armv7/keystone/cmd_mon.c create mode 100644 arch/arm/cpu/armv7/keystone/ddr3.c create mode 100644 arch/arm/cpu/armv7/keystone/init.c create mode 100644 arch/arm/cpu/armv7/keystone/msmc.c create mode 100644 arch/arm/cpu/armv7/keystone/psc.c create mode 100644 arch/arm/cpu/armv7/keystone/spl.c create mode 100644 arch/arm/include/asm/arch-keystone/clock-k2hk.h create mode 100644 arch/arm/include/asm/arch-keystone/clock.h create mode 100644 arch/arm/include/asm/arch-keystone/clock_defs.h create mode 100644 arch/arm/include/asm/arch-keystone/emif_defs.h create mode 100644 arch/arm/include/asm/arch-keystone/hardware-k2hk.h create mode 100644 arch/arm/include/asm/arch-keystone/hardware.h create mode 100644 arch/arm/include/asm/arch-keystone/i2c_defs.h create mode 100644 arch/arm/include/asm/arch-keystone/nand_defs.h create mode 100644 arch/arm/include/asm/arch-keystone/psc_defs.h create mode 100644 arch/arm/include/asm/arch-keystone/spl.h create mode 100644 arch/arm/lib/arch_timer.c create mode 100644 board/ti/k2hk_evm/Makefile create mode 100644 board/ti/k2hk_evm/README create mode 100644 board/ti/k2hk_evm/board.c create mode 100644 board/ti/k2hk_evm/ddr3.c create mode 100644 drivers/i2c/davinci_i2c.h create mode 100644 include/configs/k2hk_evm.h create mode 100644 tools/gpheader.h create mode 100644 tools/gpimage-common.c create mode 100644 tools/gpimage.c -- 1.7.9.5

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