April 2014 - U-Boot

[U-Boot] [Question] bardrate both in gd_t and bd_t
by Masahiro Yamada 04 Apr '14

04 Apr '14

Hi. I notice bardrate parameter bd_t as well as gd_t. In include/asm-generic/global_data.h typedef struct global_data { bd_t *bd; unsigned long flags; unsigned int baudrate; We have "baudrate" here. E.g. arch/arm/include/asm/u-boot.h typedef struct bd_info { unsigned int bi_baudrate; /* serial console baudrate */ We have "bi_baudrate". My question is what's the difference between gd->baudrate and bd->bi_baudrate. Why do we need both? Since baudrate is a common paramter for all architectures, bd->bi_baudrate looks weird to me. Best Regards Masahiro Yamada

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[U-Boot] [PATCH 1/2] ZM7300 driver
by Shaveta Leekha 04 Apr '14

04 Apr '14

Adds Support for PowerOne ZM7300 voltage regulator. This device is available on some Freescale Boards like B4860QDS and has to be programmed to adjust the voltage on the board. The device is accessible via I2C interface. Signed-off-by: Shaveta Leekha <shaveta(a)freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal(a)freescale.com> --- board/freescale/common/Makefile | 1 + board/freescale/common/zm7300.c | 235 +++++++++++++++++++++++++++++++++++++++ board/freescale/common/zm7300.h | 22 ++++ 3 files changed, 258 insertions(+), 0 deletions(-) create mode 100644 board/freescale/common/zm7300.c create mode 100644 board/freescale/common/zm7300.h diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index f6a0879..22b57cc 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -48,6 +48,7 @@ obj-$(CONFIG_P5020DS) += ics307_clk.o obj-$(CONFIG_P5040DS) += ics307_clk.o obj-$(CONFIG_VSC_CROSSBAR) += vsc3316_3308.o obj-$(CONFIG_IDT8T49N222A) += idt8t49n222a_serdes_clk.o +obj-$(CONFIG_ZM7300) += zm7300.o # deal with common files for P-series corenet based devices obj-$(CONFIG_P2041RDB) += p_corenet/ diff --git a/board/freescale/common/zm7300.c b/board/freescale/common/zm7300.c new file mode 100644 index 0000000..ed79b43 --- /dev/null +++ b/board/freescale/common/zm7300.c @@ -0,0 +1,235 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* Power-One ZM7300 DPM */ +#include "zm7300.h" + +#define DPM_WP 0x96 +#define WRP_OPCODE 0x01 +#define WRM_OPCODE 0x02 +#define RRP_OPCODE 0x11 + +#define DPM_SUCCESS 0x01 +#define DPM_EXEC_FAIL 0x00 + +static const uint16_t hex_to_1_10mv[] = { + 5000, + 5125, + 5250, + 5375, + 5500, + 5625, + 5750, + 5875, + 6000, + 6125, + 6250, + 6375, + 6500, + 6625, + 6750, + 6875, + 7000, + 7125, + 7250, + 7375, + 7500, + 7625, + 7750, + 7875, + 8000, + 8125, + 8250, + 8375, + 8500, + 8625, + 8750, + 8875, + 9000, + 9125, + 9250, + 9375, + 9500, /* 0.95mV */ + 9625, + 9750, + 9875, + 10000, /* 1.0V */ + 10125, + 10250, + 10375, + 10500, + 10625, + 10750, + 10875, + 11000, + 11125, + 11250, + 11375, + 11500, + 11625, + 11750, + 11875, + 12000, + 12125, + 12250, + 12375, + 0, /* reserved */ +}; + + +/* Read Data d from Register r of POL p */ +u8 dpm_rrp(uchar r) +{ + u8 dpm_rrp[5], ret[5]; + + ret[0] = RRP_OPCODE; + /* POL is 0 */ + ret[1] = 0; + ret[2] = r; + i2c_read(I2C_DPM_ADDR, 0, -3, ret, 2); + if (ret[1] == DPM_SUCCESS) { /* the DPM returned success as status */ + debug("RRP_OPCODE returned success data is %x\n", ret[0]); + return ret[0]; + } else { + return -1; + } +} + +/* Write Data d into DPM register r (RAM) */ +int dpm_wrm(u8 r, u8 d) +{ + u8 dpm_wrm[5], ret[5]; + + ret[0] = WRM_OPCODE; + ret[1] = r; + ret[2] = d; + i2c_read(I2C_DPM_ADDR, 0, -3, ret, 1); + if (ret[0] == DPM_SUCCESS) { /* the DPM returned success as status */ + debug("WRM_OPCODE returned success data is %x\n", ret[0]); + return ret[0]; + } else { + return -1; + } +} + +/* Write Data d into Register r of POL(s) a */ +int dpm_wrp(u8 r, u8 d) +{ + u8 dpm_wrp[7], ret[7]; + + ret[0] = WRP_OPCODE; + /* only POL0 is present */ + ret[1] = 0x01; + ret[2] = 0x00; + ret[3] = 0x00; + ret[4] = 0x00; + ret[5] = r; + ret[6] = d; + i2c_read(I2C_DPM_ADDR, 0, -7, ret, 1); + if (ret[0] == DPM_SUCCESS) { /* the DPM returned success as status */ + debug("WRP_OPCODE returned success data is %x\n", ret[0]); + return 0; + } else { + return -1; + } +} + +/* Uses the DPM command RRP */ +u8 zm_read(uchar reg) +{ + u8 d; + d = dpm_rrp(reg); + return d; +} + +/* ZM_write -- + Steps: + a. Write data to the register + b. Read data from register and compare to written value + c. Return return_code & voltage_read +*/ +u8 zm_write(u8 reg, u8 data) +{ + u8 d; + + /* write data to register */ + dpm_wrp(reg, data); + + /* read register and compare to written value */ + d = dpm_rrp(reg); + if (d != data) { + printf("zm_write : Comparison register data failed\n"); + return -1; + } + + return d; +} + +/* zm_write_out_voltage + * voltage in 1/10 mV + */ +int zm_write_voltage(int voltage) +{ + u8 reg = 0x7, vid; + uint16_t voltage_read; + u8 ret; + + vid = (voltage - 5000) / ZM_STEP; + + ret = zm_write(reg, vid); + if (ret != -1) { + voltage_read = hex_to_1_10mv[ret]; + debug("voltage set to %dmV\n", voltage_read/10); + return voltage_read; + } + return -1; +} + +/* zm_read_out_voltage + * voltage in 1/10 mV + */ +int zm_read_voltage(void) +{ + u8 reg = 0x7; + u8 ret; + int voltage; + + ret = zm_read(reg); + if (ret != -1) { + voltage = hex_to_1_10mv[ret]; + debug("Voltage read is %dmV\n", voltage/10); + return voltage; + } else { + return -1; + } +} + +int zm_disable_wp() +{ + u8 new_wp_value; + + /* Disable using Write-Protect register 0x96 */ + new_wp_value = 0x8; + if ((dpm_wrm(DPM_WP, new_wp_value)) < 0) { + printf("Disable Write-Protect register failed\n"); + return -1; + } + return 0; +} + +int zm_enable_wp() +{ + u8 orig_wp_value; + orig_wp_value = 0x0; + + /* Enable using Write-Protect register 0x96 */ + if ((dpm_wrm(DPM_WP, orig_wp_value)) < 0) { + printf("Enable Write-Protect register failed\n"); + return -1; + } + return 0; +} + diff --git a/board/freescale/common/zm7300.h b/board/freescale/common/zm7300.h new file mode 100644 index 0000000..6b4d035 --- /dev/null +++ b/board/freescale/common/zm7300.h @@ -0,0 +1,22 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ZM7300_H_ +#define __ZM7300_H 1_ + +#include <common.h> +#include <i2c.h> +#include <errno.h> +#include <asm/io.h> + +#define ZM_STEP 125 +int zm7300_set_voltage(int voltage_1_10mv); +int zm_write_voltage(int voltage); +int zm_read_voltage(void); +int zm_disable_wp(void); +int zm_enable_wp(void); + +#endif /* __ZM7300_H_ */ -- 1.7.6.GIT

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[U-Boot] CONFIG_LOADADDR vs CONFIG_SYS_LOAD_ADDR
by Masahiro Yamada 04 Apr '14

04 Apr '14

Hi. I sometimes get confused by similar naming macros. In my understanding, CONFIG_LOADADDR or CONFIG_SYS_LOAD_ADDR is used as default address by such commands as "bootm", "tftpboot", etc. If both are defined, it looks like CONFIG_LOADADDR takes precedence (as far as I tested). Do we need both? Is it a good idea to merge them? Best Regards Masahiro Yamada

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Re: [U-Boot] [PATCH] omap3: igep00x0: fix NAND_BOOT for igep_0020 and igep_0030
by Gupta, Pekon 04 Apr '14

04 Apr '14

(re-sending as earlier mail got moderated). Hi Enric, >From: Enric Balletbo Serra [mailto:eballetbo@gmail.com] >2014-04-03 9:09 GMT+02:00 Pekon Gupta <pekon(a)ti.com>: >> fixes commit e37e954eba3edb5015a0a02880d57517f57425d8 >> OMAP3: igep00x0: Convert to ti_omap3_common.h. >> >> Above commit introduced compilation error when building igep0020 and igep0030 >> boards for NAND boot. It removed 'CONFIG_SYS_NAND_U_BOOT_START' which tells >> SPL/MLO offset of u-boot.img in NAND. >> >> Signed-off-by: Pekon Gupta <pekon(a)ti.com> >> --- >> include/configs/omap3_igep00x0.h | 2 ++ >> 1 file changed, 2 insertions(+) >> >> diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h >> index 8b8583a..4e87d6b 100644 >> --- a/include/configs/omap3_igep00x0.h >> +++ b/include/configs/omap3_igep00x0.h >> @@ -199,6 +199,8 @@ >> #define CONFIG_SYS_NAND_ECCSIZE 512 >> #define CONFIG_SYS_NAND_ECCBYTES 3 >> #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW >> +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE >> +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 > > >These two defines are defined in ti_armv7_common.h. The >ti_armv7_common.h is included by ti_omap3_common.h, and >omap3_igep00x0.h includes this file. So should not be necessary define >this. I tried to build current mainline using igep0020_nand_config and >built without errors for me. Which branch are you using ? > My bad, I din't check that one of my local commits had removed above two defines from "ti_armv7_common.h", because these are board-specific configs, and should be in individual board-configs. I got misled because one of your commits (e37e954) removes these two defines and has title "OMAP3: igep00x0: Convert to ti_omap3_common.h." Sorry about noise, please ignore this patch. I'll merge these changes with my other patch, where I move out board-specific configs from "ti_armv7_common.h" with regards, pekon

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[U-Boot] [PATCH 1/8] imx-common: add board_video_skip
by Eric Bénard 04 Apr '14

04 Apr '14

this function is shared by several board and thus can be factorized Signed-off-by: Eric Bénard <eric(a)eukrea.com> --- arch/arm/imx-common/Makefile | 1 + arch/arm/imx-common/video.c | 55 +++++++++++++++++++++++++++++++++ arch/arm/include/asm/imx-common/video.h | 20 ++++++++++++ 3 files changed, 76 insertions(+) create mode 100644 arch/arm/imx-common/video.c create mode 100644 arch/arm/include/asm/imx-common/video.h diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile index 16809fe..2a7fc42 100644 --- a/arch/arm/imx-common/Makefile +++ b/arch/arm/imx-common/Makefile @@ -19,6 +19,7 @@ obj-y += misc.o endif ifeq ($(SOC),$(filter $(SOC),mx6)) obj-$(CONFIG_CMD_SATA) += sata.o +obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o endif obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o obj-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o diff --git a/arch/arm/imx-common/video.c b/arch/arm/imx-common/video.c new file mode 100644 index 0000000..8db5a84 --- /dev/null +++ b/arch/arm/imx-common/video.c @@ -0,0 +1,55 @@ +/* + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/errno.h> +#include <asm/imx-common/video.h> + +extern struct display_info_t const displays[]; +extern size_t display_number; + +int board_video_skip(void) +{ + int i; + int ret; + char const *panel = getenv("panel"); + if (!panel) { + for (i = 0; i < display_number; i++) { + struct display_info_t const *dev = displays+i; + if (dev->detect && dev->detect(dev)) { + panel = dev->mode.name; + printf("auto-detected panel %s\n", panel); + break; + } + } + if (!panel) { + panel = displays[0].mode.name; + printf("No panel detected: default to %s\n", panel); + i = 0; + } + } else { + for (i = 0; i < display_number; i++) { + if (!strcmp(panel, displays[i].mode.name)) + break; + } + } + if (i < display_number) { + ret = ipuv3_fb_init(&displays[i].mode, 0, + displays[i].pixfmt); + if (!ret) { + displays[i].enable(displays+i); + printf("Display: %s (%ux%u)\n", + displays[i].mode.name, + displays[i].mode.xres, + displays[i].mode.yres); + } else + printf("LCD %s cannot be configured: %d\n", + displays[i].mode.name, ret); + } else { + printf("unsupported panel %s\n", panel); + return -EINVAL; + } + + return 0; +} diff --git a/arch/arm/include/asm/imx-common/video.h b/arch/arm/include/asm/imx-common/video.h new file mode 100644 index 0000000..e0c4ef4 --- /dev/null +++ b/arch/arm/include/asm/imx-common/video.h @@ -0,0 +1,20 @@ +/* + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __IMX_VIDEO_H_ +#define __IMX_VIDEO_H_ + +#include <linux/fb.h> +#include <ipu_pixfmt.h> + +struct display_info_t { + int bus; + int addr; + int pixfmt; + int (*detect)(struct display_info_t const *dev); + void (*enable)(struct display_info_t const *dev); + struct fb_videomode mode; +}; + +#endif -- 1.9.0

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[U-Boot] post tests in arm uboot
by shobin b 03 Apr '14

03 Apr '14

Hi, I enabled post in u boot(I am using toradex colibrit20 board).In post i enabled memory and i2c tests in u boot. Its working fine.After that i did watchdog test and then i flashed my u boot to board.It shows following it is hanged up to post watchdog, U-Boot 2011.06-00001-g2715f5b-dirty (Apr 02 2014 - 13:31:05) TEGRA2 In memory_post_test1 In memory_post_test1 In memory_post_test1 In memory_post_test1 MEMORY POST TEST 1 OK.......... In memory_post_test2 MEMORY POST TEST 2 OK.......... In memory_post_test3 MEMORY POST TEST 3 OK.......... In memory_post_test4MEMORY POST TEST 4 OK..........DRAM: 256 MiBPOST memory PASSEDNAND: 512 MiBMMC: Tegra2 SD/MMC: 0*** Warning - bad CRC, using default environment Board: Toradex Colibri T20Missing Colibri config blockNet: Net Initialization SkippedNo ethernet found.POST watchdog Please give me a solution.

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[U-Boot] [PATCH] am33xx: add support for beaglebone NAND cape
by Pekon Gupta 03 Apr '14

03 Apr '14

Beaglebone Board can be connected to expansion boards to add devices to them. These expansion boards are called 'capes'. This patch adds support for following versions of Beaglebone(AM335x) NAND capes (a) NAND Device with bus-width=16, block-size=128k, page-size=2k, oob-size=64 (b) NAND Device with bus-width=16, block-size=256k, page-size=4k, oob-size=224 Further information and datasheets can be found at [1] and [2] * How to boot from NAND using Memory Expander + NAND Cape ? * - Important: As BOOTSEL values are sampled only at POR, so after changing any setting on SW2 (DIP switch), disconnect and reconnect all board power supply (including mini-USB console port) to POR the beaglebone. - Selection of ECC scheme for NAND cape(a), ROM code expects BCH8_HW ecc-scheme for NAND cape(b), ROM code expects BCH16_HW ecc-scheme - Selction of boot modes can be controlled via DIP switch(SW2) present on Memory Expander cape. SW2[SWITCH_BOOT] == OFF follow default boot order MMC-> SPI -> UART -> USB SW2[SWITCH_BOOT] == ON boot mode selected via DIP switch(SW2) So to flash NAND, first boot via MMC or other sources and then switch to SW2[SWITCH_BOOT]=ON to boot from NAND Cape. - For NAND boot following switch settings need to be followed SW2[ 0] = ON (SYSBOOT[ 0]==0: NAND boot mode selected ) SW2[ 1] = ON (SYSBOOT[ 1]==0: -- do -- ) SW2[ 2] = OFF (SYSBOOT[ 2]==1: -- do -- ) SW2[ 3] = OFF (SYSBOOT[ 3]==1: -- do -- ) SW2[ 4] = ON (SYSBOOT[ 4]==0: -- do -- ) SW2[ 8] = OFF (SYSBOOT[ 8]==1: 0:x8 device, 1:x16 device ) SW2[ 9] = ON (SYSBOOT[ 9]==0: ECC done by ROM ) SW2[10] = ON (SYSBOOT[10]==0: Non Muxed device ) SW2[11] = ON (SYSBOOT[11]==0: -- do -- ) [1] http://beagleboardtoys.info/index.php?title=BeagleBone_Memory_Expansion [2] http://beagleboardtoys.info/index.php?title=BeagleBone_4Gb_16-Bit_NAND_Modu… Signed-off-by: Pekon Gupta <pekon(a)ti.com> --- board/ti/am335x/mux.c | 75 +++++++++++++++++++++++++++++++++++++-------------- 1 file changed, 55 insertions(+), 20 deletions(-) diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c index b2bfda5..9ddcad0 100644 --- a/board/ti/am335x/mux.c +++ b/board/ti/am335x/mux.c @@ -171,25 +171,53 @@ static struct module_pin_mux mii1_pin_mux[] = { {-1}, }; -static struct module_pin_mux nand_pin_mux[] = { - {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ - {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ - {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ - {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ - {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ - {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ - {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ - {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ - {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ - {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ - {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ - {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ - {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ - {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ - {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ +#ifdef CONFIG_NAND +static struct module_pin_mux nand_x16_pin_mux[] = { + {OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD0 */ + {OFFSET(gpmc_ad1), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD1 */ + {OFFSET(gpmc_ad2), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD2 */ + {OFFSET(gpmc_ad3), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD3 */ + {OFFSET(gpmc_ad4), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD4 */ + {OFFSET(gpmc_ad5), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD5 */ + {OFFSET(gpmc_ad6), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD6 */ + {OFFSET(gpmc_ad7), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD7 */ + {OFFSET(gpmc_ad8), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD8 */ + {OFFSET(gpmc_ad9), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD9 */ + {OFFSET(gpmc_ad10), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD10 */ + {OFFSET(gpmc_ad11), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD11 */ + {OFFSET(gpmc_ad12), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD12 */ + {OFFSET(gpmc_ad13), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD13 */ + {OFFSET(gpmc_ad14), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD14 */ + {OFFSET(gpmc_ad15), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD15 */ + {OFFSET(gpmc_wait0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* nWAIT */ + {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN)}, /* nWP */ + {OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)}, /* nCS */ + {OFFSET(gpmc_wen), (MODE(0) | PULLDOWN_EN)}, /* WEN */ + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLDOWN_EN)}, /* OE */ + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLDOWN_EN)}, /* ADV_ALE */ + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)}, /* BE_CLE */ {-1}, }; +static struct module_pin_mux nand_x8_pin_mux[] = { + {OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD0 */ + {OFFSET(gpmc_ad1), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD1 */ + {OFFSET(gpmc_ad2), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD2 */ + {OFFSET(gpmc_ad3), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD3 */ + {OFFSET(gpmc_ad4), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD4 */ + {OFFSET(gpmc_ad5), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD5 */ + {OFFSET(gpmc_ad6), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD6 */ + {OFFSET(gpmc_ad7), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD7 */ + {OFFSET(gpmc_wait0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* nWAIT */ + {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN)}, /* nWP */ + {OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)}, /* nCS */ + {OFFSET(gpmc_wen), (MODE(0) | PULLDOWN_EN)}, /* WEN */ + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLDOWN_EN)}, /* OE */ + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLDOWN_EN)}, /* ADV_ALE */ + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)}, /* BE_CLE */ + {-1}, +}; +#endif #if defined(CONFIG_NOR) && !defined(CONFIG_NOR_BOOT) static struct module_pin_mux bone_norcape_pin_mux[] = { {OFFSET(lcd_data0), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A0 */ @@ -336,11 +364,12 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header) configure_module_pin_mux(i2c1_pin_mux); configure_module_pin_mux(mii1_pin_mux); configure_module_pin_mux(mmc0_pin_mux); -#ifndef CONFIG_NOR - configure_module_pin_mux(mmc1_pin_mux); -#endif #if defined(CONFIG_NOR) && !defined(CONFIG_NOR_BOOT) configure_module_pin_mux(bone_norcape_pin_mux); +#elif defined(CONFIG_NAND) + configure_module_pin_mux(nand_x16_pin_mux); +#else + configure_module_pin_mux(mmc1_pin_mux); #endif } else if (board_is_gp_evm(header)) { /* General Purpose EVM */ @@ -351,8 +380,10 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header) if (profile & ~PROFILE_2) configure_module_pin_mux(i2c1_pin_mux); /* Profiles 2 & 3 don't have NAND */ +#ifdef CONFIG_NAND if (profile & ~(PROFILE_2 | PROFILE_3)) - configure_module_pin_mux(nand_pin_mux); + configure_module_pin_mux(nand_x8_pin_mux); +#endif else if (profile == PROFILE_2) { configure_module_pin_mux(mmc1_pin_mux); configure_module_pin_mux(spi0_pin_mux); @@ -377,7 +408,11 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header) configure_module_pin_mux(i2c1_pin_mux); configure_module_pin_mux(mii1_pin_mux); configure_module_pin_mux(mmc0_pin_mux); +#if defined(CONFIG_NAND) + configure_module_pin_mux(nand_x16_pin_mux); +#else configure_module_pin_mux(mmc1_pin_mux); +#endif } else { puts("Unknown board, cannot configure pinmux."); hang(); -- 1.8.5.1.163.gd7aced9

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[U-Boot] [PATCH v3 0/3] enable support for x16 NAND devices
by Pekon Gupta 03 Apr '14

03 Apr '14

*changes v2 -> v3* [PATCH v3 1/3] (new) porting Brian Norri's patch from linux tree This patch allows reading of ONFI params independent of controller configuration and NAND device width. [PATCH v3 2/2] rebase [PATCH v2 2/4] on latest release [PATCH v3 3/3] (new) cleaned remaining GPMC_NAND_ECC_LP_xx macros from OMAP3 platform Compile Tested#> ./MAKEALL -s omap3 -s omap4 -s omap5 -s dra7xx -s am33xx *changes v1 -> v2* [PATCH v2 1/4]: - dropped NAND_BUSWIDTH_AUTO, instead using CONFIG_SYS_NAND_ONFI_DETECTION - added check in nand_flash_detect_onfi() for x8 mode [PATCH v2 2/4]: (new) Adds CONFIG_SYS_NAND_DEVICE_WIDTH - updated for auto-detection of bus-width in non-SPL and ONFI_DETECTION mode Refer: http://lists.denx.de/pipermail/u-boot/2013-September/163748.html [PATCH v2 3/4] <no update> [PATCH v2 4/4] disabled Pulls on output only I/O pads. - updated commit description to add details about NAND cape *original v1* This series includes independent patch-sets aiming to enable x16 NAND support on AM33xx boards (like beaglebone-LT). [PATCH 1/4]: This patch is ported from linux driver/mtd/nand to allow detection device-width of NAND by reading ONFI parameter page. [PATCH 2/4]: enable NAND_BUSWIDTH_AUTO feature in omap_nand.c [PATCH 3/4]: cleaning of GPMC configs for NAND and NOR Brian Norris (1): mtd: nand: don't use read_buf for 8-bit ONFI transfers Pekon Gupta (2): mtd: nand: omap: add CONFIG_SYS_NAND_DEVICE_WIDTH to determine NAND device bus-width omap3: remove remnant macros GPMC_NAND_ECC_LP_x8_LAYOUT and GPMC_NAND_ECC_LP_x16_LAYOUT arch/arm/cpu/armv7/omap3/mem.c | 12 ------------ arch/arm/include/asm/arch-omap3/mem.h | 8 -------- board/compulab/cm_t35/cm_t35.c | 12 ++++++------ doc/README.nand | 9 +++++++++ drivers/mtd/nand/nand_base.c | 5 +++-- drivers/mtd/nand/omap_gpmc.c | 13 +++++++++---- include/configs/am335x_evm.h | 1 + include/configs/am335x_igep0033.h | 1 + include/configs/am3517_crane.h | 1 + include/configs/am3517_evm.h | 1 + include/configs/cm_t335.h | 2 +- include/configs/cm_t35.h | 1 + include/configs/devkit8000.h | 1 + include/configs/dig297.h | 1 + include/configs/mcx.h | 1 + include/configs/omap3_beagle.h | 1 + include/configs/omap3_evm_common.h | 2 +- include/configs/omap3_igep00x0.h | 1 + include/configs/omap3_logic.h | 1 + include/configs/omap3_overo.h | 1 + include/configs/omap3_pandora.h | 2 +- include/configs/omap3_zoom1.h | 1 + include/configs/pengwyn.h | 2 +- include/configs/siemens-am33x-common.h | 1 + include/configs/tam3517-common.h | 1 + include/configs/tao3530.h | 2 +- include/configs/tricorder.h | 1 + include/configs/tseries.h | 2 +- 28 files changed, 49 insertions(+), 38 deletions(-) -- 1.8.5.1.163.gd7aced9

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[U-Boot] [PATCH] board/t104xrdb: Add support of CPLD
by Prabhakar Kushwaha 03 Apr '14

03 Apr '14

T1040RDB and T1042RDB_PI has CPLD. Here CPLD controls board mux/features. This support of CPLD includes - files and register defintion - Commands to swtich alternate bank and default bank Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- Changes for v2: - Updated the cpld command Changes for v3: - fix typo Changes for v4: - fix typo Changes for v5: - fix cpld registers while printing - rebased on top of below patch powerpc/t104xrdb: Unification of T104xRDB header files http://patchwork.ozlabs.org/patch/335207/ board/freescale/t104xrdb/Makefile | 1 + board/freescale/t104xrdb/cpld.c | 112 +++++++++++++++++++++++++++++++++++ board/freescale/t104xrdb/cpld.h | 40 +++++++++++++ board/freescale/t104xrdb/t104xrdb.c | 13 ++++ include/configs/T104xRDB.h | 8 +++ 5 files changed, 174 insertions(+) create mode 100644 board/freescale/t104xrdb/cpld.c create mode 100644 board/freescale/t104xrdb/cpld.h diff --git a/board/freescale/t104xrdb/Makefile b/board/freescale/t104xrdb/Makefile index e51fb7a..7e7bfb1 100644 --- a/board/freescale/t104xrdb/Makefile +++ b/board/freescale/t104xrdb/Makefile @@ -6,6 +6,7 @@ obj-y += t104xrdb.o +obj-y += cpld.o obj-y += ddr.o obj-y += eth.o obj-$(CONFIG_PCI) += pci.o diff --git a/board/freescale/t104xrdb/cpld.c b/board/freescale/t104xrdb/cpld.c new file mode 100644 index 0000000..df0e348 --- /dev/null +++ b/board/freescale/t104xrdb/cpld.c @@ -0,0 +1,112 @@ +/** + * Copyright 2014 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + * + * This file provides support for the board-specific CPLD used on some Freescale + * reference boards. + * + * The following macros need to be defined: + * + * CONFIG_SYS_CPLD_BASE-The virtual address of the base of the CPLD register map + */ + +#include <common.h> +#include <command.h> +#include <asm/io.h> + +#include "cpld.h" + +u8 cpld_read(unsigned int reg) +{ + void *p = (void *)CONFIG_SYS_CPLD_BASE; + + return in_8(p + reg); +} + +void cpld_write(unsigned int reg, u8 value) +{ + void *p = (void *)CONFIG_SYS_CPLD_BASE; + + out_8(p + reg, value); +} + +/** + * Set the boot bank to the alternate bank + */ +void cpld_set_altbank(void) +{ + u8 reg = CPLD_READ(flash_ctl_status); + + reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_ALTBANK; + + CPLD_WRITE(flash_ctl_status, reg); + CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET); +} + +/** + * Set the boot bank to the default bank + */ +void cpld_set_defbank(void) +{ + u8 reg = CPLD_READ(flash_ctl_status); + + reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_DFLTBANK; + + CPLD_WRITE(flash_ctl_status, reg); + CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET); +} + +#ifdef DEBUG +static void cpld_dump_regs(void) +{ + printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver)); + printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub)); + printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver)); + printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver)); + printf("reset_ctl1 = 0x%02x\n", CPLD_READ(reset_ctl1)); + printf("reset_ctl2 = 0x%02x\n", CPLD_READ(reset_ctl2)); + printf("int_status = 0x%02x\n", CPLD_READ(int_status)); + printf("flash_ctl_status = 0x%02x\n", CPLD_READ(flash_ctl_status)); + printf("fan_ctl_status = 0x%02x\n", CPLD_READ(fan_ctl_status)); + printf("led_ctl_status = 0x%02x\n", CPLD_READ(led_ctl_status)); + printf("sfp_ctl_status = 0x%02x\n", CPLD_READ(sfp_ctl_status)); + printf("misc_ctl_status = 0x%02x\n", CPLD_READ(misc_ctl_status)); + printf("boot_override = 0x%02x\n", CPLD_READ(boot_override)); + printf("boot_config1 = 0x%02x\n", CPLD_READ(boot_config1)); + printf("boot_config2 = 0x%02x\n", CPLD_READ(boot_config2)); + putc('\n'); +} +#endif + +int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int rc = 0; + + if (argc <= 1) + return cmd_usage(cmdtp); + + if (strcmp(argv[1], "reset") == 0) { + if (strcmp(argv[2], "altbank") == 0) + cpld_set_altbank(); + else + cpld_set_defbank(); +#ifdef DEBUG + } else if (strcmp(argv[1], "dump") == 0) { + cpld_dump_regs(); +#endif + } else + rc = cmd_usage(cmdtp); + + return rc; +} + +U_BOOT_CMD( + cpld, CONFIG_SYS_MAXARGS, 1, do_cpld, + "Reset the board or alternate bank", + "reset - hard reset to default bank\n" + "cpld reset altbank - reset to alternate bank\n" +#ifdef DEBUG + "cpld dump - display the CPLD registers\n" +#endif + ); diff --git a/board/freescale/t104xrdb/cpld.h b/board/freescale/t104xrdb/cpld.h new file mode 100644 index 0000000..0da9a01 --- /dev/null +++ b/board/freescale/t104xrdb/cpld.h @@ -0,0 +1,40 @@ +/** + * Copyright 2013 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + * + * This file provides support for the ngPIXIS, a board-specific FPGA used on + * some Freescale reference boards. + */ + +/* + * CPLD register set. Feel free to add board-specific #ifdefs where necessary. + */ +struct cpld_data { + u8 cpld_ver; /* 0x00 - CPLD Major Revision Register */ + u8 cpld_ver_sub; /* 0x01 - CPLD Minor Revision Register */ + u8 hw_ver; /* 0x02 - Hardware Revision Register */ + u8 sw_ver; /* 0x03 - Software Revision register */ + u8 res0[12]; /* 0x04 - 0x0F - not used */ + u8 reset_ctl1; /* 0x10 - Reset control Register1 */ + u8 reset_ctl2; /* 0x11 - Reset control Register2 */ + u8 int_status; /* 0x12 - Interrupt status Register */ + u8 flash_ctl_status; /* 0x13 - Flash control and status register */ + u8 fan_ctl_status; /* 0x14 - Fan control and status register */ + u8 led_ctl_status; /* 0x15 - LED control and status register */ + u8 sfp_ctl_status; /* 0x16 - SFP control and status register */ + u8 misc_ctl_status; /* 0x17 - Miscellanies ctrl & status register*/ + u8 boot_override; /* 0x18 - Boot override register */ + u8 boot_config1; /* 0x19 - Boot config override register*/ + u8 boot_config2; /* 0x1A - Boot config override register*/ +} cpld_data_t; + + +/* Pointer to the CPLD register set */ + +u8 cpld_read(unsigned int reg); +void cpld_write(unsigned int reg, u8 value); + +#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) +#define CPLD_WRITE(reg, value)\ + cpld_write(offsetof(struct cpld_data, reg), value) diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c index 6e29d64..b48133a 100644 --- a/board/freescale/t104xrdb/t104xrdb.c +++ b/board/freescale/t104xrdb/t104xrdb.c @@ -19,14 +19,27 @@ #include <fm_eth.h> #include "t104xrdb.h" +#include "cpld.h" DECLARE_GLOBAL_DATA_PTR; int checkboard(void) { struct cpu_type *cpu = gd->arch.cpu; + u8 sw; printf("Board: %sRDB\n", cpu->name); + printf("Board rev: 0x%02x CPLD ver: 0x%02x, ", + CPLD_READ(hw_ver), CPLD_READ(sw_ver)); + + sw = CPLD_READ(flash_ctl_status); + sw = ((sw & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT); + + if (sw <= 7) + printf("vBank: %d\n", sw); + else + printf("Unsupported Bank=%x\n", sw); + return 0; } diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 8d2fdb0..2bbb78c 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -179,6 +179,14 @@ #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} /* CPLD on IFC */ +#define CPLD_LBMAP_MASK 0x3F +#define CPLD_BANK_SEL_MASK 0x07 +#define CPLD_BANK_OVERRIDE 0x40 +#define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ +#define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */ +#define CPLD_LBMAP_RESET 0xFF +#define CPLD_LBMAP_SHIFT 0x03 + #define CONFIG_SYS_CPLD_BASE 0xffdf0000 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) #define CONFIG_SYS_CSPR2_EXT (0xf) -- 1.7.9.5

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[U-Boot] [PATCH] fs/fat: correct FAT16/12 file finding in root dir
by Josh Wu 03 Apr '14

03 Apr '14

When write a file into FAT file system, if not find the file in the root dir sectors, it will call get_fatent_value() to get next cluster number via lookup the FAT table. The issue is FAT table only can find the cluster number start to 2. If current clust is in root dir, then curclust is a negative number or 0, 1. So get_fatenv_value() cannot get correct next cluster number. In this case we just increase the curclust. That means return the next cluster in root dir. Signed-off-by: Josh Wu <josh.wu(a)atmel.com> --- fs/fat/fat_write.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/fs/fat/fat_write.c b/fs/fat/fat_write.c index 9f5e911..e495fdc 100644 --- a/fs/fat/fat_write.c +++ b/fs/fat/fat_write.c @@ -881,6 +881,17 @@ static dir_entry *find_directory_entry(fsdata *mydata, int startsect, return dentptr; } + if (mydata->fatsize != 32 && (int)curclust < 2 ) { + /* Current clust is in root dir, set to next clust */ + curclust++; + if ((int)curclust < 2) + continue; + + /* Reach the end of root dir */ + empty_dentptr = dentptr; + return NULL; + } + curclust = get_fatent_value(mydata, dir_curclust); if ((curclust >= 0xffffff8) || (curclust >= 0xfff8)) { empty_dentptr = dentptr; -- 1.7.9.5

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