March 2014 - U-Boot

[U-Boot] [PATCH v2] m68k: Remove M5271EVB and idmr board support
by Masahiro Yamada 10 Mar '14

10 Mar '14

CONFIG_SYS_HZ must be always 1000, but M5271EVB.h defines it as 1000000 and idmr.h defines it as (50000000 / 64). When compiling these two boards, a warning message is displayed: time.c:14:2: warning: #warning "CONFIG_SYS_HZ must be 1000 and should not be defined by platforms" [-Wcpp] There are no board maintainers for them so this commit just deletes them. Signed-off-by: Masahiro Yamada <yamada.m(a)jp.panasonic.com> Cc: Jason Jin <Jason.jin(a)freescale.com> --- Changes in v2: - Rebase on commit 6853e6aa - Fill 'Commit' column of doc/README.scrapyard for IXP boards board/freescale/m5271evb/Makefile | 8 - board/freescale/m5271evb/config.mk | 9 - board/freescale/m5271evb/m5271evb.c | 115 ------------ board/freescale/m5271evb/u-boot.lds | 85 --------- board/idmr/Makefile | 8 - board/idmr/config.mk | 9 - board/idmr/flash.c | 342 ------------------------------------ board/idmr/idmr.c | 152 ---------------- board/idmr/u-boot.lds | 82 --------- boards.cfg | 2 - doc/README.scrapyard | 16 +- include/configs/M5271EVB.h | 234 ------------------------ include/configs/idmr.h | 240 ------------------------- 13 files changed, 9 insertions(+), 1293 deletions(-) delete mode 100644 board/freescale/m5271evb/Makefile delete mode 100644 board/freescale/m5271evb/config.mk delete mode 100644 board/freescale/m5271evb/m5271evb.c delete mode 100644 board/freescale/m5271evb/u-boot.lds delete mode 100644 board/idmr/Makefile delete mode 100644 board/idmr/config.mk delete mode 100644 board/idmr/flash.c delete mode 100644 board/idmr/idmr.c delete mode 100644 board/idmr/u-boot.lds delete mode 100644 include/configs/M5271EVB.h delete mode 100644 include/configs/idmr.h diff --git a/board/freescale/m5271evb/Makefile b/board/freescale/m5271evb/Makefile deleted file mode 100644 index 77138c6..0000000 --- a/board/freescale/m5271evb/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = m5271evb.o diff --git a/board/freescale/m5271evb/config.mk b/board/freescale/m5271evb/config.mk deleted file mode 100644 index 957f584..0000000 --- a/board/freescale/m5271evb/config.mk +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. -# Coldfire contribution by Bernhard Kuhn <bkuhn(a)metrowerks.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CONFIG_SYS_TEXT_BASE = 0xffe00000 diff --git a/board/freescale/m5271evb/m5271evb.c b/board/freescale/m5271evb/m5271evb.c deleted file mode 100644 index 5981a27..0000000 --- a/board/freescale/m5271evb/m5271evb.c +++ /dev/null @@ -1,115 +0,0 @@ -/* - * (C) Copyright 2000-2006 - * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/immap.h> - -int checkboard (void) { - puts ("Board: Freescale M5271EVB\n"); - return 0; -}; - -phys_size_t initdram (int board_type) { - - int i; - - /* Enable Address lines 23-21 and lower 16bits of data path */ - mbar_writeByte(MCF_GPIO_PAR_AD, MCF_GPIO_AD_ADDR23 | - MCF_GPIO_AD_ADDR22 | MCF_GPIO_AD_ADDR21 | - MCF_GPIO_AD_DATAL); - - /* Set CS2 pin to be SD_CS0 */ - mbar_writeByte(MCF_GPIO_PAR_CS, mbar_readByte(MCF_GPIO_PAR_CS) - | MCF_GPIO_PAR_CS_PAR_CS2); - - /* Configure SDRAM Control Pin Assignemnt Register */ - mbar_writeByte(MCF_GPIO_PAR_SDRAM, MCF_GPIO_SDRAM_CSSDCS_00 | - MCF_GPIO_SDRAM_SDWE | MCF_GPIO_SDRAM_SCAS | - MCF_GPIO_SDRAM_SRAS | MCF_GPIO_SDRAM_SCKE | - MCF_GPIO_SDRAM_SDCS_11); - asm(" nop"); - - /* - * Check to see if the SDRAM has already been initialized - * by a run control tool - */ - if (!(mbar_readLong(MCF_SDRAMC_DACR0) & MCF_SDRAMC_DACRn_RE)) { - /* Initialize DRAM Control Register: DCR */ - mbar_writeShort(MCF_SDRAMC_DCR, - MCF_SDRAMC_DCR_RTIM(2) - | MCF_SDRAMC_DCR_RC(0x2E)); - asm(" nop"); - - /* - * Initialize DACR0 - * - * CASL: 01 - * CBM: cmd at A20, bank select bits 21 and up - * PS: 32bit port size - */ - mbar_writeLong(MCF_SDRAMC_DACR0, - MCF_SDRAMC_DACRn_BA(CONFIG_SYS_SDRAM_BASE>>18) - | MCF_SDRAMC_DACRn_CASL(1) - | MCF_SDRAMC_DACRn_CBM(3) - | MCF_SDRAMC_DACRn_PS(0)); - asm(" nop"); - - /* Initialize DMR0 */ - mbar_writeLong(MCF_SDRAMC_DMR0, - MCF_SDRAMC_DMRn_BAM_16M - | MCF_SDRAMC_DMRn_V); - asm(" nop"); - - /* Set IP bit in DACR */ - mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0) - | MCF_SDRAMC_DACRn_IP); - asm(" nop"); - - /* Wait at least 20ns to allow banks to precharge */ - for (i = 0; i < 5; i++) - asm(" nop"); - - /* Write to this block to initiate precharge */ - *(u32 *)(CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5; - asm(" nop"); - - /* Set RE bit in DACR */ - mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0) - | MCF_SDRAMC_DACRn_RE); - - /* Wait for at least 8 auto refresh cycles to occur */ - for (i = 0; i < 2000; i++) - asm(" nop"); - - /* Finish the configuration by issuing the MRS */ - mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0) - | MCF_SDRAMC_DACRn_MRS); - asm(" nop"); - - /* - * Write to the SDRAM Mode Register A0-A11 = 0x400 - * - * Write Burst Mode = Programmed Burst Length - * Op Mode = Standard Op - * CAS Latency = 2 - * Burst Type = Sequential - * Burst Length = 1 - */ - *(u32 *)(CONFIG_SYS_SDRAM_BASE + 0x400) = 0xa5a5a5a5; - asm(" nop"); - } - - return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; -}; - -int testdram (void) { - - /* TODO: XXX XXX XXX */ - printf ("DRAM test not implemented!\n"); - - return (0); -} diff --git a/board/freescale/m5271evb/u-boot.lds b/board/freescale/m5271evb/u-boot.lds deleted file mode 100644 index 3defcd2..0000000 --- a/board/freescale/m5271evb/u-boot.lds +++ /dev/null @@ -1,85 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(m68k) - -SECTIONS -{ - .text : - { - arch/m68k/cpu/mcf52x2/start.o (.text*) - - . = DEFINED(env_offset) ? env_offset : .; - common/env_embedded.o (.ppcenv) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - - .reloc : - { - __got_start = .; - KEEP(*(.got)) - __got_end = .; - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - _sbss = .; - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - _ebss = .; - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/idmr/Makefile b/board/idmr/Makefile deleted file mode 100644 index 67c2384..0000000 --- a/board/idmr/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = idmr.o flash.o diff --git a/board/idmr/config.mk b/board/idmr/config.mk deleted file mode 100644 index 840a37e..0000000 --- a/board/idmr/config.mk +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. -# Coldfire contribution by Bernhard Kuhn <bkuhn(a)metrowerks.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CONFIG_SYS_TEXT_BASE = 0xff800000 diff --git a/board/idmr/flash.c b/board/idmr/flash.c deleted file mode 100644 index 52eb105..0000000 --- a/board/idmr/flash.c +++ /dev/null @@ -1,342 +0,0 @@ -/* - * (C) Copyright 2000-2006 - * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> - -#define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE -#define FLASH_BANK_SIZE 0x800000 -#define EN29LV640 0x227e227e - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -void flash_print_info (flash_info_t * info) -{ - int i; - - switch (info->flash_id & FLASH_VENDMASK) { - case (AMD_MANUFACT & FLASH_VENDMASK): - printf ("AMD: "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case (EN29LV640 & FLASH_TYPEMASK): - printf ("EN29LV640 (16Mbit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - goto Done; - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) { - printf ("\n "); - } - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - - Done: - return; -} - - -unsigned long flash_init (void) -{ - int i, j; - ulong size = 0; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - ulong flashbase = 0; - - flash_info[i].flash_id = - (AMD_MANUFACT & FLASH_VENDMASK) | - (EN29LV640 & FLASH_TYPEMASK); - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); - if (i == 0) - flashbase = PHYS_FLASH_1; - else - panic ("configured to many flash banks!\n"); - - for (j = 0; j < flash_info[i].sector_count; j++) { - flash_info[i].start[j] = flashbase + 0x10000 * j; - } - size += flash_info[i].size; - } - - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + 0x2ffff, &flash_info[0]); - - return size; -} - - -#define CMD_READ_ARRAY 0x00F0 -#define CMD_UNLOCK1 0x00AA -#define CMD_UNLOCK2 0x0055 -#define CMD_ERASE_SETUP 0x0080 -#define CMD_ERASE_CONFIRM 0x0030 -#define CMD_PROGRAM 0x00A0 -#define CMD_UNLOCK_BYPASS 0x0020 - -#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00000555<<1))) -#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA<<1))) - -#define BIT_ERASE_DONE 0x0080 -#define BIT_RDY_MASK 0x0080 -#define BIT_PROGRAM_ERROR 0x0020 -#define BIT_TIMEOUT 0x80000000 /* our flag */ - -#define READY 1 -#define ERR 2 -#define TMO 4 - - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - ulong result; - int iflag, prot, sect; - int rc = ERR_OK; - int chip1; - ulong start; - - /* first look for protection bits */ - - if (info->flash_id == FLASH_UNKNOWN) - return ERR_UNKNOWN_FLASH_TYPE; - - if ((s_first < 0) || (s_first > s_last)) { - return ERR_INVAL; - } - - if ((info->flash_id & FLASH_VENDMASK) != - (AMD_MANUFACT & FLASH_VENDMASK)) { - return ERR_UNKNOWN_FLASH_VENDOR; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) - return ERR_PROTECTED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - iflag = disable_interrupts (); - - printf ("\n"); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - if (info->protect[sect] == 0) { /* not protected */ - volatile u16 *addr = - (volatile u16 *) (info->start[sect]); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - *addr = CMD_ERASE_CONFIRM; - - /* wait until flash is ready */ - chip1 = 0; - - do { - result = *addr; - - /* check timeout */ - if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT * CONFIG_SYS_HZ / 1000) { - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - chip1 = TMO; - break; - } - - if (!chip1 - && (result & 0xFFFF) & BIT_ERASE_DONE) - chip1 = READY; - - } while (!chip1); - - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - - if (chip1 == ERR) { - rc = ERR_PROG_ERROR; - goto outahere; - } - if (chip1 == TMO) { - rc = ERR_TIMOUT; - goto outahere; - } - - printf ("ok.\n"); - } else { /* it was protected */ - - printf ("protected!\n"); - } - } - - if (ctrlc ()) - printf ("User Interrupt!\n"); - - outahere: - /* allow flash to settle - wait 10 ms */ - printf("Waiting 10 ms..."); - udelay (10000); - -/* for (i = 0; i < 10 * 1000 * 1000; ++i) - asm(" nop"); -*/ - - printf("done\n"); - if (iflag) - enable_interrupts (); - - - return rc; -} - -static int write_word (flash_info_t * info, ulong dest, ulong data) -{ - volatile u16 *addr = (volatile u16 *) dest; - ulong result; - int rc = ERR_OK; - int iflag; - int chip1; - ulong start; - - /* - * Check if Flash is (sufficiently) erased - */ - result = *addr; - if ((result & data) != data) - return ERR_NOT_ERASED; - - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - iflag = disable_interrupts (); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_PROGRAM; - *addr = data; - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - /* wait until flash is ready */ - chip1 = 0; - do { - result = *addr; - - /* check timeout */ - if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT * CONFIG_SYS_HZ / 1000) { - chip1 = ERR | TMO; - break; - } - if (!chip1 && ((result & 0x80) == (data & 0x80))) - chip1 = READY; - - } while (!chip1); - - *addr = CMD_READ_ARRAY; - - if (chip1 == ERR || *addr != data) - rc = ERR_PROG_ERROR; - - if (iflag) - enable_interrupts (); - - return rc; -} - - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong wp, data; - int rc; - - if (addr & 1) { - printf ("unaligned destination not supported\n"); - return ERR_ALIGN; - } - -#if 0 - if (cnt & 1) { - printf ("odd transfer sizes not supported\n"); - return ERR_ALIGN; - } -#endif - - wp = addr; - - if (addr & 1) { - data = (*((volatile u8 *) addr) << 8) | *((volatile u8 *) - src); - if ((rc = write_word (info, wp - 1, data)) != 0) { - return (rc); - } - src += 1; - wp += 1; - cnt -= 1; - } - - while (cnt >= 2) { - data = *((volatile u16 *) src); - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - src += 2; - wp += 2; - cnt -= 2; - } - - if (cnt == 1) { - data = (*((volatile u8 *) src) << 8) | - *((volatile u8 *) (wp + 1)); - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - src += 1; - wp += 1; - cnt -= 1; - } - - return ERR_OK; -} diff --git a/board/idmr/idmr.c b/board/idmr/idmr.c deleted file mode 100644 index 73660d8..0000000 --- a/board/idmr/idmr.c +++ /dev/null @@ -1,152 +0,0 @@ -/* - * (C) Copyright 2000-2006 - * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/immap.h> - -int checkboard (void) { - puts ("Board: iDMR\n"); - return 0; -}; - -phys_size_t initdram (int board_type) { - int i; - - /* - * After reset, CS0 is configured to cover entire address space. We - * need to configure it to its proper values, so that writes to - * CONFIG_SYS_SDRAM_BASE and vicinity during SDRAM controller setup below do - * now fall under CS0 (see 16.3.1 of the MCF5271 Reference Manual). - */ - - /* Flash chipselect, CS0 */ - /* ;CSAR0: Flash at 0xFF800000 */ - mbar_writeShort(0x0080, 0xFF80); - - /* CSCR0: Flash 6 waits, 16bit */ - mbar_writeShort(0x008A, 0x1980); - - /* CSMR0: Flash 8MB, R/W, valid */ - mbar_writeLong(0x0084, 0x007F0001); - - - /* - * SDRAM configuration proper - */ - - /* - * Address/Data Pin Assignment Reg.: enable address lines 23-21; do - * not enable data pins D[15:0], as we have 16 bit port to SDRAM - */ - mbar_writeByte(MCF_GPIO_PAR_AD, - MCF_GPIO_AD_ADDR23 | - MCF_GPIO_AD_ADDR22 | - MCF_GPIO_AD_ADDR21); - - /* No need to configure BS pins - reset values are OK */ - - /* Chip Select Pin Assignment Reg.: set CS[1-7] to GPIO */ - mbar_writeByte(MCF_GPIO_PAR_CS, 0x00); - - /* SDRAM Control Pin Assignment Reg. */ - mbar_writeByte(MCF_GPIO_PAR_SDRAM, - MCF_GPIO_SDRAM_CSSDCS_00 | /* no matter: PAR_CS=0 */ - MCF_GPIO_SDRAM_SDWE | - MCF_GPIO_SDRAM_SCAS | - MCF_GPIO_SDRAM_SRAS | - MCF_GPIO_SDRAM_SCKE | - MCF_GPIO_SDRAM_SDCS_01); - - /* - * Wait 100us. We run the bus at 50MHz, one cycle is 20ns. So 5 - * iterations will do, but we do 10 just to be safe. - */ - for (i = 0; i < 10; ++i) - asm(" nop"); - - - /* 1. Initialize DRAM Control Register: DCR */ - mbar_writeShort(MCF_SDRAMC_DCR, - MCF_SDRAMC_DCR_RTIM(0x10) | /* 65ns */ - MCF_SDRAMC_DCR_RC(0x60)); /* 1562 cycles */ - - - /* - * 2. Initialize DACR0 - * - * CL: 11 (CL=3: 0x03, 0x02; CL=2: 0x1) - * CBM: cmd at A20, bank select bits 21 and up - * PS: 16 bit - */ - mbar_writeLong(MCF_SDRAMC_DACR0, - MCF_SDRAMC_DACRn_BA(CONFIG_SYS_SDRAM_BASE>>18) | - MCF_SDRAMC_DACRn_BA(0x00) | - MCF_SDRAMC_DACRn_CASL(0x03) | - MCF_SDRAMC_DACRn_CBM(0x03) | - MCF_SDRAMC_DACRn_PS(0x03)); - - /* Initialize DMR0 */ - mbar_writeLong(MCF_SDRAMC_DMR0, - MCF_SDRAMC_DMRn_BAM_16M | - MCF_SDRAMC_DMRn_V); - - - /* 3. Set IP bit in DACR to initiate PALL command */ - mbar_writeLong(MCF_SDRAMC_DACR0, - mbar_readLong(MCF_SDRAMC_DACR0) | - MCF_SDRAMC_DACRn_IP); - - /* Write to this block to initiate precharge */ - *(volatile u16 *)(CONFIG_SYS_SDRAM_BASE) = 0xa5a5; - - /* - * Wait at least 20ns to allow banks to precharge (t_RP = 20ns). We - * wait a wee longer, just to be safe. - */ - for (i = 0; i < 5; ++i) - asm(" nop"); - - - /* 4. Set RE bit in DACR */ - mbar_writeLong(MCF_SDRAMC_DACR0, - mbar_readLong(MCF_SDRAMC_DACR0) | - MCF_SDRAMC_DACRn_RE); - - /* - * Wait for at least 8 auto refresh cycles to occur, i.e. at least - * 781 bus cycles. - */ - for (i = 0; i < 1000; ++i) - asm(" nop"); - - /* Finish the configuration by issuing the MRS */ - mbar_writeLong(MCF_SDRAMC_DACR0, - mbar_readLong(MCF_SDRAMC_DACR0) | - MCF_SDRAMC_DACRn_MRS); - - /* - * Write to the SDRAM Mode Register A0-A11 = 0x400 - * - * Write Burst Mode = Programmed Burst Length - * Op Mode = Standard Op - * CAS Latency = 3 - * Burst Type = Sequential - * Burst Length = 1 - */ - *(volatile u32 *)(CONFIG_SYS_SDRAM_BASE + 0x1800) = 0xa5a5a5a5; - - return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; -}; - - -int testdram (void) { - - /* TODO: XXX XXX XXX */ - printf ("DRAM test not implemented!\n"); - - return (0); -} diff --git a/board/idmr/u-boot.lds b/board/idmr/u-boot.lds deleted file mode 100644 index 4071f70..0000000 --- a/board/idmr/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(m68k) - -SECTIONS -{ - .text : - { - arch/m68k/cpu/mcf52x2/start.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - - .reloc : - { - __got_start = .; - KEEP(*(.got)) - __got_end = .; - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - _sbss = .; - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - _ebss = .; - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/boards.cfg b/boards.cfg index 0e663d9..9d0384e 100644 --- a/boards.cfg +++ b/boards.cfg @@ -444,7 +444,6 @@ Active m68k mcf5227x - freescale m52277evb Active m68k mcf5227x - freescale m52277evb M52277EVB_stmicro M52277EVB:CF_SBF,SYS_STMICRO_BOOT,SYS_TEXT_BASE=0x43E00000 TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> Active m68k mcf523x - freescale m5235evb M5235EVB M5235EVB:SYS_TEXT_BASE=0xFFE00000 TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> Active m68k mcf523x - freescale m5235evb M5235EVB_Flash32 M5235EVB:NORFLASH_PS32BIT,SYS_TEXT_BASE=0xFFC00000 TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> -Active m68k mcf52x2 - - - idmr - - Active m68k mcf52x2 - - cobra5272 cobra5272 - - Active m68k mcf52x2 - BuS eb_cpu5282 eb_cpu5282 eb_cpu5282:SYS_TEXT_BASE=0xFF000000,SYS_MONITOR_BASE=0xFF000400 Jens Scharsig <esw(a)bus-elektronik.de> Active m68k mcf52x2 - BuS eb_cpu5282 eb_cpu5282_internal eb_cpu5282:SYS_TEXT_BASE=0xF0000000,SYS_MONITOR_BASE=0xF0000418 Jens Scharsig <esw(a)bus-elektronik.de> @@ -453,7 +452,6 @@ Active m68k mcf52x2 - freescale m5208evbe Active m68k mcf52x2 - freescale m5249evb M5249EVB - - Active m68k mcf52x2 - freescale m5253demo M5253DEMO - TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> Active m68k mcf52x2 - freescale m5253evbe M5253EVBE - Hayden Fraser <Hayden.Fraser(a)freescale.com> -Active m68k mcf52x2 - freescale m5271evb M5271EVB - - Active m68k mcf52x2 - freescale m5272c3 M5272C3 - - Active m68k mcf52x2 - freescale m5275evb M5275EVB - - Active m68k mcf52x2 - freescale m5282evb M5282EVB - - diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 6b41445..7d67033 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,13 +11,15 @@ easily if here is something they might want to dig for... Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= -dvl_host arm ixp - 2014-01-28 Michael Schwingen <michael(a)schwingen.org> -actux4 arm ixp - 2014-01-28 Michael Schwingen <michael(a)schwingen.org> -actux3 arm ixp - 2014-01-28 Michael Schwingen <michael(a)schwingen.org> -actux2 arm ixp - 2014-01-28 Michael Schwingen <michael(a)schwingen.org> -actux1 arm ixp - 2014-01-28 Michael Schwingen <michael(a)schwingen.org> -mx1ads arm arm920t - 2014-01-13 -mini2440 arm arm920t - 2014-01-13 Gabriel Huau <contact(a)huau-gabriel.fr> +idmr m68k mcf52x2 - 2014-01-28 +M5271EVB m68k mcf52x2 - 2014-01-28 +dvl_host arm ixp e317de6b 2014-01-28 Michael Schwingen <michael(a)schwingen.org> +actux4 arm ixp 6ff7aafa 2014-01-28 Michael Schwingen <michael(a)schwingen.org> +actux3 arm ixp 38da33f3 2014-01-28 Michael Schwingen <michael(a)schwingen.org> +actux2 arm ixp 13e0ee7f 2014-01-28 Michael Schwingen <michael(a)schwingen.org> +actux1 arm ixp 373ee048 2014-01-28 Michael Schwingen <michael(a)schwingen.org> +mx1ads arm arm920t e570aca9 2014-01-13 +mini2440 arm arm920t af5b9b1f 2014-01-13 Gabriel Huau <contact(a)huau-gabriel.fr> omap730p2 arm arm926ejs 79c5c08d 2013-11-11 pn62 powerpc mpc824x 649acfe1 2013-11-11 Wolfgang Grandegger <wg(a)grandegger.com> pdnb3 arm ixp 304db0b 2013-09-24 Stefan Roese <sr(a)denx.de> diff --git a/include/configs/M5271EVB.h b/include/configs/M5271EVB.h deleted file mode 100644 index a9531b0..0000000 --- a/include/configs/M5271EVB.h +++ /dev/null @@ -1,234 +0,0 @@ -/* - * Configuation settings for the Freescale M5271EVB - * - * Based on MC5272C3 and r5200 board configs - * (C) Copyright 2006 Lab X Technologies <zachary.landau(a)labxtechnologies.com> - * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner(a)telex.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef _M5271EVB_H -#define _M5271EVB_H - -/* - * High Level Configuration Options (easy to change) - */ -#define CONFIG_MCF52x2 /* define processor family */ -#define CONFIG_M5271 /* define processor type */ -#define CONFIG_M5271EVB /* define board type */ - -#define CONFIG_MCFTMR - -#define CONFIG_MCFUART -#define CONFIG_SYS_UART_PORT (0) -#define CONFIG_BAUDRATE 115200 - -#undef CONFIG_WATCHDOG /* disable watchdog */ - -/* Configuration for environment - * Environment is embedded in u-boot in the second sector of the flash - */ -#ifndef CONFIG_MONITOR_IS_IN_RAM -#define CONFIG_ENV_OFFSET 0x4000 -#else -#define CONFIG_ENV_ADDR 0xffe04000 -#endif -#define CONFIG_ENV_SECT_SIZE 0x2000 -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_PING -#define CONFIG_CMD_NET -#define CONFIG_CMD_MII -#define CONFIG_CMD_ELF -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_MISC - -#undef CONFIG_CMD_LOADS -#define CONFIG_CMD_LOADB -#define CONFIG_CMDLINE_EDITING 1 /* enables command line history */ -#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */ - -#define CONFIG_MCFFEC -#ifdef CONFIG_MCFFEC -# define CONFIG_MII 1 -# define CONFIG_MII_INIT 1 -# define CONFIG_SYS_DISCOVER_PHY -# define CONFIG_SYS_RX_ETH_BUFFER 8 -# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN - -# define CONFIG_SYS_FEC0_PINMUX 0 -# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE -# define MCFFEC_TOUT_LOOP 50000 -/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ -# ifndef CONFIG_SYS_DISCOVER_PHY -# define FECDUPLEX FULL -# define FECSPEED _100BASET -# else -# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN -# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN -# endif -# endif /* CONFIG_SYS_DISCOVER_PHY */ -#endif - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 80000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300 -#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR - -#define CONFIG_BOOTDELAY 1 /* autoboot after 1 seconds */ -#define CONFIG_BOOTFILE "u-boot.bin" -#ifdef CONFIG_MCFFEC -# define CONFIG_NET_RETRY_COUNT 5 -# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 -# define CONFIG_IPADDR 192.162.1.2 -# define CONFIG_NETMASK 255.255.255.0 -# define CONFIG_SERVERIP 192.162.1.1 -# define CONFIG_GATEWAYIP 192.162.1.1 -# define CONFIG_OVERWRITE_ETHADDR_ONCE -#endif /* FEC_ENET */ - -#define CONFIG_HOSTNAME M5271EVB -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "loadaddr=10000\0" \ - "uboot=u-boot.bin\0" \ - "load=tftp $loadaddr $uboot\0" \ - "upd=run load; run prog\0" \ - "prog=prot off ffe00000 ffe3ffff;" \ - "era ffe00000 ffe3ffff;" \ - "cp.b $loadaddr ffe00000 $filesize;" \ - "save\0" \ - "" - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_LOAD_ADDR 0x00100000 - -#define CONFIG_SYS_MEMTEST_START 0x400 -#define CONFIG_SYS_MEMTEST_END 0x380000 - -#define CONFIG_SYS_HZ 1000000 - -/* Clock configuration - * The external oscillator is a 25.000 MHz - * CONFIG_SYS_CLK for ColdFire V2 sets cpu_clk (not bus_clk) - * bus_clk = (cpu_clk/2) (fixed ratio) - * - * If CONFIG_SYS_CLK is changed. the CONFIG_SYS_MCF_SYNCR must be updated to - * match the new clock speed. Max cpu_clk is 150 MHz. - */ -#define CONFIG_SYS_CLK 100000000 -#define CONFIG_SYS_MCF_SYNCR (MCF_SYNCR_MFD_4X | MCF_SYNCR_RFD_DIV1) - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -#define CONFIG_SYS_MBAR 0x40000000 /* Register Base Addrs */ - -/* - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ -#define CONFIG_SYS_FLASH_BASE 0xffe00000 - -#ifdef CONFIG_MONITOR_IS_IN_RAM -#define CONFIG_SYS_MONITOR_BASE 0x20000 -#else -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) -#endif - -#define CONFIG_SYS_MONITOR_LEN 0x40000 -#define CONFIG_SYS_MALLOC_LEN (256 << 10) -#define CONFIG_SYS_BOOTPARAMS_LEN (64*1024) - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization ?? - */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) - -/* FLASH organization */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max number of sectors on one chip */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 1000 - -#define CONFIG_SYS_FLASH_CFI 1 -#define CONFIG_FLASH_CFI_DRIVER 1 -#define CONFIG_SYS_FLASH_SIZE 0x200000 - -/* Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 16 - -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ - CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ - CF_CACR_DISD | CF_CACR_INVI | \ - CF_CACR_CEIB | CF_CACR_DCM | \ - CF_CACR_EUSP) - -/* Chip Select 0 : Boot Flash */ -#define CONFIG_SYS_CS0_BASE 0xFFE00000 -#define CONFIG_SYS_CS0_MASK 0x001F0001 -#define CONFIG_SYS_CS0_CTRL 0x00001980 - -/* Chip Select 1 : External SRAM */ -#define CONFIG_SYS_CS1_BASE 0x30000000 -#define CONFIG_SYS_CS1_MASK 0x00070001 -#define CONFIG_SYS_CS1_CTRL 0x00001900 - -#endif /* _M5271EVB_H */ diff --git a/include/configs/idmr.h b/include/configs/idmr.h deleted file mode 100644 index b882cf0..0000000 --- a/include/configs/idmr.h +++ /dev/null @@ -1,240 +0,0 @@ -/* - * Configuration settings for the iDMR board - * - * Based on MC5272C3, r5200 and M5271EVB board configs - * (C) Copyright 2006 Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. - * (C) Copyright 2006 Lab X Technologies <zachary.landau(a)labxtechnologies.com> - * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner(a)telex.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _IDMR_H -#define _IDMR_H - - -/* - * High Level Configuration Options (easy to change) - */ - -#define CONFIG_MCF52x2 /* define processor family */ -#define CONFIG_M5271 /* define processor type */ -#define CONFIG_IDMR /* define board type */ - -#undef CONFIG_WATCHDOG /* disable watchdog */ - -/* - * Default environment settings - */ -#define CONFIG_BOOTCOMMAND "run net_nfs" -#define CONFIG_BOOTDELAY 5 -#define CONFIG_MCFUART -#define CONFIG_SYS_UART_PORT (0) -#define CONFIG_BAUDRATE 19200 -#define CONFIG_ETHADDR 00:06:3b:01:41:55 -#define CONFIG_ETHPRIME -#define CONFIG_IPADDR 192.168.30.1 -#define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_ROOTPATH "" -#define CONFIG_GATEWAYIP 192.168.1.1 -#define CONFIG_NETMASK 255.255.0.0 -#define CONFIG_HOSTNAME idmr -#define CONFIG_BOOTFILE "/tftpboot/idmr/uImage" -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root " \ - "filesystem over NFS; echo" - -#define CONFIG_MCFTMR - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):" \ - "$(netmask):$(hostname):$(netdev):off panic=1\0" \ - "flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \ - "flash_self=run ramargs addip;bootm $(kernel_addr) " \ - "$(ramdisk_addr)\0" \ - "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ - "ethact=FEC\0 " \ - "update=prot off ff800000 ff81ffff; era ff800000 ff81ffff; " \ - "cp.b 200000 ff800000 $(filesize);" \ - "prot on ff800000 ff81ffff\0" \ - "load=tftp 200000 $(u-boot)\0" \ - "u-boot=/tftpboot/idmr/u-boot.bin\0" \ - "" - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_PING -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_NET - -#undef CONFIG_CMD_LOADS -#undef CONFIG_CMD_LOADB - - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/* - * Configuration for environment, which occupies third sector in flash. - */ -#ifndef CONFIG_MONITOR_IS_IN_RAM -#define CONFIG_ENV_ADDR 0xff820000 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_IS_IN_FLASH -#else /* CONFIG_MONITOR_IS_IN_RAM */ -#define CONFIG_ENV_OFFSET 0x4000 -#define CONFIG_ENV_SECT_SIZE 0x2000 -#define CONFIG_ENV_IS_IN_FLASH -#endif /* !CONFIG_MONITOR_IS_IN_RAM */ - -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_LOAD_ADDR 0x00100000 - -#define CONFIG_SYS_MEMTEST_START 0x400 -#define CONFIG_SYS_MEMTEST_END 0x380000 - -#define CONFIG_SYS_HZ (50000000 / 64) -#define CONFIG_SYS_CLK 100000000 - -#define CONFIG_SYS_MBAR 0x40000000 /* Register Base Addrs */ - -/* - * Ethernet - */ -#define CONFIG_MCFFEC -#ifdef CONFIG_MCFFEC -# define CONFIG_MII 1 -# define CONFIG_MII_INIT 1 -# define CONFIG_SYS_DISCOVER_PHY -# define CONFIG_SYS_RX_ETH_BUFFER 8 -# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN - -# define CONFIG_SYS_FEC0_PINMUX 0 -# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE -# define MCFFEC_TOUT_LOOP 50000 -/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ -# ifndef CONFIG_SYS_DISCOVER_PHY -# define FECDUPLEX FULL -# define FECSPEED _100BASET -# else -# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN -# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN -# endif -# endif /* CONFIG_SYS_DISCOVER_PHY */ -#endif - -/* - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ -#define CONFIG_SYS_FLASH_BASE 0xff800000 - -#ifdef CONFIG_MONITOR_IS_IN_RAM -#define CONFIG_SYS_MONITOR_BASE 0x20000 -#else /* !CONFIG_MONITOR_IS_IN_RAM */ -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) -#endif /* CONFIG_MONITOR_IS_IN_RAM */ - -#define CONFIG_SYS_MONITOR_LEN 0x20000 -#define CONFIG_SYS_MALLOC_LEN (256 << 10) -#define CONFIG_SYS_BOOTPARAMS_LEN (64*1024) - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization ?? - */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) - -/* FLASH organization */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 1000 - -#define CONFIG_SYS_FLASH_SIZE 0x800000 -/* - * #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 - */ - -/* Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 16 - -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ - CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ - CF_CACR_DISD | CF_CACR_INVI | \ - CF_CACR_CEIB | CF_CACR_DCM | \ - CF_CACR_EUSP) - -/* Port configuration */ -#define CONFIG_SYS_FECI2C 0xF0 - - -/* Dynamic MTD partition support */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=idmr-0" - -#define MTDPARTS_DEFAULT "mtdparts=idmr-0:128k(u-boot)," \ - "64k(env)," \ - "640k(kernel)," \ - "2m(rootfs)," \ - "-(user)"; - -#if defined(CONFIG_CMD_MII) -#error "MII commands don't work on iDMR board and should not be enabled." -#endif - -#endif /* _IDMR_H */ -- 1.8.3.2

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[U-Boot] Pull request: u-boot-arm/master
by Albert ARIBAUD 10 Mar '14

10 Mar '14

Hi Tom, The following changes since commit eeb72e67619b98d2502fe634a3a5d9953de92ad0: Merge branch 'master' of git://git.denx.de/u-boot-arm (2014-02-26 16:49:58 -0500) are available in the git repository at: git://git.denx.de/u-boot-arm master for you to fetch changes up to 27019e4a949fc3be2e895ac20839c4d4d119f902: arm: atmel: sama5d3: add nand spl boot support (2014-03-09 19:19:13 +0100) ---------------------------------------------------------------- Albert ARIBAUD (1): Merge branch 'u-boot-tegra/master' into 'u-boot-arm/master' Andreas Henriksson (2): at91sam9263ek: add mmc support at91 gpio: fix typo in compatibility macro Bo Shen (4): ARM: atmel: add sama5d3 Xplained board support arm: atmel: sama5d3: add spi spl boot support mtd: nand: atmel: prepare for nand spl boot support arm: atmel: sama5d3: add nand spl boot support Dave Gerlach (3): ARM: AM43xx: EMIF: configure self-refresh entry delay ARM: AM43xx: Write sdram_config to secure_emif_sdram_config ARM: AM43xx: Change DDR3 Reset Value Enric Balletbo i Serra (1): OMAP3: igep00x0: Enable required clocks for GPIO that are used. Hannes Petermaier (1): board/BuR/common: fix phy addresses Lokesh Vutla (1): ARM: AM4372: Update EMIF registers for DDR3 Mugunthan V N (6): drivers: net: cpsw: add support to have phy address from cpsw platform data ARM: AM43xx: clocks: Enable CPGMAC clock control ARM: AM43xx: Add CPSW support to AM43xx EPOS and GP EVM ARM: AM335x: add support for reading cpsw 2nd mac address from efuse ARM: DRA7xx: add support for reading cpsw 2nd mac from efuse ARM: AM43xx: Add Ethernet boot support to SPL Stefan Roese (1): arm: am335x: DXR2: Reset SMSC LAN9303 switch via GPIO upon bootup Stephen Warren (8): ARM: tegra: move CONFIG_TEGRAnn ARM: tegra: fix pmc_pwrgate_timer_mult register definition ARM: tegra: fix NV_PA_CSITE_BASE for Tegra124 ARM: tegra: simplify halt_avp() ARM: tegra: set CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS ARM: tegra: convert tegra to use distro defaults ARM: tegra: rework boot scripts ARM: tegra: implement bootcmd_pxe arch/arm/cpu/arm720t/tegra-common/cpu.c | 5 ++- arch/arm/cpu/arm720t/tegra124/cpu.c | 4 +-- arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c | 25 ++++++++++++++ arch/arm/cpu/armv7/am33xx/clock_am43xx.c | 1 + arch/arm/cpu/armv7/am33xx/ddr.c | 5 +-- arch/arm/cpu/armv7/am33xx/emif4.c | 2 +- arch/arm/cpu/at91-common/spl.c | 4 +++ arch/arm/include/asm/arch-at91/gpio.h | 2 +- arch/arm/include/asm/arch-at91/spl.h | 4 +++ arch/arm/include/asm/arch-tegra/pmc.h | 11 +++++++ arch/arm/include/asm/arch-tegra/tegra.h | 5 +++ arch/arm/include/asm/arch-tegra114/tegra.h | 2 ++ arch/arm/include/asm/arch-tegra124/tegra.h | 2 ++ arch/arm/include/asm/arch-tegra20/tegra.h | 2 ++ arch/arm/include/asm/arch-tegra30/tegra.h | 2 ++ board/BuR/common/common.c | 4 +-- board/atmel/at91sam9263ek/at91sam9263ek.c | 10 ++++++ board/atmel/sama5d3_xplained/Makefile | 15 +++++++++ board/atmel/sama5d3_xplained/sama5d3_xplained.c | 130 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ board/atmel/sama5d3xek/sama5d3xek.c | 4 +++ board/compulab/cm_t335/cm_t335.c | 2 +- board/isee/igep0033/board.c | 2 +- board/phytec/pcm051/board.c | 4 +-- board/siemens/dxr2/board.c | 9 ++++- board/siemens/dxr2/mux.c | 2 ++ board/siemens/pxm2/board.c | 4 +-- board/siemens/rut/board.c | 4 +-- board/silica/pengwyn/board.c | 4 +-- board/ti/am335x/board.c | 19 +++++++++-- board/ti/am43xx/board.c | 100 ++++++++++++++++++++++++++++++++++++++++++++++++++++++- board/ti/am43xx/mux.c | 44 +++++++++++++++++++++++-- board/ti/dra7xx/evm.c | 19 +++++++++-- board/ti/ti814x/evm.c | 4 +-- boards.cfg | 2 ++ drivers/mtd/nand/atmel_nand.c | 208 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ drivers/net/cpsw.c | 4 +-- include/configs/am335x_evm.h | 1 - include/configs/am335x_igep0033.h | 1 - include/configs/am43xx_evm.h | 26 +++++++++++++++ include/configs/at91sam9263ek.h | 13 ++++++++ include/configs/bur_am335x_common.h | 1 - include/configs/cm_t335.h | 1 - include/configs/dra7xx_evm.h | 1 - include/configs/dxr2.h | 2 +- include/configs/omap3_igep00x0.h | 5 +++ include/configs/pcm051.h | 1 - include/configs/pengwyn.h | 1 - include/configs/pxm2.h | 1 - include/configs/rut.h | 1 - include/configs/sama5d3_xplained.h | 203 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ include/configs/sama5d3xek.h | 23 +++++++++++++ include/configs/tegra-common-post.h | 57 ++++++++++++++++++++++++++------ include/configs/tegra-common.h | 20 +++-------- include/configs/tegra114-common.h | 10 +++--- include/configs/tegra124-common.h | 6 +--- include/configs/tegra20-common.h | 10 +++--- include/configs/tegra30-common.h | 10 +++--- include/configs/ti814x_evm.h | 1 - include/configs/ti_am335x_common.h | 1 + include/cpsw.h | 2 +- include/nand.h | 6 ++++ 61 files changed, 983 insertions(+), 91 deletions(-) create mode 100644 board/atmel/sama5d3_xplained/Makefile create mode 100644 board/atmel/sama5d3_xplained/sama5d3_xplained.c create mode 100644 include/configs/sama5d3_xplained.h Amicalement, -- Albert.

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[U-Boot] [PULL] u-boot-usb/master
by Marek Vasut 10 Mar '14

10 Mar '14

The following changes since commit 247161b8160fc699b0a517f081220bb50bc502a8: Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx (2014-03-07 20:54:22 -0500) are available in the git repository at: git://git.denx.de/u-boot-usb.git master for you to fetch changes up to eb838e7d84a5211ccca0662297b4dfd1cc29e9df: usb: create common header virtual root hub descriptors (2014-03-10 18:53:36 +0100) ---------------------------------------------------------------- Stephen Warren (3): ush: ehci: initialize altnext pointers in QH usb: ehci: fully align interrupt QHs/QTDs usb: create common header virtual root hub descriptors arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.c | 99 +--------------------------------------------------------------------- arch/powerpc/cpu/mpc5xxx/usb_ohci.c | 99 +--------------------------------------------------------------------- arch/powerpc/cpu/ppc4xx/usb_ohci.c | 99 +--------------------------------------------------------------------- arch/sparc/cpu/leon3/usb_uhci.c | 107 +++------------------------------------------------------------------------- board/mpl/common/usb_uhci.c | 115 +++------------------------------------------------------------------------------- drivers/usb/host/ehci-hcd.c | 8 ++++-- drivers/usb/host/isp116x-hcd.c | 100 +---------------------------------------------------------------------- drivers/usb/host/ohci-hcd.c | 98 +--------------------------------------------------------------------- drivers/usb/host/ohci-s3c24xx.c | 95 +------------------------------------------------------------------- drivers/usb/host/r8a66597-hcd.c | 104 +------------------------------------------------------------------------- drivers/usb/musb/musb_hcd.c | 93 +----------------------------------------------------------------- include/usbroothubdes.h | 129 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 12 files changed, 149 insertions(+), 997 deletions(-) create mode 100644 include/usbroothubdes.h

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[U-Boot] omap24xx_i2c: i2c 16-bit write to pcf8575
by Richard Retanubun 10 Mar '14

10 Mar '14

Hello, My platform is a dra7xx_evm. My code baseline is denx master I am trying to write to the pcf8575 i2c gpio expander at address 0x21 (bit P4) I can read 16-bit okay in this version, but 16-bit writing is not working. // Display current values i2c md 21 0.0 2 0000: f7 eb .. // Set bit P4 to 1 i2c mw 21 0.0 0xffeb 2 // But it remains at 0xf7 i2c md 21 0.0 2 0000: f7 eb .. When we put scopes on the i2c lines, it seems that the i2c mw transaction produces a longer i2c bus sequence that does not map to the [Start:Addr:W:A:P7-P0:A:P17-P10:A:Stop] that the pcf8575 device expects. Either I am invoking "i2c mw" incorrectly, or the oma24xx_i2c driver is not handling i2c 16-bit writes correctly yet. Any hints will be appreciated. Thanks for everyone's time -- Richard Retanubun

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[U-Boot] [PATCH] fsl_i2c: Add write-then-read transaction interface for I2C slave
by Shaveta Leekha 10 Mar '14

10 Mar '14

Most of the I2C slaves support accesses in the typical style viz.read/write series of bytes at particular address offset. These transactions are currently supportd in the i2c driver using i2c_read and i2c_write APIs. I2C EEPROMs, RTC, etc fall in this category. The transactions look like:" START:Address:Tx:Offset:RESTART:Address[0..4]:Tx/Rx:data[0..n]:STOP" However there are certain devices which support accesses in terms of the transactions as follows: "START:Address:Tx:Txdata[0..n1]:Clock_stretching: RESTART:Address:Rx:data[0..n2]" The Txdata is typically a command and some associated data, similarly Rxdata could be command status plus some data received as a response to the command sent. i2c_write_read() function provides support for such transactions (multiple bytes write followed by read) Signed-off-by: Poonam Aggrwal <poonam.aggrwal(a)freescale.com> Signed-off-by: Shaveta Leekha <shaveta(a)freescale.com> --- drivers/i2c/fsl_i2c.c | 64 ++++++++++++++++++++++++++++++++++++++++++----- drivers/i2c/i2c_core.c | 7 +++++ include/i2c.h | 19 ++++++++++--- 3 files changed, 78 insertions(+), 12 deletions(-) diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c index 291ad94..838c1b1 100644 --- a/drivers/i2c/fsl_i2c.c +++ b/drivers/i2c/fsl_i2c.c @@ -472,6 +472,56 @@ fsl_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr, int alen, return -1; } +/* To perform any generic transaction on a I2C slave which involves + + START: Address: Write bytes(cmd + data): clock extension: + RESTART: Address: Read bytes (data + status): STOP + + This is different from standard I2C devices which are supported + in existing i2c_read and i2c_write functions. + */ +int +fsl_i2c_write_read(struct i2c_adapter *adap, u8 dev, u8 *wdata, int wlength, + u8 *rdata, int rlength) +{ + struct fsl_i2c *device = (struct fsl_i2c *)i2c_dev[adap->hwadapnr]; + + int i = -1; /* signal error */ + + if (i2c_wait4bus(adap)) + return -1; + +/* Generate a START and send the Address and the Tx Bytes to the slave. + * "START: Address: Write bytes wdata[wlength]" + */ + if (i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0) + i = __i2c_write(adap, wdata, wlength); + + if (i != wlength) + return -1; + +/* Now issue a READ by generating a RESTART condition + * "RESTART: Address: Read bytes rdata[rlength]" + * Some slaves may also do clock stretching and keep the SCL low until + * they finish some command processing at their end. The I2C controller + * will wait for the clock stretching period to get over before generating + * the RESTART condition on the bus. + */ + if (rlength + && i2c_write_addr(adap, dev, I2C_READ_BIT, 1) != 0) + i = __i2c_read(adap, rdata, rlength); + +/* Generate STOP */ + writeb(I2C_CR_MEN, &device->cr); + + if (i2c_wait4bus(adap)) /* Wait until STOP */ + debug("i2c_write_read: wait4bus timed out\n"); + + if (i != rlength) + return -1; + + return 0; +} static int fsl_i2c_probe(struct i2c_adapter *adap, uchar chip) @@ -503,12 +553,12 @@ static unsigned int fsl_i2c_set_bus_speed(struct i2c_adapter *adap, * Register fsl i2c adapters */ U_BOOT_I2C_ADAP_COMPLETE(fsl_0, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read, - fsl_i2c_write, fsl_i2c_set_bus_speed, - CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE, - 0) -#ifdef CONFIG_SYS_FSL_I2C2_OFFSET + fsl_i2c_write, fsl_i2c_write_read, + fsl_i2c_set_bus_speed, CONFIG_SYS_FSL_I2C_SPEED, + CONFIG_SYS_FSL_I2C_SLAVE, 0); +#ifdef CONFIG_SYS_I2C2_OFFSET U_BOOT_I2C_ADAP_COMPLETE(fsl_1, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read, - fsl_i2c_write, fsl_i2c_set_bus_speed, - CONFIG_SYS_FSL_I2C2_SPEED, CONFIG_SYS_FSL_I2C2_SLAVE, - 1) + fsl_i2c_write, fsl_i2c_write_read, + fsl_i2c_set_bus_speed, CONFIG_SYS_FSL_I2C2_SPEED, + CONFIG_SYS_FSL_I2C2_SLAVE, 1); #endif diff --git a/drivers/i2c/i2c_core.c b/drivers/i2c/i2c_core.c index 18d6736..6647856 100644 --- a/drivers/i2c/i2c_core.c +++ b/drivers/i2c/i2c_core.c @@ -341,6 +341,13 @@ int i2c_write(uint8_t chip, unsigned int addr, int alen, return I2C_ADAP->write(I2C_ADAP, chip, addr, alen, buffer, len); } +int i2c_write_read(uchar chip, uint8_t *wbuffer, int wlen, uint8_t *rbuffer, + int rlen) +{ + return I2C_ADAP->write_read(I2C_ADAP, chip, wbuffer, wlen, + rbuffer, rlen); +} + unsigned int i2c_set_bus_speed(unsigned int speed) { unsigned int ret; diff --git a/include/i2c.h b/include/i2c.h index 1b4078e..7bac20a 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -65,6 +65,9 @@ struct i2c_adapter { int (*write)(struct i2c_adapter *adap, uint8_t chip, uint addr, int alen, uint8_t *buffer, int len); + int (*write_read)(struct i2c_adapter *adap, uint8_t chip, + uint8_t *wbuffer, int wlength, uint8_t *rbuffer, + int rlength); uint (*set_bus_speed)(struct i2c_adapter *adap, uint speed); int speed; @@ -75,13 +78,14 @@ struct i2c_adapter { char *name; }; -#define U_BOOT_I2C_MKENT_COMPLETE(_init, _probe, _read, _write, \ +#define U_BOOT_I2C_MKENT_COMPLETE(_init, _probe, _read, _write, _write_read, \ _set_speed, _speed, _slaveaddr, _hwadapnr, _name) \ { \ .init = _init, \ .probe = _probe, \ .read = _read, \ .write = _write, \ + .write_read = _write_read, \ .set_bus_speed = _set_speed, \ .speed = _speed, \ .slaveaddr = _slaveaddr, \ @@ -90,10 +94,11 @@ struct i2c_adapter { .name = #_name \ }; -#define U_BOOT_I2C_ADAP_COMPLETE(_name, _init, _probe, _read, _write, \ - _set_speed, _speed, _slaveaddr, _hwadapnr) \ - ll_entry_declare(struct i2c_adapter, _name, i2c) = \ - U_BOOT_I2C_MKENT_COMPLETE(_init, _probe, _read, _write, \ +#define U_BOOT_I2C_ADAP_COMPLETE(_name, _init, _probe, _read, _write, \ + _write_read, _set_speed, _speed, _slaveaddr, \ + _hwadapnr) \ + ll_entry_declare(struct i2c_adapter, _name, i2c) = \ + U_BOOT_I2C_MKENT_COMPLETE(_init, _probe, _read, _write, _write_read, \ _set_speed, _speed, _slaveaddr, _hwadapnr, _name); struct i2c_adapter *i2c_get_adapter(int index); @@ -237,6 +242,8 @@ int i2c_read(uint8_t chip, unsigned int addr, int alen, int i2c_write(uint8_t chip, unsigned int addr, int alen, uint8_t *buffer, int len); +int i2c_write_read(uint8_t chip, uchar *wbuffer, int wlen, uchar *rbuffer, + int rlen); /* * Utility routines to read/write registers. @@ -302,6 +309,8 @@ int i2c_probe(uchar chip); */ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len); int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len); +int i2c_write_read(uchar chip, uchar *wbuffer, int wlen, uchar *rbuffer, + int rlen); /* * Utility routines to read/write registers. -- 1.7.6.GIT

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[U-Boot] [PULL] u-boot-atmel/master -> u-boot-arm/master
by Andreas Bießmann 10 Mar '14

10 Mar '14

Dear Albert Aribaud, please pull the following changes from u-boot-atmel/master into u-boot-arm/master. The following changes since commit de4fdfc1f22d70c23be5443dafacb8163023f9b1: Merge branch 'u-boot-tegra/master' into 'u-boot-arm/master' (2014-03-07 14:32:42 +0100) are available in the git repository at: git://git.denx.de/u-boot-atmel.git master for you to fetch changes up to 27019e4a949fc3be2e895ac20839c4d4d119f902: arm: atmel: sama5d3: add nand spl boot support (2014-03-09 19:19:13 +0100) ---------------------------------------------------------------- Andreas Henriksson (2): at91sam9263ek: add mmc support at91 gpio: fix typo in compatibility macro Bo Shen (4): ARM: atmel: add sama5d3 Xplained board support arm: atmel: sama5d3: add spi spl boot support mtd: nand: atmel: prepare for nand spl boot support arm: atmel: sama5d3: add nand spl boot support arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c | 25 +++ arch/arm/cpu/at91-common/spl.c | 4 + arch/arm/include/asm/arch-at91/gpio.h | 2 +- arch/arm/include/asm/arch-at91/spl.h | 4 + board/atmel/at91sam9263ek/at91sam9263ek.c | 10 + board/atmel/sama5d3_xplained/Makefile | 15 ++ board/atmel/sama5d3_xplained/sama5d3_xplained.c | 130 +++++++++++++ board/atmel/sama5d3xek/sama5d3xek.c | 4 + boards.cfg | 2 + drivers/mtd/nand/atmel_nand.c | 208 +++++++++++++++++++++ include/configs/at91sam9263ek.h | 13 ++ include/configs/sama5d3_xplained.h | 203 ++++++++++++++++++++ include/configs/sama5d3xek.h | 23 +++ include/nand.h | 6 + 14 files changed, 648 insertions(+), 1 deletion(-) create mode 100644 board/atmel/sama5d3_xplained/Makefile create mode 100644 board/atmel/sama5d3_xplained/sama5d3_xplained.c create mode 100644 include/configs/sama5d3_xplained.h

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[U-Boot] [PATCH v5 1/2] QE/FMAN: modify CONFIG_SYS_QE_FMAN_FW_ADDR to CONFIG_SYS_FMAN_FW_ADDR and CONFIG_SYS_QE_FW_ADDR
by Zhao Qiang 10 Mar '14

10 Mar '14

CONFIG_SYS_QE_FMAN_FW_ADDR is used to both Fman and QE for microcode address. Now using CONFIG_SYS_FMAN_FW_ADDR for Fman microcode address, and CONFIG_SYS_QE_FW_ADDR for QE microcode address. Signed-off-by: Zhao Qiang <B45475(a)freescale.com> --- Changes for v2: - no Changes for v3: - no Changes for v4: - no Changes for v5: - modify CONFIG_SYS_QE_FW_ADDR to CONFIG_SYS_FMAN_FW_ADDR for kmp204x README | 9 +++++++-- arch/powerpc/cpu/mpc85xx/cpu_init.c | 2 +- drivers/net/fm/fm.c | 12 ++++++------ drivers/qe/qe.c | 2 +- include/configs/B4860QDS.h | 10 +++++----- include/configs/MPC8569MDS.h | 2 +- include/configs/P1023RDB.h | 2 +- include/configs/P1023RDS.h | 4 ++-- include/configs/P2041RDB.h | 10 +++++----- include/configs/T1040QDS.h | 8 ++++---- include/configs/T1040RDB.h | 8 ++++---- include/configs/T1042RDB_PI.h | 8 ++++---- include/configs/T2080QDS.h | 10 +++++----- include/configs/T4240EMU.h | 2 +- include/configs/T4240QDS.h | 10 +++++----- include/configs/corenet_ds.h | 10 +++++----- include/configs/km/km8309-common.h | 2 +- include/configs/km/kmp204x-common.h | 2 +- include/configs/p1_p2_rdb_pc.h | 2 +- include/configs/p1_twr.h | 2 +- 20 files changed, 61 insertions(+), 56 deletions(-) diff --git a/README b/README index 176de61..b2b2d73 100644 --- a/README +++ b/README @@ -4445,8 +4445,13 @@ This firmware often needs to be loaded during U-Boot booting, so macros are used to identify the storage device (NOR flash, SPI, etc) and the address within that device. -- CONFIG_SYS_QE_FMAN_FW_ADDR - The address in the storage device where the firmware is located. The +- CONFIG_SYS_FMAN_FW_ADDR + The address in the storage device where the FMAN microcode is located. The + meaning of this address depends on which CONFIG_SYS_QE_FW_IN_xxx macro + is also specified. + +- CONFIG_SYS_QE_FW_ADDR + The address in the storage device where the QE microcode is located. The meaning of this address depends on which CONFIG_SYS_QE_FW_IN_xxx macro is also specified. diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index b31efb7..ec6eefb 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -743,7 +743,7 @@ void cpu_secondary_init_r(void) /* load QE firmware from NAND flash to DDR first */ ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_IN_NAND, - &fw_length, (u_char *)CONFIG_SYS_QE_FMAN_FW_ADDR); + &fw_length, (u_char *)CONFIG_SYS_QE_FW_ADDR); if (ret && ret == -EUCLEAN) { printf ("NAND read for QE firmware at offset %x failed %d\n", diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c index bca20b3..400e9dd 100644 --- a/drivers/net/fm/fm.c +++ b/drivers/net/fm/fm.c @@ -350,16 +350,16 @@ int fm_init_common(int index, struct ccsr_fman *reg) { int rc; #if defined(CONFIG_SYS_QE_FMAN_FW_IN_NOR) - void *addr = (void *)CONFIG_SYS_QE_FMAN_FW_ADDR; + void *addr = (void *)CONFIG_SYS_FMAN_FW_ADDR; #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_NAND) size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH; void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH); - rc = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_ADDR, + rc = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_FMAN_FW_ADDR, &fw_length, (u_char *)addr); if (rc == -EUCLEAN) { printf("NAND read of FMAN firmware at offset 0x%x failed %d\n", - CONFIG_SYS_QE_FMAN_FW_ADDR, rc); + CONFIG_SYS_FMAN_FW_ADDR, rc); } #elif defined(CONFIG_SYS_QE_FW_IN_SPIFLASH) struct spi_flash *ucode_flash; @@ -371,7 +371,7 @@ int fm_init_common(int index, struct ccsr_fman *reg) if (!ucode_flash) printf("SF: probe for ucode failed\n"); else { - ret = spi_flash_read(ucode_flash, CONFIG_SYS_QE_FMAN_FW_ADDR, + ret = spi_flash_read(ucode_flash, CONFIG_SYS_FMAN_FW_ADDR, CONFIG_SYS_QE_FMAN_FW_LENGTH, addr); if (ret) printf("SF: read for ucode failed\n"); @@ -381,7 +381,7 @@ int fm_init_common(int index, struct ccsr_fman *reg) int dev = CONFIG_SYS_MMC_ENV_DEV; void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH); u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512; - u32 blk = CONFIG_SYS_QE_FMAN_FW_ADDR / 512; + u32 blk = CONFIG_SYS_FMAN_FW_ADDR / 512; struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV); if (!mmc) @@ -395,7 +395,7 @@ int fm_init_common(int index, struct ccsr_fman *reg) flush_cache((ulong)addr, cnt * 512); } #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_REMOTE) - void *addr = (void *)CONFIG_SYS_QE_FMAN_FW_ADDR; + void *addr = (void *)CONFIG_SYS_FMAN_FW_ADDR; #else void *addr = NULL; #endif diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index b5ddc4b..b1da75e 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -165,7 +165,7 @@ void qe_init(uint qe_base) /* * Upload microcode to IRAM for those SOCs which do not have ROM in QE. */ - qe_upload_firmware((const void *)CONFIG_SYS_QE_FMAN_FW_ADDR); + qe_upload_firmware((const void *)CONFIG_SYS_QE_FW_ADDR); /* enable the microcode in IRAM */ out_be32(&qe_immr->iram.iready,QE_IRAM_READY); diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index 39c0b6d..d4d606f 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -597,7 +597,7 @@ unsigned long get_board_ddr_clk(void); * env, so we got 0x110000. */ #define CONFIG_SYS_QE_FW_IN_SPIFLASH -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 +#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 #elif defined(CONFIG_SDCARD) /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is @@ -605,10 +605,10 @@ unsigned long get_board_ddr_clk(void); * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC -#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_QE_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) /* * Slave has no ucode locally, it can fetch this from remote. When implementing @@ -618,10 +618,10 @@ unsigned long get_board_ddr_clk(void); * master LAW->the ucode address in master's memory space. */ #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index d877e8b..5208069 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -494,7 +494,7 @@ extern unsigned long get_clock_freq(void); /* QE microcode/firmware address */ #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xfff00000 +#define CONFIG_SYS_QE_FW_ADDR 0xfff00000 /* * BOOTP options diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h index 78a0aa2..7c83362 100644 --- a/include/configs/P1023RDB.h +++ b/include/configs/P1023RDB.h @@ -361,7 +361,7 @@ extern unsigned long get_clock_freq(void); /* Default address of microcode for the Linux Fman driver */ /* QE microcode/firmware address */ #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) diff --git a/include/configs/P1023RDS.h b/include/configs/P1023RDS.h index d2aaf98..5d015e0 100644 --- a/include/configs/P1023RDS.h +++ b/include/configs/P1023RDS.h @@ -502,10 +502,10 @@ extern unsigned long get_clock_freq(void); /* Default address of microcode for the Linux Fman driver */ /* QE microcode/firmware address */ #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 #else #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x1f00000 +#define CONFIG_SYS_FMAN_FW_ADDR 0x1f00000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 6934c61..a02e438 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -508,7 +508,7 @@ unsigned long get_board_sys_clk(unsigned long dummy); * env, so we got 0x110000. */ #define CONFIG_SYS_QE_FW_IN_SPIFLASH -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 +#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 #elif defined(CONFIG_SDCARD) /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is @@ -516,10 +516,10 @@ unsigned long get_board_sys_clk(unsigned long dummy); * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC -#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680) +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_QE_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) /* * Slave has no ucode locally, it can fetch this from remote. When implementing @@ -529,10 +529,10 @@ unsigned long get_board_sys_clk(unsigned long dummy); * master LAW->the ucode address in master's memory space. */ #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 91b511b..0282922 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -579,7 +579,7 @@ unsigned long get_board_ddr_clk(void); * env, so we got 0x110000. */ #define CONFIG_SYS_QE_FW_IN_SPIFLASH -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 +#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 #elif defined(CONFIG_SDCARD) /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is @@ -587,13 +587,13 @@ unsigned long get_board_ddr_clk(void); * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC -#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680) +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_QE_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) diff --git a/include/configs/T1040RDB.h b/include/configs/T1040RDB.h index 65b4b26..1ca1a1a 100644 --- a/include/configs/T1040RDB.h +++ b/include/configs/T1040RDB.h @@ -517,7 +517,7 @@ * env, so we got 0x110000. */ #define CONFIG_SYS_QE_FW_IN_SPIFLASH -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 +#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 #elif defined(CONFIG_SDCARD) /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is @@ -525,13 +525,13 @@ * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC -#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680) +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_QE_FMAN_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_FMAN_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) diff --git a/include/configs/T1042RDB_PI.h b/include/configs/T1042RDB_PI.h index 104bb92..5b248e4 100644 --- a/include/configs/T1042RDB_PI.h +++ b/include/configs/T1042RDB_PI.h @@ -525,7 +525,7 @@ * env, so we got 0x110000. */ #define CONFIG_SYS_QE_FW_IN_SPIFLASH -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 +#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 #elif defined(CONFIG_SDCARD) /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is @@ -533,13 +533,13 @@ * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC -#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680) +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_QE_FMAN_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_FMAN_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) diff --git a/include/configs/T2080QDS.h b/include/configs/T2080QDS.h index d6d1f93..26828e5 100644 --- a/include/configs/T2080QDS.h +++ b/include/configs/T2080QDS.h @@ -540,7 +540,7 @@ unsigned long get_board_ddr_clk(void); * env, so we got 0x110000. */ #define CONFIG_SYS_QE_FW_IN_SPIFLASH -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 +#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 #elif defined(CONFIG_SDCARD) /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is @@ -548,10 +548,10 @@ unsigned long get_board_ddr_clk(void); * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC -#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680) +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_QE_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) /* * Slave has no ucode locally, it can fetch this from remote. When implementing @@ -561,10 +561,10 @@ unsigned long get_board_ddr_clk(void); * master LAW->the ucode address in master's memory space. */ #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) diff --git a/include/configs/T4240EMU.h b/include/configs/T4240EMU.h index c81c457..ad5a9a6 100644 --- a/include/configs/T4240EMU.h +++ b/include/configs/T4240EMU.h @@ -98,7 +98,7 @@ #define CONFIG_SYS_INTERLAKEN #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h index 0d43c27..d88b3b5 100644 --- a/include/configs/T4240QDS.h +++ b/include/configs/T4240QDS.h @@ -375,7 +375,7 @@ unsigned long get_board_ddr_clk(void); * env, so we got 0x110000. */ #define CONFIG_SYS_QE_FW_IN_SPIFLASH -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 +#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 #elif defined(CONFIG_SDCARD) /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is @@ -383,10 +383,10 @@ unsigned long get_board_ddr_clk(void); * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC -#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680) +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_QE_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) /* * Slave has no ucode locally, it can fetch this from remote. When implementing @@ -396,10 +396,10 @@ unsigned long get_board_ddr_clk(void); * master LAW->the ucode address in master's memory space. */ #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index fa748f7..be00871 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -514,7 +514,7 @@ * env, so we got 0x110000. */ #define CONFIG_SYS_QE_FW_IN_SPIFLASH -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 +#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 #elif defined(CONFIG_SDCARD) /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is @@ -522,10 +522,10 @@ * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC -#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680) +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_QE_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) /* * Slave has no ucode locally, it can fetch this from remote. When implementing @@ -535,10 +535,10 @@ * master LAW->the ucode address in master's memory space. */ #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) diff --git a/include/configs/km/km8309-common.h b/include/configs/km/km8309-common.h index 47355ab..d27911f 100644 --- a/include/configs/km/km8309-common.h +++ b/include/configs/km/km8309-common.h @@ -28,7 +28,7 @@ /* QE microcode/firmware address */ #define CONFIG_SYS_QE_FMAN_FW_IN_NOR /* at end of uboot partition, before env */ -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xF00B0000 +#define CONFIG_SYS_QE_FW_ADDR 0xF00B0000 /* * System IO Config diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h index 0463fcb..c04aad6 100644 --- a/include/configs/km/kmp204x-common.h +++ b/include/configs/km/kmp204x-common.h @@ -334,7 +334,7 @@ unsigned long get_board_sys_clk(unsigned long dummy); * ucode is stored after env, so we got 0x120000. */ #define CONFIG_SYS_QE_FW_IN_SPIFLASH -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x120000 +#define CONFIG_SYS_FMAN_FW_ADDR 0x120000 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 95e23ac..93a0aa9 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -769,7 +769,7 @@ #ifdef CONFIG_QE /* QE microcode/firmware address */ #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xefec0000 +#define CONFIG_SYS_QE_FW_ADDR 0xefec0000 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #endif /* CONFIG_QE */ diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h index a7fe90f..f6b76b8 100644 --- a/include/configs/p1_twr.h +++ b/include/configs/p1_twr.h @@ -352,7 +352,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #ifdef CONFIG_QE /* QE microcode/firmware address */ #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xefec0000 +#define CONFIG_SYS_QE_FW_ADDR 0xefec0000 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #endif /* CONFIG_QE */ -- 1.8.5

1 1

[U-Boot] kbuild: wrong version_autogenerated.h
by Andreas Bießmann 10 Mar '14

10 Mar '14

Dear Masahiro Yamada, I noticed a wrongly generated version_autogenerated.h with my default workflow: ---8<--- andreas@andreas-pc % PATH=$AVR32_PATH:$PATH BUILD_NCPUS=2 BUILD_NBUILDS=6 CROSS_COMPILE=avr32-linux- MAKEALL_LOGDIR=/tmp/makeall_logs BUILD_DIR=/tmp/makeall_buildavr32 ./MAKEALL grasshopper Configuring for grasshopper board... text data bss dec hex filename 105427 9518 21388 136333 2148d /tmp/makeall_buildavr32/grasshopper/u-boot --------------------- SUMMARY ---------------------------- Boards compiled: 0 ---------------------------------------------------------- PATH=$AVR32_PATH:$PATH BUILD_NCPUS=2 BUILD_NBUILDS=6 CROSS_COMPILE= = = 10,69s user 2,68s system 198% cpu 6,740 total andreas@andreas-pc % cat /tmp/makeall_buildavr32/grasshopper/include/generated/version_autogenerated.h #define PLAIN_VERSION "" #define U_BOOT_VERSION "U-Boot " PLAIN_VERSION #define CC_VERSION_STRING "avr32-linux-gcc (OSELAS.Toolchain-2011.11.0) 4.4.7" #define LD_VERSION_STRING "GNU ld (GNU Binutils) 2.20.1.20100303" andreas@andreas-pc % --->8--- However using make directly is working correctly: ---8<--- andreas@andreas-pc % PATH=$AVR32_PATH:$PATH CROSS_COMPILE=avr32-linux- make -s O=/tmp/build_grasshopper grasshopper_config all Configuring for grasshopper board... PATH=$AVR32_PATH:$PATH CROSS_COMPILE=avr32-linux- make -s grasshopper_config 9,84s user 2,66s system 81% cpu 15,406 total andreas@andreas-pc % cat /tmp/build_grasshopper/include/generated/version_autogenerated.h #define PLAIN_VERSION "2014.04-rc1-00277-g180e065" #define U_BOOT_VERSION "U-Boot " PLAIN_VERSION #define CC_VERSION_STRING "avr32-linux-gcc (OSELAS.Toolchain-2011.11.0) 4.4.7" #define LD_VERSION_STRING "GNU ld (GNU Binutils) 2.20.1.20100303" andreas@andreas-pc % --->8--- I haven't seen anything about that on the list, is it a known bug? Is MAKEALL still a tool to use or is it outdated? At the moment I have not the time to dive into that problem, maybe I find some minutes next week. Best regards Andreas Bießmann

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[U-Boot] [PATCH v2 0/5] ARM: refactor start.S files
by Albert ARIBAUD 09 Mar '14

09 Mar '14

This series aims at refactoring start.S files. Some of these files contain cache-related or cpu-reset-related core, which is moved where it belongs. Useless symbols are removed, and finally, exception vector code, common across all ARM CPUs, is moved in its own file. At this point, the start.S files only contain CPU-specific reset sequences. NOTE: this series should be applied above the "arm: remove unneeded symbol offsets and _TEXT_BASE" series. Changes in v2: - fixed checkpatch issues in arch/arm/cpu/arm946es/cpu.c - fixed checkpatch issues in arch/arm/cpu/sa1100/cpu.c - rebased onto u-boot-arm/master (de4fdfc1) - adjusted comment in Zynq linker script Albert ARIBAUD (5): arm1136: move cache code from start.S to cache.c arm: move reset_cpu from start.S into cpu.c arm: pxa: move SP check from start.S to cpuinfo.c arm: remove unused _end_vect and _vectors_end symbols arm: move exception handling out of start.S files arch/arm/cpu/arm1136/start.S | 254 +---------------------- arch/arm/cpu/arm1176/start.S | 198 +----------------- arch/arm/cpu/arm720t/start.S | 229 +-------------------- arch/arm/cpu/arm920t/ep93xx/u-boot.lds | 3 +- arch/arm/cpu/arm920t/start.S | 216 +------------------- arch/arm/cpu/arm926ejs/mxs/start.S | 92 +-------- arch/arm/cpu/arm926ejs/spear/start.S | 27 +-- arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds | 1 + arch/arm/cpu/arm926ejs/start.S | 262 +----------------------- arch/arm/cpu/arm946es/cpu.c | 13 ++ arch/arm/cpu/arm946es/start.S | 246 +--------------------- arch/arm/cpu/arm_intcm/start.S | 228 +-------------------- arch/arm/cpu/armv7/start.S | 253 +---------------------- arch/arm/cpu/armv7/zynq/u-boot.lds | 2 +- arch/arm/cpu/pxa/cpuinfo.c | 6 + arch/arm/cpu/pxa/start.S | 253 +---------------------- arch/arm/cpu/sa1100/cpu.c | 14 ++ arch/arm/cpu/sa1100/start.S | 225 +------------------- arch/arm/cpu/u-boot-spl.lds | 1 + arch/arm/cpu/u-boot.lds | 1 + arch/arm/lib/Makefile | 2 +- arch/arm/lib/cache.c | 13 +- arch/arm/lib/vectors.S | 304 ++++++++++++++++++++++++++++ board/compulab/cm_t335/u-boot.lds | 1 + board/freescale/mx31ads/u-boot.lds | 1 + board/ti/am335x/u-boot.lds | 1 + 26 files changed, 371 insertions(+), 2475 deletions(-) create mode 100644 arch/arm/lib/vectors.S -- 1.8.3.2

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[U-Boot] [PATCH v2 0/3] arm: atmel: sama5d3: add spi and nand spl boot support
by Bo Shen 09 Mar '14

09 Mar '14

This patch enable spi and nand spl boot support on sama5d3xek Changes in v2: - Address the comments from Scott Wood Bo Shen (3): arm: atmel: sama5d3: add spi spl boot support mtd: nand: atmel: prepare for nand spl boot support arm: atmel: sama5d3: add nand spl boot support arch/arm/cpu/at91-common/spl.c | 4 + arch/arm/include/asm/arch-at91/spl.h | 4 + board/atmel/sama5d3xek/sama5d3xek.c | 4 + drivers/mtd/nand/atmel_nand.c | 208 +++++++++++++++++++++++++++++++++++ include/configs/sama5d3xek.h | 23 ++++ include/nand.h | 6 + 6 files changed, 249 insertions(+) -- 1.8.5.2

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