March 2014 - U-Boot

[U-Boot] [PATCH v2] boards.cfg: move boards with invalid emails to Orphan
by Masahiro Yamada 11 Mar '14

11 Mar '14

When I cc board maintainers, some of them result in bounce mails. It turned out the following do not work any more: Yuli Barcohen <yuli(a)arabellasw.com> Travis Sawyer <travis.sawyer(a)sandburst.com> Yusdi Santoso <yusdi_santoso(a)adaptec.com> David Updegraff <dave(a)cray.com> Sangmoon Kim <dogoil(a)etinsys.com> Anton Vorontsov <avorontsov(a)ru.mvista.com> Blackfin Team <u-boot-devel(a)blackfin.uclinux.org> Bluetechnix Tinyboards <bluetechnix(a)blackfin.uclinux.org> Andre Schwarz <andre.schwarz(a)matrix-vision.de> For the blackfin boards where Sonic Zhang is also listed as a maintainer, dead addresses should be simply dropped. For all of the others, the status should be changed to "Orphan". We have adopted the definition of "Orphan" as: board is not actively maintained any more but still builds, and any address associated with it is that of the last known maintainer(s) Even though the emails do not work any more, they carry information. We want to keep them. Besides, Orphan boards have been collected at the bottom of boards.cfg. (This is done when we run "tools/reformat.py") Add separators to distinguish them from those which were moved to Orphan 6 months ago. I believe it will be helpful in future to find which boards are old enough to be removed from the code base. Signed-off-by: Masahiro Yamada <yamada.m(a)jp.panasonic.com> Cc: Detlev Zundel <dzu(a)denx.de> Cc: Tom Rini <trini(a)ti.com> Cc: Albert ARIBAUD <albert.u.boot(a)aribaud.net> --- Changes in v2: - For the blackfin boards where Sonic Zhang is also listed as a maintainer, dead addresses should be simply dropped. - Move to "Orphan" instead of marking as "dead address" - Move more orphan boards: Andre Schwarz <andre.schwarz(a)matrix-vision.de> Tirumala Marri <tmarri(a)apm.com> are invalid too. boards.cfg | 122 +++++++++++++++++++++++++++++++------------------------------ 1 file changed, 62 insertions(+), 60 deletions(-) diff --git a/boards.cfg b/boards.cfg index a32f46b..180d5bb 100644 --- a/boards.cfg +++ b/boards.cfg @@ -417,40 +417,32 @@ Active avr32 at32ap at32ap700x in-circuit - Active avr32 at32ap at32ap700x mimc - mimc200 - Mark Jackson <mpfj(a)mimc.co.uk> Active avr32 at32ap at32ap700x miromico - hammerhead - Julien May <julien.may(a)miromico.ch>:Alex Raimondi <alex.raimondi(a)miromico.ch> Active blackfin blackfin - - - bct-brettl2 - Peter Meerwald <devel(a)bct-electronic.com> -Active blackfin blackfin - - - bf506f-ezkit - Sonic Zhang <sonic.adi(a)gmail.com>:Blackfin Team <u-boot-devel(a)blackfin.uclinux.org> -Active blackfin blackfin - - - bf518f-ezbrd - Sonic Zhang <sonic.adi(a)gmail.com>:Blackfin Team <u-boot-devel(a)blackfin.uclinux.org> +Active blackfin blackfin - - - bf506f-ezkit - Sonic Zhang <sonic.adi(a)gmail.com> +Active blackfin blackfin - - - bf518f-ezbrd - Sonic Zhang <sonic.adi(a)gmail.com> Active blackfin blackfin - - - bf525-ucr2 - Haitao Zhang <hzhang(a)ucrobotics.com>:Chong Huang <chuang(a)ucrobotics.com> -Active blackfin blackfin - - - bf526-ezbrd - Sonic Zhang <sonic.adi(a)gmail.com>:Blackfin Team <u-boot-devel(a)blackfin.uclinux.org> -Active blackfin blackfin - - - bf527-ad7160-eval - Sonic Zhang <sonic.adi(a)gmail.com>:Blackfin Team <u-boot-devel(a)blackfin.uclinux.org> -Active blackfin blackfin - - - bf527-ezkit - Sonic Zhang <sonic.adi(a)gmail.com>:Blackfin Team <u-boot-devel(a)blackfin.uclinux.org> -Active blackfin blackfin - - - bf527-sdp - Sonic Zhang <sonic.adi(a)gmail.com>:Blackfin Team <u-boot-devel(a)blackfin.uclinux.org> -Active blackfin blackfin - - - bf533-ezkit - Sonic Zhang <sonic.adi(a)gmail.com>:Blackfin Team <u-boot-devel(a)blackfin.uclinux.org> -Active blackfin blackfin - - - bf533-stamp - Sonic Zhang <sonic.adi(a)gmail.com>:Blackfin Team <u-boot-devel(a)blackfin.uclinux.org> +Active blackfin blackfin - - - bf526-ezbrd - Sonic Zhang <sonic.adi(a)gmail.com> +Active blackfin blackfin - - - bf527-ad7160-eval - Sonic Zhang <sonic.adi(a)gmail.com> +Active blackfin blackfin - - - bf527-ezkit - Sonic Zhang <sonic.adi(a)gmail.com> +Active blackfin blackfin - - - bf527-sdp - Sonic Zhang <sonic.adi(a)gmail.com> +Active blackfin blackfin - - - bf533-ezkit - Sonic Zhang <sonic.adi(a)gmail.com> +Active blackfin blackfin - - - bf533-stamp - Sonic Zhang <sonic.adi(a)gmail.com> Active blackfin blackfin - - - bf537-minotaur - Martin Strubel <strubel(a)section5.ch> -Active blackfin blackfin - - - bf537-pnav - Sonic Zhang <sonic.adi(a)gmail.com>:Blackfin Team <u-boot-devel(a)blackfin.uclinux.org> +Active blackfin blackfin - - - bf537-pnav - Sonic Zhang <sonic.adi(a)gmail.com> Active blackfin blackfin - - - bf537-srv1 - Martin Strubel <strubel(a)section5.ch> -Active blackfin blackfin - - - bf537-stamp - Sonic Zhang <sonic.adi(a)gmail.com>:Blackfin Team <u-boot-devel(a)blackfin.uclinux.org> -Active blackfin blackfin - - - bf538f-ezkit - Sonic Zhang <sonic.adi(a)gmail.com>:Blackfin Team <u-boot-devel(a)blackfin.uclinux.org> -Active blackfin blackfin - - - bf548-ezkit - Sonic Zhang <sonic.adi(a)gmail.com>:Blackfin Team <u-boot-devel(a)blackfin.uclinux.org> +Active blackfin blackfin - - - bf537-stamp - Sonic Zhang <sonic.adi(a)gmail.com> +Active blackfin blackfin - - - bf538f-ezkit - Sonic Zhang <sonic.adi(a)gmail.com> +Active blackfin blackfin - - - bf548-ezkit - Sonic Zhang <sonic.adi(a)gmail.com> Active blackfin blackfin - - - bf561-acvilon - Anton Shurpin <shurpin.aa(a)niistt.ru>:Valentin Yakovenkov <yakovenkov(a)niistt.ru> -Active blackfin blackfin - - - bf561-ezkit - Sonic Zhang <sonic.adi(a)gmail.com>:Blackfin Team <u-boot-devel(a)blackfin.uclinux.org> -Active blackfin blackfin - - - bf609-ezkit - Sonic Zhang <sonic.adi(a)gmail.com>:Blackfin Team <u-boot-devel(a)blackfin.uclinux.org> +Active blackfin blackfin - - - bf561-ezkit - Sonic Zhang <sonic.adi(a)gmail.com> +Active blackfin blackfin - - - bf609-ezkit - Sonic Zhang <sonic.adi(a)gmail.com> Active blackfin blackfin - - - blackstamp - Wojtek Skulski <skulski(a)pas.rochester.edu>:Wojtek Skulski <info(a)skutek.com>:Benjamin Matthews <mben12(a)gmail.com> Active blackfin blackfin - - - blackvme - Wojtek Skulski <skulski(a)pas.rochester.edu>:Wojtek Skulski <info(a)skutek.com>:Benjamin Matthews <mben12(a)gmail.com> Active blackfin blackfin - - - br4 - Dimitar Penev <dpn(a)switchfin.org> -Active blackfin blackfin - - - cm-bf527 - Bluetechnix Tinyboards <bluetechnix(a)blackfin.uclinux.org> -Active blackfin blackfin - - - cm-bf533 - Bluetechnix Tinyboards <bluetechnix(a)blackfin.uclinux.org> -Active blackfin blackfin - - - cm-bf537e - Bluetechnix Tinyboards <bluetechnix(a)blackfin.uclinux.org> -Active blackfin blackfin - - - cm-bf537u - Bluetechnix Tinyboards <bluetechnix(a)blackfin.uclinux.org> -Active blackfin blackfin - - - cm-bf548 - Bluetechnix Tinyboards <bluetechnix(a)blackfin.uclinux.org> -Active blackfin blackfin - - - cm-bf561 - Bluetechnix Tinyboards <bluetechnix(a)blackfin.uclinux.org> Active blackfin blackfin - - - dnp5370 - M.Hasewinkel (MHA) <info(a)ssv-embedded.de> Active blackfin blackfin - - - ibf-dsp561 - I-SYST Micromodule <support(a)i-syst.com> Active blackfin blackfin - - - ip04 - Brent Kandetzki <brentk(a)teleco.com> Active blackfin blackfin - - - pr1 - Dimitar Penev <dpn(a)switchfin.org> -Active blackfin blackfin - - - tcm-bf518 - Bluetechnix Tinyboards <bluetechnix(a)blackfin.uclinux.org> -Active blackfin blackfin - - - tcm-bf537 - Bluetechnix Tinyboards <bluetechnix(a)blackfin.uclinux.org> -Active blackfin blackfin - - bf527-ezkit bf527-ezkit-v2 bf527-ezkit:BF527_EZKIT_REV_2_1 Sonic Zhang <sonic.adi(a)gmail.com>:Blackfin Team <u-boot-devel(a)blackfin.uclinux.org> +Active blackfin blackfin - - bf527-ezkit bf527-ezkit-v2 bf527-ezkit:BF527_EZKIT_REV_2_1 Sonic Zhang <sonic.adi(a)gmail.com> Active m68k mcf5227x - freescale m52277evb M52277EVB M52277EVB:SYS_SPANSION_BOOT,SYS_TEXT_BASE=0x00000000 TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> Active m68k mcf5227x - freescale m52277evb M52277EVB_stmicro M52277EVB:CF_SBF,SYS_STMICRO_BOOT,SYS_TEXT_BASE=0x43E00000 TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> Active m68k mcf523x - freescale m5235evb M5235EVB M5235EVB:SYS_TEXT_BASE=0xFFE00000 TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> @@ -622,8 +614,6 @@ Active powerpc mpc5xxx - intercontrol digsy_mtc Active powerpc mpc5xxx - manroland - hmi1001 - - Active powerpc mpc5xxx - manroland - mucmc52 - Heiko Schocher <hs(a)denx.de> Active powerpc mpc5xxx - manroland - uc101 - Heiko Schocher <hs(a)denx.de> -Active powerpc mpc5xxx - matrix_vision mvbc_p MVBC_P MVBC_P:MVBC_P Andre Schwarz <andre.schwarz(a)matrix-vision.de> -Active powerpc mpc5xxx - matrix_vision mvsmr MVSMR - Andre Schwarz <andre.schwarz(a)matrix-vision.de> Active powerpc mpc5xxx - phytec pcm030 pcm030 - Jon Smirl <jonsmirl(a)gmail.com> Active powerpc mpc5xxx - phytec pcm030 pcm030_LOWBOOT pcm030:SYS_TEXT_BASE=0xFF000000 Jon Smirl <jonsmirl(a)gmail.com> Active powerpc mpc5xxx - tqc tqm5200 aev - - @@ -646,13 +636,10 @@ Active powerpc mpc824x - - cpc45 Active powerpc mpc824x - - cpc45 CPC45_ROMBOOT CPC45:BOOT_ROM Josef Wagner <Wagner(a)Microsys.de> Active powerpc mpc824x - - cu824 CU824 - Wolfgang Denk <wd(a)denx.de> Active powerpc mpc824x - - eXalion eXalion - Torsten Demke <torsten.demke(a)fci.com> -Active powerpc mpc824x - - hidden_dragon HIDDEN_DRAGON - Yusdi Santoso <yusdi_santoso(a)adaptec.com> Active powerpc mpc824x - - musenki MUSENKI - Jim Thompson <jim(a)musenki.com> Active powerpc mpc824x - - mvblue MVBLUE - - Active powerpc mpc824x - - sandpoint Sandpoint8240 - Wolfgang Denk <wd(a)denx.de> Active powerpc mpc824x - - sandpoint Sandpoint8245 - Jim Thompson <jim(a)musenki.com> -Active powerpc mpc824x - etin - debris - Sangmoon Kim <dogoil(a)etinsys.com> -Active powerpc mpc824x - etin - kvme080 - Sangmoon Kim <dogoil(a)etinsys.com> Active powerpc mpc8260 - - - atc - Wolfgang Denk <wd(a)denx.de> Active powerpc mpc8260 - - - ep8260 - Frank Panno <fpanno(a)delphintech.com> Active powerpc mpc8260 - - - ep82xxm - - @@ -665,11 +652,8 @@ Active powerpc mpc8260 - - cpu86 Active powerpc mpc8260 - - cpu86 CPU86_ROMBOOT CPU86:BOOT_ROM Wolfgang Denk <wd(a)denx.de> Active powerpc mpc8260 - - cpu87 CPU87 - - Active powerpc mpc8260 - - cpu87 CPU87_ROMBOOT CPU87:BOOT_ROM - -Active powerpc mpc8260 - - ep8248 ep8248 - Yuli Barcohen <yuli(a)arabellasw.com> Active powerpc mpc8260 - - ids8247 IDS8247 - Heiko Schocher <hs(a)denx.de> Active powerpc mpc8260 - - iphase4539 IPHASE4539 - Wolfgang Grandegger <wg(a)denx.de> -Active powerpc mpc8260 - - ispan ISPAN - Yuli Barcohen <yuli(a)arabellasw.com> -Active powerpc mpc8260 - - ispan ISPAN_REVB ISPAN:SYS_REV_B Yuli Barcohen <yuli(a)arabellasw.com> Active powerpc mpc8260 - - muas3001 muas3001 - Heiko Schocher <hs(a)denx.de> Active powerpc mpc8260 - - muas3001 muas3001_dev muas3001:MUAS_DEV_BOARD Heiko Schocher <hs(a)denx.de> Active powerpc mpc8260 - - pm826 PM825 PM826:PCI,SYS_TEXT_BASE=0xFF000000 Wolfgang Denk <wd(a)denx.de> @@ -684,25 +668,6 @@ Active powerpc mpc8260 - - pm828 Active powerpc mpc8260 - - pm828 PM828_PCI PM828:PCI - Active powerpc mpc8260 - - pm828 PM828_ROMBOOT PM828:BOOT_ROM,SYS_TEXT_BASE=0xFF800000 - Active powerpc mpc8260 - - pm828 PM828_ROMBOOT_PCI PM828:PCI,BOOT_ROM,SYS_TEXT_BASE=0xFF800000 - -Active powerpc mpc8260 - - rattler Rattler - Yuli Barcohen <yuli(a)arabellasw.com> -Active powerpc mpc8260 - - rattler Rattler8248 Rattler:MPC8248 Yuli Barcohen <yuli(a)arabellasw.com> -Active powerpc mpc8260 - - zpc1900 ZPC1900 - Yuli Barcohen <yuli(a)arabellasw.com> -Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS Yuli Barcohen <yuli(a)arabellasw.com> -Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_33MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=33000000 Yuli Barcohen <yuli(a)arabellasw.com> -Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_33MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=33000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli(a)arabellasw.com> -Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_40MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=40000000 Yuli Barcohen <yuli(a)arabellasw.com> -Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_40MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=40000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli(a)arabellasw.com> -Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli(a)arabellasw.com> -Active powerpc mpc8260 - freescale mpc8260ads MPC8272ADS MPC8260ADS:ADSTYPE=CONFIG_SYS_8272ADS Yuli Barcohen <yuli(a)arabellasw.com> -Active powerpc mpc8260 - freescale mpc8260ads MPC8272ADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8272ADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli(a)arabellasw.com> -Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS Yuli Barcohen <yuli(a)arabellasw.com> -Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-VR MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000 Yuli Barcohen <yuli(a)arabellasw.com> -Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-VR_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli(a)arabellasw.com> -Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS Yuli Barcohen <yuli(a)arabellasw.com> -Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_66MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000 Yuli Barcohen <yuli(a)arabellasw.com> -Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_66MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli(a)arabellasw.com> -Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli(a)arabellasw.com> -Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli(a)arabellasw.com> Active powerpc mpc8260 - freescale mpc8266ads MPC8266ADS - Rune Torgersen <runet(a)innovsys.com> Active powerpc mpc8260 - funkwerk vovpn-gw VoVPN-GW_66MHz VoVPN-GW:CLKIN_66MHz - Active powerpc mpc8260 - keymile km82xx mgcoge km82xx:MGCOGE Holger Brunck <holger.brunck(a)keymile.com> @@ -753,8 +718,6 @@ Active powerpc mpc83xx - freescale mpc8360emds Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66_HOST_33 MPC8360EMDS:CLKIN_66MHZ,PCI,PCI_33M,PQ_MDS_PIB=1 Dave Liu <daveliu(a)freescale.com> Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66_HOST_66 MPC8360EMDS:CLKIN_66MHZ,PCI,PCI_66M,PQ_MDS_PIB=1 Dave Liu <daveliu(a)freescale.com> Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66_SLAVE MPC8360EMDS:CLKIN_66MHZ,PCI,PCISLAVE Dave Liu <daveliu(a)freescale.com> -Active powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK - Anton Vorontsov <avorontsov(a)ru.mvista.com> -Active powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK_33 MPC8360ERDK:CLKIN_33MHZ Anton Vorontsov <avorontsov(a)ru.mvista.com> Active powerpc mpc83xx - freescale mpc837xemds MPC837XEMDS - Dave Liu <daveliu(a)freescale.com> Active powerpc mpc83xx - freescale mpc837xemds MPC837XEMDS_HOST MPC837XEMDS:PCI Dave Liu <daveliu(a)freescale.com> Active powerpc mpc83xx - freescale mpc837xerdb MPC837XERDB - Joe D'Abbraccio <ljd015(a)freescale.com> @@ -766,8 +729,6 @@ Active powerpc mpc83xx - keymile km83xx Active powerpc mpc83xx - keymile km83xx suvd3 suvd3:SUVD3 Holger Brunck <holger.brunck(a)keymile.com> Active powerpc mpc83xx - keymile km83xx tuge1 tuxx1:TUGE1 Holger Brunck <holger.brunck(a)keymile.com> Active powerpc mpc83xx - keymile km83xx tuxx1 tuxx1:TUXX1 Holger Brunck <holger.brunck(a)keymile.com> -Active powerpc mpc83xx - matrix_vision mergerbox MERGERBOX - Andre Schwarz <andre.schwarz(a)matrix-vision.de> -Active powerpc mpc83xx - matrix_vision mvblm7 MVBLM7 - Andre Schwarz <andre.schwarz(a)matrix-vision.de> Active powerpc mpc83xx - sheldon simpc8313 SIMPC8313_LP SIMPC8313:NAND_LP Ron Madrid <info(a)sheldoninst.com> Active powerpc mpc83xx - sheldon simpc8313 SIMPC8313_SP SIMPC8313:NAND_SP Ron Madrid <info(a)sheldoninst.com> Active powerpc mpc83xx - tqc tqm834x TQM834x - - @@ -1021,8 +982,6 @@ Active powerpc mpc8xx - - - Active powerpc mpc8xx - - - spc1920 - - Active powerpc mpc8xx - - - svm_sc8xx - John Zhan <zhanz(a)sinovee.com> Active powerpc mpc8xx - - - v37 - - -Active powerpc mpc8xx - - adder Adder - Yuli Barcohen <yuli(a)arabellasw.com> -Active powerpc mpc8xx - - adder AdderII Adder:MPC852T Yuli Barcohen <yuli(a)arabellasw.com> Active powerpc mpc8xx - - cogent cogent_mpc8xx - Murray Jensen <Murray.Jensen(a)csiro.au> Active powerpc mpc8xx - - esteem192e ESTEEM192E - Conn Clark <clark(a)esteem.com> Active powerpc mpc8xx - - fads MPC86xADS - - @@ -1115,7 +1074,6 @@ Active powerpc ppc4xx - - w7o Active powerpc ppc4xx - - w7o W7OLMG - Erik Theisen <etheisen(a)mindspring.com> Active powerpc ppc4xx - amcc - acadia - Stefan Roese <sr(a)denx.de> Active powerpc ppc4xx - amcc - bamboo - Stefan Roese <sr(a)denx.de> -Active powerpc ppc4xx - amcc - bluestone - Tirumala Marri <tmarri(a)apm.com> Active powerpc ppc4xx - amcc - bubinga - - Active powerpc ppc4xx - amcc - ebony - Stefan Roese <sr(a)denx.de> Active powerpc ppc4xx - amcc - katmai - Stefan Roese <sr(a)denx.de> @@ -1143,7 +1101,6 @@ Active powerpc ppc4xx - avnet fx12mm Active powerpc ppc4xx - avnet fx12mm fx12mm_flash fx12mm:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc405-generic/init.o Georg Schardt <schardt(a)team-ctech.de> Active powerpc ppc4xx - avnet v5fx30teval v5fx30teval v5fx30teval:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o Ricardo Ribalda <ricardo.ribalda(a)uam.es> Active powerpc ppc4xx - avnet v5fx30teval v5fx30teval_flash v5fx30teval:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc440-generic/init.o Ricardo Ribalda <ricardo.ribalda(a)uam.es> -Active powerpc ppc4xx - cray L1 CRAYL1 - David Updegraff <dave(a)cray.com> Active powerpc ppc4xx - dave PPChameleonEVB CATcenter CATcenter:PPCHAMELEON_MODULE_MODEL=1 - Active powerpc ppc4xx - dave PPChameleonEVB CATcenter_25 CATcenter:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_25 - Active powerpc ppc4xx - dave PPChameleonEVB CATcenter_33 CATcenter:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_33 - @@ -1193,8 +1150,6 @@ Active powerpc ppc4xx - mpl mip405 Active powerpc ppc4xx - mpl pip405 PIP405 - Denis Peter <d.peter(a)mpl.ch> Active powerpc ppc4xx - prodrive - alpr - Stefan Roese <sr(a)denx.de> Active powerpc ppc4xx - prodrive - p3p440 - Stefan Roese <sr(a)denx.de> -Active powerpc ppc4xx - sandburst karef KAREF - Travis Sawyer (travis.sawyer(a)sandburst.com> -Active powerpc ppc4xx - sandburst metrobox METROBOX - Travis Sawyer (travis.sawyer(a)sandburst.com> Active powerpc ppc4xx - xes - xpedite1000 - Peter Tyser <ptyser(a)xes-inc.com> Active powerpc ppc4xx - xilinx ml507 ml507 ml507:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o Ricardo Ribalda <ricardo.ribalda(a)uam.es> Active powerpc ppc4xx - xilinx ml507 ml507_flash ml507:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc440-generic/init.o Ricardo Ribalda <ricardo.ribalda(a)uam.es> @@ -1231,6 +1186,53 @@ Active sparc leon3 - gaisler - Active sparc leon3 - gaisler - gr_xc3s_1500 - - Active sparc leon3 - gaisler - grsim - - Active x86 x86 coreboot chromebook-x86 coreboot coreboot-x86 coreboot:SYS_TEXT_BASE=0x01110000 - +# The following were moved to "Orphan" in March, 2014 +Orphan blackfin blackfin - - - cm-bf527 - Bluetechnix Tinyboards <bluetechnix(a)blackfin.uclinux.org> +Orphan blackfin blackfin - - - cm-bf533 - Bluetechnix Tinyboards <bluetechnix(a)blackfin.uclinux.org> +Orphan blackfin blackfin - - - cm-bf537e - Bluetechnix Tinyboards <bluetechnix(a)blackfin.uclinux.org> +Orphan blackfin blackfin - - - cm-bf537u - Bluetechnix Tinyboards <bluetechnix(a)blackfin.uclinux.org> +Orphan blackfin blackfin - - - cm-bf548 - Bluetechnix Tinyboards <bluetechnix(a)blackfin.uclinux.org> +Orphan blackfin blackfin - - - cm-bf561 - Bluetechnix Tinyboards <bluetechnix(a)blackfin.uclinux.org> +Orphan blackfin blackfin - - - tcm-bf518 - Bluetechnix Tinyboards <bluetechnix(a)blackfin.uclinux.org> +Orphan blackfin blackfin - - - tcm-bf537 - Bluetechnix Tinyboards <bluetechnix(a)blackfin.uclinux.org> +Orphan powerpc mpc5xxx - matrix_vision mvbc_p MVBC_P MVBC_P:MVBC_P Andre Schwarz <andre.schwarz(a)matrix-vision.de> +Orphan powerpc mpc5xxx - matrix_vision mvsmr MVSMR - Andre Schwarz <andre.schwarz(a)matrix-vision.de> +Orphan powerpc mpc824x - - hidden_dragon HIDDEN_DRAGON - Yusdi Santoso <yusdi_santoso(a)adaptec.com> +Orphan powerpc mpc824x - etin - debris - Sangmoon Kim <dogoil(a)etinsys.com> +Orphan powerpc mpc824x - etin - kvme080 - Sangmoon Kim <dogoil(a)etinsys.com> +Orphan powerpc mpc8260 - - ep8248 ep8248 - Yuli Barcohen <yuli(a)arabellasw.com> +Orphan powerpc mpc8260 - - ispan ISPAN - Yuli Barcohen <yuli(a)arabellasw.com> +Orphan powerpc mpc8260 - - ispan ISPAN_REVB ISPAN:SYS_REV_B Yuli Barcohen <yuli(a)arabellasw.com> +Orphan powerpc mpc8260 - - rattler Rattler - Yuli Barcohen <yuli(a)arabellasw.com> +Orphan powerpc mpc8260 - - rattler Rattler8248 Rattler:MPC8248 Yuli Barcohen <yuli(a)arabellasw.com> +Orphan powerpc mpc8260 - - zpc1900 ZPC1900 - Yuli Barcohen <yuli(a)arabellasw.com> +Orphan powerpc mpc8260 - freescale mpc8260ads MPC8260ADS MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS Yuli Barcohen <yuli(a)arabellasw.com> +Orphan powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_33MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=33000000 Yuli Barcohen <yuli(a)arabellasw.com> +Orphan powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_33MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=33000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli(a)arabellasw.com> +Orphan powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_40MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=40000000 Yuli Barcohen <yuli(a)arabellasw.com> +Orphan powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_40MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=40000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli(a)arabellasw.com> +Orphan powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli(a)arabellasw.com> +Orphan powerpc mpc8260 - freescale mpc8260ads MPC8272ADS MPC8260ADS:ADSTYPE=CONFIG_SYS_8272ADS Yuli Barcohen <yuli(a)arabellasw.com> +Orphan powerpc mpc8260 - freescale mpc8260ads MPC8272ADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8272ADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli(a)arabellasw.com> +Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS Yuli Barcohen <yuli(a)arabellasw.com> +Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS-VR MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000 Yuli Barcohen <yuli(a)arabellasw.com> +Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS-VR_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli(a)arabellasw.com> +Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS Yuli Barcohen <yuli(a)arabellasw.com> +Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_66MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000 Yuli Barcohen <yuli(a)arabellasw.com> +Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_66MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli(a)arabellasw.com> +Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli(a)arabellasw.com> +Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli(a)arabellasw.com> +Orphan powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK - Anton Vorontsov <avorontsov(a)ru.mvista.com> +Orphan powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK_33 MPC8360ERDK:CLKIN_33MHZ Anton Vorontsov <avorontsov(a)ru.mvista.com> +Orphan powerpc mpc83xx - matrix_vision mergerbox MERGERBOX - Andre Schwarz <andre.schwarz(a)matrix-vision.de> +Orphan powerpc mpc83xx - matrix_vision mvblm7 MVBLM7 - Andre Schwarz <andre.schwarz(a)matrix-vision.de> +Orphan powerpc mpc8xx - - adder Adder - Yuli Barcohen <yuli(a)arabellasw.com> +Orphan powerpc mpc8xx - - adder AdderII Adder:MPC852T Yuli Barcohen <yuli(a)arabellasw.com> +Orphan powerpc ppc4xx - amcc - bluestone - Tirumala Marri <tmarri(a)apm.com> +Orphan powerpc ppc4xx - cray L1 CRAYL1 - David Updegraff <dave(a)cray.com> +Orphan powerpc ppc4xx - sandburst karef KAREF - Travis Sawyer <travis.sawyer(a)sandburst.com> +Orphan powerpc ppc4xx - sandburst metrobox METROBOX - Travis Sawyer <travis.sawyer(a)sandburst.com> +# The following were move to "Orphan" in September, 2013 Orphan arm arm1136 mx31 - imx31_phycore imx31_phycore_eet imx31_phycore:IMX31_PHYCORE_EET (resigned) Guennadi Liakhovetski <g.liakhovetski(a)gmx.de> Orphan arm arm1136 mx31 freescale - mx31ads - (resigned) Guennadi Liakhovetski <g.liakhovetski(a)gmx.de> Orphan arm pxa - - - lubbock - (dead address) Kyle Harris <kharris(a)nexus-tech.net> -- 1.8.3.2

3 5

[U-Boot] [ANN] U-Boot v2014.04-rc2 released
by Tom Rini 11 Mar '14

11 Mar '14

Hey all, I've pushed v2014.04-rc2 out to the repository and tarballs should exist soon. The good news this time around is Masahiro did some more updates to the system and we're now building faster than before. This should be noticable in both the single config build and arch/soc/vendor/etc builds. As always, if anything is broken please speak up. Thanks all! -- Tom

2 1

[U-Boot] [PATCH][v4] powerpc/mpc85xx: SECURE BOOT- Add secure boot target for B4860QDS
by Aneesh Bansal 11 Mar '14

11 Mar '14

Changes: 1. L2 cache is being invalidated by Boot ROM code for e6500 core. So removing the invalidation from start.S 2. Clear the LAW and corresponding configuration for CPC. Boot ROM code uses it as hosekeeping area. 3. For Secure boot, CPC is configured as SRAM and used as house keeping area. This configuration is to be disabled once in uboot. Earlier this disabling of CPC as SRAM was happening in cpu_init_r. As a result cache invalidation function was getting skipped in case CPC is configured as SRAM.This was causing random crashes. Signed-off-by: Aneesh Bansal <aneesh.bansal(a)freescale.com> --- README | 4 ++++ arch/powerpc/cpu/mpc85xx/cpu_init.c | 27 ++++++++++++++++++++++----- arch/powerpc/cpu/mpc85xx/start.S | 3 ++- arch/powerpc/include/asm/fsl_secure_boot.h | 6 ++++++ boards.cfg | 1 + 5 files changed, 35 insertions(+), 6 deletions(-) Changes from v3: Renamed the macro to indicate CPC configured as SRAM at U-boot entry to CONFIG_SYS_CPC_SRAM diff --git a/README b/README index 216f0c7..e26833d 100644 --- a/README +++ b/README @@ -427,6 +427,10 @@ The following options need to be configured: In this mode, a single differential clock is used to supply clocks to the sysclock, ddrclock and usbclock. + CONFIG_SYS_CPC_SRAM + This CONFIG is defined when the SPC is configured as SRAM at the + time of U-boot entry. + - Generic CPU options: CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index b31efb7..5cd7cb1 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -125,17 +125,14 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm) #endif #ifdef CONFIG_SYS_FSL_CPC -static void enable_cpc(void) +#if defined(CONFIG_RAMBOOT_PBL) || defined(CONFIG_SYS_CPC_SRAM) +static void disable_cpc_sram(void) { int i; - u32 size = 0; cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { - u32 cpccfg0 = in_be32(&cpc->cpccfg0); - size += CPC_CFG0_SZ_K(cpccfg0); -#ifdef CONFIG_RAMBOOT_PBL if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) { /* find and disable LAW of SRAM */ struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR); @@ -150,8 +147,21 @@ static void enable_cpc(void) out_be32(&cpc->cpccsr0, 0); out_be32(&cpc->cpcsrcr0, 0); } + } +} #endif +static void enable_cpc(void) +{ + int i; + u32 size = 0; + + cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; + + for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { + u32 cpccfg0 = in_be32(&cpc->cpccfg0); + size += CPC_CFG0_SZ_K(cpccfg0); + #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS); #endif @@ -250,6 +260,10 @@ void cpu_init_f (void) law = find_law(CONFIG_SYS_PBI_FLASH_BASE); if (law.index != -1) disable_law(law.index); + +#if defined(CONFIG_SYS_CPC_SRAM) + disable_cpc_sram(); +#endif #endif #ifdef CONFIG_CPM2 @@ -550,6 +564,9 @@ skip_l2: puts("disabled\n"); #endif +#if defined(CONFIG_RAMBOOT_PBL) + disable_cpc_sram(); +#endif enable_cpc(); #ifndef CONFIG_SYS_FSL_NO_SERDES diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index dbbd8e5..4ef0985 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -115,7 +115,8 @@ _start_e500: #endif -#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC) +#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC) && \ + !defined(CONFIG_E6500) /* ISBC uses L2 as stack. * Disable L2 cache here so that u-boot can enable it later * as part of it's normal flow diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 4c7f0b1..68498df 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -15,5 +15,11 @@ #endif #define CONFIG_SYS_PBI_FLASH_WINDOW 0xcff80000 +#if defined(CONFIG_B4860QDS) +#define CONFIG_SYS_CPC_SRAM +#undef CONFIG_SYS_INIT_L3_ADDR +#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000 +#endif + #endif #endif diff --git a/boards.cfg b/boards.cfg index 14cd151..65678ca 100644 --- a/boards.cfg +++ b/boards.cfg @@ -782,6 +782,7 @@ Active powerpc mpc85xx - freescale b4860qds Active powerpc mpc85xx - freescale b4860qds B4420QDS_NAND B4860QDS:PPC_B4420,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale b4860qds B4420QDS_SPIFLASH B4860QDS:PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale b4860qds B4860QDS B4860QDS:PPC_B4860 - +Active powerpc mpc85xx - freescale b4860qds B4860QDS_SECURE_BOOT B4860QDS:PPC_B4860,SECURE_BOOT Aneesh Bansal <aneesh.bansal(a)freescale.com> Active powerpc mpc85xx - freescale b4860qds B4860QDS_NAND B4860QDS:PPC_B4860,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale b4860qds B4860QDS_SPIFLASH B4860QDS:PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale b4860qds B4860QDS_SRIO_PCIE_BOOT B4860QDS:PPC_B4860,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 - -- 1.8.1.4

4 13

[U-Boot] [PATCH] cfi_flash: Micron Nor flash don't support read operation after send write command
by Qi Wang 王起 (qiwang) 11 Mar '14

11 Mar '14

Micron Nor flash don't support read operation after send write command. As below, flash_write_cmd(info, sector, offset, AMD_CMD_WRITE_TO_BUFFER); cnt = len >> shift; flash_write_cmd(info, sector, offset, cnt - 1); switch (info->portwidth) { case FLASH_CFI_8BIT: while (cnt-- > 0) { flash_write8(flash_read8(src), dst); src += 1, dst += 1; } break; If the src address locate in NOR flash, flash_read operation will be failed. So, read out the data to DRAM before send write command operation. Signed-off-by: Qi Wang<qiwang(a)micron.com> --- drivers/mtd/cfi_flash.c | 70 +++++++++++++++++++++++++++++++---------------- 1 file changed, 46 insertions(+), 24 deletions(-) diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index a389cd1..0f532c0 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -25,6 +25,8 @@ #include <environment.h> #include <mtd/cfi_flash.h> #include <watchdog.h> +#include <malloc.h> +#include <asm-generic/errno.h> /* * This file implements a Common Flash Interface (CFI) driver for @@ -855,6 +857,8 @@ static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, int cnt; int retcode; void *src = cp; + void *src2; + void *src2_bak; void *dst = (void *)dest; void *dst2 = dst; int flag = 1; @@ -880,29 +884,45 @@ static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, goto out_unmap; } + src2 = malloc(len); + if(!src2) + { + free(src2); + return -ENOMEM; + } + + src2_bak = src2; cnt = len >> shift; while ((cnt-- > 0) && (flag == 1)) { switch (info->portwidth) { case FLASH_CFI_8BIT: - flag = ((flash_read8(dst2) & flash_read8(src)) == - flash_read8(src)); + *(u8 *)src2 = flash_read8(src); + flag = ((flash_read8(dst2) & *(u8 *)src2) == + *(u8 *)src2); src += 1, dst2 += 1; + src2 +=1; break; case FLASH_CFI_16BIT: - flag = ((flash_read16(dst2) & flash_read16(src)) == - flash_read16(src)); + *(u16 *)src2 = flash_read16(src); + flag = ((flash_read16(dst2) & *(u16 *)src2) == + *(u16 *)src2); src += 2, dst2 += 2; + src2 += 2; break; case FLASH_CFI_32BIT: - flag = ((flash_read32(dst2) & flash_read32(src)) == - flash_read32(src)); + *(u32 *)src2 = flash_read32(src); + flag = ((flash_read32(dst2) & *(u32 *)src2) == + *(u32 *)src2); src += 4, dst2 += 4; + src2 += 4; break; case FLASH_CFI_64BIT: - flag = ((flash_read64(dst2) & flash_read64(src)) == - flash_read64(src)); + *(u64 *)src2 = flash_read64(src); + flag = ((flash_read64(dst2) & *(u64 *)src2) == + *(u64 *)src2); src += 8, dst2 += 8; + src2 += 8; break; } } @@ -912,6 +932,7 @@ static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, } src = cp; + src2 = src2_bak; sector = find_sector (info, dest); switch (info->vendor) { @@ -934,20 +955,20 @@ static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, while (cnt-- > 0) { switch (info->portwidth) { case FLASH_CFI_8BIT: - flash_write8(flash_read8(src), dst); - src += 1, dst += 1; + flash_write8(*(u8 *)src2, dst); + src2 += 1, dst += 1; break; case FLASH_CFI_16BIT: - flash_write16(flash_read16(src), dst); - src += 2, dst += 2; + flash_write16(*(u16 *)src2, dst); + src2 += 2, dst += 2; break; case FLASH_CFI_32BIT: - flash_write32(flash_read32(src), dst); - src += 4, dst += 4; + flash_write32(*(u32 *)src2, dst); + src2 += 4, dst += 4; break; case FLASH_CFI_64BIT: - flash_write64(flash_read64(src), dst); - src += 8, dst += 8; + flash_write64(*(u64 *)src2, dst); + src2 += 8, dst += 8; break; default: retcode = ERR_INVAL; @@ -977,26 +998,26 @@ static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, switch (info->portwidth) { case FLASH_CFI_8BIT: while (cnt-- > 0) { - flash_write8(flash_read8(src), dst); - src += 1, dst += 1; + flash_write8(*(u8 *)src2, dst); + src2 += 1, dst += 1; } break; case FLASH_CFI_16BIT: while (cnt-- > 0) { - flash_write16(flash_read16(src), dst); - src += 2, dst += 2; + flash_write16(*(u16 *)src2, dst); + src2 += 2, dst += 2; } break; case FLASH_CFI_32BIT: while (cnt-- > 0) { - flash_write32(flash_read32(src), dst); - src += 4, dst += 4; + flash_write32(*(u32 *)src2, dst); + src2 += 4, dst += 4; } break; case FLASH_CFI_64BIT: while (cnt-- > 0) { - flash_write64(flash_read64(src), dst); - src += 8, dst += 8; + flash_write64(*(u64 *)src2, dst); + src2 += 8, dst += 8; } break; default: @@ -1023,6 +1044,7 @@ static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, } out_unmap: + free(src2_bak); return retcode; } #endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ -- 1.7.9.5 Qi Wang Best wishes

1 0

[U-Boot] data abort on usb start, arndale
by armdev ftm 11 Mar '14

11 Mar '14

Hi, We have recently started working on arndale and running u-boot head on it. Seems like it is crashing on our setup with a data abort on usb start. Can anyone please confirm and suggest a fix / solution Our last mail was stuck in moderation, sending again U-Boot 2014.04-rc1-00486-geeb72e6 (Mar 11 2014 - 11:44:32) for ARNDALE CPU: Exynos5250@1000MHz Board: Arndale I2C: i2c_init: failed to init bus 0 for speed = 100000 ready DRAM: 2 GiB trace: copying 00084f98 bytes of early data from 50000000 to beff0000 trace: enabled WARNING: Caches not enabled MMC: EXYNOS DWMMC: 0, EXYNOS DWMMC: 1 i2c_init: failed to init bus 0 for speed = 100000 In: serial Out: serial Err: serial Net: Net Initialization Skipped No ethernet found. Hit any key to stop autoboot: 0 ARNDALE # usb start (Re)start USB... USB0: data abort pc : [<bef8524c>] lr : [<bef85298>] sp : beb5f9c0 ip : 00000003 fp : 00000000 r10: 00000000 r9 : beb62ecc r8 : befbcc80 r7 : befbcc84 r6 : 0000ffff r5 : 000000ff r4 : 00000001 r3 : 00000000 r2 : 00000001 r1 : 000000ff r0 : 0000ffff Flags: nzCv IRQs off FIQs off Mode SVC_32 Resetting CPU ... Thanks and Regards Armdev@FTM Team

1 0

[U-Boot] [PATCH v4 1/2] nand/denali: Adding Denali NAND driver support
by Chin Liang See 11 Mar '14

11 Mar '14

To add the Denali NAND driver support into U-Boot. It required information such as register base address from configuration header file within include/configs folder. Signed-off-by: Chin Liang See <clsee(a)altera.com> Cc: Artem Bityutskiy <artem.bityutskiy(a)linux.intel.com> Cc: David Woodhouse <David.Woodhouse(a)intel.com> Cc: Brian Norris <computersforpeace(a)gmail.com> Cc: Scott Wood <scottwood(a)freescale.com> Cc: Masahiro Yamada <yamada.m(a)jp.panasonic.com> --- Changes for v4 - Added cache flush to handle dcache enabled - Used standard return where 0 for pass - Removed unnecessary casting - Used standard readl and writel Changes for v3 - Fixed coding style Changes for v2 - Enable this driver support for SOCFPGA --- drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/denali_nand.c | 1146 ++++++++++++++++++++++++++++++++++++++++ drivers/mtd/nand/denali_nand.h | 493 +++++++++++++++++ 3 files changed, 1640 insertions(+) create mode 100644 drivers/mtd/nand/denali_nand.c create mode 100644 drivers/mtd/nand/denali_nand.h diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 02b149c..24e8218 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -39,6 +39,7 @@ obj-$(CONFIG_NAND_ECC_BCH) += nand_bch.o obj-$(CONFIG_NAND_ATMEL) += atmel_nand.o obj-$(CONFIG_DRIVER_NAND_BFIN) += bfin_nand.o obj-$(CONFIG_NAND_DAVINCI) += davinci_nand.o +obj-$(CONFIG_NAND_DENALI) += denali_nand.o obj-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_nand.o obj-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o diff --git a/drivers/mtd/nand/denali_nand.c b/drivers/mtd/nand/denali_nand.c new file mode 100644 index 0000000..ffa69ad --- /dev/null +++ b/drivers/mtd/nand/denali_nand.c @@ -0,0 +1,1146 @@ +/* + * Copyright (C) 2013-2014 Altera Corporation <www.altera.com> + * Copyright (C) 2009-2010, Intel Corporation and its suppliers. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <nand.h> +#include <asm/errno.h> +#include <asm/io.h> + +#include "denali_nand.h" + +#define NAND_DEFAULT_TIMINGS -1 + +static struct denali_nand_info denali; +static int onfi_timing_mode = NAND_DEFAULT_TIMINGS; + +/* We define a macro here that combines all interrupts this driver uses into + * a single constant value, for convenience. */ +#define DENALI_IRQ_ALL (INTR_STATUS__DMA_CMD_COMP | \ + INTR_STATUS__ECC_TRANSACTION_DONE | \ + INTR_STATUS__ECC_ERR | \ + INTR_STATUS__PROGRAM_FAIL | \ + INTR_STATUS__LOAD_COMP | \ + INTR_STATUS__PROGRAM_COMP | \ + INTR_STATUS__TIME_OUT | \ + INTR_STATUS__ERASE_FAIL | \ + INTR_STATUS__RST_COMP | \ + INTR_STATUS__ERASE_COMP | \ + INTR_STATUS__ECC_UNCOR_ERR | \ + INTR_STATUS__INT_ACT | \ + INTR_STATUS__LOCKED_BLK) + +/* indicates whether or not the internal value for the flash bank is + * valid or not */ +#define CHIP_SELECT_INVALID -1 + +#define SUPPORT_8BITECC 1 + +/* These constants are defined by the driver to enable common driver + * configuration options. */ +#define SPARE_ACCESS 0x41 +#define MAIN_ACCESS 0x42 +#define MAIN_SPARE_ACCESS 0x43 + +#define DENALI_UNLOCK_START 0x10 +#define DENALI_UNLOCK_END 0x11 +#define DENALI_LOCK 0x21 +#define DENALI_LOCK_TIGHT 0x31 +#define DENALI_BUFFER_LOAD 0x60 +#define DENALI_BUFFER_WRITE 0x62 + +#define DENALI_READ 0 +#define DENALI_WRITE 0x100 + +#define DENALI_DATA_OFFSET_ADDRESS 0x10 + +/* types of device accesses. We can issue commands and get status */ +#define COMMAND_CYCLE 0 +#define ADDR_CYCLE 1 +#define STATUS_CYCLE 2 + +/* this is a helper macro that allows us to + * format the bank into the proper bits for the controller */ +#define BANK(x) ((x) << 24) + +/* Interrupts are cleared by writing a 1 to the appropriate status bit */ +static inline void clear_interrupt(uint32_t irq_mask) +{ + uint32_t intr_status_reg = 0; + intr_status_reg = INTR_STATUS(denali.flash_bank); + writel(irq_mask, denali.flash_reg + intr_status_reg); +} + +static uint32_t read_interrupt_status(void) +{ + uint32_t intr_status_reg = 0; + intr_status_reg = INTR_STATUS(denali.flash_bank); + return readl(denali.flash_reg + intr_status_reg); +} + +static void clear_interrupts(void) +{ + uint32_t status = 0; + status = read_interrupt_status(); + clear_interrupt(status); + denali.irq_status = 0; +} + +static void denali_irq_enable(uint32_t int_mask) +{ + int i; + for (i = 0; i < denali.max_banks; ++i) + writel(int_mask, denali.flash_reg + INTR_EN(i)); +} + +static uint32_t wait_for_irq(uint32_t irq_mask) +{ + unsigned long timeout = 1000000; + uint32_t intr_status; + + do { + intr_status = read_interrupt_status() & DENALI_IRQ_ALL; + if (intr_status & irq_mask) { + denali.irq_status &= ~irq_mask; + /* our interrupt was detected */ + break; + } + udelay(1); + timeout--; + } while (timeout != 0); + + if (timeout == 0) { + /* timeout */ + printf("Denali timeout with interrupt status %08x\n", + read_interrupt_status()); + intr_status = 0; + } + return intr_status; +} + +/* + * Certain operations for the denali NAND controller use an indexed mode to + * read/write data. The operation is performed by writing the address value + * of the command to the device memory followed by the data. This function + * abstracts this common operation. +*/ +static void index_addr(uint32_t address, uint32_t data) +{ + writel(address, denali.flash_mem); + writel(data, denali.flash_mem + DENALI_DATA_OFFSET_ADDRESS); +} + +/* Perform an indexed read of the device */ +static void index_addr_read_data(uint32_t address, uint32_t *pdata) +{ + writel(address, denali.flash_mem); + *pdata = readl(denali.flash_mem + DENALI_DATA_OFFSET_ADDRESS); +} + +/* We need to buffer some data for some of the NAND core routines. + * The operations manage buffering that data. */ +static void reset_buf(void) +{ + denali.buf.head = 0; + denali.buf.tail = 0; +} + +static void write_byte_to_buf(uint8_t byte) +{ + BUG_ON(denali.buf.tail >= sizeof(denali.buf.buf)); + denali.buf.buf[denali.buf.tail++] = byte; +} + +/* resets a specific device connected to the core */ +static void reset_bank(void) +{ + uint32_t irq_status; + uint32_t irq_mask = INTR_STATUS__RST_COMP | + INTR_STATUS__TIME_OUT; + + clear_interrupts(); + + writel(1 << denali.flash_bank, denali.flash_reg + DEVICE_RESET); + + irq_status = wait_for_irq(irq_mask); + if (irq_status & INTR_STATUS__TIME_OUT) + debug(KERN_ERR "reset bank failed.\n"); +} + +/* Reset the flash controller */ +static uint32_t denali_nand_reset(void) +{ + uint32_t i; + + for (i = 0; i < denali.max_banks; i++) + writel(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT, + denali.flash_reg + INTR_STATUS(i)); + + for (i = 0; i < denali.max_banks; i++) { + writel(1 << i, denali.flash_reg + DEVICE_RESET); + while (!(readl(denali.flash_reg + INTR_STATUS(i)) & + (INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT))) + if (readl(denali.flash_reg + INTR_STATUS(i)) & + INTR_STATUS__TIME_OUT) + debug(KERN_DEBUG "NAND Reset operation " + "timed out on bank %d\n", i); + } + + for (i = 0; i < denali.max_banks; i++) + writel(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT, + denali.flash_reg + INTR_STATUS(i)); + + return 0; +} + +/* this routine calculates the ONFI timing values for a given mode and + * programs the clocking register accordingly. The mode is determined by + * the get_onfi_nand_para routine. + */ +static void nand_onfi_timing_set(uint32_t mode) +{ + uint32_t trea[6] = {40, 30, 25, 20, 20, 16}; + uint32_t trp[6] = {50, 25, 17, 15, 12, 10}; + uint32_t treh[6] = {30, 15, 15, 10, 10, 7}; + uint32_t trc[6] = {100, 50, 35, 30, 25, 20}; + uint32_t trhoh[6] = {0, 15, 15, 15, 15, 15}; + uint32_t trloh[6] = {0, 0, 0, 0, 5, 5}; + uint32_t tcea[6] = {100, 45, 30, 25, 25, 25}; + uint32_t tadl[6] = {200, 100, 100, 100, 70, 70}; + uint32_t trhw[6] = {200, 100, 100, 100, 100, 100}; + uint32_t trhz[6] = {200, 100, 100, 100, 100, 100}; + uint32_t twhr[6] = {120, 80, 80, 60, 60, 60}; + uint32_t tcs[6] = {70, 35, 25, 25, 20, 15}; + + uint32_t tclsrising = 1; + uint32_t data_invalid_rhoh, data_invalid_rloh, data_invalid; + uint32_t dv_window = 0; + uint32_t en_lo, en_hi; + uint32_t acc_clks; + uint32_t addr_2_data, re_2_we, re_2_re, we_2_re, cs_cnt; + + en_lo = DIV_ROUND_UP(trp[mode], CLK_X); + en_hi = DIV_ROUND_UP(treh[mode], CLK_X); +#if ONFI_BLOOM_TIME + if ((en_hi * CLK_X) < (treh[mode] + 2)) + en_hi++; +#endif + + if ((en_lo + en_hi) * CLK_X < trc[mode]) + en_lo += DIV_ROUND_UP((trc[mode] - (en_lo + en_hi) * CLK_X), + CLK_X); + + if ((en_lo + en_hi) < CLK_MULTI) + en_lo += CLK_MULTI - en_lo - en_hi; + + while (dv_window < 8) { + data_invalid_rhoh = en_lo * CLK_X + trhoh[mode]; + + data_invalid_rloh = (en_lo + en_hi) * CLK_X + trloh[mode]; + + data_invalid = + data_invalid_rhoh < + data_invalid_rloh ? data_invalid_rhoh : data_invalid_rloh; + + dv_window = data_invalid - trea[mode]; + + if (dv_window < 8) + en_lo++; + } + + acc_clks = DIV_ROUND_UP(trea[mode], CLK_X); + + while (((acc_clks * CLK_X) - trea[mode]) < 3) + acc_clks++; + + if ((data_invalid - acc_clks * CLK_X) < 2) + debug(KERN_WARNING "%s, Line %d: Warning!\n", + __FILE__, __LINE__); + + addr_2_data = DIV_ROUND_UP(tadl[mode], CLK_X); + re_2_we = DIV_ROUND_UP(trhw[mode], CLK_X); + re_2_re = DIV_ROUND_UP(trhz[mode], CLK_X); + we_2_re = DIV_ROUND_UP(twhr[mode], CLK_X); + cs_cnt = DIV_ROUND_UP((tcs[mode] - trp[mode]), CLK_X); + if (!tclsrising) + cs_cnt = DIV_ROUND_UP(tcs[mode], CLK_X); + if (cs_cnt == 0) + cs_cnt = 1; + + if (tcea[mode]) { + while (((cs_cnt * CLK_X) + trea[mode]) < tcea[mode]) + cs_cnt++; + } + +#if MODE5_WORKAROUND + if (mode == 5) + acc_clks = 5; +#endif + + /* Sighting 3462430: Temporary hack for MT29F128G08CJABAWP:B */ + if ((readl(denali.flash_reg + MANUFACTURER_ID) == 0) && + (readl(denali.flash_reg + DEVICE_ID) == 0x88)) + acc_clks = 6; + + writel(acc_clks, denali.flash_reg + ACC_CLKS); + writel(re_2_we, denali.flash_reg + RE_2_WE); + writel(re_2_re, denali.flash_reg + RE_2_RE); + writel(we_2_re, denali.flash_reg + WE_2_RE); + writel(addr_2_data, denali.flash_reg + ADDR_2_DATA); + writel(en_lo, denali.flash_reg + RDWR_EN_LO_CNT); + writel(en_hi, denali.flash_reg + RDWR_EN_HI_CNT); + writel(cs_cnt, denali.flash_reg + CS_SETUP_CNT); +} + +/* queries the NAND device to see what ONFI modes it supports. */ +static uint32_t get_onfi_nand_para(void) +{ + int i; + /* we needn't to do a reset here because driver has already + * reset all the banks before + * */ + if (!(readl(denali.flash_reg + ONFI_TIMING_MODE) & + ONFI_TIMING_MODE__VALUE)) + return -EIO; + + for (i = 5; i > 0; i--) { + if (readl(denali.flash_reg + ONFI_TIMING_MODE) & + (0x01 << i)) + break; + } + + nand_onfi_timing_set(i); + + /* By now, all the ONFI devices we know support the page cache */ + /* rw feature. So here we enable the pipeline_rw_ahead feature */ + return 0; +} + +static void get_samsung_nand_para(uint8_t device_id) +{ + if (device_id == 0xd3) { /* Samsung K9WAG08U1A */ + /* Set timing register values according to datasheet */ + writel(5, denali.flash_reg + ACC_CLKS); + writel(20, denali.flash_reg + RE_2_WE); + writel(12, denali.flash_reg + WE_2_RE); + writel(14, denali.flash_reg + ADDR_2_DATA); + writel(3, denali.flash_reg + RDWR_EN_LO_CNT); + writel(2, denali.flash_reg + RDWR_EN_HI_CNT); + writel(2, denali.flash_reg + CS_SETUP_CNT); + } +} + +static void get_toshiba_nand_para(void) +{ + uint32_t tmp; + + /* Workaround to fix a controller bug which reports a wrong */ + /* spare area size for some kind of Toshiba NAND device */ + if ((readl(denali.flash_reg + DEVICE_MAIN_AREA_SIZE) == 4096) && + (readl(denali.flash_reg + DEVICE_SPARE_AREA_SIZE) + == 64)){ + writel(216, denali.flash_reg + DEVICE_SPARE_AREA_SIZE); + tmp = readl(denali.flash_reg + DEVICES_CONNECTED) * + readl(denali.flash_reg + DEVICE_SPARE_AREA_SIZE); + writel(tmp, denali.flash_reg + LOGICAL_PAGE_SPARE_SIZE); +#if SUPPORT_15BITECC + writel(15, denali.flash_reg + ECC_CORRECTION); +#elif SUPPORT_8BITECC + writel(8, denali.flash_reg + ECC_CORRECTION); +#endif + } +} + +static void get_hynix_nand_para(uint8_t device_id) +{ + uint32_t main_size, spare_size; + + switch (device_id) { + case 0xD5: /* Hynix H27UAG8T2A, H27UBG8U5A or H27UCG8VFA */ + case 0xD7: /* Hynix H27UDG8VEM, H27UCG8UDM or H27UCG8V5A */ + writel(128, denali.flash_reg + PAGES_PER_BLOCK); + writel(4096, denali.flash_reg + DEVICE_MAIN_AREA_SIZE); + writel(224, denali.flash_reg + DEVICE_SPARE_AREA_SIZE); + main_size = 4096 * + readl(denali.flash_reg + DEVICES_CONNECTED); + spare_size = 224 * + readl(denali.flash_reg + DEVICES_CONNECTED); + writel(main_size, denali.flash_reg + LOGICAL_PAGE_DATA_SIZE); + writel(spare_size, denali.flash_reg + LOGICAL_PAGE_SPARE_SIZE); + writel(0, denali.flash_reg + DEVICE_WIDTH); +#if SUPPORT_15BITECC + writel(15, denali.flash_reg + ECC_CORRECTION); +#elif SUPPORT_8BITECC + writel(8, denali.flash_reg + ECC_CORRECTION); +#endif + break; + default: + debug(KERN_WARNING + "Spectra: Unknown Hynix NAND (Device ID: 0x%x)." + "Will use default parameter values instead.\n", + device_id); + } +} + +/* determines how many NAND chips are connected to the controller. Note for + * Intel CE4100 devices we don't support more than one device. + */ +static void find_valid_banks(void) +{ + uint32_t id[denali.max_banks]; + int i; + + denali.total_used_banks = 1; + for (i = 0; i < denali.max_banks; i++) { + index_addr((uint32_t)(MODE_11 | (i << 24) | 0), 0x90); + index_addr((uint32_t)(MODE_11 | (i << 24) | 1), 0); + index_addr_read_data((uint32_t)(MODE_11 | (i << 24) | 2), + &id[i]); + + if (i == 0) { + if (!(id[i] & 0x0ff)) + break; + } else { + if ((id[i] & 0x0ff) == (id[0] & 0x0ff)) + denali.total_used_banks++; + else + break; + } + } +} + +/* + * Use the configuration feature register to determine the maximum number of + * banks that the hardware supports. + */ +static void detect_max_banks(void) +{ + uint32_t features = readl(denali.flash_reg + FEATURES); + denali.max_banks = 2 << (features & FEATURES__N_BANKS); +} + +static void detect_partition_feature(void) +{ + /* For MRST platform, denali.fwblks represent the + * number of blocks firmware is taken, + * FW is in protect partition and MTD driver has no + * permission to access it. So let driver know how many + * blocks it can't touch. + * */ + if (readl(denali.flash_reg + FEATURES) & FEATURES__PARTITION) { + if ((readl(denali.flash_reg + PERM_SRC_ID(1)) & + PERM_SRC_ID__SRCID) == SPECTRA_PARTITION_ID) { + denali.fwblks = + ((readl(denali.flash_reg + MIN_MAX_BANK(1)) & + MIN_MAX_BANK__MIN_VALUE) * + denali.blksperchip) + + + (readl(denali.flash_reg + MIN_BLK_ADDR(1)) & + MIN_BLK_ADDR__VALUE); + } else { + denali.fwblks = SPECTRA_START_BLOCK; + } + } else { + denali.fwblks = SPECTRA_START_BLOCK; + } +} + +static uint32_t denali_nand_timing_set(void) +{ + uint32_t id_bytes[5], addr; + uint8_t i, maf_id, device_id; + + /* Use read id method to get device ID and other + * params. For some NAND chips, controller can't + * report the correct device ID by reading from + * DEVICE_ID register + * */ + addr = (uint32_t)MODE_11 | BANK(denali.flash_bank); + index_addr((uint32_t)addr | 0, 0x90); + index_addr((uint32_t)addr | 1, 0); + for (i = 0; i < 5; i++) + index_addr_read_data(addr | 2, &id_bytes[i]); + maf_id = id_bytes[0]; + device_id = id_bytes[1]; + + if (readl(denali.flash_reg + ONFI_DEVICE_NO_OF_LUNS) & + ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE) { /* ONFI 1.0 NAND */ + if (get_onfi_nand_para()) + return -EIO; + } else if (maf_id == 0xEC) { /* Samsung NAND */ + get_samsung_nand_para(device_id); + } else if (maf_id == 0x98) { /* Toshiba NAND */ + get_toshiba_nand_para(); + } else if (maf_id == 0xAD) { /* Hynix NAND */ + get_hynix_nand_para(device_id); + } + + find_valid_banks(); + + detect_partition_feature(); + + /* If the user specified to override the default timings + * with a specific ONFI mode, we apply those changes here. + */ + if (onfi_timing_mode != NAND_DEFAULT_TIMINGS) + nand_onfi_timing_set(onfi_timing_mode); + + return 0; +} + +/* validation function to verify that the controlling software is making + * a valid request + */ +static inline bool is_flash_bank_valid(int flash_bank) +{ + return (flash_bank >= 0 && flash_bank < 4); +} + +static void denali_irq_init(void) +{ + uint32_t int_mask = 0; + int i; + + /* Disable global interrupts */ + writel(0, denali.flash_reg + GLOBAL_INT_ENABLE); + + int_mask = DENALI_IRQ_ALL; + + /* Clear all status bits */ + for (i = 0; i < denali.max_banks; ++i) + writel(0xFFFF, denali.flash_reg + INTR_STATUS(i)); + + denali_irq_enable(int_mask); +} + +/* This helper function setups the registers for ECC and whether or not + * the spare area will be transferred. */ +static void setup_ecc_for_xfer(bool ecc_en, bool transfer_spare) +{ + int ecc_en_flag = 0, transfer_spare_flag = 0; + + /* set ECC, transfer spare bits if needed */ + ecc_en_flag = ecc_en ? ECC_ENABLE__FLAG : 0; + transfer_spare_flag = transfer_spare ? TRANSFER_SPARE_REG__FLAG : 0; + + /* Enable spare area/ECC per user's request. */ + writel(ecc_en_flag, denali.flash_reg + ECC_ENABLE); + /* applicable for MAP01 only */ + writel(transfer_spare_flag, denali.flash_reg + TRANSFER_SPARE_REG); +} + +/* sends a pipeline command operation to the controller. See the Denali NAND + * controller's user guide for more information (section 4.2.3.6). + */ +static int denali_send_pipeline_cmd(bool ecc_en, bool transfer_spare, + int access_type, int op) +{ + uint32_t addr = 0x0, cmd = 0x0, irq_status = 0, irq_mask = 0; + uint32_t page_count = 1; /* always read a page */ + + if (op == DENALI_READ) + irq_mask = INTR_STATUS__LOAD_COMP; + else if (op == DENALI_WRITE) + irq_mask = INTR_STATUS__PROGRAM_COMP | + INTR_STATUS__PROGRAM_FAIL; + else + BUG(); + + /* clear interrupts */ + clear_interrupts(); + + /* setup ECC and transfer spare reg */ + setup_ecc_for_xfer(ecc_en, transfer_spare); + + addr = BANK(denali.flash_bank) | denali.page; + + /* setup the acccess type */ + cmd = MODE_10 | addr; + index_addr((uint32_t)cmd, access_type); + + /* setup the pipeline command */ + if (access_type == SPARE_ACCESS && op == DENALI_WRITE) + index_addr((uint32_t)cmd, DENALI_BUFFER_WRITE); + else if (access_type == SPARE_ACCESS && op == DENALI_READ) + index_addr((uint32_t)cmd, DENALI_BUFFER_LOAD); + else + index_addr((uint32_t)cmd, 0x2000 | op | page_count); + + /* wait for command to be accepted */ + irq_status = wait_for_irq(irq_mask); + if ((irq_status & irq_mask) != irq_mask) + return -EIO; + + if (access_type != SPARE_ACCESS) { + cmd = MODE_01 | addr; + writel(cmd, denali.flash_mem); + } + return 0; +} + +/* helper function that simply writes a buffer to the flash */ +static int write_data_to_flash_mem(const void *buf, int len) +{ + uint32_t i = 0, *buf32; + + /* verify that the len is a multiple of 4. see comment in + * read_data_from_flash_mem() */ + BUG_ON((len % 4) != 0); + + /* write the data to the flash memory */ + buf32 = (uint32_t *)buf; + for (i = 0; i < len / 4; i++) + writel(*buf32++, denali.flash_mem + DENALI_DATA_OFFSET_ADDRESS); + return i * 4; /* intent is to return the number of bytes read */ +} + +static void denali_mode_main_access(void) +{ + uint32_t addr, cmd; + addr = BANK(denali.flash_bank) | denali.page; + cmd = MODE_10 | addr; + index_addr(cmd, MAIN_ACCESS); +} + +static void denali_mode_main_spare_access(void) +{ + uint32_t addr, cmd; + addr = BANK(denali.flash_bank) | denali.page; + cmd = MODE_10 | addr; + index_addr(cmd, MAIN_SPARE_ACCESS); +} + +/* Writes OOB data to the device. + * This code unused under normal U-Boot console as normally page write raw + * to be used for write oob data with main data. + */ +static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) +{ + uint32_t cmd; + + denali.page = page; + debug("* write_oob_data *\n"); + + /* We need to write to buffer first through MAP00 command */ + cmd = MODE_00 | BANK(denali.flash_bank); + writel(cmd, denali.flash_mem); + + /* send the data into flash buffer */ + write_data_to_flash_mem(buf, mtd->oobsize); + + /* activate the write through MAP10 commands */ + if (denali_send_pipeline_cmd(false, false, SPARE_ACCESS, DENALI_WRITE)) + return -EIO; + + return 0; +} + +/* this function examines buffers to see if they contain data that + * indicate that the buffer is part of an erased region of flash. + */ +bool is_erased(uint8_t *buf, int len) +{ + int i = 0; + for (i = 0; i < len; i++) + if (buf[i] != 0xFF) + return false; + return true; +} + + +/* programs the controller to either enable/disable DMA transfers */ +static void denali_enable_dma(bool en) +{ + uint32_t reg_val = 0x0; + + if (en) + reg_val = DMA_ENABLE__FLAG; + + writel(reg_val, denali.flash_reg + DMA_ENABLE); + readl(denali.flash_reg + DMA_ENABLE); +} + +/* setups the HW to perform the data DMA */ +static void denali_setup_dma_sequence(int op) +{ + const int page_count = 1; + uint32_t mode; + uint32_t addr = (uint32_t)denali.buf.dma_buf; + + flush_dcache_range(addr, addr + sizeof(denali.buf.dma_buf)); + + mode = MODE_10 | BANK(denali.flash_bank); + + /* DMA is a four step process */ + + /* 1. setup transfer type and # of pages */ + index_addr(mode | denali.page, 0x2000 | op | page_count); + + /* 2. set memory high address bits 23:8 */ + index_addr(mode | ((uint32_t)(addr >> 16) << 8), 0x2200); + + /* 3. set memory low address bits 23:8 */ + index_addr(mode | ((uint32_t)addr << 8), 0x2300); + + /* 4. interrupt when complete, burst len = 64 bytes*/ + index_addr(mode | 0x14000, 0x2400); +} + +/* Common DMA function */ +static uint32_t denali_dma_configuration(uint32_t ops, bool raw_xfer, + uint32_t irq_mask, int oob_required) +{ + uint32_t irq_status = 0; + /* setup_ecc_for_xfer(bool ecc_en, bool transfer_spare) */ + setup_ecc_for_xfer(!raw_xfer, oob_required); + + /* clear any previous interrupt flags */ + clear_interrupts(); + + /* enable the DMA */ + denali_enable_dma(true); + + /* setup the DMA */ + denali_setup_dma_sequence(ops); + + /* wait for operation to complete */ + irq_status = wait_for_irq(irq_mask); + + /* if ECC fault happen, seems we need delay before turning off DMA. + * If not, the controller will go into non responsive condition */ + if (irq_status & INTR_STATUS__ECC_UNCOR_ERR) + udelay(100); + + /* disable the DMA */ + denali_enable_dma(false); + + return irq_status; +} + +static int write_page(struct mtd_info *mtd, struct nand_chip *chip, + const uint8_t *buf, bool raw_xfer, int oob_required) +{ + uint32_t irq_status = 0; + uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP; + + denali.status = 0; + + /* copy buffer into DMA buffer */ + memcpy((void *)denali.buf.dma_buf, buf, mtd->writesize); + + /* need extra memcpoy for raw transfer */ + if (raw_xfer) + memcpy((void *)denali.buf.dma_buf + mtd->writesize, + chip->oob_poi, mtd->oobsize); + + /* setting up DMA */ + irq_status = denali_dma_configuration(DENALI_WRITE, raw_xfer, irq_mask, + oob_required); + + /* if timeout happen, error out */ + if (!(irq_status & INTR_STATUS__DMA_CMD_COMP)) { + debug("DMA timeout for denali write_page\n"); + denali.status = NAND_STATUS_FAIL; + return -EIO; + } + + if (irq_status & INTR_STATUS__LOCKED_BLK) { + debug("Failed as write to locked block\n"); + denali.status = NAND_STATUS_FAIL; + return -EIO; + } + return 0; +} + +/* NAND core entry points */ + +/* + * this is the callback that the NAND core calls to write a page. Since + * writing a page with ECC or without is similar, all the work is done + * by write_page above. + */ +static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip, + const uint8_t *buf, int oob_required) +{ + /* + * for regular page writes, we let HW handle all the ECC + * data written to the device. + */ + debug("denali_write_page at page %08x\n", denali.page); + + if (oob_required) + /* switch to main + spare access */ + denali_mode_main_spare_access(); + else + /* switch to main access only */ + denali_mode_main_access(); + + return write_page(mtd, chip, buf, false, oob_required); +} + +/* + * This is the callback that the NAND core calls to write a page without ECC. + * raw access is similar to ECC page writes, so all the work is done in the + * write_page() function above. + */ +static int denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, + const uint8_t *buf, int oob_required) +{ + /* + * for raw page writes, we want to disable ECC and simply write + * whatever data is in the buffer. + */ + debug("denali_write_page_raw at page %08x\n", denali.page); + + if (oob_required) + /* switch to main + spare access */ + denali_mode_main_spare_access(); + else + /* switch to main access only */ + denali_mode_main_access(); + + return write_page(mtd, chip, buf, true, oob_required); +} + +static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip, + int page) +{ + return write_oob_data(mtd, chip->oob_poi, page); +} + +/* raw include ECC value and all the spare area */ +static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, + uint8_t *buf, int oob_required, int page) +{ + uint32_t irq_status, irq_mask = INTR_STATUS__DMA_CMD_COMP; + + debug("denali_read_page_raw at page %08x\n", page); + if (denali.page != page) { + debug("Missing NAND_CMD_READ0 command\n"); + return -EIO; + } + + if (oob_required) + /* switch to main + spare access */ + denali_mode_main_spare_access(); + else + /* switch to main access only */ + denali_mode_main_access(); + + /* setting up the DMA where ecc_enable is false */ + irq_status = denali_dma_configuration(DENALI_READ, true, irq_mask, + oob_required); + + /* if timeout happen, error out */ + if (!(irq_status & INTR_STATUS__DMA_CMD_COMP)) { + debug("DMA timeout for denali_read_page_raw\n"); + return -EIO; + } + + /* splitting the content to destination buffer holder */ + memcpy(chip->oob_poi, (denali.buf.dma_buf + mtd->writesize), + mtd->oobsize); + memcpy(buf, denali.buf.dma_buf, mtd->writesize); + debug("buf %02x %02x\n", buf[0], buf[1]); + debug("chip->oob_poi %02x %02x\n", chip->oob_poi[0], chip->oob_poi[1]); + return 0; +} + +static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip, + uint8_t *buf, int oob_required, int page) +{ + uint32_t irq_status, irq_mask = INTR_STATUS__DMA_CMD_COMP; + + debug("denali_read_page at page %08x\n", page); + if (denali.page != page) { + debug("Missing NAND_CMD_READ0 command\n"); + return -EIO; + } + + if (oob_required) + /* switch to main + spare access */ + denali_mode_main_spare_access(); + else + /* switch to main access only */ + denali_mode_main_access(); + + /* setting up the DMA where ecc_enable is true */ + irq_status = denali_dma_configuration(DENALI_READ, false, irq_mask, + oob_required); + + memcpy(buf, (const void *)denali.buf.dma_buf, mtd->writesize); + debug("buf %02x %02x\n", buf[0], buf[1]); + + /* check whether any ECC error */ + if (irq_status & INTR_STATUS__ECC_UNCOR_ERR) { + /* is the ECC cause by erase page, check using read_page_raw */ + debug(" Uncorrected ECC detected\n"); + denali_read_page_raw(mtd, chip, buf, oob_required, denali.page); + + if (is_erased(buf, mtd->writesize) == true && + is_erased(chip->oob_poi, mtd->oobsize) == true) { + debug(" ECC error cause by erased block\n"); + /* false alarm, return the 0xFF */ + } else { + return -EIO; + } + } + memcpy(buf, (const void *)denali.buf.dma_buf, mtd->writesize); + return 0; +} + +static uint8_t denali_read_byte(struct mtd_info *mtd) +{ + uint32_t addr, result; + addr = (uint32_t)MODE_11 | BANK(denali.flash_bank); + index_addr_read_data((uint32_t)addr | 2, &result); + return (uint8_t)result & 0xFF; +} + +static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip, + int page) +{ + debug("denali_read_oob at page %08x\n", page); + denali.page = page; + return denali_read_page_raw(mtd, chip, denali.buf.buf, 1, page); +} + +static void denali_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) +{ + uint32_t i, addr, result; + + /* delay for tR (data transfer from Flash array to data register) */ + udelay(25); + + /* ensure device completed else additional delay and polling */ + wait_for_irq(INTR_STATUS__INT_ACT); + + addr = (uint32_t)MODE_11 | BANK(denali.flash_bank); + for (i = 0; i < len; i++) { + index_addr_read_data((uint32_t)addr | 2, &result); + write_byte_to_buf(result); + } + memcpy(buf, denali.buf.buf, len); +} + +static void denali_select_chip(struct mtd_info *mtd, int chip) +{ + denali.flash_bank = chip; +} + +static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip) +{ + int status = denali.status; + denali.status = 0; + + return status; +} + +static void denali_erase(struct mtd_info *mtd, int page) +{ + uint32_t cmd = 0x0, irq_status = 0; + + debug("denali_erase at page %08x\n", page); + + /* clear interrupts */ + clear_interrupts(); + + /* setup page read request for access type */ + cmd = MODE_10 | BANK(denali.flash_bank) | page; + index_addr((uint32_t)cmd, 0x1); + + /* wait for erase to complete or failure to occur */ + irq_status = wait_for_irq(INTR_STATUS__ERASE_COMP | + INTR_STATUS__ERASE_FAIL); + + if (irq_status & INTR_STATUS__ERASE_FAIL || + irq_status & INTR_STATUS__LOCKED_BLK) + denali.status = NAND_STATUS_FAIL; + else + denali.status = 0; +} + +static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col, + int page) +{ + uint32_t addr; + + switch (cmd) { + case NAND_CMD_PAGEPROG: + break; + case NAND_CMD_STATUS: + addr = MODE_11 | BANK(denali.flash_bank); + index_addr(addr | 0, cmd); + break; + case NAND_CMD_PARAM: + clear_interrupts(); + case NAND_CMD_READID: + reset_buf(); + /* sometimes ManufactureId read from register is not right + * e.g. some of Micron MT29F32G08QAA MLC NAND chips + * So here we send READID cmd to NAND insteand + * */ + addr = MODE_11 | BANK(denali.flash_bank); + index_addr(addr | 0, cmd); + index_addr(addr | 1, col & 0xFF); + break; + case NAND_CMD_READ0: + case NAND_CMD_SEQIN: + denali.page = page; + break; + case NAND_CMD_RESET: + reset_bank(); + break; + case NAND_CMD_READOOB: + /* TODO: Read OOB data */ + break; + case NAND_CMD_ERASE1: + /* + * supporting block erase only, not multiblock erase as + * it will cross plane and software need complex calculation + * to identify the block count for the cross plane + */ + denali_erase(mtd, page); + break; + case NAND_CMD_ERASE2: + /* nothing to do here as it was done during NAND_CMD_ERASE1 */ + break; + case NAND_CMD_UNLOCK1: + addr = MODE_10 | BANK(denali.flash_bank) | page; + index_addr(addr | 0, DENALI_UNLOCK_START); + break; + case NAND_CMD_UNLOCK2: + addr = MODE_10 | BANK(denali.flash_bank) | page; + index_addr(addr | 0, DENALI_UNLOCK_END); + break; + case NAND_CMD_LOCK: + addr = MODE_10 | BANK(denali.flash_bank); + index_addr(addr | 0, DENALI_LOCK); + break; + case NAND_CMD_LOCK_TIGHT: + addr = MODE_10 | BANK(denali.flash_bank); + index_addr(addr | 0, DENALI_LOCK_TIGHT); + break; + default: + printf(": unsupported command received 0x%x\n", cmd); + break; + } +} + +/* stubs for ECC functions not used by the NAND core */ +static int denali_ecc_calculate(struct mtd_info *mtd, const uint8_t *data, + uint8_t *ecc_code) +{ + BUG(); + return -EIO; +} + +static int denali_ecc_correct(struct mtd_info *mtd, uint8_t *data, + uint8_t *read_ecc, uint8_t *calc_ecc) +{ + BUG(); + return -EIO; +} + +static void denali_ecc_hwctl(struct mtd_info *mtd, int mode) +{ + BUG(); +} +/* end NAND core entry points */ + +/* Initialization code to bring the device up to a known good state */ +static void denali_hw_init(void) +{ + /* + * tell driver how many bit controller will skip before writing + * ECC code in OOB. This is normally used for bad block marker + */ + writel(CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES, + denali.flash_reg + SPARE_AREA_SKIP_BYTES); + detect_max_banks(); + denali_nand_reset(); + writel(0x0F, denali.flash_reg + RB_PIN_ENABLED); + writel(CHIP_EN_DONT_CARE__FLAG, + denali.flash_reg + CHIP_ENABLE_DONT_CARE); + writel(0xffff, denali.flash_reg + SPARE_AREA_MARKER); + + /* Should set value for these registers when init */ + writel(0, denali.flash_reg + TWO_ROW_ADDR_CYCLES); + writel(1, denali.flash_reg + ECC_ENABLE); + denali_nand_timing_set(); + denali_irq_init(); +} + +/* + * Although controller spec said SLC ECC is forceb to be 4bit, but denali + * controller in MRST only support 15bit and 8bit ECC correction + */ +#ifdef CONFIG_SYS_NAND_15BIT_HW_ECC_OOBFIRST +#define ECC_15BITS 26 +static struct nand_ecclayout nand_15bit_oob = { + .eccbytes = ECC_15BITS, +}; +#else +#define ECC_8BITS 14 +static struct nand_ecclayout nand_8bit_oob = { + .eccbytes = ECC_8BITS, +}; +#endif /* CONFIG_SYS_NAND_15BIT_HW_ECC_OOBFIRST */ + +void denali_nand_init(struct nand_chip *nand) +{ + denali.flash_reg = (void __iomem *)CONFIG_SYS_NAND_REGS_BASE; + denali.flash_mem = (void __iomem *)CONFIG_SYS_NAND_DATA_BASE; + + nand->chip_delay = 0; +#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT + /* check whether flash got BBT table (located at end of flash). As we + * use NAND_BBT_NO_OOB, the BBT page will start with + * bbt_pattern. We will have mirror pattern too */ + nand->options |= NAND_BBT_USE_FLASH; + /* + * We are using main + spare with ECC support. As BBT need ECC support, + * we need to ensure BBT code don't write to OOB for the BBT pattern. + * All BBT info will be stored into data area with ECC support. + */ + nand->options |= NAND_BBT_NO_OOB; +#endif + + nand->ecc.mode = NAND_ECC_HW; + nand->ecc.size = CONFIG_NAND_DENALI_ECC_SIZE; + nand->ecc.read_oob = denali_read_oob; + nand->ecc.write_oob = denali_write_oob; + nand->ecc.read_page = denali_read_page; + nand->ecc.read_page_raw = denali_read_page_raw; + nand->ecc.write_page = denali_write_page; + nand->ecc.write_page_raw = denali_write_page_raw; +#ifdef CONFIG_SYS_NAND_15BIT_HW_ECC_OOBFIRST + /* 15bit ECC */ + nand->ecc.bytes = 26; + nand->ecc.layout = &nand_15bit_oob; +#else /* 8bit ECC */ + nand->ecc.bytes = 14; + nand->ecc.layout = &nand_8bit_oob; +#endif + nand->ecc.calculate = denali_ecc_calculate; + nand->ecc.correct = denali_ecc_correct; + nand->ecc.hwctl = denali_ecc_hwctl; + + /* Set address of hardware control function */ + nand->cmdfunc = denali_cmdfunc; + nand->read_byte = denali_read_byte; + nand->read_buf = denali_read_buf; + nand->select_chip = denali_select_chip; + nand->waitfunc = denali_waitfunc; + denali_hw_init(); +} + +int board_nand_init(struct nand_chip *chip) +{ + puts("NAND: Denali NAND controller\n"); + denali_nand_init(chip); + return 0; +} diff --git a/drivers/mtd/nand/denali_nand.h b/drivers/mtd/nand/denali_nand.h new file mode 100644 index 0000000..4fd9ffc --- /dev/null +++ b/drivers/mtd/nand/denali_nand.h @@ -0,0 +1,493 @@ +/* + * Copyright (C) 2013-2014 Altera Corporation <www.altera.com> + * Copyright (C) 2009-2010, Intel Corporation and its suppliers. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +typedef int irqreturn_t; + +#define IRQ_HANDLED 1 +#define IRQ_NONE 0 + +#define DEVICE_RESET 0x0 +#define DEVICE_RESET__BANK0 0x0001 +#define DEVICE_RESET__BANK1 0x0002 +#define DEVICE_RESET__BANK2 0x0004 +#define DEVICE_RESET__BANK3 0x0008 + +#define TRANSFER_SPARE_REG 0x10 +#define TRANSFER_SPARE_REG__FLAG 0x0001 + +#define LOAD_WAIT_CNT 0x20 +#define LOAD_WAIT_CNT__VALUE 0xffff + +#define PROGRAM_WAIT_CNT 0x30 +#define PROGRAM_WAIT_CNT__VALUE 0xffff + +#define ERASE_WAIT_CNT 0x40 +#define ERASE_WAIT_CNT__VALUE 0xffff + +#define INT_MON_CYCCNT 0x50 +#define INT_MON_CYCCNT__VALUE 0xffff + +#define RB_PIN_ENABLED 0x60 +#define RB_PIN_ENABLED__BANK0 0x0001 +#define RB_PIN_ENABLED__BANK1 0x0002 +#define RB_PIN_ENABLED__BANK2 0x0004 +#define RB_PIN_ENABLED__BANK3 0x0008 + +#define MULTIPLANE_OPERATION 0x70 +#define MULTIPLANE_OPERATION__FLAG 0x0001 + +#define MULTIPLANE_READ_ENABLE 0x80 +#define MULTIPLANE_READ_ENABLE__FLAG 0x0001 + +#define COPYBACK_DISABLE 0x90 +#define COPYBACK_DISABLE__FLAG 0x0001 + +#define CACHE_WRITE_ENABLE 0xa0 +#define CACHE_WRITE_ENABLE__FLAG 0x0001 + +#define CACHE_READ_ENABLE 0xb0 +#define CACHE_READ_ENABLE__FLAG 0x0001 + +#define PREFETCH_MODE 0xc0 +#define PREFETCH_MODE__PREFETCH_EN 0x0001 +#define PREFETCH_MODE__PREFETCH_BURST_LENGTH 0xfff0 + +#define CHIP_ENABLE_DONT_CARE 0xd0 +#define CHIP_EN_DONT_CARE__FLAG 0x01 + +#define ECC_ENABLE 0xe0 +#define ECC_ENABLE__FLAG 0x0001 + +#define GLOBAL_INT_ENABLE 0xf0 +#define GLOBAL_INT_EN_FLAG 0x01 + +#define WE_2_RE 0x100 +#define WE_2_RE__VALUE 0x003f + +#define ADDR_2_DATA 0x110 +#define ADDR_2_DATA__VALUE 0x003f + +#define RE_2_WE 0x120 +#define RE_2_WE__VALUE 0x003f + +#define ACC_CLKS 0x130 +#define ACC_CLKS__VALUE 0x000f + +#define NUMBER_OF_PLANES 0x140 +#define NUMBER_OF_PLANES__VALUE 0x0007 + +#define PAGES_PER_BLOCK 0x150 +#define PAGES_PER_BLOCK__VALUE 0xffff + +#define DEVICE_WIDTH 0x160 +#define DEVICE_WIDTH__VALUE 0x0003 + +#define DEVICE_MAIN_AREA_SIZE 0x170 +#define DEVICE_MAIN_AREA_SIZE__VALUE 0xffff + +#define DEVICE_SPARE_AREA_SIZE 0x180 +#define DEVICE_SPARE_AREA_SIZE__VALUE 0xffff + +#define TWO_ROW_ADDR_CYCLES 0x190 +#define TWO_ROW_ADDR_CYCLES__FLAG 0x0001 + +#define MULTIPLANE_ADDR_RESTRICT 0x1a0 +#define MULTIPLANE_ADDR_RESTRICT__FLAG 0x0001 + +#define ECC_CORRECTION 0x1b0 +#define ECC_CORRECTION__VALUE 0x001f + +#define READ_MODE 0x1c0 +#define READ_MODE__VALUE 0x000f + +#define WRITE_MODE 0x1d0 +#define WRITE_MODE__VALUE 0x000f + +#define COPYBACK_MODE 0x1e0 +#define COPYBACK_MODE__VALUE 0x000f + +#define RDWR_EN_LO_CNT 0x1f0 +#define RDWR_EN_LO_CNT__VALUE 0x001f + +#define RDWR_EN_HI_CNT 0x200 +#define RDWR_EN_HI_CNT__VALUE 0x001f + +#define MAX_RD_DELAY 0x210 +#define MAX_RD_DELAY__VALUE 0x000f + +#define CS_SETUP_CNT 0x220 +#define CS_SETUP_CNT__VALUE 0x001f + +#define SPARE_AREA_SKIP_BYTES 0x230 +#define SPARE_AREA_SKIP_BYTES__VALUE 0x003f + +#define SPARE_AREA_MARKER 0x240 +#define SPARE_AREA_MARKER__VALUE 0xffff + +#define DEVICES_CONNECTED 0x250 +#define DEVICES_CONNECTED__VALUE 0x0007 + +#define DIE_MASK 0x260 +#define DIE_MASK__VALUE 0x00ff + +#define FIRST_BLOCK_OF_NEXT_PLANE 0x270 +#define FIRST_BLOCK_OF_NEXT_PLANE__VALUE 0xffff + +#define WRITE_PROTECT 0x280 +#define WRITE_PROTECT__FLAG 0x0001 + +#define RE_2_RE 0x290 +#define RE_2_RE__VALUE 0x003f + +#define MANUFACTURER_ID 0x300 +#define MANUFACTURER_ID__VALUE 0x00ff + +#define DEVICE_ID 0x310 +#define DEVICE_ID__VALUE 0x00ff + +#define DEVICE_PARAM_0 0x320 +#define DEVICE_PARAM_0__VALUE 0x00ff + +#define DEVICE_PARAM_1 0x330 +#define DEVICE_PARAM_1__VALUE 0x00ff + +#define DEVICE_PARAM_2 0x340 +#define DEVICE_PARAM_2__VALUE 0x00ff + +#define LOGICAL_PAGE_DATA_SIZE 0x350 +#define LOGICAL_PAGE_DATA_SIZE__VALUE 0xffff + +#define LOGICAL_PAGE_SPARE_SIZE 0x360 +#define LOGICAL_PAGE_SPARE_SIZE__VALUE 0xffff + +#define REVISION 0x370 +#define REVISION__VALUE 0xffff + +#define ONFI_DEVICE_FEATURES 0x380 +#define ONFI_DEVICE_FEATURES__VALUE 0x003f + +#define ONFI_OPTIONAL_COMMANDS 0x390 +#define ONFI_OPTIONAL_COMMANDS__VALUE 0x003f + +#define ONFI_TIMING_MODE 0x3a0 +#define ONFI_TIMING_MODE__VALUE 0x003f + +#define ONFI_PGM_CACHE_TIMING_MODE 0x3b0 +#define ONFI_PGM_CACHE_TIMING_MODE__VALUE 0x003f + +#define ONFI_DEVICE_NO_OF_LUNS 0x3c0 +#define ONFI_DEVICE_NO_OF_LUNS__NO_OF_LUNS 0x00ff +#define ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE 0x0100 + +#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L 0x3d0 +#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L__VALUE 0xffff + +#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U 0x3e0 +#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U__VALUE 0xffff + +#define FEATURES 0x3f0 +#define FEATURES__N_BANKS 0x0003 +#define FEATURES__ECC_MAX_ERR 0x003c +#define FEATURES__DMA 0x0040 +#define FEATURES__CMD_DMA 0x0080 +#define FEATURES__PARTITION 0x0100 +#define FEATURES__XDMA_SIDEBAND 0x0200 +#define FEATURES__GPREG 0x0400 +#define FEATURES__INDEX_ADDR 0x0800 + +#define TRANSFER_MODE 0x400 +#define TRANSFER_MODE__VALUE 0x0003 + +#define INTR_STATUS(__bank) (0x410 + ((__bank) * 0x50)) +#define INTR_EN(__bank) (0x420 + ((__bank) * 0x50)) + +/* + * Some versions of the IP have the ECC fixup handled in hardware. In this + * configuration we only get interrupted when the error is uncorrectable. + * Unfortunately this bit replaces INTR_STATUS__ECC_TRANSACTION_DONE from the + * old IP. + */ +#define INTR_STATUS__ECC_UNCOR_ERR 0x0001 +#define INTR_STATUS__ECC_TRANSACTION_DONE 0x0001 +#define INTR_STATUS__ECC_ERR 0x0002 +#define INTR_STATUS__DMA_CMD_COMP 0x0004 +#define INTR_STATUS__TIME_OUT 0x0008 +#define INTR_STATUS__PROGRAM_FAIL 0x0010 +#define INTR_STATUS__ERASE_FAIL 0x0020 +#define INTR_STATUS__LOAD_COMP 0x0040 +#define INTR_STATUS__PROGRAM_COMP 0x0080 +#define INTR_STATUS__ERASE_COMP 0x0100 +#define INTR_STATUS__PIPE_CPYBCK_CMD_COMP 0x0200 +#define INTR_STATUS__LOCKED_BLK 0x0400 +#define INTR_STATUS__UNSUP_CMD 0x0800 +#define INTR_STATUS__INT_ACT 0x1000 +#define INTR_STATUS__RST_COMP 0x2000 +#define INTR_STATUS__PIPE_CMD_ERR 0x4000 +#define INTR_STATUS__PAGE_XFER_INC 0x8000 + +#define INTR_EN__ECC_TRANSACTION_DONE 0x0001 +#define INTR_EN__ECC_ERR 0x0002 +#define INTR_EN__DMA_CMD_COMP 0x0004 +#define INTR_EN__TIME_OUT 0x0008 +#define INTR_EN__PROGRAM_FAIL 0x0010 +#define INTR_EN__ERASE_FAIL 0x0020 +#define INTR_EN__LOAD_COMP 0x0040 +#define INTR_EN__PROGRAM_COMP 0x0080 +#define INTR_EN__ERASE_COMP 0x0100 +#define INTR_EN__PIPE_CPYBCK_CMD_COMP 0x0200 +#define INTR_EN__LOCKED_BLK 0x0400 +#define INTR_EN__UNSUP_CMD 0x0800 +#define INTR_EN__INT_ACT 0x1000 +#define INTR_EN__RST_COMP 0x2000 +#define INTR_EN__PIPE_CMD_ERR 0x4000 +#define INTR_EN__PAGE_XFER_INC 0x8000 + +#define PAGE_CNT(__bank) (0x430 + ((__bank) * 0x50)) +#define ERR_PAGE_ADDR(__bank) (0x440 + ((__bank) * 0x50)) +#define ERR_BLOCK_ADDR(__bank) (0x450 + ((__bank) * 0x50)) + +#define DATA_INTR 0x550 +#define DATA_INTR__WRITE_SPACE_AV 0x0001 +#define DATA_INTR__READ_DATA_AV 0x0002 + +#define DATA_INTR_EN 0x560 +#define DATA_INTR_EN__WRITE_SPACE_AV 0x0001 +#define DATA_INTR_EN__READ_DATA_AV 0x0002 + +#define GPREG_0 0x570 +#define GPREG_0__VALUE 0xffff + +#define GPREG_1 0x580 +#define GPREG_1__VALUE 0xffff + +#define GPREG_2 0x590 +#define GPREG_2__VALUE 0xffff + +#define GPREG_3 0x5a0 +#define GPREG_3__VALUE 0xffff + +#define ECC_THRESHOLD 0x600 +#define ECC_THRESHOLD__VALUE 0x03ff + +#define ECC_ERROR_BLOCK_ADDRESS 0x610 +#define ECC_ERROR_BLOCK_ADDRESS__VALUE 0xffff + +#define ECC_ERROR_PAGE_ADDRESS 0x620 +#define ECC_ERROR_PAGE_ADDRESS__VALUE 0x0fff +#define ECC_ERROR_PAGE_ADDRESS__BANK 0xf000 + +#define ECC_ERROR_ADDRESS 0x630 +#define ECC_ERROR_ADDRESS__OFFSET 0x0fff +#define ECC_ERROR_ADDRESS__SECTOR_NR 0xf000 + +#define ERR_CORRECTION_INFO 0x640 +#define ERR_CORRECTION_INFO__BYTEMASK 0x00ff +#define ERR_CORRECTION_INFO__DEVICE_NR 0x0f00 +#define ERR_CORRECTION_INFO__ERROR_TYPE 0x4000 +#define ERR_CORRECTION_INFO__LAST_ERR_INFO 0x8000 + +#define DMA_ENABLE 0x700 +#define DMA_ENABLE__FLAG 0x0001 + +#define IGNORE_ECC_DONE 0x710 +#define IGNORE_ECC_DONE__FLAG 0x0001 + +#define DMA_INTR 0x720 +#define DMA_INTR__TARGET_ERROR 0x0001 +#define DMA_INTR__DESC_COMP_CHANNEL0 0x0002 +#define DMA_INTR__DESC_COMP_CHANNEL1 0x0004 +#define DMA_INTR__DESC_COMP_CHANNEL2 0x0008 +#define DMA_INTR__DESC_COMP_CHANNEL3 0x0010 +#define DMA_INTR__MEMCOPY_DESC_COMP 0x0020 + +#define DMA_INTR_EN 0x730 +#define DMA_INTR_EN__TARGET_ERROR 0x0001 +#define DMA_INTR_EN__DESC_COMP_CHANNEL0 0x0002 +#define DMA_INTR_EN__DESC_COMP_CHANNEL1 0x0004 +#define DMA_INTR_EN__DESC_COMP_CHANNEL2 0x0008 +#define DMA_INTR_EN__DESC_COMP_CHANNEL3 0x0010 +#define DMA_INTR_EN__MEMCOPY_DESC_COMP 0x0020 + +#define TARGET_ERR_ADDR_LO 0x740 +#define TARGET_ERR_ADDR_LO__VALUE 0xffff + +#define TARGET_ERR_ADDR_HI 0x750 +#define TARGET_ERR_ADDR_HI__VALUE 0xffff + +#define CHNL_ACTIVE 0x760 +#define CHNL_ACTIVE__CHANNEL0 0x0001 +#define CHNL_ACTIVE__CHANNEL1 0x0002 +#define CHNL_ACTIVE__CHANNEL2 0x0004 +#define CHNL_ACTIVE__CHANNEL3 0x0008 + +#define ACTIVE_SRC_ID 0x800 +#define ACTIVE_SRC_ID__VALUE 0x00ff + +#define PTN_INTR 0x810 +#define PTN_INTR__CONFIG_ERROR 0x0001 +#define PTN_INTR__ACCESS_ERROR_BANK0 0x0002 +#define PTN_INTR__ACCESS_ERROR_BANK1 0x0004 +#define PTN_INTR__ACCESS_ERROR_BANK2 0x0008 +#define PTN_INTR__ACCESS_ERROR_BANK3 0x0010 +#define PTN_INTR__REG_ACCESS_ERROR 0x0020 + +#define PTN_INTR_EN 0x820 +#define PTN_INTR_EN__CONFIG_ERROR 0x0001 +#define PTN_INTR_EN__ACCESS_ERROR_BANK0 0x0002 +#define PTN_INTR_EN__ACCESS_ERROR_BANK1 0x0004 +#define PTN_INTR_EN__ACCESS_ERROR_BANK2 0x0008 +#define PTN_INTR_EN__ACCESS_ERROR_BANK3 0x0010 +#define PTN_INTR_EN__REG_ACCESS_ERROR 0x0020 + +#define PERM_SRC_ID(__bank) (0x830 + ((__bank) * 0x40)) +#define PERM_SRC_ID__SRCID 0x00ff +#define PERM_SRC_ID__DIRECT_ACCESS_ACTIVE 0x0800 +#define PERM_SRC_ID__WRITE_ACTIVE 0x2000 +#define PERM_SRC_ID__READ_ACTIVE 0x4000 +#define PERM_SRC_ID__PARTITION_VALID 0x8000 + +#define MIN_BLK_ADDR(__bank) (0x840 + ((__bank) * 0x40)) +#define MIN_BLK_ADDR__VALUE 0xffff + +#define MAX_BLK_ADDR(__bank) (0x850 + ((__bank) * 0x40)) +#define MAX_BLK_ADDR__VALUE 0xffff + +#define MIN_MAX_BANK(__bank) (0x860 + ((__bank) * 0x40)) +#define MIN_MAX_BANK__MIN_VALUE 0x0003 +#define MIN_MAX_BANK__MAX_VALUE 0x000c + +/* lld.h */ +#define GOOD_BLOCK 0 +#define DEFECTIVE_BLOCK 1 +#define READ_ERROR 2 + +#define CLK_X 5 +#define CLK_MULTI 4 + +/* spectraswconfig.h */ +#define CMD_DMA 0 + +#define SPECTRA_PARTITION_ID 0 +/**** Block Table and Reserved Block Parameters *****/ +#define SPECTRA_START_BLOCK 3 +#define NUM_FREE_BLOCKS_GATE 30 + +/* KBV - Updated to LNW scratch register address */ +#define SCRATCH_REG_ADDR CONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR +#define SCRATCH_REG_SIZE 64 + +#define GLOB_HWCTL_DEFAULT_BLKS 2048 + +#define SUPPORT_15BITECC 1 +#define SUPPORT_8BITECC 1 + +#define CUSTOM_CONF_PARAMS 0 + +#define ONFI_BLOOM_TIME 1 +#define MODE5_WORKAROUND 0 + +/* lld_nand.h */ +/* + * NAND Flash Controller Device Driver + * Copyright (c) 2009, Intel Corporation and its suppliers. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * + */ + +#ifndef _LLD_NAND_ +#define _LLD_NAND_ + +#define MODE_00 0x00000000 +#define MODE_01 0x04000000 +#define MODE_10 0x08000000 +#define MODE_11 0x0C000000 + + +#define DATA_TRANSFER_MODE 0 +#define PROTECTION_PER_BLOCK 1 +#define LOAD_WAIT_COUNT 2 +#define PROGRAM_WAIT_COUNT 3 +#define ERASE_WAIT_COUNT 4 +#define INT_MONITOR_CYCLE_COUNT 5 +#define READ_BUSY_PIN_ENABLED 6 +#define MULTIPLANE_OPERATION_SUPPORT 7 +#define PRE_FETCH_MODE 8 +#define CE_DONT_CARE_SUPPORT 9 +#define COPYBACK_SUPPORT 10 +#define CACHE_WRITE_SUPPORT 11 +#define CACHE_READ_SUPPORT 12 +#define NUM_PAGES_IN_BLOCK 13 +#define ECC_ENABLE_SELECT 14 +#define WRITE_ENABLE_2_READ_ENABLE 15 +#define ADDRESS_2_DATA 16 +#define READ_ENABLE_2_WRITE_ENABLE 17 +#define TWO_ROW_ADDRESS_CYCLES 18 +#define MULTIPLANE_ADDRESS_RESTRICT 19 +#define ACC_CLOCKS 20 +#define READ_WRITE_ENABLE_LOW_COUNT 21 +#define READ_WRITE_ENABLE_HIGH_COUNT 22 + +#define ECC_SECTOR_SIZE 512 + +#define DENALI_BUF_SIZE (NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE) + +struct nand_buf { + int head; + int tail; + /* seprating dma_buf as buf can be used for status read purpose */ + uint8_t dma_buf[DENALI_BUF_SIZE] __aligned(64); + uint8_t buf[DENALI_BUF_SIZE]; +}; + +#define INTEL_CE4100 1 +#define INTEL_MRST 2 +#define DT 3 + +struct denali_nand_info { + struct mtd_info mtd; + struct nand_chip *nand; + + int flash_bank; /* currently selected chip */ + int status; + int platform; + struct nand_buf buf; + struct device *dev; + int total_used_banks; + uint32_t block; /* stored for future use */ + uint32_t page; + void __iomem *flash_reg; /* Mapped io reg base address */ + void __iomem *flash_mem; /* Mapped io reg base address */ + + /* elements used by ISR */ + /*struct completion complete;*/ + + uint32_t irq_status; + int irq_debug_array[32]; + int idx; + int irq; + + uint32_t devnum; /* represent how many nands connected */ + uint32_t fwblks; /* represent how many blocks FW used */ + uint32_t totalblks; + uint32_t blksperchip; + uint32_t bbtskipbytes; + uint32_t max_banks; +}; + +#endif /*_LLD_NAND_*/ -- 1.7.9.5

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[U-Boot] [PATCH] net: asix: don't pad odd-length TX packets
by Stephen Warren 10 Mar '14

10 Mar '14

From: Stephen Warren <swarren(a)nvidia.com> For Ethernet/USB RX packets, the ASIX HW pads odd-sized packets so that they have an even size. Currently, asix_recv() does remove this padding, and asic_send() adds equivalent padding in the TX path. However, the HW does not appear to need this packing for TX packets in practical testing with "ASIX Elec. Corp. AX88x72A 000001" Vendor: 0x0b95 Product 0x7720 Version 0.1. The Linux kernel does no such padding for the TX path. Remove the padding from the TX path: * For consistency with the Linux kernel. * NVIDIA has a Tegra simulator which validates that the length of USB packets sent to an ASIX device matches the packet length value inside the packet data. Having U-Boot and the kernel do the same thing when creating the TX packets simplifies the simulator's validation. Cc: Lucas Stach <dev(a)lynxeye.de> Cc: Marek Vasut <marex(a)denx.de> Cc: Simon Glass <sjg(a)chromium.org> Signed-off-by: Stephen Warren <swarren(a)nvidia.com> --- drivers/usb/eth/asix.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/usb/eth/asix.c b/drivers/usb/eth/asix.c index 659533a8d4e4..ce133f00698d 100644 --- a/drivers/usb/eth/asix.c +++ b/drivers/usb/eth/asix.c @@ -468,8 +468,6 @@ static int asix_send(struct eth_device *eth, void *packet, int length) memcpy(msg, &packet_len, sizeof(packet_len)); memcpy(msg + sizeof(packet_len), (void *)packet, length); - if (length & 1) - length++; err = usb_bulk_msg(dev->pusb_dev, usb_sndbulkpipe(dev->pusb_dev, dev->ep_out), -- 1.8.1.5

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[U-Boot] [PATCH] .gitignore: ignore include/config/*
by Masahiro Yamada 10 Mar '14

10 Mar '14

Signed-off-by: Masahiro Yamada <yamada.m(a)jp.panasonic.com> --- .gitignore | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/.gitignore b/.gitignore index ffe0cc7..cba5eac 100644 --- a/.gitignore +++ b/.gitignore @@ -51,6 +51,10 @@ /spl/* /tpl/ +# +# Generated include files +# +/include/config/ /include/generated/ /include/spl-autoconf.mk /include/tpl-autoconf.mk -- 1.8.3.2

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[U-Boot] [PATCH] kbuild: fix a bug of make rule of version_autogenerated.h
by Masahiro Yamada 10 Mar '14

10 Mar '14

include/generated/version_autogenerated.h was not correctly generated on the parallel build (with -j option). Signed-off-by: Masahiro Yamada <yamada.m(a)jp.panasonic.com> Reported-by: Andreas Bießmann <andreas.devel(a)googlemail.com> --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index ee16d8c..f3f3a2a 100644 --- a/Makefile +++ b/Makefile @@ -1022,7 +1022,7 @@ define filechk_timestamp.h LC_ALL=C date +'#define U_BOOT_TIME "%T"') endef -$(version_h): $(srctree)/Makefile FORCE +$(version_h): include/config/uboot.release FORCE $(call filechk,version.h) $(timestamp_h): $(srctree)/Makefile FORCE -- 1.8.3.2

2 1

[U-Boot] [PATCH] cfb_console: force natural alignment of unzipped bitmap images
by Eric Nelson 10 Mar '14

10 Mar '14

Bitmaps contain 32-bit integers aligned at offsets of +2, +6 within the bmp_header structure. This patch forces them to be aligned properly when gzipped bitmaps are used. Refer to these files for more details: doc/README.displaying-bmps doc/README.arm-unaligned-accesses Signed-off-by: Eric Nelson <eric.nelson(a)boundarydevices.com> --- drivers/video/cfb_console.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c index 6db4073..2209148 100644 --- a/drivers/video/cfb_console.c +++ b/drivers/video/cfb_console.c @@ -1473,7 +1473,10 @@ int video_display_bitmap(ulong bmp_image, int x, int y) printf("Error: malloc in gunzip failed!\n"); return 1; } - if (gunzip(dst, CONFIG_SYS_VIDEO_LOGO_MAX_SIZE, + /* NB: we need to force offset of +2 + * See doc/README.displaying-bmps + */ + if (gunzip(dst+2, CONFIG_SYS_VIDEO_LOGO_MAX_SIZE-2, (uchar *) bmp_image, &len) != 0) { printf("Error: no valid bmp or bmp.gz image at %lx\n", @@ -1489,7 +1492,7 @@ int video_display_bitmap(ulong bmp_image, int x, int y) /* * Set addr to decompressed image */ - bmp = (bmp_image_t *) dst; + bmp = (bmp_image_t *)(dst+2); if (!((bmp->header.signature[0] == 'B') && (bmp->header.signature[1] == 'M'))) { -- 1.8.3.2

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