December 2014 - U-Boot

[U-Boot] [PATCH v1 0/3] arm, am335x: siemens board updates
by Heiko Schocher 05 Dec '14

05 Dec '14

This series contains some updates for the am335x based boards from siemens. - Patch: arm, am335x, siemens: fix factoryset interpretation fixes an error in the siemens factoryset implementation - Patch: arm, am335x, siemens: read COMP/ver from factoryset reads also the "COMP/ver" value from the siemens factoryset - Patch: arm, am335x: siemens boards add FIT support - adds FIT support as we now boot kernels with DT - create a u-boot envvariable "boardid" which is used for selecting the DT from the FIT image. Heiko Schocher (3): arm, am335x, siemens: fix factoryset interpretation arm, am335x, siemens: read COMP/ver from factoryset arm, am335x: siemens boards add FIT support board/siemens/common/board.c | 9 ------- board/siemens/common/factoryset.c | 52 ++++++++++++++++++++++++++------------- board/siemens/common/factoryset.h | 2 ++ board/siemens/draco/board.c | 9 +++++++ board/siemens/pxm2/board.c | 34 +++++++++++++++++++++++++ board/siemens/rut/board.c | 23 +++++++++++++++++ include/configs/pxm2.h | 4 +++ include/configs/rut.h | 4 +++ 8 files changed, 111 insertions(+), 26 deletions(-) -- 1.8.3.1

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[U-Boot] [PATCH v2] mtd: nand: omap_gpmc: Always use ready/busy pin
by Stefan Roese 05 Dec '14

05 Dec '14

The functions to detect the state of the ready / busy signal is already available but only used in the SPL case. Lets use it always, also for the main U-Boot. As all boards should have this HW connection. Testing on Siemens Draco (am335x) showed a small perfomance gain by using this ready pin to detect the NAND chip state. Here the values tested on Draco with Hynix 4GBit NAND: Without NAND ready pin: U-Boot# time nand read 80400000 0 400000 NAND read: device 0 offset 0x0, size 0x400000 4194304 bytes read: OK time: 2.947 seconds, 2947 ticks With NAND ready pin: U-Boot# time nand read 80400000 0 400000 NAND read: device 0 offset 0x0, size 0x400000 4194304 bytes read: OK time: 2.795 seconds, 2795 ticks So an increase of approx. 5%. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Tom Rini <trini(a)ti.com> Cc: Scott Wood <scottwood(a)freescale.com> Cc: Roger Meier <r.meier(a)siemens.com> Cc: Samuel Egli <samuel.egli(a)siemens.com> --- v2: - Only one patch now in this series - Drop the new define and make this change unconditional drivers/mtd/nand/omap_gpmc.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index 40d6705..93829a4 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -73,14 +73,11 @@ static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd, writeb(cmd, this->IO_ADDR_W); } -#ifdef CONFIG_SPL_BUILD /* Check wait pin as dev ready indicator */ -static int omap_spl_dev_ready(struct mtd_info *mtd) +static int omap_dev_ready(struct mtd_info *mtd) { return gpmc_cfg->status & (1 << 8); } -#endif - /* * gen_true_ecc - This function will generate true ECC value, which @@ -887,7 +884,9 @@ int board_nand_init(struct nand_chip *nand) nand->read_buf = nand_read_buf16; else nand->read_buf = nand_read_buf; - nand->dev_ready = omap_spl_dev_ready; #endif + + nand->dev_ready = omap_dev_ready; + return 0; } -- 2.1.3

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[U-Boot] [PATCH] arm: am33xx: Handle NAND+I2C boot-device the same way as NAND
by Stefan Roese 05 Dec '14

05 Dec '14

Re-map NAND&I2C boot-device to the "normal" NAND boot-device. Otherwise the SPL boot IF can't handle this device correctly. Somehow booting with Hynix 4GBit NAND H27U4G8 on Siemens Draco leads to this boot-device passed to SPL from the BootROM. With this change, Draco boots just fine into main U-Boot. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Tom Rini <trini(a)ti.com> Cc: Roger Meier <r.meier(a)siemens.com> Cc: Samuel Egli <samuel.egli(a)siemens.com> --- arch/arm/cpu/armv7/omap-common/boot-common.c | 15 +++++++++++++-- arch/arm/include/asm/arch-am33xx/spl.h | 1 + 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c index fb535eb..14791e4 100644 --- a/arch/arm/cpu/armv7/omap-common/boot-common.c +++ b/arch/arm/cpu/armv7/omap-common/boot-common.c @@ -33,8 +33,19 @@ void save_omap_boot_params(void) * used. But it not correct to assume that romcode structure * encoding would be same as u-boot. So use the defined offsets. */ - gd->arch.omap_boot_params.omap_bootdevice = boot_device = - *((u8 *)(rom_params + BOOT_DEVICE_OFFSET)); + boot_device = *((u8 *)(rom_params + BOOT_DEVICE_OFFSET)); + +#if defined(BOOT_DEVICE_NAND_I2C) + /* + * Re-map NAND&I2C boot-device to the "normal" NAND boot-device. + * Otherwise the SPL boot IF can't handle this device correctly. + * Somehow booting with Hynix 4GBit NAND H27U4G8 on Siemens + * Draco leads to this boot-device passed to SPL from the BootROM. + */ + if (boot_device == BOOT_DEVICE_NAND_I2C) + boot_device = BOOT_DEVICE_NAND; +#endif + gd->arch.omap_boot_params.omap_bootdevice = boot_device; gd->arch.omap_boot_params.ch_flags = *((u8 *)(rom_params + CH_FLAGS_OFFSET)); diff --git a/arch/arm/include/asm/arch-am33xx/spl.h b/arch/arm/include/asm/arch-am33xx/spl.h index 8543f43..e756418 100644 --- a/arch/arm/include/asm/arch-am33xx/spl.h +++ b/arch/arm/include/asm/arch-am33xx/spl.h @@ -25,6 +25,7 @@ #else #define BOOT_DEVICE_XIP 2 #define BOOT_DEVICE_NAND 5 +#define BOOT_DEVICE_NAND_I2C 6 #if defined(CONFIG_AM33XX) #define BOOT_DEVICE_MMC1 8 #define BOOT_DEVICE_MMC2 9 /* eMMC or daughter card */ -- 2.1.3

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[U-Boot] [PATCH 01/11] arm: omap5: don't enable misc_init_r by default
by Felipe Balbi 05 Dec '14

05 Dec '14

Out of all OMAP5-like boards, only one of them needs CONFIG_MISC_INIT_R, so it's best to enable that for that particular board only, instead of enabling for all boards unconditionally. Signed-off-by: Felipe Balbi <balbi(a)ti.com> --- board/ti/dra7xx/evm.c | 12 ------------ include/configs/cm_t54.h | 1 - include/configs/omap5_uevm.h | 1 + include/configs/ti_omap5_common.h | 1 - 4 files changed, 1 insertion(+), 14 deletions(-) diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 37df7b2..6522241 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -96,18 +96,6 @@ int board_late_init(void) return 0; } -/** - * @brief misc_init_r - Configure EVM board specific configurations - * such as power configurations, ethernet initialization as phase2 of - * boot sequence - * - * @return 0 - */ -int misc_init_r(void) -{ - return 0; -} - static void do_set_mux32(u32 base, struct pad_conf_entry const *array, int size) { diff --git a/include/configs/cm_t54.h b/include/configs/cm_t54.h index 641ab48..92ce1e1 100644 --- a/include/configs/cm_t54.h +++ b/include/configs/cm_t54.h @@ -16,7 +16,6 @@ #include <configs/ti_omap5_common.h> -#undef CONFIG_MISC_INIT_R #undef CONFIG_SPL_OS_BOOT /* Enable Generic board */ diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index e8dc462..e07795f 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -23,6 +23,7 @@ #define CONFIG_SYS_NS16550_COM3 UART3_BASE #define CONFIG_BAUDRATE 115200 +#define CONFIG_MISC_INIT_R /* MMC ENV related defines */ #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */ diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index 3166392..5b03fb1 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -19,7 +19,6 @@ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_MISC_INIT_R #define CONFIG_ARCH_CPU_INIT #define CONFIG_SYS_CACHELINE_SIZE 64 -- 2.1.0.GIT

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[U-Boot] Fix for ns16550 driver hanging on OMAP4
by Gregoire Gentil 05 Dec '14

05 Dec '14

Here is a patch to apply the same fix on OMAP4 boards as on OMAP3, in order to prevent ns16550 hanging during SPL boot, Grégoire diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 8f05191..a1d3781 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -132,9 +132,9 @@ static void NS16550_setbrg(NS16550_t com_port, int baud_divisor) void NS16550_init(NS16550_t com_port, int baud_divisor) { -#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_OMAP34XX)) +#if (defined(CONFIG_SPL_BUILD) && (defined(CONFIG_OMAP34XX) || defined(CONFIG_OMAP44XX))) /* - * On some OMAP3 devices when UART3 is configured for boot mode before + * On some OMAP3/OMAP4 devices when UART3 is configured for boot mode before * SPL starts only THRE bit is set. We have to empty the transmitter * before initialization starts. */ Grégoire

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[U-Boot] [PATCH] ARM: OMAP5: DRA7xx: Fix misleading comments in mux_data.h
by Lubomir Popov 05 Dec '14

05 Dec '14

The comments on the QSPI pad assignments erronously swapped the qspi1_d0 and qspi1_d1 functionality and could cause confusion. QSPI1_D[0] is in fact muxed on pad U1 (gpmc_a16), and QSPI1_D[1] - on pad P3 (gpmc_a17). Fixing comments. Signed-off-by: Lubomir Popov <l-popov(a)ti.com> --- board/ti/dra7xx/mux_data.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h index 7276014..4824077 100644 --- a/board/ti/dra7xx/mux_data.h +++ b/board/ti/dra7xx/mux_data.h @@ -130,8 +130,8 @@ const struct pad_conf_entry core_padconf_array_essential[] = { {GPMC_A13, (IEN | PDIS | M1)}, /* QSPI1_RTCLK */ {GPMC_A14, (IEN | PDIS | M1)}, /* QSPI1_D[3] */ {GPMC_A15, (IEN | PDIS | M1)}, /* QSPI1_D[2] */ - {GPMC_A16, (IEN | PDIS | M1)}, /* QSPI1_D[1] */ - {GPMC_A17, (IEN | PDIS | M1)}, /* QSPI1_D[0] */ + {GPMC_A16, (IEN | PDIS | M1)}, /* QSPI1_D[0] */ + {GPMC_A17, (IEN | PDIS | M1)}, /* QSPI1_D[1] */ {GPMC_A18, (M1)}, /* QSPI1_SCLK */ {GPMC_A3, (IEN | PDIS | M1)}, /* QSPI1_CS2 */ {GPMC_A4, (IEN | PDIS | M1)}, /* QSPI1_CS3 */ -- 1.7.9.5

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[U-Boot] [PATCH] ARM: OMAP5: DRA7xx: Enable 8-bit eMMC access on the dra7xx_evm
by Lubomir Popov 05 Dec '14

05 Dec '14

Tested on a Vayu EVM Rev.E2 with DRA752 ES1.1 Signed-off-by: Lubomir Popov <l-popov(a)ti.com> --- include/configs/dra7xx_evm.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 2eaabde..174a711 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -50,6 +50,7 @@ #define CONFIG_EFI_PARTITION #define CONFIG_PARTITION_UUIDS #define CONFIG_CMD_PART +#define CONFIG_HSMMC2_8BIT /* CPSW Ethernet */ #define CONFIG_CMD_NET /* 'bootp' and 'tftp' */ -- 1.7.9.5

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[U-Boot] [PATCH v4 0/3] mmc: Board-specific MMC power initializations
by Paul Kocialkowski 05 Dec '14

05 Dec '14

Changelog: v4: * Switch board_mmc_power_init to void since there is no return value check * Add dev_index to twl4030_power_mmc_init, common ramp-up delay * twl4030_power_mmc_init call with the relevant dev_index on boards * No check against CONFIG_TWL4030_POWER (an obvious linker error is better than a strange runtime error) v3: Changes to make v2 apply on master v2: Implement board_mmc_power_init instead of define

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[U-Boot] [PATCH 00/25] x86: Add Intel Queensbay platform support
by Bin Meng 05 Dec '14

05 Dec '14

This patch series add the Intel Queensbay platform support. The Queensbay platform includes an Atom E6xx processor (codename Tunnel Creek) and a Platform Controller Hub EG20T (codename Topcliff). The support depends on Intel Firmware Support Package (FSP) to initialize the processor and chipset including system memory. With this patch series, U-Boot boots to Linux kernel. Validated on an Intel Crown Bay board with kernel 3.17. Note I did not clean up the original FSP codes released by Intel with U-Boot coding convention. So there will be coding style issues reported by the patch checkers against patch#11 and #12 in this series. Bin Meng (25): x86: Make ROM_SIZE configurable in Kconfig tools/ifdtool: Support writing multiple files (-w) simultaneously x86: Refactor u-boot.rom build rules x86: Clean up asm-offsets x86: ich6-gpio: Make setup_pch_gpios() a weak function x86: Add Intel Crown Bay board dts file x86: Add a simple superio driver for SMSC LPC47M x86: Add Intel Topcliff PCH device IDs x86: ich-spi: Add Intel Tunnel Creek SPI controller support x86: ich6-gpio: Add Intel Tunnel Creek GPIO support x86: Initial import from Intel FSP release for Queensbay platform x86: queensbay: Adapt FSP support codes x86: Add post failure codes for bist and car x86: Support Intel FSP initialization path in start.S x86: Add a simple command to show FSP HOB information x86: Integrate Tunnel Creek processor microcode x86: Add basic support to queensbay platform and crownbay board x86: Add queensbay and crownbay Kconfig files x86: Add crownbay defconfig and config.h x86: Enable the queensbay cpu directory build x86: Include FSP and CMC binary in the u-boot.rom build rules x86: crownbay: Add SPI flash support x86: crownbay: Enable Intel E1000 NIC support x86: crownbay: Add SDHCI support x86: Add a README.x86 for U-Boot on x86 support Makefile | 56 +- arch/x86/Kconfig | 91 +- arch/x86/cpu/Makefile | 1 + arch/x86/cpu/ivybridge/cpu.c | 1 + arch/x86/cpu/queensbay/Kconfig | 75 ++ arch/x86/cpu/queensbay/M0220661105.inc | 1288 ++++++++++++++++++++ arch/x86/cpu/queensbay/Makefile | 9 + arch/x86/cpu/queensbay/fsp_configs.c | 36 + arch/x86/cpu/queensbay/fsp_support.c | 635 ++++++++++ arch/x86/cpu/queensbay/tnc.c | 72 ++ arch/x86/cpu/queensbay/tnc_car.S | 75 ++ arch/x86/cpu/queensbay/tnc_dram.c | 81 ++ arch/x86/cpu/queensbay/tnc_pci.c | 62 + arch/x86/cpu/queensbay/topcliff.c | 44 + arch/x86/cpu/start.S | 40 +- arch/x86/dts/Makefile | 3 +- arch/x86/dts/crownbay.dts | 53 + arch/x86/include/asm/arch-ivybridge/gpio.h | 3 + arch/x86/include/asm/arch-queensbay/fsp/fsp_api.h | 84 ++ .../include/asm/arch-queensbay/fsp/fsp_bootmode.h | 30 + arch/x86/include/asm/arch-queensbay/fsp/fsp_ffs.h | 482 ++++++++ arch/x86/include/asm/arch-queensbay/fsp/fsp_fv.h | 223 ++++ arch/x86/include/asm/arch-queensbay/fsp/fsp_hob.h | 400 ++++++ .../asm/arch-queensbay/fsp/fsp_infoheader.h | 94 ++ .../include/asm/arch-queensbay/fsp/fsp_platform.h | 21 + .../include/asm/arch-queensbay/fsp/fsp_support.h | 140 +++ .../x86/include/asm/arch-queensbay/fsp/fsp_types.h | 198 +++ arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h | 57 + arch/x86/include/asm/arch-queensbay/gpio.h | 13 + arch/x86/include/asm/global_data.h | 3 + arch/x86/include/asm/gpio.h | 2 +- arch/x86/include/asm/pnp_def.h | 83 ++ arch/x86/include/asm/post.h | 2 + arch/x86/lib/Makefile | 1 + arch/x86/lib/asm-offsets.c | 5 +- arch/x86/lib/cmd_hob.c | 71 ++ board/google/chromebook_link/Kconfig | 1 + board/google/chromebook_link/link.c | 40 + board/intel/crownbay/Kconfig | 20 + board/intel/crownbay/MAINTAINERS | 6 + board/intel/crownbay/Makefile | 7 + board/intel/crownbay/crownbay.c | 26 + board/intel/crownbay/start.S | 9 + configs/crownbay_defconfig | 6 + doc/README.x86 | 123 ++ drivers/gpio/intel_ich6_gpio.c | 67 +- drivers/misc/Makefile | 1 + drivers/misc/smsc_lpc47m.c | 31 + drivers/spi/ich.c | 3 +- include/configs/crownbay.h | 61 + include/pci_ids.h | 8 + include/smsc_lpc47m.h | 19 + lib/asm-offsets.c | 3 - tools/ifdtool.c | 29 +- tools/ifdtool.h | 2 + 55 files changed, 4903 insertions(+), 93 deletions(-) create mode 100644 arch/x86/cpu/queensbay/Kconfig create mode 100644 arch/x86/cpu/queensbay/M0220661105.inc create mode 100644 arch/x86/cpu/queensbay/Makefile create mode 100644 arch/x86/cpu/queensbay/fsp_configs.c create mode 100644 arch/x86/cpu/queensbay/fsp_support.c create mode 100644 arch/x86/cpu/queensbay/tnc.c create mode 100644 arch/x86/cpu/queensbay/tnc_car.S create mode 100644 arch/x86/cpu/queensbay/tnc_dram.c create mode 100644 arch/x86/cpu/queensbay/tnc_pci.c create mode 100644 arch/x86/cpu/queensbay/topcliff.c create mode 100644 arch/x86/dts/crownbay.dts create mode 100644 arch/x86/include/asm/arch-queensbay/fsp/fsp_api.h create mode 100644 arch/x86/include/asm/arch-queensbay/fsp/fsp_bootmode.h create mode 100644 arch/x86/include/asm/arch-queensbay/fsp/fsp_ffs.h create mode 100644 arch/x86/include/asm/arch-queensbay/fsp/fsp_fv.h create mode 100644 arch/x86/include/asm/arch-queensbay/fsp/fsp_hob.h create mode 100644 arch/x86/include/asm/arch-queensbay/fsp/fsp_infoheader.h create mode 100644 arch/x86/include/asm/arch-queensbay/fsp/fsp_platform.h create mode 100644 arch/x86/include/asm/arch-queensbay/fsp/fsp_support.h create mode 100644 arch/x86/include/asm/arch-queensbay/fsp/fsp_types.h create mode 100644 arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h create mode 100644 arch/x86/include/asm/arch-queensbay/gpio.h create mode 100644 arch/x86/include/asm/pnp_def.h create mode 100644 arch/x86/lib/cmd_hob.c create mode 100644 board/intel/crownbay/Kconfig create mode 100644 board/intel/crownbay/MAINTAINERS create mode 100644 board/intel/crownbay/Makefile create mode 100644 board/intel/crownbay/crownbay.c create mode 100644 board/intel/crownbay/start.S create mode 100644 configs/crownbay_defconfig create mode 100644 doc/README.x86 create mode 100644 drivers/misc/smsc_lpc47m.c create mode 100644 include/configs/crownbay.h create mode 100644 include/smsc_lpc47m.h -- 1.8.2.1

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[U-Boot] [PATCH 24/25] x86: crownbay: Add SDHCI support
by Bin Meng 05 Dec '14

05 Dec '14

There are two standard SD card slots on the Crown Bay board, which are connected to the Topcliff PCH SDIO controllers. Enable the SDHC support so that we can use them. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- arch/x86/cpu/queensbay/Makefile | 2 +- arch/x86/cpu/queensbay/topcliff.c | 44 +++++++++++++++++++++++++++++++++++++++ include/configs/crownbay.h | 6 ++++++ 3 files changed, 51 insertions(+), 1 deletion(-) create mode 100644 arch/x86/cpu/queensbay/topcliff.c diff --git a/arch/x86/cpu/queensbay/Makefile b/arch/x86/cpu/queensbay/Makefile index ace04ca..2c2ec01 100644 --- a/arch/x86/cpu/queensbay/Makefile +++ b/arch/x86/cpu/queensbay/Makefile @@ -4,6 +4,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += tnc_car.o tnc_dram.o tnc.o +obj-y += tnc_car.o tnc_dram.o tnc.o topcliff.o obj-y += fsp_configs.o fsp_support.o obj-$(CONFIG_PCI) += tnc_pci.o diff --git a/arch/x86/cpu/queensbay/topcliff.c b/arch/x86/cpu/queensbay/topcliff.c new file mode 100644 index 0000000..4d2a24a --- /dev/null +++ b/arch/x86/cpu/queensbay/topcliff.c @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2014, Bin Meng <bmeng.cn(a)gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <malloc.h> +#include <pci.h> +#include <pci_ids.h> +#include <sdhci.h> + +static struct pci_device_id mmc_supported[] = { + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_0 }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_1 }, + { } +}; + +int cpu_mmc_init(bd_t *bis) +{ + struct sdhci_host *mmc_host; + pci_dev_t devbusfn; + u32 iobase; + int i; + + for (i = 0; i < 2; i++) { + devbusfn = pci_find_devices(mmc_supported, i); + if (devbusfn == -1) + return -ENODEV; + + mmc_host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host)); + if (!mmc_host) + return -ENOMEM; + + mmc_host->name = "Topcliff SDHCI"; + pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &iobase); + mmc_host->ioaddr = (void *)iobase; + mmc_host->quirks = 0; + add_sdhci(mmc_host, 0, 0); + } + + return 1; +} diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h index 09a52ab..b9db6b7 100644 --- a/include/configs/crownbay.h +++ b/include/configs/crownbay.h @@ -48,6 +48,12 @@ #define CONFIG_SPI_FLASH_SST +#define CONFIG_MMC +#define CONFIG_SDHCI +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC_SDMA +#define CONFIG_CMD_MMC + /* Video is not supported */ #undef CONFIG_VIDEO #undef CONFIG_CFB_CONSOLE -- 1.8.2.1

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