December 2014 - U-Boot

[U-Boot] [PATCH 05/25] x86: ich6-gpio: Make setup_pch_gpios() a weak function
by Bin Meng 05 Dec '14

05 Dec '14

Define a weak verion of setup_pch_gpios() in the ich6-gpio driver and move the actual setup codes into the board support codes, so that the driver does not need to know any platform specific stuff (ie: include the platform specifc chipset header file). Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- arch/x86/include/asm/arch-coreboot/gpio.h | 3 ++ arch/x86/include/asm/arch-ivybridge/gpio.h | 3 ++ board/google/chromebook_link/link.c | 40 +++++++++++++++++++++++ drivers/gpio/intel_ich6_gpio.c | 52 +++--------------------------- 4 files changed, 50 insertions(+), 48 deletions(-) diff --git a/arch/x86/include/asm/arch-coreboot/gpio.h b/arch/x86/include/asm/arch-coreboot/gpio.h index 4951a8c..31edef9 100644 --- a/arch/x86/include/asm/arch-coreboot/gpio.h +++ b/arch/x86/include/asm/arch-coreboot/gpio.h @@ -7,4 +7,7 @@ #ifndef _X86_ARCH_GPIO_H_ #define _X86_ARCH_GPIO_H_ +/* Where in config space is the register that points to the GPIO registers? */ +#define PCI_CFG_GPIOBASE 0x48 + #endif /* _X86_ARCH_GPIO_H_ */ diff --git a/arch/x86/include/asm/arch-ivybridge/gpio.h b/arch/x86/include/asm/arch-ivybridge/gpio.h index 4951a8c..31edef9 100644 --- a/arch/x86/include/asm/arch-ivybridge/gpio.h +++ b/arch/x86/include/asm/arch-ivybridge/gpio.h @@ -7,4 +7,7 @@ #ifndef _X86_ARCH_GPIO_H_ #define _X86_ARCH_GPIO_H_ +/* Where in config space is the register that points to the GPIO registers? */ +#define PCI_CFG_GPIOBASE 0x48 + #endif /* _X86_ARCH_GPIO_H_ */ diff --git a/board/google/chromebook_link/link.c b/board/google/chromebook_link/link.c index 1822237..4d95c1c 100644 --- a/board/google/chromebook_link/link.c +++ b/board/google/chromebook_link/link.c @@ -7,6 +7,9 @@ #include <common.h> #include <cros_ec.h> #include <asm/gpio.h> +#include <asm/io.h> +#include <asm/pci.h> +#include <asm/arch/pch.h> int arch_early_init_r(void) { @@ -121,3 +124,40 @@ int board_early_init_f(void) return 0; } + +void setup_pch_gpios(u32 gpiobase, const struct pch_gpio_map *gpio) +{ + /* GPIO Set 1 */ + if (gpio->set1.level) + outl(*((u32 *)gpio->set1.level), gpiobase + GP_LVL); + if (gpio->set1.mode) + outl(*((u32 *)gpio->set1.mode), gpiobase + GPIO_USE_SEL); + if (gpio->set1.direction) + outl(*((u32 *)gpio->set1.direction), gpiobase + GP_IO_SEL); + if (gpio->set1.reset) + outl(*((u32 *)gpio->set1.reset), gpiobase + GP_RST_SEL1); + if (gpio->set1.invert) + outl(*((u32 *)gpio->set1.invert), gpiobase + GPI_INV); + if (gpio->set1.blink) + outl(*((u32 *)gpio->set1.blink), gpiobase + GPO_BLINK); + + /* GPIO Set 2 */ + if (gpio->set2.level) + outl(*((u32 *)gpio->set2.level), gpiobase + GP_LVL2); + if (gpio->set2.mode) + outl(*((u32 *)gpio->set2.mode), gpiobase + GPIO_USE_SEL2); + if (gpio->set2.direction) + outl(*((u32 *)gpio->set2.direction), gpiobase + GP_IO_SEL2); + if (gpio->set2.reset) + outl(*((u32 *)gpio->set2.reset), gpiobase + GP_RST_SEL2); + + /* GPIO Set 3 */ + if (gpio->set3.level) + outl(*((u32 *)gpio->set3.level), gpiobase + GP_LVL3); + if (gpio->set3.mode) + outl(*((u32 *)gpio->set3.mode), gpiobase + GPIO_USE_SEL3); + if (gpio->set3.direction) + outl(*((u32 *)gpio->set3.direction), gpiobase + GP_IO_SEL3); + if (gpio->set3.reset) + outl(*((u32 *)gpio->set3.reset), gpiobase + GP_RST_SEL3); +} diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c index b095d17..3a2e1b0 100644 --- a/drivers/gpio/intel_ich6_gpio.c +++ b/drivers/gpio/intel_ich6_gpio.c @@ -34,16 +34,9 @@ #include <asm/gpio.h> #include <asm/io.h> #include <asm/pci.h> -#ifdef CONFIG_X86_RESET_VECTOR -#include <asm/arch/pch.h> -#define SUPPORT_GPIO_SETUP -#endif #define GPIO_PER_BANK 32 -/* Where in config space is the register that points to the GPIO registers? */ -#define PCI_CFG_GPIOBASE 0x48 - struct ich6_bank_priv { /* These are I/O addresses */ uint32_t use_sel; @@ -51,44 +44,9 @@ struct ich6_bank_priv { uint32_t lvl; }; -#ifdef SUPPORT_GPIO_SETUP -static void setup_pch_gpios(const struct pch_gpio_map *gpio) +__weak void setup_pch_gpios(u32 gpiobase, const struct pch_gpio_map *gpio) { - u16 gpiobase = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; - - /* GPIO Set 1 */ - if (gpio->set1.level) - outl(*((u32 *)gpio->set1.level), gpiobase + GP_LVL); - if (gpio->set1.mode) - outl(*((u32 *)gpio->set1.mode), gpiobase + GPIO_USE_SEL); - if (gpio->set1.direction) - outl(*((u32 *)gpio->set1.direction), gpiobase + GP_IO_SEL); - if (gpio->set1.reset) - outl(*((u32 *)gpio->set1.reset), gpiobase + GP_RST_SEL1); - if (gpio->set1.invert) - outl(*((u32 *)gpio->set1.invert), gpiobase + GPI_INV); - if (gpio->set1.blink) - outl(*((u32 *)gpio->set1.blink), gpiobase + GPO_BLINK); - - /* GPIO Set 2 */ - if (gpio->set2.level) - outl(*((u32 *)gpio->set2.level), gpiobase + GP_LVL2); - if (gpio->set2.mode) - outl(*((u32 *)gpio->set2.mode), gpiobase + GPIO_USE_SEL2); - if (gpio->set2.direction) - outl(*((u32 *)gpio->set2.direction), gpiobase + GP_IO_SEL2); - if (gpio->set2.reset) - outl(*((u32 *)gpio->set2.reset), gpiobase + GP_RST_SEL2); - - /* GPIO Set 3 */ - if (gpio->set3.level) - outl(*((u32 *)gpio->set3.level), gpiobase + GP_LVL3); - if (gpio->set3.mode) - outl(*((u32 *)gpio->set3.mode), gpiobase + GPIO_USE_SEL3); - if (gpio->set3.direction) - outl(*((u32 *)gpio->set3.direction), gpiobase + GP_IO_SEL3); - if (gpio->set3.reset) - outl(*((u32 *)gpio->set3.reset), gpiobase + GP_RST_SEL3); + return; } /* TODO: Move this to device tree, or platform data */ @@ -96,7 +54,6 @@ void ich_gpio_set_gpio_map(const struct pch_gpio_map *map) { gd->arch.gpio_map = map; } -#endif /* SUPPORT_GPIO_SETUP */ static int gpio_ich6_ofdata_to_platdata(struct udevice *dev) { @@ -198,12 +155,11 @@ static int ich6_gpio_probe(struct udevice *dev) struct gpio_dev_priv *uc_priv = dev->uclass_priv; struct ich6_bank_priv *bank = dev_get_priv(dev); -#ifdef SUPPORT_GPIO_SETUP if (gd->arch.gpio_map) { - setup_pch_gpios(gd->arch.gpio_map); + setup_pch_gpios(plat->base_addr, gd->arch.gpio_map); gd->arch.gpio_map = NULL; } -#endif + uc_priv->gpio_count = GPIO_PER_BANK; uc_priv->bank_name = plat->bank_name; bank->use_sel = plat->base_addr; -- 1.8.2.1

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[U-Boot] [PATCH 02/25] tools/ifdtool: Support writing multiple files (-w) simultaneously
by Bin Meng 05 Dec '14

05 Dec '14

Currently ifdtool only supports writing one file (-w) at a time. This looks verbose when generating u-boot.rom for x86 targets. This change allows at most 16 files to be written simultaneously. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- tools/ifdtool.c | 29 ++++++++++++++++++++++------- tools/ifdtool.h | 2 ++ 2 files changed, 24 insertions(+), 7 deletions(-) diff --git a/tools/ifdtool.c b/tools/ifdtool.c index a4b481f..58640ca 100644 --- a/tools/ifdtool.c +++ b/tools/ifdtool.c @@ -732,6 +732,7 @@ static void print_usage(const char *name) " -x | --extract: extract intel fd modules\n" " -i | --inject <region>:<module> inject file <module> into region <region>\n" " -w | --write <addr>:<file> write file to appear at memory address <addr>\n" + " multiple files can be written simultaneously\n" " -s | --spifreq <20|33|50> set the SPI frequency\n" " -e | --em100 set SPI frequency to 20MHz and disable\n" " Dual Output Fast Read Support\n" @@ -782,7 +783,9 @@ int main(int argc, char *argv[]) char *addr_str = NULL; int region_type = -1, inputfreq = 0; enum spi_frequency spifreq = SPI_FREQUENCY_20MHZ; - unsigned int addr = 0; + unsigned int addr[WRITE_NUM] = { 0 }; + char *wr_fname[WRITE_NUM] = { NULL }; + unsigned char wr_idx, wr_num = 0; int rom_size = -1; bool write_it; char *filename; @@ -886,11 +889,17 @@ int main(int argc, char *argv[]) break; case 'w': mode_write = 1; - if (get_two_words(optarg, &addr_str, &src_fname)) { - print_usage(argv[0]); - exit(EXIT_FAILURE); + if (wr_num < WRITE_NUM) { + if (get_two_words(optarg, &addr_str, + &wr_fname[wr_num])) { + print_usage(argv[0]); + exit(EXIT_FAILURE); + } + addr[wr_num] = strtol(optarg, NULL, 0); + wr_num++; + } else { + fprintf(stderr, "The number of files to write simultaneously exceeds the limitation (%d)\n", WRITE_NUM); } - addr = strtol(optarg, NULL, 0); break; case 'x': mode_extract = 1; @@ -1002,8 +1011,14 @@ int main(int argc, char *argv[]) if (mode_inject) ret = inject_region(image, size, region_type, src_fname); - if (mode_write) - ret = write_data(image, size, addr, src_fname); + if (mode_write) { + for (wr_idx = 0; wr_idx < wr_num; wr_idx++) { + ret = write_data(image, size, + addr[wr_idx], wr_fname[wr_idx]); + if (ret) + break; + } + } if (mode_spifreq) set_spi_frequency(image, size, spifreq); diff --git a/tools/ifdtool.h b/tools/ifdtool.h index fbec421..72ba1de 100644 --- a/tools/ifdtool.h +++ b/tools/ifdtool.h @@ -14,6 +14,8 @@ #define IFDTOOL_VERSION "1.1-U-Boot" +#define WRITE_NUM 16 + enum spi_frequency { SPI_FREQUENCY_20MHZ = 0, SPI_FREQUENCY_33MHZ = 1, -- 1.8.2.1

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[U-Boot] U-Boot crashes and keeps rebooting when upgraded DDR to 1GB from 512 MB
by KK_82 05 Dec '14

05 Dec '14

Hi, I've been facing this issue where u-boot continuously reboots. I'm using Freescale MPC83XX system and upgraded DDR in my box to 1GB from 512 MB. U-Boot detects the DDR size as 1GB but while doing data walk on chip select 2 it reboots. I tried following things but nothing worked: 1. Disabled PCI support to avoid higher memory occupation by PCI driver 2. I disabled chip select data walk code 3. Validated Hardware by running vxworks bootloader on the box 4. Verified all the base address, DDR registers addresses and their values. Does anybody have faced similar kind of problem? Please share you views. Thanks & Regards KK -- View this message in context: http://u-boot.10912.n7.nabble.com/U-Boot-crashes-and-keeps-rebooting-when-u… Sent from the U-Boot mailing list archive at Nabble.com.

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Re: [U-Boot] Hi Simon, Problems about RSA public exponents for verified boot
by Simon Glass 05 Dec '14

05 Dec '14

+Michael, U-Boot mailing list Hi, On 30 November 2014 at 19:26, Duxiaoqiang <duxiaoqiang(a)huawei.com> wrote: > > Hi Simon > > > > When I test verified boot with new version of U-boot and new version of mkimage, I encountered a alignment problem about RSA public key exponents. > > > > I tested verified boot successful few months ago with version of 2014.07-rc4, but failed with the same configuration and operations this time. > > > > Problem logs as below: > > > > > > I debug this problem and noticed that the problem was caused by pulic_exponent’s address: 0xff78a04c, this address was not aligned to 8 byte, but this address was pointed by a uint64 * type of pointer. > > Panic happened in function rsa_verify_with_keynode, just as below: > > > > By compared the u-boot.dtb file that signed with RSA public key, I noticed that there are differences about PUBLIC_EXPONENT. > > With the older version of mkimage, there’s no public exponent section. And this problem only happens when I use the new version of mkimage tool. > > > > I also checked uboot’s code, it seems that there’s lack of mechanism to guarantee the alignment about public exponent section. > > > > Can you give some suggestions about this problem. Appreciate your time. Copying Michael. Perhaps we need a safer version of fdt64_to_cpu()? But you might be the first to run this on aarch64. I have not tried it yet, but I do now have a platform. Regards, Simon

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[U-Boot] [PATCH 23/25] x86: crownbay: Enable Intel E1000 NIC support
by Bin Meng 05 Dec '14

05 Dec '14

We don't have driver for the Intel Topcliff PCH Gigabit Ethernet controller for now, so enable the Intle E1000 NIC support, which can be plugged into any PCIe slot on the Crown Bay board. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- board/intel/crownbay/crownbay.c | 6 ++++++ include/configs/crownbay.h | 1 + 2 files changed, 7 insertions(+) diff --git a/board/intel/crownbay/crownbay.c b/board/intel/crownbay/crownbay.c index bbd2596..d2d74a5 100644 --- a/board/intel/crownbay/crownbay.c +++ b/board/intel/crownbay/crownbay.c @@ -6,6 +6,7 @@ #include <common.h> #include <asm/pnp_def.h> +#include <netdev.h> #include <smsc_lpc47m.h> #define SERIAL_DEV PNP_DEV(0x2e, 4) @@ -18,3 +19,8 @@ int board_early_init_f(void) lpc47m_enable_serial(SERIAL_DEV, UART0_BASE); return 0; } + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h index a051b11..09a52ab 100644 --- a/include/configs/crownbay.h +++ b/include/configs/crownbay.h @@ -37,6 +37,7 @@ #define CONFIG_SYS_EARLY_PCI_INIT #define CONFIG_PCI_PNP +#define CONFIG_E1000 #define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \ "stdout=serial\0" \ -- 1.8.2.1

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[U-Boot] [PATCH 20/25] x86: Enable the queensbay cpu directory build
by Bin Meng 05 Dec '14

05 Dec '14

Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- arch/x86/cpu/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index 7f09db5..5033d2b 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -15,6 +15,7 @@ obj-y += interrupts.o cpu.o call64.o obj-$(CONFIG_SYS_COREBOOT) += coreboot/ obj-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += ivybridge/ obj-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ivybridge/ +obj-$(CONFIG_INTEL_QUEENSBAY) += queensbay/ obj-y += lapic.o obj-$(CONFIG_PCI) += pci.o obj-y += turbo.o -- 1.8.2.1

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[U-Boot] [PATCH 13/25] x86: Add post failure codes for bist and car
by Bin Meng 04 Dec '14

04 Dec '14

Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- arch/x86/cpu/ivybridge/cpu.c | 1 + arch/x86/include/asm/post.h | 2 ++ 2 files changed, 3 insertions(+) diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index 60976db..969b07b 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -263,6 +263,7 @@ static void enable_usb_bar(void) static int report_bist_failure(void) { if (gd->arch.bist != 0) { + post_code(POST_BIST_FAILURE); printf("BIST failed: %08x\n", gd->arch.bist); return -EFAULT; } diff --git a/arch/x86/include/asm/post.h b/arch/x86/include/asm/post.h index 6d2ae5d..f49ce99 100644 --- a/arch/x86/include/asm/post.h +++ b/arch/x86/include/asm/post.h @@ -33,6 +33,8 @@ #define POST_LAPIC 0x30 #define POST_RAM_FAILURE 0xea +#define POST_BIST_FAILURE 0xeb +#define POST_CAR_FAILURE 0xec /* Output a post code using al - value must be 0 to 0xff */ #ifdef __ASSEMBLY__ -- 1.8.2.1

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[U-Boot] [PATCH 09/25] x86: ich-spi: Add Intel Tunnel Creek SPI controller support
by Bin Meng 04 Dec '14

04 Dec '14

Add Intel Tunnel Creek SPI controller support which is an ICH7 compatible device. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- drivers/spi/ich.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index f5c6f3e..0e00edf 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -158,7 +158,8 @@ void spi_free_slave(struct spi_slave *slave) */ static int get_ich_version(uint16_t device_id) { - if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC) + if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC || + device_id == PCI_DEVICE_ID_INTEL_ITC_LPC) return 7; if ((device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN && -- 1.8.2.1

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[U-Boot] [PATCH 08/25] x86: Add Intel Topcliff PCH device IDs
by Bin Meng 04 Dec '14

04 Dec '14

Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- include/pci_ids.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/pci_ids.h b/include/pci_ids.h index ee98bee..26f4748 100644 --- a/include/pci_ids.h +++ b/include/pci_ids.h @@ -2998,6 +2998,14 @@ #define PCI_DEVICE_ID_INTEL_82454NX 0x84cb #define PCI_DEVICE_ID_INTEL_84460GX 0x84ea #define PCI_DEVICE_ID_INTEL_IXP4XX 0x8500 +#define PCI_DEVICE_ID_INTEL_TCF_GBE 0x8802 +#define PCI_DEVICE_ID_INTEL_TCF_SDIO_0 0x8809 +#define PCI_DEVICE_ID_INTEL_TCF_SDIO_1 0x880a +#define PCI_DEVICE_ID_INTEL_TCF_SATA 0x880b +#define PCI_DEVICE_ID_INTEL_TCF_UART_0 0x8811 +#define PCI_DEVICE_ID_INTEL_TCF_UART_1 0x8812 +#define PCI_DEVICE_ID_INTEL_TCF_UART_2 0x8813 +#define PCI_DEVICE_ID_INTEL_TCF_UART_3 0x8814 #define PCI_DEVICE_ID_INTEL_IXP2800 0x9004 #define PCI_DEVICE_ID_INTEL_S21152BB 0xb152 -- 1.8.2.1

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[U-Boot] [PATCH 06/25] x86: Add Intel Crown Bay board dts file
by Bin Meng 04 Dec '14

04 Dec '14

Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- arch/x86/dts/Makefile | 3 ++- arch/x86/dts/crownbay.dts | 53 +++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 55 insertions(+), 1 deletion(-) create mode 100644 arch/x86/dts/crownbay.dts diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile index bb3b116..3b5d6da 100644 --- a/arch/x86/dts/Makefile +++ b/arch/x86/dts/Makefile @@ -1,6 +1,7 @@ dtb-y += link.dtb \ chromebook_link.dtb \ - alex.dtb + alex.dtb \ + crownbay.dtb targets += $(dtb-y) diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts new file mode 100644 index 0000000..399dafb --- /dev/null +++ b/arch/x86/dts/crownbay.dts @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2014, Bin Meng <bmeng.cn(a)gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +/include/ "coreboot.dtsi" + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "Intel Crown Bay"; + compatible = "intel,crownbay", "intel,queensbay"; + + config { + silent_console = <0>; + }; + + gpioa { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0 0x20>; + bank-name = "A"; + }; + + gpiob { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x20 0x20>; + bank-name = "B"; + }; + + serial { + reg = <0x3f8 8>; + clock-frequency = <115200>; + }; + + chosen { }; + memory { device_type = "memory"; reg = <0 0>; }; + + spi { + #address-cells = <1>; + #size-cells = <0>; + compatible = "intel,ich7"; + spi-flash@0 { + reg = <0>; + compatible = "sst,25vf016b", "spi-flash"; + memory-map = <0xffe00000 0x00200000>; + }; + }; +}; -- 1.8.2.1

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