December 2014 - U-Boot

[U-Boot] [PATCH 0/6] ARM: atmel: enable usb ethernet gadget
by Bo Shen 19 Jan '15

19 Jan '15

This patch set enable the usb ethernet on SAMA5D4 base boards, including sama5d4ek and sama5d4_xplained board. Bo Shen (6): ARM: atmel: sama5d4: add usb platform data ARM: atmel: sama5d4: add usb device initial code ARM: atmel: sama5d4ek: add option for usb ethernet gadget ARM: atmel: sama5d4ek: enable usb ethernet gadget ARM: atmel: sama5d4_xplained: add option for usb ethernet gadget ARM: atmel: sama5d4_xplained: enable usb ethernet gadget arch/arm/cpu/armv7/at91/sama5d4_devices.c | 16 ++++++++++++++++ arch/arm/include/asm/arch-at91/atmel_usba_udc.h | 2 +- board/atmel/sama5d4_xplained/sama5d4_xplained.c | 11 +++++++++++ board/atmel/sama5d4ek/sama5d4ek.c | 11 +++++++++++ include/configs/sama5d4_xplained.h | 8 ++++++++ include/configs/sama5d4ek.h | 8 ++++++++ 6 files changed, 55 insertions(+), 1 deletion(-) -- 2.1.0.24.g4109c28

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[U-Boot] [PATCH] arm: at91: snapper9260: Drop invalid CONFIG_SKIP_RELOCATE_UBOOT
by Simon Glass 19 Jan '15

19 Jan '15

This config is not valid, so drop it. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- include/configs/snapper9260.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/configs/snapper9260.h b/include/configs/snapper9260.h index 942af2e..9fa644f 100644 --- a/include/configs/snapper9260.h +++ b/include/configs/snapper9260.h @@ -34,7 +34,6 @@ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SKIP_RELOCATE_UBOOT #define CONFIG_DISPLAY_CPUINFO #define CONFIG_FIT -- 2.2.0.rc0.207.ga3a616c

2 1

[U-Boot] [PATCH 1/2] arm, at91: corvus board updates
by Heiko Schocher 19 Jan '15

19 Jan '15

- corvus board fix problems with toshiba nand chips on the corvus board problems with toshiba chips Manufacturer ID: 0x98 Chip ID: 0xdc encounterd. Solve this in the following way: - set other nand timings - enable CONFIG_SYS_NAND_READY_PIN - correct the MACH_TYPE setting Signed-off-by: Heiko Schocher <hs(a)denx.de> --- board/siemens/corvus/board.c | 12 +++++++----- include/configs/corvus.h | 4 ++-- 2 files changed, 9 insertions(+), 7 deletions(-) diff --git a/board/siemens/corvus/board.c b/board/siemens/corvus/board.c index 0a11540..f3f6dae 100644 --- a/board/siemens/corvus/board.c +++ b/board/siemens/corvus/board.c @@ -43,13 +43,13 @@ static void corvus_nand_hw_init(void) writel(csa, &matrix->ebicsa); /* Configure SMC CS3 for NAND/SmartMedia */ - writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | - AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0), &smc->cs[3].setup); - writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) | - AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(2), + writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) | + AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4), &smc->cs[3].pulse); - writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(4), + writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7), &smc->cs[3].cycle); writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | AT91_SMC_MODE_EXNW_DISABLE | @@ -62,9 +62,11 @@ static void corvus_nand_hw_init(void) &smc->cs[3].mode); at91_periph_clk_enable(ATMEL_ID_PIOC); + at91_periph_clk_enable(ATMEL_ID_PIOA); /* Enable NandFlash */ at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); } #if defined(CONFIG_SPL_BUILD) diff --git a/include/configs/corvus.h b/include/configs/corvus.h index 5b50c1d..ace511f 100644 --- a/include/configs/corvus.h +++ b/include/configs/corvus.h @@ -18,6 +18,7 @@ #define MACH_TYPE_CORVUS 2066 +#define CONFIG_MACH_TYPE MACH_TYPE_CORVUS #define CONFIG_SYS_GENERIC_BOARD /* * Warning: changing CONFIG_SYS_TEXT_BASE requires @@ -106,6 +107,7 @@ /* our CLE is AD22 */ #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8 #endif /* Ethernet */ @@ -171,7 +173,6 @@ #define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_GPIO_SUPPORT -#define CONFIG_SYS_NAND_ENABLE_PIN_SPL (2*32 + 14) #define CONFIG_SPL_NAND_SUPPORT #define CONFIG_SPL_NAND_DRIVERS #define CONFIG_SPL_NAND_BASE @@ -184,7 +185,6 @@ #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_SIZE (256*1024*1024) #define CONFIG_SYS_NAND_PAGE_SIZE 2048 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ -- 1.8.3.1

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[U-Boot] [PATCH v1 0/3] arm, at91: taurus board updates
by Heiko Schocher 19 Jan '15

19 Jan '15

This series enables THUMB mode in SPL for the taurus board. On this hw are 16k only for SPL code, so THUMB mode is needed, because we need to detect the nor flash on the spi bus. This is needed because we want to erase sector 0 of the spi nor flash if the recovery button is pressed in SPL. Heiko Schocher (3): arm, arm926ejs: make thumb mode compileable arm, at91: enable thumb mode for taurus board in SPL taurus, spl: erase also spi flash if recovery button is pressed arch/arm/cpu/arm926ejs/cpu.c | 2 ++ arch/arm/lib/cache.c | 2 ++ board/siemens/taurus/taurus.c | 24 +++++++++++++++--------- include/configs/taurus.h | 23 ++++++++++++++++++++++- 4 files changed, 41 insertions(+), 10 deletions(-) -- 1.8.3.1

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[U-Boot] [PATCH] arm: mx6: Add Barco platinum-picon and platinum-titanium
by Stefan Roese 19 Jan '15

19 Jan '15

This patch adds the new Barco platinum platform. It currently includes those two boards: platinum-titanium ----------------- This is the same board as the titanium that is already supported in mainline U-Boot. But its now moved to this new platform to support multiple "flavors" of imx6 boards in one directory. Its also moved to support SPL booting. And with this we use the run-time DDR configuration of this SPL support. The board is equipped with the Micron MT41J128M16JT-125 DDR chips. We now can remove the DDR related registers tuples from the imximage.cfg file. As all this is done in the SPL at run-time. platinum-picon -------------- This board is new and based on the MX6DL with 1GiB DDR using the Micron MT41K256M16HA DDR3 chips. Its also equipped with 2 NAND chips (each 512MiB). Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Stefano Babic <sbabic(a)denx.de> Cc: Pieter Ronsijn <pieter.ronsijn(a)barco.com> --- arch/arm/Kconfig | 11 ++ board/barco/platinum/Kconfig | 37 ++++ board/barco/platinum/MAINTAINERS | 7 + board/barco/platinum/Makefile | 14 ++ board/barco/platinum/platinum.c | 217 +++++++++++++++++++++ board/barco/platinum/platinum.h | 88 +++++++++ board/barco/platinum/platinum_picon.c | 244 +++++++++++++++++++++++ board/barco/platinum/platinum_titanium.c | 209 ++++++++++++++++++++ board/barco/platinum/spl_picon.c | 182 ++++++++++++++++++ board/barco/platinum/spl_titanium.c | 185 ++++++++++++++++++ configs/platinum_picon_defconfig | 4 + configs/platinum_titanium_defconfig | 4 + include/configs/platinum.h | 319 +++++++++++++++++++++++++++++++ include/configs/platinum_picon.h | 31 +++ include/configs/platinum_titanium.h | 38 ++++ 15 files changed, 1590 insertions(+) create mode 100644 board/barco/platinum/Kconfig create mode 100644 board/barco/platinum/MAINTAINERS create mode 100644 board/barco/platinum/Makefile create mode 100644 board/barco/platinum/platinum.c create mode 100644 board/barco/platinum/platinum.h create mode 100644 board/barco/platinum/platinum_picon.c create mode 100644 board/barco/platinum/platinum_titanium.c create mode 100644 board/barco/platinum/spl_picon.c create mode 100644 board/barco/platinum/spl_titanium.c create mode 100644 configs/platinum_picon_defconfig create mode 100644 configs/platinum_titanium_defconfig create mode 100644 include/configs/platinum.h create mode 100644 include/configs/platinum_picon.h create mode 100644 include/configs/platinum_titanium.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 034ab33..6a45478 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -660,6 +660,16 @@ config TARGET_OT1200 bool "Bachmann OT1200" select CPU_V7 +config TARGET_PLATINUM_PICON + bool "Support platinum-picon" + select CPU_V7 + select SUPPORT_SPL + +config TARGET_PLATINUM_TITANIUM + bool "Support platinum-titanium" + select CPU_V7 + select SUPPORT_SPL + config OMAP34XX bool "OMAP34XX SoC" select CPU_V7 @@ -862,6 +872,7 @@ source "board/atmel/sama5d4_xplained/Kconfig" source "board/atmel/sama5d4ek/Kconfig" source "board/bachmann/ot1200/Kconfig" source "board/balloon3/Kconfig" +source "board/barco/platinum/Kconfig" source "board/barco/titanium/Kconfig" source "board/bluegiga/apx4devkit/Kconfig" source "board/bluewater/snapper9260/Kconfig" diff --git a/board/barco/platinum/Kconfig b/board/barco/platinum/Kconfig new file mode 100644 index 0000000..8bbad24 --- /dev/null +++ b/board/barco/platinum/Kconfig @@ -0,0 +1,37 @@ +if TARGET_PLATINUM_PICON + +config SYS_CPU + default "armv7" + +config SYS_VENDOR + default "barco" + +config SYS_SOC + default "mx6" + +config SYS_BOARD + default "platinum" + +config SYS_CONFIG_NAME + default "platinum_picon" + +endif + +if TARGET_PLATINUM_TITANIUM + +config SYS_CPU + default "armv7" + +config SYS_VENDOR + default "barco" + +config SYS_SOC + default "mx6" + +config SYS_BOARD + default "platinum" + +config SYS_CONFIG_NAME + default "platinum_titanium" + +endif diff --git a/board/barco/platinum/MAINTAINERS b/board/barco/platinum/MAINTAINERS new file mode 100644 index 0000000..a22584b --- /dev/null +++ b/board/barco/platinum/MAINTAINERS @@ -0,0 +1,7 @@ +PLATINUM BOARD +M: Stefan Roese <sr(a)denx.de> +S: Maintained +F: board/barco/platinum/ +F: include/configs/platinum.h +F: configs/platinum_picon_defconfig +F: configs/platinum_titanium_defconfig diff --git a/board/barco/platinum/Makefile b/board/barco/platinum/Makefile new file mode 100644 index 0000000..abc9419 --- /dev/null +++ b/board/barco/platinum/Makefile @@ -0,0 +1,14 @@ +# +# Copyright (C) 2014, Barco (www.barco.com) +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := platinum.o +obj-$(CONFIG_TARGET_PLATINUM_PICON) += platinum_picon.o +obj-$(CONFIG_TARGET_PLATINUM_TITANIUM) += platinum_titanium.o + +ifneq ($(CONFIG_SPL_BUILD),) +obj-$(CONFIG_TARGET_PLATINUM_PICON) += spl_picon.o +obj-$(CONFIG_TARGET_PLATINUM_TITANIUM) += spl_titanium.o +endif diff --git a/board/barco/platinum/platinum.c b/board/barco/platinum/platinum.c new file mode 100644 index 0000000..1485a48 --- /dev/null +++ b/board/barco/platinum/platinum.c @@ -0,0 +1,217 @@ +/* + * Copyright (C) 2014, Barco (www.barco.com) + * Copyright (C) 2014 Stefan Roese <sr(a)denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <miiphy.h> +#include <netdev.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/boot_mode.h> + +#include "platinum.h" + +DECLARE_GLOBAL_DATA_PTR; + +iomux_v3_cfg_t const usdhc3_pads[] = { + MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ +}; + +iomux_v3_cfg_t nfc_pads[] = { + MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +struct fsl_esdhc_cfg usdhc_cfg[] = { + { USDHC3_BASE_ADDR }, +}; + +void setup_gpmi_nand(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* config gpmi nand iomux */ + imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads)); + + /* config gpmi and bch clock to 100 MHz */ + clrsetbits_le32(&mxc_ccm->cs2cdr, + MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | + MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | + MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, + MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | + MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | + MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); + + /* enable gpmi and bch clock gating */ + setbits_le32(&mxc_ccm->CCGR4, + MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); + + /* enable apbh clock gating */ + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + + return 0; +} + +int board_ehci_hcd_init(int port) +{ + return 0; +} + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + + if (cfg->esdhc_base == usdhc_cfg[0].esdhc_base) { + unsigned sd3_cd = IMX_GPIO_NR(7, 0); + gpio_direction_input(sd3_cd); + return !gpio_get_value(sd3_cd); + } + + return 0; +} + +int board_mmc_init(bd_t *bis) +{ + imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +} + +void board_init_gpio(void) +{ + platinum_init_gpio(); +} + +void board_init_gpmi_nand(void) +{ + setup_gpmi_nand(); +} + +void board_init_i2c(void) +{ + platinum_setup_i2c(); +} + +void board_init_spi(void) +{ + platinum_setup_spi(); +} + +void board_init_uart(void) +{ + platinum_setup_uart(); +} + +void board_init_usb(void) +{ + platinum_init_usb(); +} + +void board_init_finished(void) +{ + platinum_init_finished(); +} + +int board_phy_config(struct phy_device *phydev) +{ + return platinum_phy_config(phydev); +} + +int board_eth_init(bd_t *bis) +{ + return cpu_eth_init(bis); +} + +int board_early_init_f(void) +{ + board_init_uart(); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + board_init_spi(); + + board_init_i2c(); + + board_init_gpmi_nand(); + + board_init_gpio(); + + board_init_usb(); + + board_init_finished(); + + return 0; +} + +int checkboard(void) +{ + puts("Board: " CONFIG_PLATINUM_BOARD "\n"); + return 0; +} + +static const struct boot_mode board_boot_modes[] = { + /* NAND */ + { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) }, + /* 4 bit bus width */ + { "mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00) }, + { "mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00) }, + { NULL, 0 }, +}; + +int misc_init_r(void) +{ + add_board_boot_modes(board_boot_modes); + + return 0; +} diff --git a/board/barco/platinum/platinum.h b/board/barco/platinum/platinum.h new file mode 100644 index 0000000..8650d6d --- /dev/null +++ b/board/barco/platinum/platinum.h @@ -0,0 +1,88 @@ +/* + * Copyright (C) 2014 Stefan Roese <sr(a)denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _PLATINUM_H_ +#define _PLATINUM_H_ + +#include <miiphy.h> +#include <asm/arch/crm_regs.h> + +/* Defines */ + +#define ECSPI1_PAD_CLK (PAD_CTL_SRE_SLOW | PAD_CTL_PUS_100K_DOWN | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \ + PAD_CTL_HYS) +#define ECSPI2_PAD_CLK (PAD_CTL_SRE_FAST | PAD_CTL_PUS_100K_DOWN | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_HYS) +#define ECSPI_PAD_MOSI (PAD_CTL_SRE_SLOW | PAD_CTL_PUS_100K_DOWN | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_120ohm | \ + PAD_CTL_HYS) +#define ECSPI_PAD_MISO (PAD_CTL_SRE_FAST | PAD_CTL_PUS_100K_DOWN | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \ + PAD_CTL_HYS) +#define ECSPI_PAD_SS (PAD_CTL_SRE_SLOW | PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_120ohm | \ + PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) +#define I2C_PAD_CTRL_SCL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_SLOW) + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | \ + PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | \ + PAD_CTL_HYS) + + +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +#define PC_SCL MUX_PAD_CTRL(I2C_PAD_CTRL_SCL) + +/* Prototypes */ + +int platinum_setup_enet(void); +int platinum_setup_i2c(void); +int platinum_setup_spi(void); +int platinum_setup_uart(void); +int platinum_phy_config(struct phy_device *phydev); +int platinum_init_gpio(void); +int platinum_init_usb(void); +int platinum_init_finished(void); + +static inline void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0x00C03F3F, &ccm->CCGR0); + writel(0x0030FC03, &ccm->CCGR1); + writel(0x0FFFC000, &ccm->CCGR2); + writel(0x3FF00000, &ccm->CCGR3); + writel(0xFFFFF300, &ccm->CCGR4); /* enable NAND/GPMI/BCH clks */ + writel(0x0F0000C3, &ccm->CCGR5); + writel(0x000003FF, &ccm->CCGR6); +} + +static inline void gpr_init(void) +{ + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + /* enable AXI cache for VDOA/VPU/IPU */ + writel(0xF00000CF, &iomux->gpr[4]); + /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ + writel(0x007F007F, &iomux->gpr[6]); + writel(0x007F007F, &iomux->gpr[7]); +} + +#endif /* _PLATINUM_H_ */ diff --git a/board/barco/platinum/platinum_picon.c b/board/barco/platinum/platinum_picon.c new file mode 100644 index 0000000..b2eab76 --- /dev/null +++ b/board/barco/platinum/platinum_picon.c @@ -0,0 +1,244 @@ +/* + * Copyright (C) 2014, Barco (www.barco.com) + * Copyright (C) 2014 Stefan Roese <sr(a)denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-pins.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/mxc_i2c.h> +#include <i2c.h> +#include <miiphy.h> + +#include "platinum.h" + +#define GPIO_IP_NCONFIG IMX_GPIO_NR(5, 18) +#define GPIO_HK_NCONFIG IMX_GPIO_NR(7, 13) +#define GPIO_LS_NCONFIG IMX_GPIO_NR(5, 19) + +#define GPIO_I2C0_SEL0 IMX_GPIO_NR(5, 2) +#define GPIO_I2C0_SEL1 IMX_GPIO_NR(1, 11) +#define GPIO_I2C0_ENBN IMX_GPIO_NR(1, 13) + +#define GPIO_I2C2_SEL0 IMX_GPIO_NR(1, 17) +#define GPIO_I2C2_SEL1 IMX_GPIO_NR(1, 20) +#define GPIO_I2C2_ENBN IMX_GPIO_NR(1, 14) + +#define GPIO_USB_RESET IMX_GPIO_NR(1, 5) + +iomux_v3_cfg_t const ecspi1_pads[] = { + MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(ECSPI1_PAD_CLK), + MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(ECSPI_PAD_MISO), + MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(ECSPI_PAD_MOSI), + MX6_PAD_CSI0_DAT7__ECSPI1_SS0 | MUX_PAD_CTRL(ECSPI_PAD_SS), + MX6_PAD_EIM_D24__ECSPI1_SS2 | MUX_PAD_CTRL(ECSPI_PAD_SS), + MX6_PAD_EIM_D25__ECSPI1_SS3 | MUX_PAD_CTRL(ECSPI_PAD_SS), +}; + +iomux_v3_cfg_t const ecspi2_pads[] = { + MX6_PAD_EIM_CS0__ECSPI2_SCLK | MUX_PAD_CTRL(ECSPI2_PAD_CLK), + MX6_PAD_EIM_OE__ECSPI2_MISO | MUX_PAD_CTRL(ECSPI_PAD_MISO), + MX6_PAD_EIM_CS1__ECSPI2_MOSI | MUX_PAD_CTRL(ECSPI_PAD_MOSI), + MX6_PAD_EIM_RW__ECSPI2_SS0 | MUX_PAD_CTRL(ECSPI_PAD_SS), + MX6_PAD_EIM_LBA__ECSPI2_SS1 | MUX_PAD_CTRL(ECSPI_PAD_SS), +}; + +iomux_v3_cfg_t const enet_pads[] = { + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +/* PHY nRESET */ +iomux_v3_cfg_t const phy_reset_pad = { + MX6_PAD_SD1_DAT2__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +iomux_v3_cfg_t const uart4_pads[] = { + MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT16__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT17__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +iomux_v3_cfg_t const uart5_pads[] = { + MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT18__UART5_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT19__UART5_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +iomux_v3_cfg_t const i2c0_mux_pads[] = { + MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD2_CMD__GPIO1_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD2_DAT2__GPIO1_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +iomux_v3_cfg_t const i2c2_mux_pads[] = { + MX6_PAD_SD1_DAT1__GPIO1_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD2_DAT1__GPIO1_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +struct i2c_pads_info i2c_pad_info0 = { + .scl = { + .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC_SCL, + .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC_SCL, + .gp = IMX_GPIO_NR(5, 27) + }, + .sda = { + .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC, + .gp = IMX_GPIO_NR(5, 26) + } +}; + +struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC_SCL, + .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC_SCL, + .gp = IMX_GPIO_NR(1, 3) + }, + .sda = { + .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC, + .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC, + .gp = IMX_GPIO_NR(1, 6) + } +}; + +/* + * This enet related pin-muxing and GPIO handling is done + * in SPL U-Boot. For early initialization. And to give the + * PHY some time to come out of reset before the U-Boot + * ethernet driver tries to access its registers via MDIO. + */ +int platinum_setup_enet(void) +{ + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + unsigned phy_reset = IMX_GPIO_NR(1, 19); + + /* First configure PHY reset GPIO pin */ + imx_iomux_v3_setup_pad(phy_reset_pad); + + /* Reconfigure enet muxing while PHY is in reset */ + gpio_direction_output(phy_reset, 0); + imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); + mdelay(10); + gpio_set_value(phy_reset, 1); + udelay(100); + + /* set GPIO_16 as ENET_REF_CLK_OUT */ + setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK); + + return enable_fec_anatop_clock(ENET_50MHZ); +} + +int platinum_setup_i2c(void) +{ + imx_iomux_v3_setup_multiple_pads(i2c0_mux_pads, + ARRAY_SIZE(i2c0_mux_pads)); + imx_iomux_v3_setup_multiple_pads(i2c2_mux_pads, + ARRAY_SIZE(i2c2_mux_pads)); + + mdelay(10); + + /* Disable i2c mux 0 */ + gpio_direction_output(GPIO_I2C0_SEL0, 0); + gpio_direction_output(GPIO_I2C0_SEL1, 0); + gpio_direction_output(GPIO_I2C0_ENBN, 1); + + /* Disable i2c mux 1 */ + gpio_direction_output(GPIO_I2C2_SEL0, 0); + gpio_direction_output(GPIO_I2C2_SEL1, 0); + gpio_direction_output(GPIO_I2C2_ENBN, 1); + + udelay(10); + + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); + + /* Disable all leds */ + i2c_set_bus_num(0); + i2c_reg_write(0x60, 0x05, 0x55); + + return 0; +} + +int platinum_setup_spi(void) +{ + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); + imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads)); + + return 0; +} + +int platinum_setup_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); + imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); + imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads)); + + return 0; +} + +int platinum_phy_config(struct phy_device *phydev) +{ + /* Use generic infrastructure, no specific setup */ + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +int platinum_init_gpio(void) +{ + /* Reset FPGA's */ + gpio_direction_output(GPIO_IP_NCONFIG, 0); + gpio_direction_output(GPIO_HK_NCONFIG, 0); + gpio_direction_output(GPIO_LS_NCONFIG, 0); + udelay(3); + gpio_set_value(GPIO_IP_NCONFIG, 1); + gpio_set_value(GPIO_HK_NCONFIG, 1); + gpio_set_value(GPIO_LS_NCONFIG, 1); + + /* no dmd configuration yet */ + + return 0; +} + +int platinum_init_usb(void) +{ + /* Reset usb hub */ + gpio_direction_output(GPIO_USB_RESET, 0); + udelay(100); + gpio_set_value(GPIO_USB_RESET, 1); + + return 0; +} + +int platinum_init_finished(void) +{ + /* Enable led 0 */ + i2c_set_bus_num(0); + i2c_reg_write(0x60, 0x05, 0x54); + + return 0; +} diff --git a/board/barco/platinum/platinum_titanium.c b/board/barco/platinum/platinum_titanium.c new file mode 100644 index 0000000..73a955f --- /dev/null +++ b/board/barco/platinum/platinum_titanium.c @@ -0,0 +1,209 @@ +/* + * Copyright (C) 2014, Barco (www.barco.com) + * Copyright (C) 2014 Stefan Roese <sr(a)denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-pins.h> +#include <asm/gpio.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/mxc_i2c.h> +#include <miiphy.h> +#include <micrel.h> + +#include "platinum.h" + +iomux_v3_cfg_t const ecspi1_pads[] = { + MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(ECSPI1_PAD_CLK), + MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(ECSPI_PAD_MISO), + MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(ECSPI_PAD_MOSI), + MX6_PAD_CSI0_DAT7__ECSPI1_SS0 | MUX_PAD_CTRL(ECSPI_PAD_SS), + /* non mounted spi nor flash for booting */ + MX6_PAD_EIM_D19__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EIM_D24__ECSPI1_SS2 | MUX_PAD_CTRL(ECSPI_PAD_SS), + MX6_PAD_EIM_D25__ECSPI1_SS3 | MUX_PAD_CTRL(ECSPI_PAD_SS), +}; + +iomux_v3_cfg_t const ecspi2_pads[] = { + MX6_PAD_EIM_CS0__ECSPI2_SCLK | MUX_PAD_CTRL(ECSPI2_PAD_CLK), + MX6_PAD_EIM_OE__ECSPI2_MISO | MUX_PAD_CTRL(ECSPI_PAD_MISO), + MX6_PAD_EIM_CS1__ECSPI2_MOSI | MUX_PAD_CTRL(ECSPI_PAD_MOSI), + MX6_PAD_EIM_RW__ECSPI2_SS0 | MUX_PAD_CTRL(ECSPI_PAD_SS), +}; + +iomux_v3_cfg_t const enet_pads1[] = { + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + /* pin 35 - 1 (PHY_AD2) on reset */ + MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 32 - 1 - (MODE0) all */ + MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 31 - 1 - (MODE1) all */ + MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 28 - 1 - (MODE2) all */ + MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 27 - 1 - (MODE3) all */ + MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */ + MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 42 PHY nRST */ + MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +iomux_v3_cfg_t const enet_pads2[] = { + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +iomux_v3_cfg_t const uart2_pads[] = { + MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D28__UART2_DTE_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D29__UART2_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +iomux_v3_cfg_t const uart4_pads[] = { + MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT16__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT17__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +struct i2c_pads_info i2c_pad_info0 = { + .scl = { + .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC_SCL, + .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC_SCL, + .gp = IMX_GPIO_NR(5, 27) + }, + .sda = { + .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC, + .gp = IMX_GPIO_NR(5, 26) + } +}; + +struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC_SCL, + .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC_SCL, + .gp = IMX_GPIO_NR(1, 3) + }, + .sda = { + .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC, + .gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | PC, + .gp = IMX_GPIO_NR(7, 11) + } +}; + +/* + * This enet related pin-muxing and GPIO handling is done + * in SPL U-Boot. For early initialization. And to give the + * PHY some time to come out of reset before the U-Boot + * ethernet driver tries to access its registers via MDIO. + */ +int platinum_setup_enet(void) +{ + gpio_direction_output(IMX_GPIO_NR(3, 23), 0); + gpio_direction_output(IMX_GPIO_NR(6, 30), 1); + gpio_direction_output(IMX_GPIO_NR(6, 25), 1); + gpio_direction_output(IMX_GPIO_NR(6, 27), 1); + gpio_direction_output(IMX_GPIO_NR(6, 28), 1); + gpio_direction_output(IMX_GPIO_NR(6, 29), 1); + imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1)); + gpio_direction_output(IMX_GPIO_NR(6, 24), 1); + + /* Need delay 10ms according to KSZ9021 spec */ + mdelay(10); + gpio_set_value(IMX_GPIO_NR(3, 23), 1); + udelay(100); + + imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2)); + + return 0; +} + +int platinum_setup_i2c(void) +{ + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); + + return 0; +} + +int platinum_setup_spi(void) +{ + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); + imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads)); + + return 0; +} + +int platinum_setup_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); + imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); + imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); + + return 0; +} + +int platinum_phy_config(struct phy_device *phydev) +{ + /* min rx data delay */ + ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, + 0x0); + /* min tx data delay */ + ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, + 0x0); + /* max rx/tx clock delay, min rx/tx control */ + ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, + 0xf0f0); + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +int platinum_init_gpio(void) +{ + /* Default GPIO's */ + /* Toggle CONFIG_n to reset fpga on every boot */ + gpio_direction_output(IMX_GPIO_NR(5, 18), 0); + /* Need delay >=2uS */ + udelay(3); + gpio_set_value(IMX_GPIO_NR(5, 18), 1); + + /* Default pin 1,15 high - DLP_FLASH_WPZ */ + gpio_direction_output(IMX_GPIO_NR(1, 15), 1); + + return 0; +} + +int platinum_init_usb(void) +{ + return 0; +} + +int platinum_init_finished(void) +{ + return 0; +} diff --git a/board/barco/platinum/spl_picon.c b/board/barco/platinum/spl_picon.c new file mode 100644 index 0000000..f421c21 --- /dev/null +++ b/board/barco/platinum/spl_picon.c @@ -0,0 +1,182 @@ +/* + * Copyright (C) 2014 Stefan Roese <sr(a)denx.de> + * + * Based on: gw_ventana_spl.c which is: + * Copyright (C) 2014 Gateworks Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <i2c.h> +#include <asm/io.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-ddr.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/imx-common/boot_mode.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/mxc_i2c.h> +#include <spl.h> + +#include "platinum.h" + +DECLARE_GLOBAL_DATA_PTR; + +#undef RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */ + +/* Configure MX6Q/DUAL mmdc DDR io registers */ +struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = { + /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */ + .dram_sdclk_0 = 0x00020030, + .dram_sdclk_1 = 0x00020030, + .dram_cas = 0x00020030, + .dram_ras = 0x00020030, + .dram_reset = 0x00020030, + /* SDCKE[0:1]: 100k pull-up */ + .dram_sdcke0 = 0x00003000, + .dram_sdcke1 = 0x00003000, + /* SDBA2: pull-up disabled */ + .dram_sdba2 = 0x00000000, + /* SDODT[0:1]: 100k pull-up, 40 ohm */ + .dram_sdodt0 = 0x00003030, + .dram_sdodt1 = 0x00003030, + /* SDQS[0:7]: Differential input, 40 ohm */ + .dram_sdqs0 = 0x00000030, + .dram_sdqs1 = 0x00000030, + .dram_sdqs2 = 0x00000030, + .dram_sdqs3 = 0x00000030, + .dram_sdqs4 = 0x00000030, + .dram_sdqs5 = 0x00000030, + .dram_sdqs6 = 0x00000030, + .dram_sdqs7 = 0x00000030, + /* DQM[0:7]: Differential input, 40 ohm */ + .dram_dqm0 = 0x00020030, + .dram_dqm1 = 0x00020030, + .dram_dqm2 = 0x00020030, + .dram_dqm3 = 0x00020030, + .dram_dqm4 = 0x00020030, + .dram_dqm5 = 0x00020030, + .dram_dqm6 = 0x00020030, + .dram_dqm7 = 0x00020030, +}; + +/* Configure MX6Q/DUAL mmdc GRP io registers */ +struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { + /* DDR3 */ + .grp_ddr_type = 0x000c0000, + .grp_ddrmode_ctl = 0x00020000, + /* disable DDR pullups */ + .grp_ddrpke = 0x00000000, + /* ADDR[00:16], SDBA[0:1]: 40 ohm */ + .grp_addds = 0x00000030, + /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */ + .grp_ctlds = 0x00000030, + /* DATA[00:63]: Differential input, 40 ohm */ + .grp_ddrmode = 0x00020000, + .grp_b0ds = 0x00000030, + .grp_b1ds = 0x00000030, + .grp_b2ds = 0x00000030, + .grp_b3ds = 0x00000030, + .grp_b4ds = 0x00000030, + .grp_b5ds = 0x00000030, + .grp_b6ds = 0x00000030, + .grp_b7ds = 0x00000030, +}; + +/* MT41K256M16HA-125 */ +static struct mx6_ddr3_cfg mt41k256m16ha_125 = { + .mem_speed = 1600, + .density = 4, /* 4Gbit */ + .width = 16, + .banks = 8, + .rowaddr = 15, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; + +/* + * Values from running the Freescale DDR stress tool via USB + */ +static struct mx6_mmdc_calibration mx6dq_mmdc_calib = { + /* write leveling calibration determine */ + .p0_mpwldectrl0 = 0x0044004E, + .p0_mpwldectrl1 = 0x001F0023, + /* Read DQS Gating calibration */ + .p0_mpdgctrl0 = 0x02480248, + .p0_mpdgctrl1 = 0x0210021C, + /* Read Calibration: DQS delay relative to DQ read access */ + .p0_mprddlctl = 0x42444444, + /* Write Calibration: DQ/DM delay relative to DQS write access */ + .p0_mpwrdlctl = 0x36322C32, +}; + +static void spl_dram_init(int width) +{ + struct mx6_ddr3_cfg *mem = &mt41k256m16ha_125; + struct mx6_ddr_sysinfo sysinfo = { + /* width of data bus:0=16,1=32,2=64 */ + .dsize = width / 32, + /* config for full 4GB range so that get_mem_size() works */ + .cs_density = 32, /* 32Gb per CS */ + /* single chip select */ + .ncs = 1, + .cs1_mirror = 1, + .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ +#ifdef RTT_NOM_120OHM + .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */ +#else + .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ +#endif + .walat = 0, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + }; + + mx6sdl_dram_iocfg(width, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); + mx6_dram_cfg(&sysinfo, &mx6dq_mmdc_calib, mem); +} + +/* + * Called from C runtime startup code (arch/arm/lib/crt0.S:_main) + * - we have a stack and a place to store GD, both in SRAM + * - no variable global data is available + */ +void board_init_f(ulong dummy) +{ + /* Setup AIPS and disable watchdog */ + arch_cpu_init(); + + ccgr_init(); + gpr_init(); + + /* UART iomux */ + board_early_init_f(); + + /* Setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* Init DDR with 32bit width */ + spl_dram_init(32); + + /* Clear the BSS */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* + * Setup enet related MUXing early to give the PHY + * some time to wake-up from reset + */ + platinum_setup_enet(); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} diff --git a/board/barco/platinum/spl_titanium.c b/board/barco/platinum/spl_titanium.c new file mode 100644 index 0000000..26fe26b --- /dev/null +++ b/board/barco/platinum/spl_titanium.c @@ -0,0 +1,185 @@ +/* + * Copyright (C) 2014 Stefan Roese <sr(a)denx.de> + * + * Based on: gw_ventana_spl.c which is: + * Copyright (C) 2014 Gateworks Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <i2c.h> +#include <asm/io.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-ddr.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/imx-common/boot_mode.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/mxc_i2c.h> +#include <spl.h> + +#include "platinum.h" + +DECLARE_GLOBAL_DATA_PTR; + +#undef RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */ + +/* Configure MX6Q/DUAL mmdc DDR io registers */ +struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = { + /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */ + .dram_sdclk_0 = 0x00020030, + .dram_sdclk_1 = 0x00020030, + .dram_cas = 0x00020030, + .dram_ras = 0x00020030, + .dram_reset = 0x00020030, + /* SDCKE[0:1]: 100k pull-up */ + .dram_sdcke0 = 0x00003000, + .dram_sdcke1 = 0x00003000, + /* SDBA2: pull-up disabled */ + .dram_sdba2 = 0x00000000, + /* SDODT[0:1]: 100k pull-up, 40 ohm */ + .dram_sdodt0 = 0x00003030, + .dram_sdodt1 = 0x00003030, + /* SDQS[0:7]: Differential input, 40 ohm */ + .dram_sdqs0 = 0x00000030, + .dram_sdqs1 = 0x00000030, + .dram_sdqs2 = 0x00000030, + .dram_sdqs3 = 0x00000030, + .dram_sdqs4 = 0x00000030, + .dram_sdqs5 = 0x00000030, + .dram_sdqs6 = 0x00000030, + .dram_sdqs7 = 0x00000030, + /* DQM[0:7]: Differential input, 40 ohm */ + .dram_dqm0 = 0x00020030, + .dram_dqm1 = 0x00020030, + .dram_dqm2 = 0x00020030, + .dram_dqm3 = 0x00020030, + .dram_dqm4 = 0x00020030, + .dram_dqm5 = 0x00020030, + .dram_dqm6 = 0x00020030, + .dram_dqm7 = 0x00020030, +}; + +/* Configure MX6Q/DUAL mmdc GRP io registers */ +struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = { + /* DDR3 */ + .grp_ddr_type = 0x000c0000, + .grp_ddrmode_ctl = 0x00020000, + /* disable DDR pullups */ + .grp_ddrpke = 0x00000000, + /* ADDR[00:16], SDBA[0:1]: 40 ohm */ + .grp_addds = 0x00000030, + /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */ + .grp_ctlds = 0x00000030, + /* DATA[00:63]: Differential input, 40 ohm */ + .grp_ddrmode = 0x00020000, + .grp_b0ds = 0x00000030, + .grp_b1ds = 0x00000030, + .grp_b2ds = 0x00000030, + .grp_b3ds = 0x00000030, + .grp_b4ds = 0x00000030, + .grp_b5ds = 0x00000030, + .grp_b6ds = 0x00000030, + .grp_b7ds = 0x00000030, +}; + +/* MT41J128M16JT-125 */ +static struct mx6_ddr3_cfg mt41j128m16jt_125 = { + .mem_speed = 1600, + .density = 2, + .width = 16, + .banks = 8, + .rowaddr = 14, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; + +static struct mx6_mmdc_calibration mx6dq_mmdc_calib = { + /* Write leveling calibration determine */ + .p0_mpwldectrl0 = 0x001f001f, + .p0_mpwldectrl1 = 0x001f001f, + .p1_mpwldectrl0 = 0x00440044, + .p1_mpwldectrl1 = 0x00440044, + /* Read DQS Gating calibration */ + .p0_mpdgctrl0 = 0x434b0350, + .p0_mpdgctrl1 = 0x034c0359, + .p1_mpdgctrl0 = 0x434b0350, + .p1_mpdgctrl1 = 0x03650348, + /* Read Calibration: DQS delay relative to DQ read access */ + .p0_mprddlctl = 0x4436383b, + .p1_mprddlctl = 0x39393341, + /* Write Calibration: DQ/DM delay relative to DQS write access */ + .p0_mpwrdlctl = 0x35373933, + .p1_mpwrdlctl = 0x48254a36, +}; + +static void spl_dram_init(int width) +{ + struct mx6_ddr3_cfg *mem = &mt41j128m16jt_125; + struct mx6_ddr_sysinfo sysinfo = { + /* width of data bus:0=16,1=32,2=64 */ + .dsize = width / 32, + /* config for full 4GB range so that get_mem_size() works */ + .cs_density = 32, /* 32Gb per CS */ + /* single chip select */ + .ncs = 1, + .cs1_mirror = 1, + .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ +#ifdef RTT_NOM_120OHM + .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */ +#else + .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ +#endif + .walat = 0, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + }; + + mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs); + mx6_dram_cfg(&sysinfo, &mx6dq_mmdc_calib, mem); +} + +/* + * Called from C runtime startup code (arch/arm/lib/crt0.S:_main) + * - we have a stack and a place to store GD, both in SRAM + * - no variable global data is available + */ +void board_init_f(ulong dummy) +{ + /* Setup AIPS and disable watchdog */ + arch_cpu_init(); + + ccgr_init(); + gpr_init(); + + /* UART iomux */ + board_early_init_f(); + + /* Setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* Init DDR with 32bit width */ + spl_dram_init(32); + + /* Clear the BSS */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* + * Setup enet related MUXing early to give the PHY + * some time to wake-up from reset + */ + platinum_setup_enet(); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} diff --git a/configs/platinum_picon_defconfig b/configs/platinum_picon_defconfig new file mode 100644 index 0000000..c3ca040 --- /dev/null +++ b/configs/platinum_picon_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6DL" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_PLATINUM_PICON=y diff --git a/configs/platinum_titanium_defconfig b/configs/platinum_titanium_defconfig new file mode 100644 index 0000000..db8cef9 --- /dev/null +++ b/configs/platinum_titanium_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_PLATINUM_TITANIUM=y diff --git a/include/configs/platinum.h b/include/configs/platinum.h new file mode 100644 index 0000000..134bb45 --- /dev/null +++ b/include/configs/platinum.h @@ -0,0 +1,319 @@ +/* + * Copyright (C) 2014, Barco (www.barco.com) + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __PLATINUM_CONFIG_H__ +#define __PLATINUM_CONFIG_H__ + +#define CONFIG_SYS_GENERIC_BOARD + +/* SPL */ +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT + +/* Location in NAND to read U-Boot from */ +#define CONFIG_SYS_NAND_U_BOOT_OFFS (14 * 1024 * 1024) + +#include "imx6_spl.h" /* common IMX6 SPL configuration */ +#include "mx6_common.h" +#include <asm/arch/imx-regs.h> +#include <asm/imx-common/gpio.h> + +/* + * Console configuration + */ + +#include <config_cmd_default.h> +#define CONFIG_CMD_BMODE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_FUSE +#define CONFIG_CMD_GPIO +#define CONFIG_CMD_I2C +#undef CONFIG_CMD_IMLS +#define CONFIG_CMD_MII +#define CONFIG_CMD_MMC +#define CONFIG_CMD_MTDPARTS +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NAND_TRIMFFS +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_TIME +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_CMD_USB + +/* + * Hardware configuration + */ + +/* GPIO config */ +#define CONFIG_MXC_GPIO + +/* UART config */ +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE +#define CONFIG_BAUDRATE 115200 +#define CONFIG_CONS_INDEX 1 + +/* I2C config */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_SPEED 100000 + +/* MMC config */ +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_USDHC_NUM 1 +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_DOS_PARTITION + +/* Ethernet config */ +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR + +#define CONFIG_PHYLIB + +/* USB config */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_MXC_USB_PORT 1 +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 + +/* Memory config */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#ifndef PHYS_SDRAM_SIZE +#define PHYS_SDRAM_SIZE (1024 << 20) +#endif + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024) + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH + +#ifdef CONFIG_CMD_NAND + +/* NAND config */ +#define CONFIG_NAND_MXS +#ifndef CONFIG_SYS_NAND_MAX_CHIPS +#define CONFIG_SYS_NAND_MAX_CHIPS 2 +#endif +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* DMA config, needed for GPMI/MXS NAND support */ +#define CONFIG_APBH_DMA +#define CONFIG_APBH_DMA_BURST +#define CONFIG_APBH_DMA_BURST8 + +/* Fuse support */ +#define CONFIG_MXC_OCOTP + +/* Environment in NAND */ +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET (16 << 20) +#define CONFIG_ENV_SECT_SIZE (128 << 10) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + (512 << 10)) +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE + +#else /* CONFIG_CMD_NAND */ + +/* Environment in MMC */ +#define CONFIG_ENV_SIZE (8 << 10) +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_OFFSET (6 * 64 * 1024) +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#endif /* CONFIG_CMD_NAND */ + +/* + * U-Boot configuration + */ + +/* Console boot messages */ +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +/* Tag config */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +/* Board startup config */ +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_MISC_INIT_R + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +/* Device tree support */ +#define CONFIG_OF_LIBFDT + +#define CONFIG_LOADADDR 0x12000000 +#define CONFIG_SYS_TEXT_BASE 0x17800000 + +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ + PHYS_SDRAM_SIZE - (12 << 20)) + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTCOMMAND "run bootubi_scr" + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_HUSH_PARSER + +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_PREBOOT + +#define CONFIG_SYS_CBSIZE 256 + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* MTD/UBI/UBIFS config */ +#define CONFIG_LZO +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_RBTREE + +#if (CONFIG_SYS_NAND_MAX_CHIPS == 1) +#define MTDIDS_DEFAULT "nand0=gpmi-nand" +#define MTDPARTS_DEFAULT "mtdparts=gpmi-nand:14M(spl),2M(uboot)," \ + "512k(env1),512k(env2),-(ubi)" +#elif (CONFIG_SYS_NAND_MAX_CHIPS == 2) +#define MTDIDS_DEFAULT "nand0=gpmi-nand" +#define MTDPARTS_DEFAULT "mtdparts=gpmi-nand:14M(spl),2M(uboot)," \ + "512k(env1),512k(env2),495M(ubi0)," \ + "14M(res0),2M(res1)," \ + "512k(res2),512k(res3),-(ubi1)" +#endif + +#ifndef CONFIG_SYS_DCACHE_OFF +#define CONFIG_CMD_CACHE +#endif + +/* + * Environment configuration + */ + +#if (CONFIG_SYS_NAND_MAX_CHIPS == 1) +#define CONFIG_COMMON_ENV_UBI \ + "setubipartition=env set ubipartition ubi\0" \ + "setubirfs=env set ubirfs $ubipartition:rootfs$boot_vol\0" +#elif (CONFIG_SYS_NAND_MAX_CHIPS == 2) +#define CONFIG_COMMON_ENV_UBI \ + "setubipartition=env set ubipartition ubi$boot_vol\0" \ + "setubirfs=env set ubirfs ubi0:rootfs\0" +#endif + +#define CONFIG_COMMON_ENV_MISC \ + "user=user\0" \ + "project="CONFIG_PLATINUM_PROJECT"\0" \ + "uimage=uImage\0" \ + "dtb="CONFIG_PLATINUM_CPU"-platinum-"CONFIG_PLATINUM_PROJECT".dtb\0" \ + "serverip=serverip\0" \ + "memaddrlinux=0x10800000\0" \ + "memaddrsrc=0x11000000\0" \ + "memaddrdtb=0x12000000\0" \ + "console=ttymxc0\0" \ + "baudrate=115200\0" \ + "boot_scr=boot.uboot\0" \ + "boot_vol=0\0" \ + "mtdids="MTDIDS_DEFAULT"\0" \ + "mtdparts="MTDPARTS_DEFAULT"\0" \ + "mmcfs=ext2\0" \ + "mmcrootpart=1\0" \ + \ + "setnfspath=env set nfspath /home/nfs/$user/$project/root\0" \ + "settftpfilelinux=env set tftpfilelinux $user/$project/$uimage\0" \ + "settftpfiledtb=env set tftpfiledtb $user/$project/$dtb\0" \ + "setubifilelinux=env set ubifilelinux boot/$uimage\0" \ + "setubipfiledtb=env set ubifiledtb boot/$dtb\0" \ + "setmmcrootdev=env set mmcrootdev /dev/mmcblk0p$mmcrootpart\0" \ + "setmmcfilelinux=env set mmcfilelinux /boot/$uimage\0" \ + "setmmcfiledtb=env set mmcfiledtb /boot/$dtb\0" \ + \ + "loadtftpkernel=dhcp $memaddrlinux $tftpfilelinux\0" \ + "loadtftpdtb=dhcp $memaddrdtb $tftpfiledtb\0" \ + "loadubikernel=ubifsload $memaddrlinux $ubifilelinux\0" \ + "loadubidtb=ubifsload $memaddrdtb $ubifiledtb\0" \ + "loadmmckernel=${mmcfs}load mmc 0:$mmcrootpart $memaddrlinux " \ + "$mmcfilelinux\0" \ + "loadmmcdtb=${mmcfs}load mmc 0:$mmcrootpart $memaddrdtb " \ + "$mmcfiledtb\0" \ + \ + "ubipart=ubi part $ubipartition\0" \ + "ubimount=ubifsmount $ubirfs\0" \ + \ + "setbootargscommon=env set bootargs $bootargs " \ + "console=$console,$baudrate enable_wait_mode=off\0" \ + "setbootargsmtd=env set bootargs $bootargs $mtdparts\0" \ + "setbootargsdhcp=env set bootargs $bootargs ip=dhcp\0" \ + "setbootargsubirfs=env set bootargs $bootargs " \ + "ubi.mtd=$ubipartition root=$ubirfs rootfstype=ubifs\0" \ + "setbootargsnfsrfs=env set bootargs $bootargs root=/dev/nfs " \ + "nfsroot=$serverip:$nfspath,v3,tcp\0" \ + "setbootargsmmcrfs=env set bootargs $bootargs " \ + "root=$mmcrootdev rootwait rw\0" \ + \ + "bootnet=run settftpfilelinux settftpfiledtb setnfspath " \ + "setbootargscommon setbootargsmtd setbootargsdhcp " \ + "setbootargsnfsrfs;" \ + "run loadtftpkernel loadtftpdtb;" \ + "bootm $memaddrlinux - $memaddrdtb\0" \ + "bootnet_ubirfs=run settftpfilelinux settftpfiledtb;" \ + "run setubipartition setubirfs;" \ + "run setbootargscommon setbootargsmtd " \ + "setbootargsubirfs;" \ + "run loadtftpkernel loadtftpdtb;" \ + "bootm $memaddrlinux - $memaddrdtb\0" \ + "bootubi=run setubipartition setubirfs setubifilelinux " \ + "setubipfiledtb;" \ + "run setbootargscommon setbootargsmtd " \ + "setbootargsubirfs;" \ + "run ubipart ubimount loadubikernel loadubidtb;" \ + "bootm $memaddrlinux - $memaddrdtb\0" \ + "bootubi_scr=run setubipartition setubirfs;" \ + "run ubipart ubimount;" \ + "if ubifsload ${memaddrsrc} boot/${boot_scr}; " \ + "then source ${memaddrsrc}; else run bootubi; fi\0" \ + "bootmmc=run setmmcrootdev setmmcfilelinux setmmcfiledtb " \ + "setbootargscommon setbootargsmmcrfs;" \ + "run loadmmckernel loadmmcdtb;" \ + "bootm $memaddrlinux - $memaddrdtb\0" \ + \ + "bootcmd="CONFIG_BOOTCOMMAND"\0" + +#define CONFIG_COMMON_ENV_SETTINGS CONFIG_COMMON_ENV_MISC \ + CONFIG_COMMON_ENV_UBI +#endif /* __PLATINUM_CONFIG_H__ */ diff --git a/include/configs/platinum_picon.h b/include/configs/platinum_picon.h new file mode 100644 index 0000000..4590df5 --- /dev/null +++ b/include/configs/platinum_picon.h @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2014, Barco (www.barco.com) + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __PLATINUM_PICON_CONFIG_H__ +#define __PLATINUM_PICON_CONFIG_H__ + +#define CONFIG_PLATINUM_PICON +#define CONFIG_PLATINUM_BOARD "Barco Picon" +#define CONFIG_PLATINUM_PROJECT "picon" +#define CONFIG_PLATINUM_CPU "imx6dl" + +#define CONFIG_MX6 + +#include <configs/platinum.h> + +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_FEC_MXC_PHYADDR 0 + +#define CONFIG_HOSTNAME picon + +#define CONFIG_SYS_PROMPT "picon > " + +#define CONFIG_PLATFORM_ENV_SETTINGS "\0" + +#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_COMMON_ENV_SETTINGS \ + CONFIG_PLATFORM_ENV_SETTINGS + +#endif /* __PLATINUM_PICON_CONFIG_H__ */ diff --git a/include/configs/platinum_titanium.h b/include/configs/platinum_titanium.h new file mode 100644 index 0000000..6789655 --- /dev/null +++ b/include/configs/platinum_titanium.h @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2014, Barco (www.barco.com) + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __PLATINUM_TITANIUM_CONFIG_H__ +#define __PLATINUM_TITANIUM_CONFIG_H__ + +#define CONFIG_PLATINUM_TITANIUM +#define CONFIG_PLATINUM_BOARD "Barco Titanium" +#define CONFIG_PLATINUM_PROJECT "titanium" +#define CONFIG_PLATINUM_CPU "imx6q" + +#define CONFIG_MX6 + +#define PHYS_SDRAM_SIZE (512 << 20) +#define CONFIG_SYS_NAND_MAX_CHIPS 1 + +#include <configs/platinum.h> + +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_FEC_MXC_PHYADDR 4 + +#define CONFIG_PHY_MICREL +#define CONFIG_PHY_MICREL_KSZ9021 +#define CONFIG_PHY_RESET_DELAY 1000 + +#define CONFIG_HOSTNAME titanium + +#define CONFIG_SYS_PROMPT "titanium > " + +#define CONFIG_PLATFORM_ENV_SETTINGS "\0" + +#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_COMMON_ENV_SETTINGS \ + CONFIG_PLATFORM_ENV_SETTINGS + +#endif /* __PLATINUM_TITANIUM_CONFIG_H__ */ -- 2.2.0

2 1

[U-Boot] [PATCH] mx6sxsabresd: Remove unneeded board_late_init()
by Fabio Estevam 19 Jan '15

19 Jan '15

From: Fabio Estevam <fabio.estevam(a)freescale.com> Since commit 1f98e31bc0b2c37a ("imx: mx6sxsabresd: Use the pfuze common init function") board_late_init() became empty, so we can safely remove this unneeded function. Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- board/freescale/mx6sxsabresd/mx6sxsabresd.c | 5 ----- include/configs/mx6sxsabresd.h | 1 - 2 files changed, 6 deletions(-) diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c index fd8bc72..83e0508 100644 --- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c +++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c @@ -383,11 +383,6 @@ int board_init(void) return 0; } -int board_late_init(void) -{ - return 0; -} - int checkboard(void) { puts("Board: MX6SX SABRE SDB\n"); diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index 61a7a7a..3d35c4b 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -28,7 +28,6 @@ #define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M) #define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_BOARD_LATE_INIT #define CONFIG_MXC_GPIO #define CONFIG_MXC_UART -- 1.9.1

2 1

[U-Boot] linux-sunxi/u-boot-sunxi is no longer supported, time to switch to upstream u-boot
by Hans de Goede 18 Jan '15

18 Jan '15

Hi All, There are 3 topics which I would like to cover in this mail: 1) Switching over to upstream u-boot for the linux-sunxi project 2) How to build upstream u-boot for use with linux-sunxi sunxi-3.4 kernels 3) Adding more boards to upstream u-boot 1. Switching over to upstream u-boot for the linux-sunxi project ================================================================ Upstream u-boot has had sunxi support for a while now, and has slowly been gaining a lot of features over the linux-sunxi/u-boot-sunxi version at: https://github.com/linux-sunxi/u-boot-sunxi/ Some of the new features supported upstream are booting from usb, booting from sata (ahci) and full sun6i (A31) support including SPL support. Also upstream u-boot supports using hdmi out + an usb keyboard as u-boot console, so that one does not need to solder a serial console to things like hdmi tv-dongles. Upstream u-boot also has full sun8i (A23) support in the pipeline including SPL support. One of the things which has stopped people from switching to upstream u-boot so far is that upstream u-boot did not work with the linux-sunxi sunxi-3.4 kernels, but current upstream u-boot git master: http://git.denx.de/?p=u-boot.git;a=summary Now also has support for booting older kernels, so it is time that we stop maintaining linux-sunxi/u-boot-sunxi and start focussing all our efforts on upstream u-boot. 2. How to build upstream u-boot for use with linux-sunxi sunxi-3.4 kernels ========================================================================== Here are some example instructions on how to build upstream u-boot for the Cubietruck: git clone git://git.denx.de/u-boot.git cd u-boot make -j4 CROSS_COMPILE=arm-linux-gnu- Cubietruck_defconfig # If you want to use an upstream kernel the next steps can be skipped (*) make -j4 CROSS_COMPILE=arm-linux-gnu- menuconfig # select "ARM architecture" -> "Enable workarounds for booting old kernels" # exit & save make -j4 CROSS_COMPILE=arm-linux-gnu- spl/menuconfig # select "ARM architecture" -> "Enable workarounds for booting old kernels" # exit & save # skip to here if you're using an upstream kernel make -j4 CROSS_COMPILE=arm-linux-gnu- And now you will have a u-boot-sunxi-with-spl.bin to dd to your sdcard as usual. If you look in the upstream configs directory you will already find defconfig files for a lot of popular boards there, replace Cubietruck_defconfig with the one for your board to build u-boot for your board. See below for instructions on how to add a new board if your board is missing. *) These steps can be skipped too when using sun4i (A10) or sun5i (A10s / A13) with a current linux-sunxi/stage/sunxi-3.4 kernel. 3. Adding more boards to upstream u-boot ======================================== If you own a board which is already supported in linux-sunxi/u-boot-sunxi, and is not yet upstream, please add support for it, there are 3 simple steps to add a new board to upstream u-boot, see below. If you've any trouble with this, but are willing to be listed as a contact person for this board let me know and I'll create a patch adding the board for you to test. 1) Add the dram_foo.c file for your board from linux-sunxi/u-boot-sunxi/board/sunxi to upstream u-boot/board/sunxi and add a line for it to u-boot/board/sunxi/Makefile, see existing lines there for how this should look. 2) Create a configs/foo_defconfig file for your board, take a look at configs/Cubietruck_defconfig for an example, typically all the options found in linux-sunxi/u-boot-sunxi/boards.cfg for the board go in the CONFIG_SYS_EXTRA_OPTIONS field, except for the boardname define, which gets replaced with a line like this: +S:CONFIG_TARGET_CUBIETRUCK=y 3) Add an entry for the board to board/sunxi/MAINTAINERS, with yourself as contact person for the board. For upstream u-boot we want to have a contact person for each supported board, so that users have someone to mail who owns the actual board in case of questions. This is also why we've not simply copied all the boards from linux-sunxi/u-boot-sunxi to upstream u-boot. Regards, Hans

6 10

[U-Boot] Fastboot and MUSB driver on OMAP3
by Paul Kocialkowski 18 Jan '15

18 Jan '15

I've been looking at getting fastboot working on my LG Optimus Black (P970), codename sniper, port. I found out that the BeagleBoard code is using that too, so I copied the required config options: #define CONFIG_MUSB_GADGET #define CONFIG_USB_MUSB_OMAP2PLUS #define CONFIG_MUSB_PIO_ONLY #define CONFIG_USB_GADGET_DUALSPEED #define CONFIG_TWL4030_USB 1 #define CONFIG_USB_ETHER #define CONFIG_USB_ETHER_RNDIS #define CONFIG_USB_GADGET #define CONFIG_USB_GADGET_VBUS_DRAW 0 #define CONFIG_USBDOWNLOAD_GADGET #define CONFIG_G_DNL_VENDOR_NUM 0x0451 #define CONFIG_G_DNL_PRODUCT_NUM 0xd022 #define CONFIG_G_DNL_MANUFACTURER "TI" #define CONFIG_CMD_FASTBOOT #define CONFIG_ANDROID_BOOT_IMAGE #define CONFIG_USB_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR #define CONFIG_USB_FASTBOOT_BUF_SIZE 0x07000000 And removed the ones that relate to the legacy code: -#define CONFIG_MUSB_UDC 1 -#define CONFIG_USB_OMAP3 1 -#define CONFIG_TWL4030_USB 1 -#define CONFIG_USB_DEVICE 1 -#define CONFIG_USB_TTY 1 I also added the relevant "platform" data: http://git.code.paulk.fr/gitweb/?p=u-boot-sniper.git;a=blob;f=board/lge/sni… The current state of the port is available for reference at: http://git.code.paulk.fr/gitweb/?p=u-boot-sniper.git;a=shortlog;h=refs/head… It is not yet ready to be pushed upstream. With all this, I run the fastboot command and UART shows: musb-hdrc: peripheral reset irq lost! On the host side, I get the following messages from dmesg: [11281.565099] usb 3-1: new high-speed USB device number 39 using xhci_hcd [11283.178280] usb 3-1: Device not responding to set address. [11283.378663] usb 3-1: Device not responding to set address. [11283.579739] usb 3-1: device not accepting address 39, error -71 [11283.939123] usb 3-1: new high-speed USB device number 41 using xhci_hcd [11283.939313] usb 3-1: Device not responding to set address. [11284.140316] usb 3-1: Device not responding to set address. [11284.341381] usb 3-1: device not accepting address 41, error -71 and so on until it fails: [11286.007890] hub 3-0:1.0: unable to enumerate USB device on port 1 So it fails early. Is there something more I need to do in order to get the new musb driver to work properly on my device? -- Paul Kocialkowski, Replicant developer Replicant is a fully free Android distribution running on several devices, a free software mobile operating system putting the emphasis on freedom and privacy/security. Website: http://www.replicant.us/ Blog: http://blog.replicant.us/ Wiki/tracker/forums: http://redmine.replicant.us/

1 4

[U-Boot] [PATCH v2] boards.cfg: move many unmaintained boards to Orphan
by Masahiro Yamada 17 Jan '15

17 Jan '15

Emails to the following addresses have been bouncing. Albin Tonnerre <albin.tonnerre(a)free-electrons.com> Anton Shurpin <shurpin.aa(a)niistt.ru> Brent Kandetzki <brentk(a)teleco.com> Dan Malek <dan(a)embeddedalley.com> Frank Panno <fpanno(a)delphintech.com> Gary Jennejohn <garyj(a)denx.de> Hayden Fraser <Hayden.Fraser(a)freescale.com> Eric Millbrandt <emillbrandt(a)dekaresearch.com> Haavard Skinnemoen <haavard.skinnemoen(a)atmel.com> Hans-Christian Egtvedt <hans-christian.egtvedt(a)atmel.com> Kumar Gala <kumar.gala(a)freescale.com> Joe D'Abbraccio <ljd015(a)freescale.com> John Zhan <zhanz(a)sinovee.com> Keith Outwater <Keith_Outwater(a)mvis.com> Julien May <julien.may(a)miromico.ch> Kári Davíðsson <kd(a)flaga.is> Kyle Moffett <Kyle.D.Moffett(a)boeing.com> Leo Sartre <lsartre(a)adeneo-embedded.com> Mike Dunn <mikedunn(a)newsguy.com> Dave Ellis <DGE(a)sixnetio.com> Chan-Taek Park <c-park(a)ti.com> Jerry Van Baren <gerald.vanbaren(a)smiths-aerospace.com> I am Ccing the current working addresses for some of them. If you want to get back an Orphan board to Active, please update your email address. Please do it only if you still have a real hardware to test on. Signed-off-by: Masahiro Yamada <yamada.m(a)jp.panasonic.com> Cc: Albin Tonnerre <albin.tonnerre(a)gmail.com> Cc: Anton Shurpin <anton.shurpin(a)gmail.com> Cc: Brent Kandetzki <brent.kandetzki(a)stw-technic.com> Cc: Dan Malek <dan.malek(a)konsulko.com> Cc: Gary Jennejohn <gljennjohn(a)googlemail.com> Cc: Haavard Skinnemoen <haavard.skinnemoen(a)gmail.com> ? Cc: Hans-Christian Egtvedt <egtvedt(a)samfundet.no> Cc: Kumar Gala <galak(a)kernel.crashing.org> Cc: Mike Dunn <mikedunn(a)newsguy.com> CC: Jerry Van Baren <vanbaren(a)cideas.com> --- Changes in v2: - Add CC of the current working addresses - Orphan "tnetv107xevm" board maintained by Chan-Taek Park <c-park(a)ti.com> because Tom did not respond to my request: https://www.mail-archive.com/u-boot@lists.denx.de/msg139075.html - Orphan "sacsng" board maintained by Jerry Van Baren <gerald.vanbaren(a)smiths-aerospace.com> Ccing his current address Jerry Van Baren <vanbaren(a)cideas.com> boards.cfg | 85 +++++++++++++++++++++++++++++++------------------------------- 1 file changed, 43 insertions(+), 42 deletions(-) diff --git a/boards.cfg b/boards.cfg index 5f6e7bf..535dcca 100644 --- a/boards.cfg +++ b/boards.cfg @@ -59,7 +59,6 @@ Active arm arm1136 mx35 - woodburn Active arm arm1136 mx35 CarMediaLab - flea3 - Stefano Babic <sbabic(a)denx.de> Active arm arm1136 mx35 freescale - mx35pdk - Stefano Babic <sbabic(a)denx.de> Active arm arm1176 bcm2835 raspberrypi rpi_b rpi_b - Stephen Warren <swarren(a)wwwdotorg.org> -Active arm arm1176 tnetv107x ti tnetv107xevm tnetv107x_evm - Chan-Taek Park <c-park(a)ti.com> Active arm arm720t - armltd integrator integratorap_cm720t integratorap:CM720T Linus Walleij <linus.walleij(a)linaro.org> Active arm arm920t - armltd integrator integratorap_cm920t integratorap:CM920T Linus Walleij <linus.walleij(a)linaro.org> Active arm arm920t - armltd integrator integratorcp_cm920t integratorcp:CM920T Linus Walleij <linus.walleij(a)linaro.org> @@ -116,12 +115,6 @@ Active arm arm926ejs at91 bluewater - Active arm arm926ejs at91 bluewater snapper9260 snapper9g20 snapper9260:AT91SAM9G20 Ryan Mallon <ryan(a)bluewatersys.com> Active arm arm926ejs at91 BuS vl_ma2sc vl_ma2sc - Jens Scharsig <esw(a)bus-elektronik.de> Active arm arm926ejs at91 BuS vl_ma2sc vl_ma2sc_ram vl_ma2sc:RAMLOAD Jens Scharsig <esw(a)bus-elektronik.de> -Active arm arm926ejs at91 calao sbc35_a9g20 sbc35_a9g20_eeprom sbc35_a9g20:AT91SAM9G20,SYS_USE_EEPROM Albin Tonnerre <albin.tonnerre(a)free-electrons.com> -Active arm arm926ejs at91 calao sbc35_a9g20 sbc35_a9g20_nandflash sbc35_a9g20:AT91SAM9G20,SYS_USE_NANDFLASH Albin Tonnerre <albin.tonnerre(a)free-electrons.com> -Active arm arm926ejs at91 calao tny_a9260 tny_a9260_eeprom tny_a9260:AT91SAM9260,SYS_USE_EEPROM Albin Tonnerre <albin.tonnerre(a)free-electrons.com> -Active arm arm926ejs at91 calao tny_a9260 tny_a9260_nandflash tny_a9260:AT91SAM9260,SYS_USE_NANDFLASH Albin Tonnerre <albin.tonnerre(a)free-electrons.com> -Active arm arm926ejs at91 calao tny_a9260 tny_a9g20_eeprom tny_a9260:AT91SAM9G20,SYS_USE_EEPROM Albin Tonnerre <albin.tonnerre(a)free-electrons.com> -Active arm arm926ejs at91 calao tny_a9260 tny_a9g20_nandflash tny_a9260:AT91SAM9G20,SYS_USE_NANDFLASH Albin Tonnerre <albin.tonnerre(a)free-electrons.com> Active arm arm926ejs at91 calao usb_a9263 usb_a9263_dataflash usb_a9263:AT91SAM9263,SYS_USE_DATAFLASH Mateusz Kulikowski <mateusz.kulikowski(a)gmail.com> Active arm arm926ejs at91 egnite ethernut5 ethernut5 ethernut5:AT91SAM9XE egnite GmbH <info(a)egnite.de> Active arm arm926ejs at91 emk top9000 top9000eval_xe top9000:EVAL9000 Reinhard Meyer <reinhard.meyer(a)emk-elektronik.de> @@ -320,7 +313,6 @@ Active arm armv7 mx6 boundary nitrogen6x Active arm armv7 mx6 boundary nitrogen6x nitrogen6q2g nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048 Eric Nelson <eric.nelson(a)boundarydevices.com> Active arm armv7 mx6 boundary nitrogen6x nitrogen6s nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512 Eric Nelson <eric.nelson(a)boundarydevices.com> Active arm armv7 mx6 boundary nitrogen6x nitrogen6s1g nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024 Eric Nelson <eric.nelson(a)boundarydevices.com> -Active arm armv7 mx6 congatec cgtqmx6eval cgtqmx6qeval cgtqmx6eval:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q Leo Sartre <lsartre(a)adeneo-embedded.com> Active arm armv7 mx6 embest mx6boards marsboard embestmx6boards:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,ENV_IS_IN_SPI_FLASH Eric Bénard <eric(a)eukrea.com> Active arm armv7 mx6 embest mx6boards riotboard embestmx6boards:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024,ENV_IS_IN_MMC Eric Bénard <eric(a)eukrea.com> Active arm armv7 mx6 freescale mx6qarm2 mx6qarm2 mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg Jason Liu <r64343(a)freescale.com> @@ -409,7 +401,6 @@ Active arm pxa - - - Active arm pxa - - - h2200 - Lukasz Dalek <luk0104(a)gmail.com> Active arm pxa - - - palmld - Marek Vasut <marek.vasut(a)gmail.com> Active arm pxa - - - palmtc - Marek Vasut <marek.vasut(a)gmail.com> -Active arm pxa - - - palmtreo680 - Mike Dunn <mikedunn(a)newsguy.com> Active arm pxa - - - pxa255_idp - Cliff Brake <cliff.brake(a)gmail.com> Active arm pxa - - - trizepsiv - Stefano Babic <sbabic(a)denx.de> Active arm pxa - - - xaeniax - - @@ -421,16 +412,10 @@ Active arm pxa - - vpac270 Active arm pxa - icpdas lp8x4x lp8x4x - Sergey Yanovich <ynvich(a)gmail.com> Active arm pxa - toradex - colibri_pxa270 - Marek Vasut <marek.vasut(a)gmail.com> Active arm sa1100 - - - jornada - Kristoffer Ericson <kristoffer.ericson(a)gmail.com> -Active avr32 at32ap at32ap700x atmel - atngw100 - Haavard Skinnemoen <haavard.skinnemoen(a)atmel.com> Active avr32 at32ap at32ap700x atmel - atngw100mkii - Andreas Bießmann <andreas.devel(a)googlemail.com> -Active avr32 at32ap at32ap700x atmel atstk1000 atstk1002 - Haavard Skinnemoen <haavard.skinnemoen(a)atmel.com> -Active avr32 at32ap at32ap700x atmel atstk1000 atstk1003 - Haavard Skinnemoen <haavard.skinnemoen(a)atmel.com> -Active avr32 at32ap at32ap700x atmel atstk1000 atstk1004 - Haavard Skinnemoen <haavard.skinnemoen(a)atmel.com> -Active avr32 at32ap at32ap700x atmel atstk1000 atstk1006 - Haavard Skinnemoen <haavard.skinnemoen(a)atmel.com> -Active avr32 at32ap at32ap700x earthlcd - favr-32-ezkit - Hans-Christian Egtvedt <hans-christian.egtvedt(a)atmel.com> Active avr32 at32ap at32ap700x in-circuit - grasshopper - Andreas Bießmann <andreas.devel(a)googlemail.com> Active avr32 at32ap at32ap700x mimc - mimc200 - Mark Jackson <mpfj(a)mimc.co.uk> -Active avr32 at32ap at32ap700x miromico - hammerhead - Julien May <julien.may(a)miromico.ch>:Alex Raimondi <alex.raimondi(a)miromico.ch> +Active avr32 at32ap at32ap700x miromico - hammerhead - Alex Raimondi <alex.raimondi(a)miromico.ch> Active blackfin blackfin - - - bct-brettl2 - Peter Meerwald <devel(a)bct-electronic.com> Active blackfin blackfin - - - bf506f-ezkit - Sonic Zhang <sonic.adi(a)gmail.com> Active blackfin blackfin - - - bf518f-ezbrd - Sonic Zhang <sonic.adi(a)gmail.com> @@ -447,7 +432,7 @@ Active blackfin blackfin - - - Active blackfin blackfin - - - bf537-stamp - Sonic Zhang <sonic.adi(a)gmail.com> Active blackfin blackfin - - - bf538f-ezkit - Sonic Zhang <sonic.adi(a)gmail.com> Active blackfin blackfin - - - bf548-ezkit - Sonic Zhang <sonic.adi(a)gmail.com> -Active blackfin blackfin - - - bf561-acvilon - Anton Shurpin <shurpin.aa(a)niistt.ru>:Valentin Yakovenkov <yakovenkov(a)niistt.ru> +Active blackfin blackfin - - - bf561-acvilon - Valentin Yakovenkov <yakovenkov(a)niistt.ru> Active blackfin blackfin - - - bf561-ezkit - Sonic Zhang <sonic.adi(a)gmail.com> Active blackfin blackfin - - - bf609-ezkit - Sonic Zhang <sonic.adi(a)gmail.com> Active blackfin blackfin - - - blackstamp - Wojtek Skulski <skulski(a)pas.rochester.edu>:Wojtek Skulski <info(a)skutek.com>:Benjamin Matthews <mben12(a)gmail.com> @@ -455,7 +440,6 @@ Active blackfin blackfin - - - Active blackfin blackfin - - - br4 - Dimitar Penev <dpn(a)switchfin.org> Active blackfin blackfin - - - dnp5370 - M.Hasewinkel (MHA) <info(a)ssv-embedded.de> Active blackfin blackfin - - - ibf-dsp561 - I-SYST Micromodule <support(a)i-syst.com> -Active blackfin blackfin - - - ip04 - Brent Kandetzki <brentk(a)teleco.com> Active blackfin blackfin - - - pr1 - Dimitar Penev <dpn(a)switchfin.org> Active blackfin blackfin - - bf527-ezkit bf527-ezkit-v2 bf527-ezkit:BF527_EZKIT_REV_2_1 Sonic Zhang <sonic.adi(a)gmail.com> Active m68k mcf5227x - freescale m52277evb M52277EVB M52277EVB:SYS_SPANSION_BOOT,SYS_TEXT_BASE=0x00000000 TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> @@ -469,7 +453,6 @@ Active m68k mcf52x2 - esd tasreg Active m68k mcf52x2 - freescale m5208evbe M5208EVBE - - Active m68k mcf52x2 - freescale m5249evb M5249EVB - - Active m68k mcf52x2 - freescale m5253demo M5253DEMO - TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> -Active m68k mcf52x2 - freescale m5253evbe M5253EVBE - Hayden Fraser <Hayden.Fraser(a)freescale.com> Active m68k mcf52x2 - freescale m5272c3 M5272C3 - - Active m68k mcf52x2 - freescale m5275evb M5275EVB - - Active m68k mcf52x2 - freescale m5282evb M5282EVB - - @@ -567,8 +550,6 @@ Active powerpc mpc5xxx - - a3m071 Active powerpc mpc5xxx - - a3m071 a4m2k a3m071:A4M2K Stefan Roese <sr(a)denx.de> Active powerpc mpc5xxx - - a4m072 a4m072 - Sergei Poselenov <sposelenov(a)emcraft.com> Active powerpc mpc5xxx - - bc3450 BC3450 - - -Active powerpc mpc5xxx - - galaxy5200 galaxy5200 galaxy5200:galaxy5200 Eric Millbrandt <emillbrandt(a)dekaresearch.com> -Active powerpc mpc5xxx - - galaxy5200 galaxy5200_LOWBOOT galaxy5200:galaxy5200_LOWBOOT Eric Millbrandt <emillbrandt(a)dekaresearch.com> Active powerpc mpc5xxx - - icecube icecube_5200 IceCube Wolfgang Denk <wd(a)denx.de> Active powerpc mpc5xxx - - icecube icecube_5200_DDR IceCube:MPC5200_DDR - Active powerpc mpc5xxx - - icecube icecube_5200_DDR_LOWBOOT IceCube:SYS_TEXT_BASE=0xFF800000,MPC5200_DDR - @@ -649,11 +630,9 @@ Active powerpc mpc824x - - eXalion Active powerpc mpc824x - - mvblue MVBLUE - - Active powerpc mpc824x - - sandpoint Sandpoint8240 - Wolfgang Denk <wd(a)denx.de> Active powerpc mpc8260 - - - atc - Wolfgang Denk <wd(a)denx.de> -Active powerpc mpc8260 - - - ep8260 - Frank Panno <fpanno(a)delphintech.com> Active powerpc mpc8260 - - - ep82xxm - - Active powerpc mpc8260 - - - gw8260 - Oliver Brown <obrown(a)adventnetworks.com> Active powerpc mpc8260 - - - hymod - Murray Jensen <Murray.Jensen(a)csiro.au> -Active powerpc mpc8260 - - - sacsng - Jerry Van Baren <gerald.vanbaren(a)smiths-aerospace.com> Active powerpc mpc8260 - - cogent cogent_mpc8260 - Murray Jensen <Murray.Jensen(a)csiro.au> Active powerpc mpc8260 - - cpu86 CPU86 - Wolfgang Denk <wd(a)denx.de> Active powerpc mpc8260 - - cpu86 CPU86_ROMBOOT CPU86:BOOT_ROM Wolfgang Denk <wd(a)denx.de> @@ -727,7 +706,6 @@ Active powerpc mpc83xx - freescale mpc8360emds Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66_SLAVE MPC8360EMDS:CLKIN_66MHZ,PCI,PCISLAVE Dave Liu <daveliu(a)freescale.com> Active powerpc mpc83xx - freescale mpc837xemds MPC837XEMDS - Dave Liu <daveliu(a)freescale.com> Active powerpc mpc83xx - freescale mpc837xemds MPC837XEMDS_HOST MPC837XEMDS:PCI Dave Liu <daveliu(a)freescale.com> -Active powerpc mpc83xx - freescale mpc837xerdb MPC837XERDB - Joe D'Abbraccio <ljd015(a)freescale.com> Active powerpc mpc83xx - ids ids8313 ids8313 ids8313:SYS_TEXT_BASE=0xFFF00000 Heiko Schocher <hs(a)denx.de> Active powerpc mpc83xx - keymile km83xx kmcoge5ne km8360:KMCOGE5NE Holger Brunck <holger.brunck(a)keymile.com> Active powerpc mpc83xx - keymile km83xx kmeter1 km8360:KMETER1 Holger Brunck <holger.brunck(a)keymile.com> @@ -746,7 +724,6 @@ Active powerpc mpc85xx - - sbc8548 Active powerpc mpc85xx - - sbc8548 sbc8548_PCI_66 sbc8548:PCI,66 Paul Gortmaker <paul.gortmaker(a)windriver.com> Active powerpc mpc85xx - - sbc8548 sbc8548_PCI_66_PCIE sbc8548:PCI,66,PCIE Paul Gortmaker <paul.gortmaker(a)windriver.com> Active powerpc mpc85xx - - socrates socrates - - -Active powerpc mpc85xx - exmeritus hww1u1a HWW1U1A - Kyle Moffett <Kyle.D.Moffett(a)boeing.com> Active powerpc mpc85xx - freescale b4860qds B4420QDS B4860QDS:PPC_B4420 - Active powerpc mpc85xx - freescale b4860qds B4420QDS_NAND B4860QDS:PPC_B4420,RAMBOOT_PBL,SPL_FSL_PBL,NAND - Active powerpc mpc85xx - freescale b4860qds B4420QDS_SPIFLASH B4860QDS:PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - @@ -804,16 +781,10 @@ Active powerpc mpc85xx - freescale mpc8536ds Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS_NAND MPC8536DS:NAND - Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS_SDCARD MPC8536DS:SDCARD - Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS_SPIFLASH MPC8536DS:SPIFLASH - -Active powerpc mpc85xx - freescale mpc8540ads MPC8540ADS - Kumar Gala <kumar.gala(a)freescale.com> -Active powerpc mpc85xx - freescale mpc8541cds MPC8541CDS - Kumar Gala <kumar.gala(a)freescale.com> -Active powerpc mpc85xx - freescale mpc8541cds MPC8541CDS_legacy MPC8541CDS:LEGACY Kumar Gala <kumar.gala(a)freescale.com> Active powerpc mpc85xx - freescale mpc8544ds MPC8544DS - - Active powerpc mpc85xx - freescale mpc8548cds MPC8548CDS - - Active powerpc mpc85xx - freescale mpc8548cds MPC8548CDS_36BIT MPC8548CDS:36BIT - Active powerpc mpc85xx - freescale mpc8548cds MPC8548CDS_legacy MPC8548CDS:LEGACY - -Active powerpc mpc85xx - freescale mpc8555cds MPC8555CDS - Kumar Gala <kumar.gala(a)freescale.com> -Active powerpc mpc85xx - freescale mpc8555cds MPC8555CDS_legacy MPC8555CDS:LEGACY Kumar Gala <kumar.gala(a)freescale.com> -Active powerpc mpc85xx - freescale mpc8560ads MPC8560ADS - Kumar Gala <kumar.gala(a)freescale.com> Active powerpc mpc85xx - freescale mpc8568mds MPC8568MDS - - Active powerpc mpc85xx - freescale mpc8569mds MPC8569MDS - - Active powerpc mpc85xx - freescale mpc8569mds MPC8569MDS_ATM MPC8569MDS:ATM - @@ -998,31 +969,22 @@ Active powerpc mpc85xx - gdsys p1022 Active powerpc mpc85xx - gdsys p1022 controlcenterd_TRAILBLAZER_DEVELOP controlcenterd:TRAILBLAZER,SPIFLASH,DEVELOP Dirk Eibach <eibach(a)gdsys.de> Active powerpc mpc85xx - keymile kmp204x kmcoge4 kmp204x:KMCOGE4 Valentin Longchamp <valentin.longchamp(a)keymile.com> Active powerpc mpc85xx - keymile kmp204x kmlion1 kmp204x:KMLION1 Valentin Longchamp <valentin.longchamp(a)keymile.com> -Active powerpc mpc85xx - stx stxgp3 stxgp3 - Dan Malek <dan(a)embeddedalley.com> -Active powerpc mpc85xx - stx stxssa stxssa - Dan Malek <dan(a)embeddedalley.com> -Active powerpc mpc85xx - stx stxssa stxssa_4M stxssa:STXSSA_4M Dan Malek <dan(a)embeddedalley.com> Active powerpc mpc85xx - xes - xpedite520x - - Active powerpc mpc85xx - xes - xpedite537x - - Active powerpc mpc85xx - xes - xpedite550x - - Active powerpc mpc86xx - - - sbc8641d - Paul Gortmaker <paul.gortmaker(a)windriver.com> Active powerpc mpc86xx - freescale mpc8610hpcd MPC8610HPCD - - -Active powerpc mpc86xx - freescale mpc8641hpcn MPC8641HPCN - Kumar Gala <kumar.gala(a)freescale.com> -Active powerpc mpc86xx - freescale mpc8641hpcn MPC8641HPCN_36BIT MPC8641HPCN:PHYS_64BIT Kumar Gala <kumar.gala(a)freescale.com> Active powerpc mpc86xx - xes - xpedite517x - - Active powerpc mpc8xx - - - hermes - Wolfgang Denk <wd(a)denx.de> Active powerpc mpc8xx - - - lwmon - Wolfgang Denk <wd(a)denx.de> Active powerpc mpc8xx - - - quantum - - Active powerpc mpc8xx - - - RRvision - Wolfgang Denk <wd(a)denx.de> Active powerpc mpc8xx - - - spc1920 - - -Active powerpc mpc8xx - - - svm_sc8xx - John Zhan <zhanz(a)sinovee.com> Active powerpc mpc8xx - - - v37 - - Active powerpc mpc8xx - - cogent cogent_mpc8xx - Murray Jensen <Murray.Jensen(a)csiro.au> Active powerpc mpc8xx - - esteem192e ESTEEM192E - Conn Clark <clark(a)esteem.com> Active powerpc mpc8xx - - fads MPC86xADS - - Active powerpc mpc8xx - - fads MPC885ADS - - -Active powerpc mpc8xx - - flagadm FLAGADM - Kári Davíðsson <kd(a)flaga.is> -Active powerpc mpc8xx - - gen860t GEN860T - Keith Outwater <Keith_Outwater(a)mvis.com> -Active powerpc mpc8xx - - gen860t GEN860T_SC GEN860T:SC Keith Outwater <Keith_Outwater(a)mvis.com> Active powerpc mpc8xx - - icu862 ICU862 - Wolfgang Denk <wd(a)denx.de> Active powerpc mpc8xx - - icu862 ICU862_100MHz ICU862:100MHz Wolfgang Denk <wd(a)denx.de> Active powerpc mpc8xx - - ip860 IP860 - Wolfgang Denk <wd(a)denx.de> @@ -1057,7 +1019,6 @@ Active powerpc mpc8xx - - RPXlite_dw Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_NVRAM_64_LCD RPXlite_DW:RPXlite_64MHz,LCD,NEC_NL6448BC20,ENV_IS_IN_NVRAM - Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_NVRAM_LCD RPXlite_DW:LCD,NEC_NL6448BC20,ENV_IS_IN_NVRAM - Active powerpc mpc8xx - - RRvision RRvision_LCD RRvision:LCD,SHARP_LQ104V7DS01 Wolfgang Denk <wd(a)denx.de> -Active powerpc mpc8xx - - sixnet SXNI855T - Dave Ellis <DGE(a)sixnetio.com> Active powerpc mpc8xx - - spd8xx SPD823TS - Wolfgang Denk <wd(a)denx.de> Active powerpc mpc8xx - eltec mhpc MHPC - Frank Gottschling <fgottschling(a)eltec.de> Active powerpc mpc8xx - emk top860 TOP860 - Reinhard Meyer <reinhard.meyer(a)emk-elektronik.de> @@ -1068,7 +1029,6 @@ Active powerpc mpc8xx - manroland - Active powerpc mpc8xx - snmc qs850 QS823 - - Active powerpc mpc8xx - snmc qs850 QS850 - - Active powerpc mpc8xx - snmc qs860t QS860T - - -Active powerpc mpc8xx - stx stxxtc stxxtc - Dan Malek <dan(a)embeddedalley.com> Active powerpc mpc8xx - tqc tqm8xx FPS850L - Wolfgang Denk <wd(a)denx.de> Active powerpc mpc8xx - tqc tqm8xx FPS860L - Wolfgang Denk <wd(a)denx.de> Active powerpc mpc8xx - tqc tqm8xx NSCU - - @@ -1219,6 +1179,47 @@ Active sparc leon3 - gaisler - Active sparc leon3 - gaisler - gr_xc3s_1500 - - Active sparc leon3 - gaisler - grsim - - Active x86 x86 coreboot chromebook-x86 coreboot coreboot-x86 coreboot:SYS_TEXT_BASE=0x01110000 Simon Glass <sjg(a)chromium.org> +# The following were moved to "Orphan" in June, 2014 +Orphan arm arm1176 tnetv107x ti tnetv107xevm tnetv107x_evm - Chan-Taek Park <c-park(a)ti.com> +Orphan arm arm926ejs at91 calao sbc35_a9g20 sbc35_a9g20_eeprom sbc35_a9g20:AT91SAM9G20,SYS_USE_EEPROM Albin Tonnerre <albin.tonnerre(a)free-electrons.com> +Orphan arm arm926ejs at91 calao sbc35_a9g20 sbc35_a9g20_nandflash sbc35_a9g20:AT91SAM9G20,SYS_USE_NANDFLASH Albin Tonnerre <albin.tonnerre(a)free-electrons.com> +Orphan arm arm926ejs at91 calao tny_a9260 tny_a9260_eeprom tny_a9260:AT91SAM9260,SYS_USE_EEPROM Albin Tonnerre <albin.tonnerre(a)free-electrons.com> +Orphan arm arm926ejs at91 calao tny_a9260 tny_a9260_nandflash tny_a9260:AT91SAM9260,SYS_USE_NANDFLASH Albin Tonnerre <albin.tonnerre(a)free-electrons.com> +Orphan arm arm926ejs at91 calao tny_a9260 tny_a9g20_eeprom tny_a9260:AT91SAM9G20,SYS_USE_EEPROM Albin Tonnerre <albin.tonnerre(a)free-electrons.com> +Orphan arm arm926ejs at91 calao tny_a9260 tny_a9g20_nandflash tny_a9260:AT91SAM9G20,SYS_USE_NANDFLASH Albin Tonnerre <albin.tonnerre(a)free-electrons.com> +Orphan arm armv7 mx6 congatec cgtqmx6eval cgtqmx6qeval cgtqmx6eval:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q Leo Sartre <lsartre(a)adeneo-embedded.com> +Orphan arm pxa - - - palmtreo680 - Mike Dunn <mikedunn(a)newsguy.com> +Orphan avr32 at32ap at32ap700x atmel - atngw100 - Haavard Skinnemoen <haavard.skinnemoen(a)atmel.com> +Orphan avr32 at32ap at32ap700x atmel atstk1000 atstk1002 - Haavard Skinnemoen <haavard.skinnemoen(a)atmel.com> +Orphan avr32 at32ap at32ap700x atmel atstk1000 atstk1003 - Haavard Skinnemoen <haavard.skinnemoen(a)atmel.com> +Orphan avr32 at32ap at32ap700x atmel atstk1000 atstk1004 - Haavard Skinnemoen <haavard.skinnemoen(a)atmel.com> +Orphan avr32 at32ap at32ap700x atmel atstk1000 atstk1006 - Haavard Skinnemoen <haavard.skinnemoen(a)atmel.com> +Orphan avr32 at32ap at32ap700x earthlcd - favr-32-ezkit - Hans-Christian Egtvedt <hans-christian.egtvedt(a)atmel.com> +Orphan blackfin blackfin - - - ip04 - Brent Kandetzki <brentk(a)teleco.com> +Orphan m68k mcf52x2 - freescale m5253evbe M5253EVBE - Hayden Fraser <Hayden.Fraser(a)freescale.com> +Orphan powerpc mpc5xxx - - galaxy5200 galaxy5200 galaxy5200:galaxy5200 Eric Millbrandt <emillbrandt(a)dekaresearch.com> +Orphan powerpc mpc5xxx - - galaxy5200 galaxy5200_LOWBOOT galaxy5200:galaxy5200_LOWBOOT Eric Millbrandt <emillbrandt(a)dekaresearch.com> +Orphan powerpc mpc8260 - - - ep8260 - Frank Panno <fpanno(a)delphintech.com> +Orphan powerpc mpc8260 - - - sacsng - Jerry Van Baren <gerald.vanbaren(a)smiths-aerospace.com> +Orphan powerpc mpc83xx - freescale mpc837xerdb MPC837XERDB - Joe D'Abbraccio <ljd015(a)freescale.com> +Orphan powerpc mpc85xx - exmeritus hww1u1a HWW1U1A - Kyle Moffett <Kyle.D.Moffett(a)boeing.com> +Orphan powerpc mpc85xx - freescale mpc8540ads MPC8540ADS - Kumar Gala <kumar.gala(a)freescale.com> +Orphan powerpc mpc85xx - freescale mpc8541cds MPC8541CDS - Kumar Gala <kumar.gala(a)freescale.com> +Orphan powerpc mpc85xx - freescale mpc8541cds MPC8541CDS_legacy MPC8541CDS:LEGACY Kumar Gala <kumar.gala(a)freescale.com> +Orphan powerpc mpc85xx - freescale mpc8555cds MPC8555CDS - Kumar Gala <kumar.gala(a)freescale.com> +Orphan powerpc mpc85xx - freescale mpc8555cds MPC8555CDS_legacy MPC8555CDS:LEGACY Kumar Gala <kumar.gala(a)freescale.com> +Orphan powerpc mpc85xx - freescale mpc8560ads MPC8560ADS - Kumar Gala <kumar.gala(a)freescale.com> +Orphan powerpc mpc85xx - stx stxgp3 stxgp3 - Dan Malek <dan(a)embeddedalley.com> +Orphan powerpc mpc85xx - stx stxssa stxssa - Dan Malek <dan(a)embeddedalley.com> +Orphan powerpc mpc85xx - stx stxssa stxssa_4M stxssa:STXSSA_4M Dan Malek <dan(a)embeddedalley.com> +Orphan powerpc mpc86xx - freescale mpc8641hpcn MPC8641HPCN - Kumar Gala <kumar.gala(a)freescale.com> +Orphan powerpc mpc86xx - freescale mpc8641hpcn MPC8641HPCN_36BIT MPC8641HPCN:PHYS_64BIT Kumar Gala <kumar.gala(a)freescale.com> +Orphan powerpc mpc8xx - - - svm_sc8xx - John Zhan <zhanz(a)sinovee.com> +Orphan powerpc mpc8xx - - flagadm FLAGADM - Kári Davíðsson <kd(a)flaga.is> +Orphan powerpc mpc8xx - - gen860t GEN860T - Keith Outwater <Keith_Outwater(a)mvis.com> +Orphan powerpc mpc8xx - - gen860t GEN860T_SC GEN860T:SC Keith Outwater <Keith_Outwater(a)mvis.com> +Orphan powerpc mpc8xx - - sixnet SXNI855T - Dave Ellis <DGE(a)sixnetio.com> +Orphan powerpc mpc8xx - stx stxxtc stxxtc - Dan Malek <dan(a)embeddedalley.com> # The following were moved to "Orphan" in April, 2014 Orphan powerpc 74xx_7xx - - evb64260 ZUMA - Nye Liu <nyet(a)zumanetworks.com> Orphan powerpc mpc824x - - musenki MUSENKI - Jim Thompson <jim(a)musenki.com> -- 1.9.1

4 8

[U-Boot] [PATCH v4] Export redesign
by Martin Dorwig 16 Jan '15

16 Jan '15

this is an atempt to make the export of functions typesafe. I replaced the jumptable void ** by a struct (jt_funcs) with function pointers. The EXPORT_FUNC macro now has 3 fixed parameters and one variadic parameter The first is the name of the exported function, the rest of the parameters are used to format a functionpointer in the jumptable, the EXPORT_FUNC macros are expanded three times, 1. to declare the members of the struct 2. to initialize the structmember pointers 3. to call the functions in stubs.c Signed-off-by: Martin Dorwig <dorwig(a)tetronik.com> --- Changes in v4: - add forward decl. for struct spi_slave to export.h Changes in v3: - install_hdlr/free_hdlr must be dummy, since they do not exist - blackfin cpu.c must include exports.h - rebased to master - take CONFIG_DM_SPI into account Changes in v2: - redesign the way functions are exported to standalone applications arch/blackfin/cpu/cpu.c | 3 +- board/BuS/eb_cpux9k2/cpux9k2.c | 2 +- common/cmd_load.c | 2 +- common/console.c | 20 ++++---- common/exports.c | 28 ++--------- doc/README.standalone | 41 +++++++++++----- examples/standalone/stubs.c | 64 ++++++++++++------------- include/_exports.h | 98 +++++++++++++++++++++++++++------------ include/asm-generic/global_data.h | 2 +- include/exports.h | 17 +++---- 10 files changed, 159 insertions(+), 118 deletions(-) diff --git a/arch/blackfin/cpu/cpu.c b/arch/blackfin/cpu/cpu.c index b7f1188..91aa5cc 100644 --- a/arch/blackfin/cpu/cpu.c +++ b/arch/blackfin/cpu/cpu.c @@ -24,6 +24,7 @@ #include "cpu.h" #include "initcode.h" +#include "exports.h" ulong bfin_poweron_retx; DECLARE_GLOBAL_DATA_PTR; @@ -121,7 +122,7 @@ static void display_global_data(void) printf(" |-ram_size: %lx\n", gd->ram_size); printf(" |-env_addr: %lx\n", gd->env_addr); printf(" |-env_valid: %lx\n", gd->env_valid); - printf(" |-jt(%p): %p\n", gd->jt, *(gd->jt)); + printf(" |-jt(%p): %p\n", gd->jt, gd->jt->get_version); printf(" \\-bd: %p\n", gd->bd); printf(" |-bi_boot_params: %lx\n", bd->bi_boot_params); printf(" |-bi_memstart: %lx\n", bd->bi_memstart); diff --git a/board/BuS/eb_cpux9k2/cpux9k2.c b/board/BuS/eb_cpux9k2/cpux9k2.c index 5e4778e..76ad7c4 100644 --- a/board/BuS/eb_cpux9k2/cpux9k2.c +++ b/board/BuS/eb_cpux9k2/cpux9k2.c @@ -98,7 +98,7 @@ int misc_init_r(void) puts("Error: invalid MAC at EEPROM\n"); } } - gd->jt[XF_do_reset] = (void *) do_reset; + gd->jt->do_reset = do_reset; #ifdef CONFIG_STATUS_LED status_led_set(STATUS_LED_BOOT, STATUS_LED_BLINKING); diff --git a/common/cmd_load.c b/common/cmd_load.c index f6e522c..d043e6d 100644 --- a/common/cmd_load.c +++ b/common/cmd_load.c @@ -222,7 +222,7 @@ static int read_record(char *buf, ulong len) } /* Check for the console hangup (if any different from serial) */ - if (gd->jt[XF_getc] != getc) { + if (gd->jt->getc != getc) { if (ctrlc()) { return (-1); } diff --git a/common/console.c b/common/console.c index 4695386..1ccb750 100644 --- a/common/console.c +++ b/common/console.c @@ -125,13 +125,13 @@ static int console_setfile(int file, struct stdio_dev * dev) */ switch (file) { case stdin: - gd->jt[XF_getc] = dev->getc; - gd->jt[XF_tstc] = dev->tstc; + gd->jt->getc = getc; + gd->jt->tstc = tstc; break; case stdout: - gd->jt[XF_putc] = dev->putc; - gd->jt[XF_puts] = dev->puts; - gd->jt[XF_printf] = printf; + gd->jt->putc = putc; + gd->jt->puts = puts; + gd->jt->printf = printf; break; } break; @@ -723,11 +723,11 @@ int console_init_r(void) #endif /* set default handlers at first */ - gd->jt[XF_getc] = serial_getc; - gd->jt[XF_tstc] = serial_tstc; - gd->jt[XF_putc] = serial_putc; - gd->jt[XF_puts] = serial_puts; - gd->jt[XF_printf] = serial_printf; + gd->jt->getc = serial_getc; + gd->jt->tstc = serial_tstc; + gd->jt->putc = serial_putc; + gd->jt->puts = serial_puts; + gd->jt->printf = serial_printf; /* stdin stdout and stderr are in environment */ /* scan for it */ diff --git a/common/exports.c b/common/exports.c index 88fcfc8..333107c 100644 --- a/common/exports.c +++ b/common/exports.c @@ -1,6 +1,7 @@ #include <common.h> #include <exports.h> #include <spi.h> +#include <i2c.h> DECLARE_GLOBAL_DATA_PTR; @@ -13,33 +14,10 @@ unsigned long get_version(void) return XF_VERSION; } -/* Reuse _exports.h with a little trickery to avoid bitrot */ -#define EXPORT_FUNC(sym) gd->jt[XF_##sym] = (void *)sym; - -#if !defined(CONFIG_X86) && !defined(CONFIG_PPC) -# define install_hdlr dummy -# define free_hdlr dummy -#else /* kludge for non-standard function naming */ -# define install_hdlr irq_install_handler -# define free_hdlr irq_free_handler -#endif -#ifndef CONFIG_CMD_I2C -# define i2c_write dummy -# define i2c_read dummy -#endif -#if !defined(CONFIG_CMD_SPI) || defined(CONFIG_DM_SPI) -# define spi_init dummy -# define spi_setup_slave dummy -# define spi_free_slave dummy -#endif -#ifndef CONFIG_CMD_SPI -# define spi_claim_bus dummy -# define spi_release_bus dummy -# define spi_xfer dummy -#endif +#define EXPORT_FUNC(f, a, x, ...) gd->jt->x = f; void jumptable_init(void) { - gd->jt = malloc(XF_MAX * sizeof(void *)); + gd->jt = malloc(sizeof(struct jt_funcs)); #include <_exports.h> } diff --git a/doc/README.standalone b/doc/README.standalone index e3000ef..659a12f 100644 --- a/doc/README.standalone +++ b/doc/README.standalone @@ -5,18 +5,18 @@ Design Notes on Exporting U-Boot Functions to Standalone Applications: table is allocated and initialized in the jumptable_init() routine (common/exports.c). Other routines may also modify the jump table, however. The jump table can be accessed as the 'jt' field of the - 'global_data' structure. The slot numbers for the jump table are + 'global_data' structure. The struct members for the jump table are defined in the <include/exports.h> header. E.g., to substitute the malloc() and free() functions that will be available to standalone applications, one should do the following: DECLARE_GLOBAL_DATA_PTR; - gd->jt[XF_malloc] = my_malloc; - gd->jt[XF_free] = my_free; + gd->jt->malloc = my_malloc; + gd->jt->free = my_free; - Note that the pointers to the functions all have 'void *' type and - thus the compiler cannot perform type checks on these assignments. + Note that the pointers to the functions are real function pointers + so the compiler can perform type checks on these assignments. 2. The pointer to the jump table is passed to the application in a machine-dependent way. PowerPC, ARM, MIPS, Blackfin and Nios II @@ -65,27 +65,46 @@ Design Notes on Exporting U-Boot Functions to Standalone Applications: => tftp 0x40000 hello_world.bin => go 0x40004 -5. To export some additional function foobar(), the following steps +5. To export some additional function long foobar(int i,char c), the following steps should be undertaken: - Append the following line at the end of the include/_exports.h file: - EXPORT_FUNC(foobar) + EXPORT_FUNC(foobar, long, foobar, int, char) + + Parameters to EXPORT_FUNC: + - the first parameter is the function that is exported (default implementation) + - the second parameter is the return value type + - the third parameter is the name of the member in struct jt_funcs + this is also the name that the standalone application will used. + the rest of the parameters are the function arguments - Add the prototype for this function to the include/exports.h file: - void foobar(void); + long foobar(int i, char c); + + Initialization with the default implementation is done in jumptable_init() + + You can override the default implementation using: - - Add the initialization of the jump table slot wherever - appropriate (most likely, to the jumptable_init() function): + gd->jt->foobar = another_foobar; - gd->jt[XF_foobar] = foobar; + The signature of another_foobar must then match the declaration of foobar. - Increase the XF_VERSION value by one in the include/exports.h file + - If you want to export a function which depends on a CONFIG_XXX + use 2 lines like this: + #ifdef CONFIG_FOOBAR + EXPORT_FUNC(foobar, long, foobar, int, char) + #else + EXPORT_FUNC(dummy, void, foobar, void) + #endif + + 6. The code for exporting the U-Boot functions to applications is mostly machine-independent. The only places written in assembly language are stub functions that perform the jump through the jump diff --git a/examples/standalone/stubs.c b/examples/standalone/stubs.c index 0bf690e..920a0a9 100644 --- a/examples/standalone/stubs.c +++ b/examples/standalone/stubs.c @@ -2,6 +2,8 @@ #include <exports.h> #include <linux/compiler.h> +#define FO(x) offsetof(struct jt_funcs, x) + #if defined(CONFIG_X86) /* * x86 does not have a dedicated register to store the pointer to @@ -10,23 +12,23 @@ * from flash memory. The global_data address is passed as argv[-1] * to the application program. */ -static void **jt; +static struct jt_funcs *jt; gd_t *global_data; -#define EXPORT_FUNC(x) \ +#define EXPORT_FUNC(f, a, x, ...) \ asm volatile ( \ " .globl " #x "\n" \ #x ":\n" \ " movl %0, %%eax\n" \ " movl jt, %%ecx\n" \ " jmp *(%%ecx, %%eax)\n" \ - : : "i"(XF_ ## x * sizeof(void *)) : "eax", "ecx"); + : : "i"(FO(x)) : "eax", "ecx"); #elif defined(CONFIG_PPC) /* * r2 holds the pointer to the global_data, r11 is a call-clobbered * register */ -#define EXPORT_FUNC(x) \ +#define EXPORT_FUNC(f, a, x, ...) \ asm volatile ( \ " .globl " #x "\n" \ #x ":\n" \ @@ -34,33 +36,33 @@ gd_t *global_data; " lwz %%r11, %1(%%r11)\n" \ " mtctr %%r11\n" \ " bctr\n" \ - : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "r11"); + : : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "r11"); #elif defined(CONFIG_ARM) #ifdef CONFIG_ARM64 /* * x18 holds the pointer to the global_data, x9 is a call-clobbered * register */ -#define EXPORT_FUNC(x) \ +#define EXPORT_FUNC(f, a, x, ...) \ asm volatile ( \ " .globl " #x "\n" \ #x ":\n" \ " ldr x9, [x18, %0]\n" \ " ldr x9, [x9, %1]\n" \ " br x9\n" \ - : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "x9"); + : : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "x9"); #else /* * r9 holds the pointer to the global_data, ip is a call-clobbered * register */ -#define EXPORT_FUNC(x) \ +#define EXPORT_FUNC(f, a, x, ...) \ asm volatile ( \ " .globl " #x "\n" \ #x ":\n" \ " ldr ip, [r9, %0]\n" \ " ldr pc, [ip, %1]\n" \ - : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "ip"); + : : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "ip"); #endif #elif defined(CONFIG_MIPS) /* @@ -70,19 +72,19 @@ gd_t *global_data; * it; however, GCC/mips generates an additional `nop' after each asm * statement */ -#define EXPORT_FUNC(x) \ +#define EXPORT_FUNC(f, a, x, ...) \ asm volatile ( \ " .globl " #x "\n" \ #x ":\n" \ " lw $25, %0($26)\n" \ " lw $25, %1($25)\n" \ " jr $25\n" \ - : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "t9"); + : : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "t9"); #elif defined(CONFIG_NIOS2) /* * gp holds the pointer to the global_data, r8 is call-clobbered */ -#define EXPORT_FUNC(x) \ +#define EXPORT_FUNC(f, a, x, ...) \ asm volatile ( \ " .globl " #x "\n" \ #x ":\n" \ @@ -92,13 +94,13 @@ gd_t *global_data; " ldw r8, 0(r8)\n" \ " ldw r8, %1(r8)\n" \ " jmp r8\n" \ - : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "gp"); + : : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "gp"); #elif defined(CONFIG_M68K) /* * d7 holds the pointer to the global_data, a0 is a call-clobbered * register */ -#define EXPORT_FUNC(x) \ +#define EXPORT_FUNC(f, a, x, ...) \ asm volatile ( \ " .globl " #x "\n" \ #x ":\n" \ @@ -108,50 +110,50 @@ gd_t *global_data; " adda.l %1, %%a0\n" \ " move.l (%%a0), %%a0\n" \ " jmp (%%a0)\n" \ - : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "a0"); + : : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "a0"); #elif defined(CONFIG_MICROBLAZE) /* * r31 holds the pointer to the global_data. r5 is a call-clobbered. */ -#define EXPORT_FUNC(x) \ +#define EXPORT_FUNC(f, a, x, ...) \ asm volatile ( \ " .globl " #x "\n" \ #x ":\n" \ " lwi r5, r31, %0\n" \ " lwi r5, r5, %1\n" \ " bra r5\n" \ - : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "r5"); + : : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "r5"); #elif defined(CONFIG_BLACKFIN) /* * P3 holds the pointer to the global_data, P0 is a call-clobbered * register */ -#define EXPORT_FUNC(x) \ +#define EXPORT_FUNC(f, a, x, ...) \ asm volatile ( \ " .globl _" #x "\n_" \ #x ":\n" \ " P0 = [P3 + %0]\n" \ " P0 = [P0 + %1]\n" \ " JUMP (P0)\n" \ - : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "P0"); + : : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "P0"); #elif defined(CONFIG_AVR32) /* * r6 holds the pointer to the global_data. r8 is call clobbered. */ -#define EXPORT_FUNC(x) \ +#define EXPORT_FUNC(f, a, x, ...) \ asm volatile( \ " .globl\t" #x "\n" \ #x ":\n" \ " ld.w r8, r6[%0]\n" \ " ld.w pc, r8[%1]\n" \ : \ - : "i"(offsetof(gd_t, jt)), "i"(XF_ ##x) \ + : "i"(offsetof(gd_t, jt)), "i"(FO(x)) \ : "r8"); #elif defined(CONFIG_SH) /* * r13 holds the pointer to the global_data. r1 is a call clobbered. */ -#define EXPORT_FUNC(x) \ +#define EXPORT_FUNC(f, a, x, ...) \ asm volatile ( \ " .align 2\n" \ " .globl " #x "\n" \ @@ -164,12 +166,12 @@ gd_t *global_data; " jmp @r1\n" \ " nop\n" \ " nop\n" \ - : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "r1", "r2"); + : : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "r1", "r2"); #elif defined(CONFIG_SPARC) /* * g7 holds the pointer to the global_data. g1 is call clobbered. */ -#define EXPORT_FUNC(x) \ +#define EXPORT_FUNC(f, a, x, ...) \ asm volatile( \ " .globl\t" #x "\n" \ #x ":\n" \ @@ -179,26 +181,26 @@ gd_t *global_data; " ld [%%g1 + %1], %%g1\n" \ " jmp %%g1\n" \ " nop\n" \ - : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "g1" ); + : : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "g1"); #elif defined(CONFIG_NDS32) /* * r16 holds the pointer to the global_data. gp is call clobbered. * not support reduced register (16 GPR). */ -#define EXPORT_FUNC(x) \ +#define EXPORT_FUNC(f, a, x, ...) \ asm volatile ( \ " .globl " #x "\n" \ #x ":\n" \ " lwi $r16, [$gp + (%0)]\n" \ " lwi $r16, [$r16 + (%1)]\n" \ " jr $r16\n" \ - : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "$r16"); + : : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "$r16"); #elif defined(CONFIG_OPENRISC) /* * r10 holds the pointer to the global_data, r13 is a call-clobbered * register */ -#define EXPORT_FUNC(x) \ +#define EXPORT_FUNC(f, a, x, ...) \ asm volatile ( \ " .globl " #x "\n" \ #x ":\n" \ @@ -206,12 +208,12 @@ gd_t *global_data; " l.lwz r13, %1(r13)\n" \ " l.jr r13\n" \ " l.nop\n" \ - : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "r13"); + : : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "r13"); #elif defined(CONFIG_ARC) /* * r25 holds the pointer to the global_data. r10 is call clobbered. */ -#define EXPORT_FUNC(x) \ +#define EXPORT_FUNC(f, a, x, ...) \ asm volatile( \ " .align 4\n" \ " .globl " #x "\n" \ @@ -219,7 +221,7 @@ gd_t *global_data; " ld r10, [r25, %0]\n" \ " ld r10, [r10, %1]\n" \ " j [r10]\n" \ - : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "r10"); + : : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "r10"); #else /*" addi $sp, $sp, -24\n" \ " br $r16\n" \*/ diff --git a/include/_exports.h b/include/_exports.h index 349a3c5..14e6918 100644 --- a/include/_exports.h +++ b/include/_exports.h @@ -1,32 +1,72 @@ /* - * You do not need to use #ifdef around functions that may not exist + * You need to use #ifdef around functions that may not exist * in the final configuration (such as i2c). + * use a dummyfunction as first parameter to EXPORT_FUNC. + * As an example see the CONFIG_CMD_I2C section below */ -EXPORT_FUNC(get_version) -EXPORT_FUNC(getc) -EXPORT_FUNC(tstc) -EXPORT_FUNC(putc) -EXPORT_FUNC(puts) -EXPORT_FUNC(printf) -EXPORT_FUNC(install_hdlr) -EXPORT_FUNC(free_hdlr) -EXPORT_FUNC(malloc) -EXPORT_FUNC(free) -EXPORT_FUNC(udelay) -EXPORT_FUNC(get_timer) -EXPORT_FUNC(vprintf) -EXPORT_FUNC(do_reset) -EXPORT_FUNC(getenv) -EXPORT_FUNC(setenv) -EXPORT_FUNC(simple_strtoul) -EXPORT_FUNC(strict_strtoul) -EXPORT_FUNC(simple_strtol) -EXPORT_FUNC(strcmp) -EXPORT_FUNC(i2c_write) -EXPORT_FUNC(i2c_read) -EXPORT_FUNC(spi_init) -EXPORT_FUNC(spi_setup_slave) -EXPORT_FUNC(spi_free_slave) -EXPORT_FUNC(spi_claim_bus) -EXPORT_FUNC(spi_release_bus) -EXPORT_FUNC(spi_xfer) +#ifndef EXPORT_FUNC +#define EXPORT_FUNC(a, b, c, ...) +#endif + EXPORT_FUNC(get_version, unsigned long, get_version, void) + EXPORT_FUNC(getc, int, getc, void) + EXPORT_FUNC(tstc, int, tstc, void) + EXPORT_FUNC(putc, void, putc, const char) + EXPORT_FUNC(puts, void, puts, const char *) + EXPORT_FUNC(printf, int, printf, const char*, ...) +#if defined(CONFIG_X86) || defined(CONFIG_PPC) + EXPORT_FUNC(irq_install_handler, void, install_hdlr, + int, interrupt_handler_t, void*) + + EXPORT_FUNC(irq_free_handler, void, free_hdlr, int) +#else + EXPORT_FUNC(dummy, void, install_hdlr, void) + EXPORT_FUNC(dummy, void, free_hdlr, void) +#endif + EXPORT_FUNC(malloc, void *, malloc, size_t) + EXPORT_FUNC(free, void, free, void *) + EXPORT_FUNC(udelay, void, udelay, unsigned long) + EXPORT_FUNC(get_timer, unsigned long, get_timer, unsigned long) + EXPORT_FUNC(vprintf, int, vprintf, const char *, va_list) + EXPORT_FUNC(do_reset, int, do_reset, cmd_tbl_t *, + int , int , char * const []) + EXPORT_FUNC(getenv, char *, getenv, const char*) + EXPORT_FUNC(setenv, int, setenv, const char *, const char *) + EXPORT_FUNC(simple_strtoul, unsigned long, simple_strtoul, + const char *, char **, unsigned int) + EXPORT_FUNC(strict_strtoul, int, strict_strtoul, + const char *, unsigned int , unsigned long *) + EXPORT_FUNC(simple_strtol, long, simple_strtol, + const char *, char **, unsigned int) + EXPORT_FUNC(strcmp, int, strcmp, const char *cs, const char *ct) +#ifdef CONFIG_CMD_I2C + EXPORT_FUNC(i2c_write, int, i2c_write, uchar, uint, int , uchar * , int) + EXPORT_FUNC(i2c_read, int, i2c_read, uchar, uint, int , uchar * , int) +#else + EXPORT_FUNC(dummy, void, i2c_write, void) + EXPORT_FUNC(dummy, void, i2c_read, void) +#endif + +#if !defined(CONFIG_CMD_SPI) || defined(CONFIG_DM_SPI) + EXPORT_FUNC(dummy, void, spi_init, void) + EXPORT_FUNC(dummy, void, spi_setup_slave, void) + EXPORT_FUNC(dummy, void, spi_free_slave, void) +#else + EXPORT_FUNC(spi_init, void, spi_init, void) + EXPORT_FUNC(spi_setup_slave, struct spi_slave *, spi_setup_slave, + unsigned int, unsigned int, unsigned int, unsigned int) + EXPORT_FUNC(spi_free_slave, void, spi_free_slave, struct spi_slave *) +#endif +#ifndef CONFIG_CMD_SPI + EXPORT_FUNC(dummy, void, spi_claim_bus, void) + EXPORT_FUNC(dummy, void, spi_release_bus, void) + EXPORT_FUNC(dummy, void, spi_xfer, void) +#else + EXPORT_FUNC(spi_claim_bus, int, spi_claim_bus, struct spi_slave *) + EXPORT_FUNC(spi_release_bus, void, spi_release_bus, struct spi_slave *) + EXPORT_FUNC(spi_xfer, int, spi_xfer, struct spi_slave *, + unsigned int, const void *, void *, unsigned long) +#endif + EXPORT_FUNC(ustrtoul, unsigned long, ustrtoul, + const char *, char **, unsigned int) + EXPORT_FUNC(ustrtoull, unsigned long long, ustrtoull, + const char *, char **, unsigned int) diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index 9c5a1e1..070b7ac 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -73,7 +73,7 @@ typedef struct global_data { const void *fdt_blob; /* Our device tree, NULL if none */ void *new_fdt; /* Relocated FDT */ unsigned long fdt_size; /* Space reserved for relocated FDT */ - void **jt; /* jump table */ + struct jt_funcs *jt; /* jump table */ char env_buf[32]; /* buffer for getenv() before reloc. */ #ifdef CONFIG_TRACE void *trace_buff; /* The trace buffer */ diff --git a/include/exports.h b/include/exports.h index 41d5085..d613f7d 100644 --- a/include/exports.h +++ b/include/exports.h @@ -3,6 +3,8 @@ #ifndef __ASSEMBLY__ +struct spi_slave; + /* These are declarations of exported functions available in C code */ unsigned long get_version(void); int getc(void); @@ -10,19 +12,19 @@ int tstc(void); void putc(const char); void puts(const char*); int printf(const char* fmt, ...); -void install_hdlr(int, void (*interrupt_handler_t)(void *), void*); +void install_hdlr(int, interrupt_handler_t, void*); void free_hdlr(int); void *malloc(size_t); void free(void*); void __udelay(unsigned long); unsigned long get_timer(unsigned long); int vprintf(const char *, va_list); -unsigned long simple_strtoul(const char *cp,char **endp,unsigned int base); +unsigned long simple_strtoul(const char *cp, char **endp, unsigned int base); int strict_strtoul(const char *cp, unsigned int base, unsigned long *res); char *getenv (const char *name); int setenv (const char *varname, const char *varvalue); -long simple_strtol(const char *cp,char **endp,unsigned int base); -int strcmp(const char * cs,const char * ct); +long simple_strtol(const char *cp, char **endp, unsigned int base); +int strcmp(const char *cs, const char *ct); unsigned long ustrtoul(const char *cp, char **endp, unsigned int base); unsigned long long ustrtoull(const char *cp, char **endp, unsigned int base); #if defined(CONFIG_CMD_I2C) @@ -34,14 +36,13 @@ void app_startup(char * const *); #endif /* ifndef __ASSEMBLY__ */ -enum { -#define EXPORT_FUNC(x) XF_ ## x , +struct jt_funcs { +#define EXPORT_FUNC(impl, res, func, ...) res(*func)(__VA_ARGS__); #include <_exports.h> #undef EXPORT_FUNC - - XF_MAX }; + #define XF_VERSION 6 #if defined(CONFIG_X86) -- 1.8.1.4

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