December 2014 - U-Boot

[U-Boot] [PATCH v2] powerpc/t1040qds: Add support of SD boot for T1040QDS Board
by Vijay Rai 15 Jan '15

15 Jan '15

Add support of 2 stage SD boot loader using SPL framework. here, PBL initialise the internal SRAM and copy SPL(160KB). This further initialise DDR using SPD environment and copy u-boot(768 KB) from NAND to DDR. Finally SPL transer control to u-boot. Initialise/create followings required for SPL framework - Add spl.c which defines board_init_f, board_init_r - Update tlb and ddr accordingly Add T1040QDS_SDCARD_defconfig Update t1040_pbi.cfg to support errata A-007662, A-008007 and LAW for CPC1 Signed-off-by: Vijay Rai <vijay.rai(a)freescale.com> --- changes from v1: -Updated Kconfig to support SPL option for T1040QDS arch/powerpc/cpu/mpc85xx/Kconfig | 1 + board/freescale/t1040qds/MAINTAINERS | 5 ++ board/freescale/t1040qds/Makefile | 10 ++- board/freescale/t1040qds/ddr.c | 5 +- board/freescale/t1040qds/spl.c | 155 ++++++++++++++++++++++++++++++++ board/freescale/t1040qds/t1040_pbi.cfg | 16 +++- board/freescale/t1040qds/t1040qds.c | 6 +- board/freescale/t1040qds/tlb.c | 11 +++ configs/T1040QDS_SDCARD_defconfig | 5 ++ include/configs/T1040QDS.h | 79 +++++++++++++--- 10 files changed, 273 insertions(+), 20 deletions(-) create mode 100644 board/freescale/t1040qds/spl.c create mode 100644 configs/T1040QDS_SDCARD_defconfig diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 7501eb4..7177c83 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -120,6 +120,7 @@ config TARGET_T102XRDB config TARGET_T1040QDS bool "Support T1040QDS" + select SUPPORT_SPL config TARGET_T104XRDB bool "Support T104xRDB" diff --git a/board/freescale/t1040qds/MAINTAINERS b/board/freescale/t1040qds/MAINTAINERS index 83f6b3c..44d56b6 100644 --- a/board/freescale/t1040qds/MAINTAINERS +++ b/board/freescale/t1040qds/MAINTAINERS @@ -6,6 +6,11 @@ F: include/configs/T1040QDS.h F: configs/T1040QDS_defconfig F: configs/T1040QDS_D4_defconfig +T1040QDS_SDCARD BOARD +M: Priyanka Jain <Priyanka.Jain(a)freescale.com> +S: Maintained +F: configs/T1040QDS_SDCARD_defconfig + T1040QDS_SECURE_BOOT BOARD M: Aneesh Bansal <aneesh.bansal(a)freescale.com> S: Maintained diff --git a/board/freescale/t1040qds/Makefile b/board/freescale/t1040qds/Makefile index 19ed21b..27eed4c 100644 --- a/board/freescale/t1040qds/Makefile +++ b/board/freescale/t1040qds/Makefile @@ -4,10 +4,14 @@ # SPDX-License-Identifier: GPL-2.0+ # +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +else obj-y += t1040qds.o -obj-y += ddr.o +obj-y += eth.o obj-$(CONFIG_PCI) += pci.o +obj-$(CONFIG_FSL_DIU_FB) += diu.o +endif +obj-y += ddr.o obj-y += law.o obj-y += tlb.o -obj-y += eth.o -obj-y += diu.o diff --git a/board/freescale/t1040qds/ddr.c b/board/freescale/t1040qds/ddr.c index 43f952f..6147430 100644 --- a/board/freescale/t1040qds/ddr.c +++ b/board/freescale/t1040qds/ddr.c @@ -104,13 +104,16 @@ phys_size_t initdram(int board_type) { phys_size_t dram_size; +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) puts("Initializing....using SPD\n"); dram_size = fsl_ddr_sdram(); dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; - puts(" DDR: "); +#else + dram_size = fsl_ddr_sdram_size(); +#endif return dram_size; } diff --git a/board/freescale/t1040qds/spl.c b/board/freescale/t1040qds/spl.c new file mode 100644 index 0000000..b601c95 --- /dev/null +++ b/board/freescale/t1040qds/spl.c @@ -0,0 +1,155 @@ +/* Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <malloc.h> +#include <ns16550.h> +#include <nand.h> +#include <i2c.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <spi_flash.h> +#include "../common/qixis.h" +#include "t1040qds_qixis.h" +#include <asm/mpc85xx_gpio.h> + +DECLARE_GLOBAL_DATA_PTR; + +phys_size_t get_effective_memsize(void) +{ + return CONFIG_SYS_L3_SIZE; +} + +unsigned long get_board_sys_clk(void) +{ + u8 sysclk_conf = QIXIS_READ(brdcfg[1]); + + switch (sysclk_conf & 0x0F) { + case QIXIS_SYSCLK_64: + return 64000000; + case QIXIS_SYSCLK_83: + return 83333333; + case QIXIS_SYSCLK_100: + return 100000000; + case QIXIS_SYSCLK_125: + return 125000000; + case QIXIS_SYSCLK_133: + return 133333333; + case QIXIS_SYSCLK_150: + return 150000000; + case QIXIS_SYSCLK_160: + return 160000000; + case QIXIS_SYSCLK_166: + return 166666666; + } + return 66666666; +} + +unsigned long get_board_ddr_clk(void) +{ + u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); + + switch ((ddrclk_conf & 0x30) >> 4) { + case QIXIS_DDRCLK_100: + return 100000000; + case QIXIS_DDRCLK_125: + return 125000000; + case QIXIS_DDRCLK_133: + return 133333333; + } + return 66666666; +} + +#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000 +void board_init_f(ulong bootflag) +{ + u32 plat_ratio, sys_clk, uart_clk; +#ifdef CONFIG_SPL_NAND_BOOT + u32 porsr1, pinctl; +#endif + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + +#ifdef CONFIG_SPL_NAND_BOOT + /* + * There is T1040 SoC issue where NOR, FPGA are inaccessible during + * NAND boot because IFC signals > IFC_AD7 are not enabled. + * This workaround changes RCW source to make all signals enabled. + */ + porsr1 = in_be32(&gur->porsr1); + pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000); + out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl); +#endif + + /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ + memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); + + /* Update GD pointer */ + gd = (gd_t *)(CONFIG_SPL_GD_ADDR); + + /* compiler optimization barrier needed for GCC >= 3.4 */ + __asm__ __volatile__("" : : : "memory"); + + console_init_f(); + + /* initialize selected port with appropriate baud rate */ + sys_clk = get_board_sys_clk(); + plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; + uart_clk = sys_clk * plat_ratio / 2; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + uart_clk / 16 / CONFIG_BAUDRATE); + + relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + bd_t *bd; + + bd = (bd_t *)(gd + sizeof(gd_t)); + memset(bd, 0, sizeof(bd_t)); + gd->bd = bd; + bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; + bd->bi_memsize = CONFIG_SYS_L3_SIZE; + + probecpu(); + get_clocks(); + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, + CONFIG_SPL_RELOC_MALLOC_SIZE); + +#ifdef CONFIG_SPL_MMC_BOOT + mmc_initialize(bd); +#endif + + /* relocate environment function pointers etc. */ +#ifdef CONFIG_SPL_NAND_BOOT + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif +#ifdef CONFIG_SPL_MMC_BOOT + mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif +#ifdef CONFIG_SPL_SPI_BOOT + spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif + gd->env_addr = (ulong)(CONFIG_ENV_ADDR); + gd->env_valid = 1; + + i2c_init_all(); + + puts("\n\n"); + + gd->ram_size = initdram(0); + +#ifdef CONFIG_SPL_MMC_BOOT + mmc_boot(); +#elif defined(CONFIG_SPL_SPI_BOOT) + spi_boot(); +#elif defined(CONFIG_SPL_NAND_BOOT) + nand_boot(); +#endif +} diff --git a/board/freescale/t1040qds/t1040_pbi.cfg b/board/freescale/t1040qds/t1040_pbi.cfg index 10b1a6d..f7d9a74 100644 --- a/board/freescale/t1040qds/t1040_pbi.cfg +++ b/board/freescale/t1040qds/t1040_pbi.cfg @@ -1,4 +1,14 @@ #PBI commands +#Software Workaround for errata A-007662 to train PCIe2 controller in Gen2 speed +09250100 00000400 +09250108 00002000 +#Software Workaround for errata A-008007 to reset PVR register +09000010 0000000b +09000014 c0000000 +09000018 81d00017 +89020400 a1000000 +091380c0 000f0000 +89020400 00000000 #Initialize CPC1 09010000 00200400 09138000 00000000 @@ -9,9 +19,9 @@ 09010f00 08000000 09010000 80000000 #Configure LAW for CPC1 -09000cf0 00000000 -09000cf4 fffc0000 -09000cf8 81000011 +09000cd0 00000000 +09000cd4 fffc0000 +09000cd8 81000011 #Configure alternate space 09000010 00000000 09000014 ff000000 diff --git a/board/freescale/t1040qds/t1040qds.c b/board/freescale/t1040qds/t1040qds.c index 13285be..a086e47 100644 --- a/board/freescale/t1040qds/t1040qds.c +++ b/board/freescale/t1040qds/t1040qds.c @@ -279,7 +279,11 @@ void qixis_dump_switch(void) int board_need_mem_reset(void) { - return 1; +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) + return 1; +#else + return 0; +#endif } #ifdef CONFIG_DEEP_SLEEP diff --git a/board/freescale/t1040qds/tlb.c b/board/freescale/t1040qds/tlb.c index 412c591..0a7ceda 100644 --- a/board/freescale/t1040qds/tlb.c +++ b/board/freescale/t1040qds/tlb.c @@ -53,6 +53,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), +#ifndef CONFIG_SPL_BUILD /* *I*G* - PCI */ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -82,6 +83,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 8, BOOKE_PAGESZ_16M, 1), #endif +#endif #ifdef CONFIG_SYS_DCSRBAR_PHYS SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -103,6 +105,15 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 11, BOOKE_PAGESZ_4K, 1), #endif +#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 12, BOOKE_PAGESZ_1G, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, + CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 13, BOOKE_PAGESZ_1G, 1) +#endif }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/configs/T1040QDS_SDCARD_defconfig b/configs/T1040QDS_SDCARD_defconfig new file mode 100644 index 0000000..fbee8c5 --- /dev/null +++ b/configs/T1040QDS_SDCARD_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_T1040QDS=y diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 6b396bb..c0ad90e 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -32,11 +32,46 @@ #define CONFIG_DISPLAY_BOARDINFO #ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg +#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg +#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1040_rcw.cfg +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_SYS_TEXT_BASE 0x30001000 +#define CONFIG_SPL_TEXT_BASE 0xFFFD8000 +#define CONFIG_SPL_PAD_TO 0x40000 +#define CONFIG_SPL_MAX_SIZE 0x28000 +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_SKIP_RELOCATE +#define CONFIG_SPL_COMMON_INIT_DDR +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE +#define CONFIG_SYS_NO_FLASH #endif +#define RESET_VECTOR_OFFSET 0x27FFC +#define BOOT_PAGE_OFFSET 0x27000 + +#ifdef CONFIG_SDCARD +#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_MMC_MINIMAL +#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) +#define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) +#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif +#define CONFIG_SPL_MMC_BOOT +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE @@ -75,15 +110,12 @@ #define CONFIG_ENV_OVERWRITE -#ifdef CONFIG_SYS_NO_FLASH -#define CONFIG_ENV_IS_NOWHERE -#else +#ifndef CONFIG_SYS_NO_FLASH #define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_FLASH_CFI #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE #endif -#ifndef CONFIG_SYS_NO_FLASH #if defined(CONFIG_SPIFLASH) #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_SPI_FLASH @@ -99,7 +131,7 @@ #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET (512 * 1658) +#define CONFIG_ENV_OFFSET (512 * 0x800) #elif defined(CONFIG_NAND) #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_NAND @@ -152,6 +184,17 @@ unsigned long get_board_ddr_clk(void); */ #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CONFIG_SYS_L3_SIZE 256 << 10 +#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) +#endif +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) +#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) +#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) + #define CONFIG_SYS_DCSRBAR 0xf0000000 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull @@ -362,7 +405,11 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 #endif -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif #if defined(CONFIG_RAMBOOT_PBL) #define CONFIG_SYS_RAMBOOT @@ -410,7 +457,9 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) #define CONFIG_SERIAL_MULTI /* Enable both serial ports */ +#ifndef CONFIG_SPL_BUILD #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ +#endif /* Use the HUSH parser */ #define CONFIG_SYS_HUSH_PARSER @@ -634,15 +683,21 @@ unsigned long get_board_ddr_clk(void); * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC -#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE) #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 +#endif + +#if defined(CONFIG_SDCARD) +#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) +#else #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 #endif + #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) #endif /* CONFIG_NOBQFMAN */ -- 1.7.9.5

2 1

[U-Boot] [PATCH 1/2] image: bootm: Add OpenRTOS image type
by Marek Vasut 15 Jan '15

15 Jan '15

Add separate image type for the Wittenstein OpenRTOS . Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Simon Glass <sjg(a)chromium.org> Cc: Tom Rini <trini(a)ti.com> --- common/bootm_os.c | 29 +++++++++++++++++++++++++++++ common/image.c | 4 ++++ include/image.h | 1 + 3 files changed, 34 insertions(+) diff --git a/common/bootm_os.c b/common/bootm_os.c index 5be4467..72477f0 100644 --- a/common/bootm_os.c +++ b/common/bootm_os.c @@ -404,6 +404,32 @@ static int do_bootm_integrity(int flag, int argc, char * const argv[], } #endif +#ifdef CONFIG_BOOTM_OPENRTOS +static int do_bootm_openrtos(int flag, int argc, char * const argv[], + bootm_headers_t *images) +{ + void (*entry_point)(void); + + if (flag != BOOTM_STATE_OS_GO) + return 0; + + entry_point = (void (*)(void))images->ep; + + printf("## Transferring control to OpenRTOS (at address %08lx) ...\n", + (ulong)entry_point); + + bootstage_mark(BOOTSTAGE_ID_RUN_OS); + + /* + * OpenRTOS Parameters: + * None + */ + (*entry_point)(); + + return 1; +} +#endif + static boot_os_fn *boot_os[] = { [IH_OS_U_BOOT] = do_bootm_standalone, #ifdef CONFIG_BOOTM_LINUX @@ -434,6 +460,9 @@ static boot_os_fn *boot_os[] = { #ifdef CONFIG_INTEGRITY [IH_OS_INTEGRITY] = do_bootm_integrity, #endif +#ifdef CONFIG_BOOTM_OPENRTOS + [IH_OS_OPENRTOS] = do_bootm_openrtos, +#endif }; /* Allow for arch specific config before we boot */ diff --git a/common/image.c b/common/image.c index b75a5ce..64b4281 100644 --- a/common/image.c +++ b/common/image.c @@ -120,6 +120,10 @@ static const table_entry_t uimage_os[] = { { IH_OS_SOLARIS, "solaris", "Solaris", }, { IH_OS_SVR4, "svr4", "SVR4", }, #endif +#if defined(CONFIG_BOOTM_OPENRTOS) || defined(USE_HOSTCC) + { IH_OS_OPENRTOS, "openrtos", "OpenRTOS", }, +#endif + { -1, "", "", }, }; diff --git a/include/image.h b/include/image.h index af30d60..ee3afe3 100644 --- a/include/image.h +++ b/include/image.h @@ -152,6 +152,7 @@ struct lmb; #define IH_OS_INTEGRITY 21 /* INTEGRITY */ #define IH_OS_OSE 22 /* OSE */ #define IH_OS_PLAN9 23 /* Plan 9 */ +#define IH_OS_OPENRTOS 24 /* OpenRTOS */ /* * CPU Architecture Codes (supported by Linux) -- 2.1.3

4 7

[U-Boot] [PATCH] Add support for Seagate BlackArmor NAS220
by Evgeni Dobrev 15 Jan '15

15 Jan '15

Add support for Seagate BlackArmor NAS220 Signed-off-by: Evgeni Dobrev <evgeni(a)studio-punkt.com> --- arch/arm/cpu/arm926ejs/kirkwood/Kconfig | 4 + board/Seagate/nas220/Kconfig | 12 +++ board/Seagate/nas220/MAINTAINERS | 6 ++ board/Seagate/nas220/Makefile | 7 ++ board/Seagate/nas220/kwbimage.cfg | 151 +++++++++++++++++++++++++++ board/Seagate/nas220/nas220.c | 118 ++++++++++++++++++++++ configs/nas220_defconfig | 3 + include/configs/nas220.h | 168 +++++++++++++++++++++++++++++++ 8 files changed, 469 insertions(+) create mode 100644 board/Seagate/nas220/Kconfig create mode 100644 board/Seagate/nas220/MAINTAINERS create mode 100644 board/Seagate/nas220/Makefile create mode 100644 board/Seagate/nas220/kwbimage.cfg create mode 100644 board/Seagate/nas220/nas220.c create mode 100644 configs/nas220_defconfig create mode 100644 include/configs/nas220.h diff --git a/arch/arm/cpu/arm926ejs/kirkwood/Kconfig b/arch/arm/cpu/arm926ejs/kirkwood/Kconfig index 6c037a1..45c6687 100644 --- a/arch/arm/cpu/arm926ejs/kirkwood/Kconfig +++ b/arch/arm/cpu/arm926ejs/kirkwood/Kconfig @@ -57,6 +57,9 @@ config TARGET_DOCKSTAR config TARGET_GOFLEXHOME bool "GoFlex Home Board" +config TARGET_NAS220 + bool "BlackArmor NAS220" + endchoice config SYS_SOC @@ -80,5 +83,6 @@ source "board/LaCie/wireless_space/Kconfig" source "board/raidsonic/ib62x0/Kconfig" source "board/Seagate/dockstar/Kconfig" source "board/Seagate/goflexhome/Kconfig" +source "board/Seagate/nas220/Kconfig" endif diff --git a/board/Seagate/nas220/Kconfig b/board/Seagate/nas220/Kconfig new file mode 100644 index 0000000..0fa529c --- /dev/null +++ b/board/Seagate/nas220/Kconfig @@ -0,0 +1,12 @@ +if TARGET_NAS220 + +config SYS_BOARD + default "nas220" + +config SYS_VENDOR + default "Seagate" + +config SYS_CONFIG_NAME + default "nas220" + +endif diff --git a/board/Seagate/nas220/MAINTAINERS b/board/Seagate/nas220/MAINTAINERS new file mode 100644 index 0000000..f2df7ea --- /dev/null +++ b/board/Seagate/nas220/MAINTAINERS @@ -0,0 +1,6 @@ +NAS220 BOARD +M: Evgeni Dobrev <evgeni(a)studio-punkt.com> +S: Maintained +F: board/Seagate/nas220/ +F: include/configs/nas220.h +F: configs/nas220_defconfig diff --git a/board/Seagate/nas220/Makefile b/board/Seagate/nas220/Makefile new file mode 100644 index 0000000..9de73e6 --- /dev/null +++ b/board/Seagate/nas220/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2014 Evgeni Dobrev <evgeni(a)studio-punkt.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := nas220.o diff --git a/board/Seagate/nas220/kwbimage.cfg b/board/Seagate/nas220/kwbimage.cfg new file mode 100644 index 0000000..dbbfb9c --- /dev/null +++ b/board/Seagate/nas220/kwbimage.cfg @@ -0,0 +1,151 @@ +# +# Copyright (C) 2014 Evgeni Dobrev <evgeni(a)studio-punkt.com> +# +# Based on sheevaplug/kwbimage.cfg originally written by +# Prafulla Wadaskar <prafulla(a)marvell.com> +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# +# Refer doc/README.kwbimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM nand +NAND_ECC_MODE default +NAND_PAGE_SIZE 0x0200 + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0 interface pad voltage to 1.8V +DATA 0xFFD100e0 0x1b1b1b9b + +#Dram initalization for SINGLE x16 CL=5 @ 400MHz +DATA 0xFFD01400 0x43000618 # DDR Configuration register +# bit13-0: 0xa00 (2560 DDR2 clks refresh rate) +# bit23-14: zero +# bit24: 1= enable exit self refresh mode on DDR access +# bit25: 1 required +# bit29-26: zero +# bit31-30: 01 + +DATA 0xFFD01404 0x35143000 # DDR Controller Control Low +# bit 4: 0=addr/cmd in smame cycle +# bit 5: 0=clk is driven during self refresh, we don't care for APX +# bit 6: 0=use recommended falling edge of clk for addr/cmd +# bit14: 0=input buffer always powered up +# bit18: 1=cpu lock transaction enabled +# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 +# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 3 required +# bit31: 0=no additional STARTBURST delay + +DATA 0xFFD01408 0x11012227 # DDR Timing (Low) (active cycles value +1) +# bit7-4: TRCD +# bit11- 8: TRP +# bit15-12: TWR +# bit19-16: TWTR +# bit20: TRAS msb +# bit23-21: 0x0 +# bit27-24: TRRD +# bit31-28: TRTP + +DATA 0xFFD0140C 0x00000819 # DDR Timing (High) +# bit6-0: TRFC +# bit8-7: TR2R +# bit10-9: TR2W +# bit12-11: TW2W +# bit31-13: zero required + + +DATA 0xFFD01410 0x0000000d # DDR Address Control +# bit1-0: 00, Cs0width=x8 +# bit3-2: 11, Cs0size=1Gb +# bit5-4: 00, Cs1width=nonexistent +# bit7-6: 00, Cs1size =nonexistent +# bit9-8: 00, Cs2width=nonexistent +# bit11-10: 00, Cs2size =nonexistent +# bit13-12: 00, Cs3width=nonexistent +# bit15-14: 00, Cs3size =nonexistent +# bit16: 0, Cs0AddrSel +# bit17: 0, Cs1AddrSel +# bit18: 0, Cs2AddrSel +# bit19: 0, Cs3AddrSel +# bit31-20: 0 required + +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control +# bit0: 0, OpenPage enabled +# bit31-1: 0 required + +DATA 0xFFD01418 0x00000000 # DDR Operation +# bit3-0: 0x0, DDR cmd +# bit31-4: 0 required + +DATA 0xFFD0141C 0x00000632 # DDR Mode +# bit2-0: 2, BurstLen=2 required +# bit3: 0, BurstType=0 required +# bit6-4: 4, CL=5 +# bit7: 0, TestMode=0 normal +# bit8: 0, DLL reset=0 normal +# bit11-9: 6, auto-precharge write recovery ???????????? +# bit12: 0, PD must be zero +# bit31-13: 0 required + + +DATA 0xFFD01420 0x00000040 # DDR Extended Mode +# bit0: 0, DDR DLL enabled +# bit1: 0, DDR drive strenght normal +# bit2: 0, DDR ODT control lsd (disabled) +# bit5-3: 000, required +# bit6: 1, DDR ODT control msb, (disabled) +# bit9-7: 000, required +# bit10: 0, differential DQS enabled +# bit11: 0, required +# bit12: 0, DDR output buffer enabled +# bit31-13: 0 required + +DATA 0xFFD01424 0x0000F07F # DDR Controller Control High +# bit2-0: 111, required +# bit3 : 1 , MBUS Burst Chop disabled +# bit6-4: 111, required +# bit7 : 0 +# bit8 : 0 +# bit9 : 0 , no half clock cycle addition to dataout +# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals +# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh +# bit15-12: 1111 required +# bit31-16: 0 required + +DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size +# bit0: 1, Window enabled +# bit1: 0, Write Protect disabled +# bit3-2: 00, CS0 hit selected +# bit23-4: ones, required +# bit31-24: 0x07, Size (i.e. 128MB) + +DATA 0xFFD01508 0x00000000 # CS[1]n Base address to 0x0 + +DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled + +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled + +DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low) +DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) +# bit1-0: 00, ODT0 controlled by ODT Control (low) register above +# bit3-2: 01, ODT1 active NEVER! +# bit31-4: zero, required + +DATA 0xFFD0149C 0x0000E803 # CPU ODT Control + +DATA 0xFFD01480 0x00000001 # DDR Initialization Control +#bit0=1, enable DDR init upon this register write + +DATA 0xffd01620 0x00465000 + +# End of Header extension +DATA 0x0 0x0 + diff --git a/board/Seagate/nas220/nas220.c b/board/Seagate/nas220/nas220.c new file mode 100644 index 0000000..d9a0627 --- /dev/null +++ b/board/Seagate/nas220/nas220.c @@ -0,0 +1,118 @@ +/* + * Copyright (C) 2014 Evgeni Dobrev <evgeni(a)studio-punkt.com> + * + * Based on sheevaplug.c originally written by + * Prafulla Wadaskar <prafulla(a)marvell.com> + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <miiphy.h> +#include <asm/arch/soc.h> +#include <asm/arch/mpp.h> +#include <asm/arch/cpu.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + /* + * default gpio configuration + */ + mvebu_config_gpio(NAS220_GE_OE_VAL_LOW, NAS220_GE_OE_VAL_HIGH, + NAS220_GE_OE_LOW, NAS220_GE_OE_HIGH); + + /* Multi-Purpose Pins Functionality configuration */ + static const u32 kwmpp_config[] = { + MPP0_NF_IO2, + MPP1_NF_IO3, + MPP2_NF_IO4, + MPP3_NF_IO5, + MPP4_NF_IO6, + MPP5_NF_IO7, + MPP6_SYSRST_OUTn, + MPP7_SPI_SCn, + MPP8_TW_SDA, + MPP9_TW_SCK, + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP12_GPO, + MPP13_GPIO, + MPP14_GPIO, + MPP15_SATA0_ACTn, + MPP16_SATA1_ACTn, + MPP17_SATA0_PRESENTn, + MPP18_NF_IO0, + MPP19_NF_IO1, + MPP20_GPIO, + MPP21_GPIO, + MPP22_GPIO, + MPP23_GPIO, + MPP24_GPIO, + MPP25_GPIO, + MPP26_GPIO, + MPP27_GPIO, + MPP28_GPIO, + MPP29_GPIO, + MPP30_GPIO, + MPP31_GPIO, + MPP32_GPIO, + MPP33_GPIO, + MPP34_GPIO, + MPP35_GPIO, + 0 + }; + kirkwood_mpp_conf(kwmpp_config, NULL); + return 0; +} + +int board_init(void) +{ + /* + * arch number of board + */ + gd->bd->bi_arch_number = MACH_TYPE_NAS220; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; + + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +/* Configure and enable MV88E1116 PHY */ +void reset_phy(void) +{ + u16 reg; + u16 devadr; + char *name = "egiga0"; + + if (miiphy_set_current_dev(name)) + return; + + /* command to read PHY dev address */ + if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) { + printf("Err..%s could not read PHY dev address\n", __func__); + return; + } + + /* + * Enable RGMII delay on Tx and Rx for CPU port + * Ref: sec 4.7.2 of chip datasheet + */ + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); + miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg); + reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); + miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); + + /* reset the phy */ + miiphy_reset(name, devadr); + + printf("88E1116 Initialized on %s\n", name); +} +#endif /* CONFIG_RESET_PHY_R */ diff --git a/configs/nas220_defconfig b/configs/nas220_defconfig new file mode 100644 index 0000000..5a79c51 --- /dev/null +++ b/configs/nas220_defconfig @@ -0,0 +1,3 @@ +CONFIG_ARM=y +CONFIG_KIRKWOOD=y +CONFIG_TARGET_NAS220=y diff --git a/include/configs/nas220.h b/include/configs/nas220.h new file mode 100644 index 0000000..cfb85bf --- /dev/null +++ b/include/configs/nas220.h @@ -0,0 +1,168 @@ +/* + * Copyright (C) 2014 Evgeni Dobrev <evgeni(a)studio-punkt.com> + * + * based on work from: + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CONFIG_NAS220_H +#define _CONFIG_NAS220_H + +/* + * Machine type definition and ID + */ +#define MACH_TYPE_NAS220 MACH_TYPE_RD88F6192_NAS +#define CONFIG_MACH_TYPE MACH_TYPE_NAS220 +#define CONFIG_IDENT_STRING "\nNAS 220" + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_FEROCEON_88FR131 /* #define CPU Core subversion */ +#define CONFIG_KW88F6192 /* SOC Name */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + +/* power-on led, regulator, sata0, sata1 */ +#define NAS220_GE_OE_VAL_LOW ((1 << 12)|(1 << 14)|(1 << 24)|(1 << 28)) +#define NAS220_GE_OE_VAL_HIGH (0) +#define NAS220_GE_OE_LOW (~((1 << 12)|(1 << 14)|(1 << 24)|(1 << 28))) +#define NAS220_GE_OE_HIGH (~(0)) + +/* PHY related */ +#define MV88E1116_LED_FCTRL_REG 10 +#define MV88E1116_CPRSP_CR3_REG 21 +#define MV88E1116_MAC_CTRL_REG 21 +#define MV88E1116_PGADR_REG 22 +#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) +#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) + +/* + * Commands configuration + */ +#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ +#include <config_cmd_default.h> +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NAND +#define CONFIG_CMD_SAVEENV +#define CONFIG_CMD_PING +#define CONFIG_CMD_USB +#define CONFIG_CMD_DATE +#define CONFIG_CMD_IDE +#define CONFIG_SYS_LONGHELP +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +/* Remove or override few declarations from mv-common.h */ +#undef CONFIG_SYS_PROMPT /* previously defined in mv-common.h */ +#define CONFIG_SYS_PROMPT "nas220> " + +/* + * Environment variables configurations + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SECT_SIZE 0x10000 +#else +#define CONFIG_ENV_IS_NOWHERE +#endif + +#define CONFIG_ENV_SIZE 0x10000 +#define CONFIG_ENV_OFFSET 0xa0000 + +/* + * Default environment variables + */ +#define CONFIG_BOOTCOMMAND "" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootargs=console=ttyS0,115200\0" \ + "mtdparts=mtdparts=orion_nand:0xa0000@0x0(uboot),"\ + "0x010000@0xa0000(env),"\ + "0x500000@0xc0000(uimage),"\ + "0x1a40000@0x5c0000(rootfs)\0" \ + "mtdids=nand0=orion_nand\0"\ + "bootdelay=-1\0"\ + "autostart=no\0"\ + "autoload=no\0" + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ +#define CONFIG_PHY_BASE_ADR 8 +#endif /* CONFIG_CMD_NET */ + +/* + * USB/EHCI + */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI /* Enable EHCI USB support */ +#define CONFIG_USB_EHCI_KIRKWOOD /* on Kirkwood platform */ +#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_STORAGE +#define CONFIG_DOS_PARTITION +#define CONFIG_SUPPORT_VFAT +#endif /* CONFIG_CMD_USB */ + +/* + * File system + */ +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_JFFS2 +#define CONFIG_JFFS2_NAND +#define CONFIG_JFFS2_LZO +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_RBTREE +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_LZO + +/* + * SATA + */ +#ifdef CONFIG_MVSATA_IDE +#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET +#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET +#endif + + +/* + * Device Tree + */ +#define CONFIG_OF_LIBFDT + +/* + * EFI partition + */ +#define CONFIG_EFI_PARTITION + +/* + * Date Time + */ +#ifdef CONFIG_CMD_DATE +#define CONFIG_RTC_MV +#endif /* CONFIG_CMD_DATE */ + +#define CONFIG_KIRKWOOD_GPIO + +#endif /* _CONFIG_NAS220_H */ + -- 1.7.10.4

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[U-Boot] [PATCH 0/2] arm: vf610: Change Vybrid Tower boot memory.
by Bill Pringlemeir 15 Jan '15

15 Jan '15

Without the second patch, U-Boot will not boot on the Vybrid tower systems for me. A better mechanism would be to use the SPL to load direct to DDR3. However, the gfxRAM is large enough to fit the current (~400KB) image for initial load. U-Boot is relocated to DDR3 when initialized, so the life in gfxRAM is small. I also discovered some redundant defines in the same file. include/configs/vf610twr.h | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-)

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[U-Boot] [PATCH v2 0/12] bootm: Tidy up decompression and add tests
by Simon Glass 15 Jan '15

15 Jan '15

(Note: this builds on a single patch left over from a recent series, which is why it is v2. That patch refactored the code but did not add tests.) bootm's decompression functions currently have tests in the 'test_compression' unit test command, but this calls the decompression routines directly and is more aimed at ensuring that they never overwrite their output buffer. But bootm is critical code and it is important that test coverage be adequate for the task it performs. Existing tests in test/image provide some coverage, but not for decompression. This series adds a new unit test specifically for bootm's decompression. It tests that bootm deals correctly with a normal decompress, a case where there is insufficient output buffer space, and a case where part of the data is corrupted. Previously the uncompressed case had no error checking, so this is added. This is a change in behaviour so I hope it will not cause problems. The current error message on failure is confusing, since it is unclear whether the image is too large or the data is corrupt. This is improved and patches added to make sure we can distinguish these two cases for each decompression method in most situations. The existing 'Must RESET board to recover' message is retained, but this is likely to be unnecessary, since all decompressions routines are, I believe, careful not to overwrite their output buffer even in the case of corrupted data. It may be desirable to remove it later. The output of the new sandbox 'ut_image_decomp' command is below: Testing: gzip compressed Uncompressing Kernel Image ... OK Uncompressing Kernel Image ... Error: inflate() returned -5 Image too large: increase CONFIG_SYS_BOOTM_LEN Must RESET board to recover Uncompressing Kernel Image ... Error: inflate() returned -5 Image too large: increase CONFIG_SYS_BOOTM_LEN Must RESET board to recover Testing: bzip2 compressed Uncompressing Kernel Image ... OK Uncompressing Kernel Image ... Image too large: increase CONFIG_SYS_BOOTM_LEN Must RESET board to recover Uncompressing Kernel Image ... bzip2 compressed: uncompress error -4 Must RESET board to recover Testing: lzma compressed Uncompressing Kernel Image ... OK Uncompressing Kernel Image ... Image too large: increase CONFIG_SYS_BOOTM_LEN Must RESET board to recover Uncompressing Kernel Image ... lzma compressed: uncompress error 1 Must RESET board to recover Testing: lzo compressed Uncompressing Kernel Image ... OK Uncompressing Kernel Image ... Image too large: increase CONFIG_SYS_BOOTM_LEN Must RESET board to recover Uncompressing Kernel Image ... lzo compressed: uncompress error -6 Must RESET board to recover Testing: uncompressed Loading Kernel Image ... OK Loading Kernel Image ... Image too large: increase CONFIG_SYS_BOOTM_LEN Must RESET board to recover ut_image_decomp ok Changes in v2: - Add tests to cover the code changes - Correct the overflow check for bzip2 Simon Glass (12): lzma: fix buffer bound check error further bootm: Move compression progress/error messages into a function sandbox: Correct ordering of 'sb save' commands test: Add DEBUG output option to test-fit.py bootm: Export bootm_decomp_image() test: Rename test_compression to ut_compression test: Add unit tests for bootm image decompression bootm: Use print_decomp_msg() in all cases bootm: Factor out common parts of image decompression code bzlib: Update destLen even on error gunzip: Update lenp even on error lzo: Update dst_len even on error common/bootm.c | 150 ++++++++++++++++++++++++++------------------- common/cmd_sandbox.c | 2 +- include/bootm.h | 17 +++++ lib/bzlib.c | 2 +- lib/gunzip.c | 7 ++- lib/lzma/LzmaTools.c | 4 +- lib/lzo/lzo1x_decompress.c | 4 +- test/compression.c | 93 ++++++++++++++++++++++++++-- test/dm/sf.c | 2 +- test/image/test-fit.py | 16 ++++- 10 files changed, 218 insertions(+), 79 deletions(-) -- 2.2.0.rc0.207.ga3a616c

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[U-Boot] [PATCH] .travis.yml: build u-boot on travis-ci
by Roger Meier 15 Jan '15

15 Jan '15

Signed-off-by: Roger Meier <r.meier(a)siemens.com> --- .travis.yml | 86 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 .travis.yml diff --git a/.travis.yml b/.travis.yml new file mode 100644 index 0000000..027aff2 --- /dev/null +++ b/.travis.yml @@ -0,0 +1,86 @@ +# Copyright Roger Meier <r.meier(a)siemens.com> +# SPDX-License-Identifier: GPL-2.0+ + +# build U-Boot on Travis CI - https://travis-ci.org/ + +language: c + +cache: + - apt + +install: + - sudo apt-get install -qq cppcheck sloccount sparse bc device-tree-compiler gcc-arm-linux-gnueabi + +env: + global: + - BUILD_DIR=build + - DOWNLOAD_URL="" + - INSTALL_CMD="" + - CROSS_COMPILE="" + - HOSTCC = "cc" + - HOSTCXX = "c++" + +before_script: + - if [[ "$DOWNLOAD_URL" != "" ]]; then wget $DOWNLOAD_URL ; fi + - if [[ "$INSTALL_CMD" != "" ]]; then $INSTALL_CMD ; fi + +script: + - export BUILD_NCPUS="`grep processor /proc/cpuinfo | wc -l`" + - echo "BUILD on" $BUILD_NCPUS "cpu's" + - echo $TEST_CMD && $TEST_CMD + +matrix: + include: +# arm and powerpc have too many boards for th 50min time limit +# so we need to build by vendor + - env: + - TEST_CMD="./MAKEALL -a arm -v atmel" + CROSS_COMPILE="arm-linux-gnueabi-" + - env: + - TEST_CMD="./MAKEALL -a arm -v denx" + CROSS_COMPILE="arm-linux-gnueabi-" + - env: + - TEST_CMD="./MAKEALL -a arm -v freescale" + CROSS_COMPILE="arm-linux-gnueabi-" + - env: + - TEST_CMD="./MAKEALL -a arm -v siemens" + CROSS_COMPILE="arm-linux-gnueabi-" + - env: + - TEST_CMD="./MAKEALL -a arm -v ti" + CROSS_COMPILE="arm-linux-gnueabi-" + - env: + - TEST_CMD="./MAKEALL -a x86" + - HOSTCC = "gcc" + - HOSTCXX = "g++" + - env: + - TEST_CMD="./MAKEALL -a x86" + - HOSTCC = "clang" + - HOSTCXX = "clang++" + - env: + - TEST_CMD="./MAKEALL -a powerpc -v freescale" + CROSS_COMPILE="/opt/eldk-5.4/powerpc/sysroots/i686-eldk-linux/usr/bin/powerpc-linux/powerpc-" + DOWNLOAD_URL="ftp://ftp.denx.de/pub/eldk/5.4/targets/powerpc/eldk-eglibc-i686-powerpc-toolchain-gmae-5.4.sh" + INSTALL_CMD="sh eldk-eglibc-i686-powerpc-toolchain-gmae-5.4.sh -y" + - env: + - TEST_CMD="./MAKEALL -a mips" + CROSS_COMPILE="/opt/eldk-5.4/mips/sysroots/i686-eldk-linux/usr/bin/mips32-linux/mips-linux-" + DOWNLOAD_URL="ftp://ftp.denx.de/pub/eldk/5.4/targets/mips/eldk-eglibc-i686-mips-toolchain-gmae-5.4.sh" + INSTALL_CMD="sh eldk-eglibc-i686-mips-toolchain-gmae-5.4.sh -y" + - env: + - TEST_CMD="./MAKEALL -a arm -v denx -v siemens" + CROSS_COMPILE="/opt/eldk-5.4/armv7a-hf/sysroots/i686-eldk-linux/usr/bin/armv7ahf-vfp-neon-linux-gnueabi/arm-linux-gnueabi-" + DOWNLOAD_URL="ftp://ftp.denx.de/pub/eldk/5.4/targets/armv7a-hf/eldk-eglibc-i686-arm-toolchain-gmae-5.4.sh" + INSTALL_CMD="sh eldk-eglibc-i686-arm-toolchain-gmae-5.4.sh -y" + - env: + - TEST_CMD="cppcheck --force --quiet ." + - env: + - TEST_CMD="grep -r TODO *" + - env: + - TEST_CMD="grep -r FIXME *" + - env: + - TEST_CMD="grep -r HACK *" + - env: + - TEST_CMD="sloccount ." + +notifications: + email: false -- 1.7.10.4

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[U-Boot] [PATCH v2] memsize: Fix for bug in memory sizing code
by Gerd Hoffmann 15 Jan '15

15 Jan '15

The original memory sizing code in get_ram_size clobbers the word at the base address, but forgets to restore it. Unlike the (reverted) commit b8496cced856ff411f1eb2e4eff20f5abe7080b0 we'll go save and restore the base address value at the start and then end of the function. It needs to stay cleared until the detection is done, otherwise we'll fail to detect the same piece of memory being mapped multiple times into the address space. Cc: Wolfgang Denk <wd(a)denx.de> Cc: Iwo Mergler <Iwo.Mergler(a)netcommwireless.com> Signed-off-by: Gerd Hoffmann <kraxel(a)redhat.com> --- common/memsize.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/common/memsize.c b/common/memsize.c index 589400d..72d0156 100644 --- a/common/memsize.c +++ b/common/memsize.c @@ -27,12 +27,15 @@ DECLARE_GLOBAL_DATA_PTR; long get_ram_size(long *base, long maxsize) { volatile long *addr; - long save[32]; + long save[32], save_base; long cnt; long val; long size; int i = 0; + save_base = base[0]; + sync (); + for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) { addr = base + cnt; /* pointer arith! */ sync (); @@ -43,8 +46,6 @@ long get_ram_size(long *base, long maxsize) addr = base; sync (); - save[i] = *addr; - sync (); *addr = 0; sync (); @@ -52,12 +53,12 @@ long get_ram_size(long *base, long maxsize) /* Restore the original data before leaving the function. */ sync (); - *addr = save[i]; for (cnt = 1; cnt < maxsize / sizeof(long); cnt <<= 1) { addr = base + cnt; sync (); *addr = save[--i]; } + base[0] = save_base; return (0); } @@ -73,10 +74,12 @@ long get_ram_size(long *base, long maxsize) addr = base + cnt; *addr = save[--i]; } + base[0] = save_base; return (size); } } + base[0] = save_base; return (maxsize); } -- 1.8.3.1

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[U-Boot] [PATCH] rtc: ds1307: add support for MCP7941x RTCs
by Soeren Moch 15 Jan '15

15 Jan '15

MCP7941x RTCs are very similar to ds1307. So add support in the ds1307 driver, as it is done in the linux kernel Signed-off-by: Soeren Moch <smoch(a)web.de> --- Cc: Tom Rini <trini(a)ti.com> --- drivers/rtc/ds1307.c | 30 ++++++++++++++++++++++++------ 1 file changed, 24 insertions(+), 6 deletions(-) diff --git a/drivers/rtc/ds1307.c b/drivers/rtc/ds1307.c index 03ab1a8..20da43a 100644 --- a/drivers/rtc/ds1307.c +++ b/drivers/rtc/ds1307.c @@ -10,6 +10,10 @@ /* * Date & Time support (no alarms) for Dallas Semiconductor (now Maxim) * DS1307 and DS1338/9 Real Time Clock (RTC). + * i2c address 0x68 + * + * Date & Time support (no alarms) for MCP7941x Real Time Clock (RTC). + * i2c address 0x6f * * based on ds1337.c */ @@ -52,12 +56,24 @@ #define RTC_CTL_REG_ADDR 0x07 #define RTC_SEC_BIT_CH 0x80 /* Clock Halt (in Register 0) */ +#define RTC_SEC_CH 0x80 /* Clock Halt (in Register 0) */ + +#define RTC_DAY_VBATEN 0x00 /* Battery EN (in Register 3) */ #define RTC_CTL_BIT_RS0 0x01 /* Rate select 0 */ #define RTC_CTL_BIT_RS1 0x02 /* Rate select 1 */ #define RTC_CTL_BIT_SQWE 0x10 /* Square Wave Enable */ #define RTC_CTL_BIT_OUT 0x80 /* Output Control */ +#if CONFIG_SYS_I2C_RTC_ADDR == 0x6f +#undef RTC_SEC_CH +#undef RTC_DAY_VBATEN +#undef RTC_CTL_BIT_SQWE +#define RTC_SEC_CH 0x00 /* Clock Halt (in Register 0) */ +#define RTC_DAY_VBATEN 0x08 /* Battery EN (in Register 3) */ +#define RTC_CTL_BIT_SQWE 0x40 /* Square Wave Enable */ +#endif + static uchar rtc_read (uchar reg); static void rtc_write (uchar reg, uchar val); @@ -81,11 +97,11 @@ int rtc_get (struct rtc_time *tmp) "hr: %02x min: %02x sec: %02x\n", year, mon, mday, wday, hour, min, sec); - if (sec & RTC_SEC_BIT_CH) { + if ((sec & RTC_SEC_BIT_CH) == RTC_SEC_CH) { printf ("### Warning: RTC oscillator has stopped\n"); - /* clear the CH flag */ + /* start clock */ rtc_write (RTC_SEC_REG_ADDR, - rtc_read (RTC_SEC_REG_ADDR) & ~RTC_SEC_BIT_CH); + rtc_read (RTC_SEC_REG_ADDR) ^ RTC_SEC_BIT_CH); rel = -1; } @@ -112,6 +128,9 @@ int rtc_get (struct rtc_time *tmp) */ int rtc_set (struct rtc_time *tmp) { + uchar clk_en = RTC_SEC_BIT_CH & ~RTC_SEC_CH; + uchar bat_en = RTC_DAY_VBATEN; + DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, tmp->tm_hour, tmp->tm_min, tmp->tm_sec); @@ -121,11 +140,11 @@ int rtc_set (struct rtc_time *tmp) rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100)); rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon)); - rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday + 1)); + rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday + 1) | bat_en); rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday)); rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour)); rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min)); - rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec)); + rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec) | clk_en); return 0; } @@ -142,7 +161,6 @@ void rtc_reset (void) { struct rtc_time tmp; - rtc_write (RTC_SEC_REG_ADDR, 0x00); /* clearing Clock Halt */ rtc_write (RTC_CTL_REG_ADDR, RTC_CTL_BIT_SQWE | RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS0); tmp.tm_year = 1970; -- 1.9.1

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[U-Boot] usbtty using i.MX6
by Otavio Salvador 15 Jan '15

15 Jan '15

Hello, I'd like to know if someone has succeed in using usbtty with i.MX6. I am interested in using it for one board but been not succed, it seems: /home/otavio/hacking/u-boot/drivers/serial/usbtty.c:553: undefined reference to `udc_init' drivers/serial/built-in.o: In function `usbtty_init_instances': /home/otavio/hacking/u-boot/drivers/serial/usbtty.c:686: undefined reference to `udc_setup_ep' /home/otavio/hacking/u-boot/drivers/serial/usbtty.c:708: undefined reference to `urb_link_init' /home/otavio/hacking/u-boot/drivers/serial/usbtty.c:709: undefined reference to `urb_link_init' /home/otavio/hacking/u-boot/drivers/serial/usbtty.c:710: undefined reference to `urb_link_init ... Does someone got it working? -- Otavio Salvador O.S. Systems http://www.ossystems.com.br http://code.ossystems.com.br Mobile: +55 (53) 9981-7854 Mobile: +1 (347) 903-9750

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[U-Boot] [PATCH] arm: ls102xa: Enable snooping for CCI-400 S0 slave interface
by Alison Wang 15 Jan '15

15 Jan '15

CAAM is connected to CCI-400 S0 slave interface. Disable snooping for S0 will cause CAAM self test failure. This patch is to enable snooping for S0 slave interface. Signed-off-by: Alison Wang <alison.wang(a)freescale.com> --- board/freescale/ls1021aqds/ls1021aqds.c | 3 +-- board/freescale/ls1021atwr/ls1021atwr.c | 3 +-- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index 4dda5e3..e5dea5d 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -202,10 +202,9 @@ int board_early_init_f(void) CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); /* - * Set CCI-400 Slave interface S0, S1, S2 Shareable Override Register + * Set CCI-400 Slave interface S1, S2 Shareable Override Register * All transactions are treated as non-shareable */ - out_le32(&cci->slave[0].sha_ord, CCI400_SHAORD_NON_SHAREABLE); out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index 0629d1c..2c8afc0 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -419,10 +419,9 @@ int board_init(void) struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; /* - * Set CCI-400 Slave interface S0, S1, S2 Shareable Override Register + * Set CCI-400 Slave interface S1, S2 Shareable Override Register * All transactions are treated as non-shareable */ - out_le32(&cci->slave[0].sha_ord, CCI400_SHAORD_NON_SHAREABLE); out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); out_le32(0x1185000, 0x3); -- 2.1.0.27.g96db324

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