November 2014 - U-Boot

[U-Boot] [PATCH v1 0/6] Update gdsys board support
by dirk.eibach＠gdsys.cc 07 Nov '14

07 Nov '14

From: Dirk Eibach <dirk.eibach(a)gdsys.cc> Dirk Eibach (6): board: dlvision: Reduce memory footprint mtd: Handle 29LV800BT common: Fix cmd_fpgad addressing board: dlvision-10g: Compile fix board: iocon: Fix fpga index in print_fpga_info() mpc83xx: Add gdsys hrcon board arch/powerpc/cpu/mpc83xx/Kconfig | 4 + board/gdsys/405ep/iocon.c | 198 +----------- board/gdsys/common/Makefile | 3 +- board/gdsys/common/ihs_mdio.c | 88 +++++ board/gdsys/common/ihs_mdio.h | 18 ++ board/gdsys/common/osd.c | 3 +- board/gdsys/common/phy.c | 280 ++++++++++++++++ board/gdsys/common/phy.h | 14 + board/gdsys/mpc8308/Kconfig | 12 + board/gdsys/mpc8308/MAINTAINERS | 6 + board/gdsys/mpc8308/Makefile | 9 + board/gdsys/mpc8308/hrcon.c | 677 +++++++++++++++++++++++++++++++++++++++ board/gdsys/mpc8308/mpc8308.c | 109 +++++++ board/gdsys/mpc8308/mpc8308.h | 10 + board/gdsys/mpc8308/sdram.c | 82 +++++ common/Makefile | 1 + common/cmd_fpgad.c | 32 +- common/cmd_ioloop.c | 295 +++++++++++++++++ configs/hrcon_defconfig | 3 + drivers/mtd/jedec_flash.c | 51 +++ include/configs/dlvision.h | 9 +- include/configs/hrcon.h | 614 +++++++++++++++++++++++++++++++++++ include/flash.h | 1 + include/gdsys_fpga.h | 64 +++- 24 files changed, 2373 insertions(+), 210 deletions(-) create mode 100644 board/gdsys/common/ihs_mdio.c create mode 100644 board/gdsys/common/ihs_mdio.h create mode 100644 board/gdsys/common/phy.c create mode 100644 board/gdsys/common/phy.h create mode 100644 board/gdsys/mpc8308/Kconfig create mode 100644 board/gdsys/mpc8308/MAINTAINERS create mode 100644 board/gdsys/mpc8308/Makefile create mode 100644 board/gdsys/mpc8308/hrcon.c create mode 100644 board/gdsys/mpc8308/mpc8308.c create mode 100644 board/gdsys/mpc8308/mpc8308.h create mode 100644 board/gdsys/mpc8308/sdram.c create mode 100644 common/cmd_ioloop.c create mode 100644 configs/hrcon_defconfig create mode 100644 include/configs/hrcon.h -- 1.8.3

5 17

[U-Boot] [PATCH 1/5] usb: s3c-otg: Remove useless include
by Marek Vasut 07 Nov '14

07 Nov '14

Remove the useless inclusion of arch/arm/gpio.h , which is completely bogus in this driver. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Chin Liang See <clsee(a)altera.com> Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> Cc: Vince Bridgers <vbridger(a)altera.com> Cc: Pavel Machek <pavel(a)denx.de> Cc: Stefan Roese <sr(a)denx.de> Cc: Lukasz Majewski <l.majewski(a)samsung.com> --- drivers/usb/gadget/s3c_udc_otg.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/usb/gadget/s3c_udc_otg.c b/drivers/usb/gadget/s3c_udc_otg.c index b9816df..7508b1a 100644 --- a/drivers/usb/gadget/s3c_udc_otg.c +++ b/drivers/usb/gadget/s3c_udc_otg.c @@ -31,7 +31,6 @@ #include <asm/io.h> #include <asm/mach-types.h> -#include <asm/arch/gpio.h> #include "regs-otg.h" #include <usb/lin_gadget_compat.h> -- 2.0.0

4 36

[U-Boot] [PATCH v2] arm: socfpga: Add DT support for SoCFPGA and add socfpga_socrates target
by Stefan Roese 07 Nov '14

07 Nov '14

This patch includes the latest DT sources for socfpga from the current Linux kernel. And enables CONFIG_OF_CONTROL for the new build target "socfpga_socrates" (the EBV SoCrates board) to make use of this new DT support. Until this patch, the only SoCFPGA U-Boot target in mainline is "socfpga_cyclone5". This build target is not (yet) changed to support DT. So nothing changes for this target. Even though the long-term goal should be to move all SoCFPGA targets over to DT. One of the reasons to enable DT support in SoCFPGA is, that I need to support multiple different SPI controllers for this platform. This is the QSPI Cadence controller and the Designware SPI master controller. Both are implemented in the SoCFPGA. And enabling both controllers is only possible by using the new driver model (DM). The DM SPI code only supports DT based probing. So it was easier to move SoCFPGA to DT than to add the (deprecated) platform-data based probing to the DM SPI suport. Note that the image with the dtb embedded is u-boot-dtb.img. This needs to be used now for those DT enabled boards instead of u-boot.img. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Marek Vasut <marex(a)denx.de> Cc: Chin Liang See <clsee(a)altera.com> Cc: Dinh Nguyen <dinguyen(a)altera.com> Cc: Vince Bridgers <vbridger(a)altera.com> Cc: Albert Aribaud <albert.u.boot(a)aribaud.net> Cc: Pavel Machek <pavel(a)denx.de> Cc: Simon Glass <sjg(a)chromium.org> --- v2: - As mentioned in the commit text, this new version does not move the default target to DT (yet). It adds support for the SoCrates board now based on this DT support as the first example. Nothing changes for the current socfpga_cyclone5 target. arch/arm/dts/Makefile | 2 + arch/arm/dts/socfpga.dtsi | 755 +++++++++++++++++++++++++++++ arch/arm/dts/socfpga_cyclone5.dtsi | 51 ++ arch/arm/dts/socfpga_cyclone5_socrates.dts | 50 ++ configs/socfpga_socrates_defconfig | 5 + include/dt-bindings/reset/altr,rst-mgr.h | 90 ++++ 6 files changed, 953 insertions(+) create mode 100644 arch/arm/dts/socfpga.dtsi create mode 100644 arch/arm/dts/socfpga_cyclone5.dtsi create mode 100644 arch/arm/dts/socfpga_cyclone5_socrates.dts create mode 100644 configs/socfpga_socrates_defconfig create mode 100644 include/dt-bindings/reset/altr,rst-mgr.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 52f8926..b946abe 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -40,6 +40,8 @@ dtb-$(CONFIG_ZYNQ) += zynq-zc702.dtb \ zynq-zc770-xm013.dtb dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb +dtb-$(CONFIG_SOCFPGA) += socfpga_cyclone5_socrates.dtb + targets += $(dtb-y) DTC_FLAGS += -R 4 -p 0x1000 diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi new file mode 100644 index 0000000..4472fd9 --- /dev/null +++ b/arch/arm/dts/socfpga.dtsi @@ -0,0 +1,755 @@ +/* + * Copyright (C) 2012 Altera <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "skeleton.dtsi" +#include <dt-bindings/reset/altr,rst-mgr.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + + aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac1; + serial0 = &uart0; + serial1 = &uart1; + timer0 = &timer0; + timer1 = &timer1; + timer2 = &timer2; + timer3 = &timer3; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0>; + next-level-cache = <&L2>; + }; + cpu@1 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <1>; + next-level-cache = <&L2>; + }; + }; + + intc: intc@fffed000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0xfffed000 0x1000>, + <0xfffec100 0x100>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + device_type = "soc"; + interrupt-parent = <&intc>; + ranges; + + amba { + compatible = "arm,amba-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pdma: pdma@ffe01000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0xffe01000 0x1000>; + interrupts = <0 104 4>, + <0 105 4>, + <0 106 4>, + <0 107 4>, + <0 108 4>, + <0 109 4>, + <0 110 4>, + <0 111 4>; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + clocks = <&l4_main_clk>; + clock-names = "apb_pclk"; + }; + }; + + can0: can@ffc00000 { + compatible = "bosch,d_can"; + reg = <0xffc00000 0x1000>; + interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>; + clocks = <&can0_clk>; + status = "disabled"; + }; + + can1: can@ffc01000 { + compatible = "bosch,d_can"; + reg = <0xffc01000 0x1000>; + interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>; + clocks = <&can1_clk>; + status = "disabled"; + }; + + clkmgr@ffd04000 { + compatible = "altr,clk-mgr"; + reg = <0xffd04000 0x1000>; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + osc1: osc1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + osc2: osc2 { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + f2s_periph_ref_clk: f2s_periph_ref_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + f2s_sdram_ref_clk: f2s_sdram_ref_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + main_pll: main_pll { + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <0>; + compatible = "altr,socfpga-pll-clock"; + clocks = <&osc1>; + reg = <0x40>; + + mpuclk: mpuclk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&main_pll>; + div-reg = <0xe0 0 9>; + reg = <0x48>; + }; + + mainclk: mainclk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&main_pll>; + div-reg = <0xe4 0 9>; + reg = <0x4C>; + }; + + dbg_base_clk: dbg_base_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&main_pll>; + div-reg = <0xe8 0 9>; + reg = <0x50>; + }; + + main_qspi_clk: main_qspi_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&main_pll>; + reg = <0x54>; + }; + + main_nand_sdmmc_clk: main_nand_sdmmc_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&main_pll>; + reg = <0x58>; + }; + + cfg_h2f_usr0_clk: cfg_h2f_usr0_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&main_pll>; + reg = <0x5C>; + }; + }; + + periph_pll: periph_pll { + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <0>; + compatible = "altr,socfpga-pll-clock"; + clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>; + reg = <0x80>; + + emac0_clk: emac0_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&periph_pll>; + reg = <0x88>; + }; + + emac1_clk: emac1_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&periph_pll>; + reg = <0x8C>; + }; + + per_qspi_clk: per_qsi_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&periph_pll>; + reg = <0x90>; + }; + + per_nand_mmc_clk: per_nand_mmc_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&periph_pll>; + reg = <0x94>; + }; + + per_base_clk: per_base_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&periph_pll>; + reg = <0x98>; + }; + + h2f_usr1_clk: h2f_usr1_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&periph_pll>; + reg = <0x9C>; + }; + }; + + sdram_pll: sdram_pll { + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <0>; + compatible = "altr,socfpga-pll-clock"; + clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>; + reg = <0xC0>; + + ddr_dqs_clk: ddr_dqs_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&sdram_pll>; + reg = <0xC8>; + }; + + ddr_2x_dqs_clk: ddr_2x_dqs_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&sdram_pll>; + reg = <0xCC>; + }; + + ddr_dq_clk: ddr_dq_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&sdram_pll>; + reg = <0xD0>; + }; + + h2f_usr2_clk: h2f_usr2_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&sdram_pll>; + reg = <0xD4>; + }; + }; + + mpu_periph_clk: mpu_periph_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&mpuclk>; + fixed-divider = <4>; + }; + + mpu_l2_ram_clk: mpu_l2_ram_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&mpuclk>; + fixed-divider = <2>; + }; + + l4_main_clk: l4_main_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mainclk>; + clk-gate = <0x60 0>; + }; + + l3_main_clk: l3_main_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&mainclk>; + fixed-divider = <1>; + }; + + l3_mp_clk: l3_mp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mainclk>; + div-reg = <0x64 0 2>; + clk-gate = <0x60 1>; + }; + + l3_sp_clk: l3_sp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mainclk>; + div-reg = <0x64 2 2>; + }; + + l4_mp_clk: l4_mp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mainclk>, <&per_base_clk>; + div-reg = <0x64 4 3>; + clk-gate = <0x60 2>; + }; + + l4_sp_clk: l4_sp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mainclk>, <&per_base_clk>; + div-reg = <0x64 7 3>; + clk-gate = <0x60 3>; + }; + + dbg_at_clk: dbg_at_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&dbg_base_clk>; + div-reg = <0x68 0 2>; + clk-gate = <0x60 4>; + }; + + dbg_clk: dbg_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&dbg_base_clk>; + div-reg = <0x68 2 2>; + clk-gate = <0x60 5>; + }; + + dbg_trace_clk: dbg_trace_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&dbg_base_clk>; + div-reg = <0x6C 0 3>; + clk-gate = <0x60 6>; + }; + + dbg_timer_clk: dbg_timer_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&dbg_base_clk>; + clk-gate = <0x60 7>; + }; + + cfg_clk: cfg_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&cfg_h2f_usr0_clk>; + clk-gate = <0x60 8>; + }; + + h2f_user0_clk: h2f_user0_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&cfg_h2f_usr0_clk>; + clk-gate = <0x60 9>; + }; + + emac_0_clk: emac_0_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&emac0_clk>; + clk-gate = <0xa0 0>; + }; + + emac_1_clk: emac_1_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&emac1_clk>; + clk-gate = <0xa0 1>; + }; + + usb_mp_clk: usb_mp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&per_base_clk>; + clk-gate = <0xa0 2>; + div-reg = <0xa4 0 3>; + }; + + spi_m_clk: spi_m_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&per_base_clk>; + clk-gate = <0xa0 3>; + div-reg = <0xa4 3 3>; + }; + + can0_clk: can0_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&per_base_clk>; + clk-gate = <0xa0 4>; + div-reg = <0xa4 6 3>; + }; + + can1_clk: can1_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&per_base_clk>; + clk-gate = <0xa0 5>; + div-reg = <0xa4 9 3>; + }; + + gpio_db_clk: gpio_db_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&per_base_clk>; + clk-gate = <0xa0 6>; + div-reg = <0xa8 0 24>; + }; + + h2f_user1_clk: h2f_user1_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&h2f_usr1_clk>; + clk-gate = <0xa0 7>; + }; + + sdmmc_clk: sdmmc_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; + clk-gate = <0xa0 8>; + clk-phase = <0 135>; + }; + + nand_x_clk: nand_x_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; + clk-gate = <0xa0 9>; + }; + + nand_clk: nand_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; + clk-gate = <0xa0 10>; + fixed-divider = <4>; + }; + + qspi_clk: qspi_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>; + clk-gate = <0xa0 11>; + }; + }; + }; + + gmac0: ethernet@ff700000 { + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; + altr,sysmgr-syscon = <&sysmgr 0x60 0>; + reg = <0xff700000 0x2000>; + interrupts = <0 115 4>; + interrupt-names = "macirq"; + mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ + clocks = <&emac0_clk>; + clock-names = "stmmaceth"; + resets = <&rst EMAC0_RESET>; + reset-names = "stmmaceth"; + snps,multicast-filter-bins = <256>; + snps,perfect-filter-entries = <128>; + status = "disabled"; + }; + + gmac1: ethernet@ff702000 { + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; + altr,sysmgr-syscon = <&sysmgr 0x60 2>; + reg = <0xff702000 0x2000>; + interrupts = <0 120 4>; + interrupt-names = "macirq"; + mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ + clocks = <&emac1_clk>; + clock-names = "stmmaceth"; + resets = <&rst EMAC1_RESET>; + reset-names = "stmmaceth"; + snps,multicast-filter-bins = <256>; + snps,perfect-filter-entries = <128>; + status = "disabled"; + }; + + i2c0: i2c@ffc04000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc04000 0x1000>; + clocks = <&l4_sp_clk>; + interrupts = <0 158 0x4>; + status = "disabled"; + }; + + i2c1: i2c@ffc05000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc05000 0x1000>; + clocks = <&l4_sp_clk>; + interrupts = <0 159 0x4>; + status = "disabled"; + }; + + i2c2: i2c@ffc06000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc06000 0x1000>; + clocks = <&l4_sp_clk>; + interrupts = <0 160 0x4>; + status = "disabled"; + }; + + i2c3: i2c@ffc07000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc07000 0x1000>; + clocks = <&l4_sp_clk>; + interrupts = <0 161 0x4>; + status = "disabled"; + }; + + gpio0: gpio@ff708000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0xff708000 0x1000>; + clocks = <&per_base_clk>; + status = "disabled"; + + porta: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <29>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 164 4>; + }; + }; + + gpio1: gpio@ff709000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0xff709000 0x1000>; + clocks = <&per_base_clk>; + status = "disabled"; + + portb: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <29>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 165 4>; + }; + }; + + gpio2: gpio@ff70a000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0xff70a000 0x1000>; + clocks = <&per_base_clk>; + status = "disabled"; + + portc: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <27>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 166 4>; + }; + }; + + sdr: sdr@ffc25000 { + compatible = "syscon"; + reg = <0xffc25000 0x1000>; + }; + + sdramedac { + compatible = "altr,sdram-edac"; + altr,sdr-syscon = <&sdr>; + interrupts = <0 39 4>; + }; + + L2: l2-cache@fffef000 { + compatible = "arm,pl310-cache"; + reg = <0xfffef000 0x1000>; + interrupts = <0 38 0x04>; + cache-unified; + cache-level = <2>; + arm,tag-latency = <1 1 1>; + arm,data-latency = <2 1 1>; + }; + + mmc: dwmmc0@ff704000 { + compatible = "altr,socfpga-dw-mshc"; + reg = <0xff704000 0x1000>; + interrupts = <0 139 4>; + fifo-depth = <0x400>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&l4_mp_clk>, <&sdmmc_clk>; + clock-names = "biu", "ciu"; + }; + + /* Local timer */ + timer@fffec600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xfffec600 0x100>; + interrupts = <1 13 0xf04>; + clocks = <&mpu_periph_clk>; + }; + + timer0: timer0@ffc08000 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 167 4>; + reg = <0xffc08000 0x1000>; + clocks = <&l4_sp_clk>; + clock-names = "timer"; + }; + + timer1: timer1@ffc09000 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 168 4>; + reg = <0xffc09000 0x1000>; + clocks = <&l4_sp_clk>; + clock-names = "timer"; + }; + + timer2: timer2@ffd00000 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 169 4>; + reg = <0xffd00000 0x1000>; + clocks = <&osc1>; + clock-names = "timer"; + }; + + timer3: timer3@ffd01000 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 170 4>; + reg = <0xffd01000 0x1000>; + clocks = <&osc1>; + clock-names = "timer"; + }; + + uart0: serial0@ffc02000 { + compatible = "snps,dw-apb-uart"; + reg = <0xffc02000 0x1000>; + interrupts = <0 162 4>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&l4_sp_clk>; + }; + + uart1: serial1@ffc03000 { + compatible = "snps,dw-apb-uart"; + reg = <0xffc03000 0x1000>; + interrupts = <0 163 4>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&l4_sp_clk>; + }; + + rst: rstmgr@ffd05000 { + #reset-cells = <1>; + compatible = "altr,rst-mgr"; + reg = <0xffd05000 0x1000>; + }; + + usbphy0: usbphy@0 { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + status = "okay"; + }; + + usb0: usb@ffb00000 { + compatible = "snps,dwc2"; + reg = <0xffb00000 0xffff>; + interrupts = <0 125 4>; + clocks = <&usb_mp_clk>; + clock-names = "otg"; + phys = <&usbphy0>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + usb1: usb@ffb40000 { + compatible = "snps,dwc2"; + reg = <0xffb40000 0xffff>; + interrupts = <0 128 4>; + clocks = <&usb_mp_clk>; + clock-names = "otg"; + phys = <&usbphy0>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + watchdog0: watchdog@ffd02000 { + compatible = "snps,dw-wdt"; + reg = <0xffd02000 0x1000>; + interrupts = <0 171 4>; + clocks = <&osc1>; + status = "disabled"; + }; + + watchdog1: watchdog@ffd03000 { + compatible = "snps,dw-wdt"; + reg = <0xffd03000 0x1000>; + interrupts = <0 172 4>; + clocks = <&osc1>; + status = "disabled"; + }; + + sysmgr: sysmgr@ffd08000 { + compatible = "altr,sys-mgr", "syscon"; + reg = <0xffd08000 0x4000>; + }; + }; +}; diff --git a/arch/arm/dts/socfpga_cyclone5.dtsi b/arch/arm/dts/socfpga_cyclone5.dtsi new file mode 100644 index 0000000..28c05e7 --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5.dtsi @@ -0,0 +1,51 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +/dts-v1/; +/* First 4KB has trampoline code for secondary cores. */ +/memreserve/ 0x00000000 0x0001000; +#include "socfpga.dtsi" + +/ { + soc { + clkmgr@ffd04000 { + clocks { + osc1 { + clock-frequency = <25000000>; + }; + }; + }; + + mmc0: dwmmc0@ff704000 { + num-slots = <1>; + broken-cd; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + }; + + ethernet@ff702000 { + phy-mode = "rgmii"; + phy-addr = <0xffffffff>; /* probe for phy addr */ + status = "okay"; + }; + + sysmgr@ffd08000 { + cpu1-start-addr = <0xffd080c4>; + }; + }; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts new file mode 100644 index 0000000..a1814b4 --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2014 Steffen Trumtrar <s.trumtrar(a)pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "socfpga_cyclone5.dtsi" + +/ { + model = "EBV SOCrates"; + compatible = "ebv,socrates", "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1GB */ + }; +}; + +&gmac1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rtc: rtc@68 { + compatible = "stm,m41t82"; + reg = <0x68>; + }; +}; + +&mmc { + status = "okay"; +}; diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig new file mode 100644 index 0000000..0f3896d --- /dev/null +++ b/configs/socfpga_socrates_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_SOCFPGA_CYCLONE5=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates" diff --git a/include/dt-bindings/reset/altr,rst-mgr.h b/include/dt-bindings/reset/altr,rst-mgr.h new file mode 100644 index 0000000..3f04908 --- /dev/null +++ b/include/dt-bindings/reset/altr,rst-mgr.h @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2014, Steffen Trumtrar <s.trumtrar(a)pengutronix.de> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_H +#define _DT_BINDINGS_RESET_ALTR_RST_MGR_H + +/* MPUMODRST */ +#define CPU0_RESET 0 +#define CPU1_RESET 1 +#define WDS_RESET 2 +#define SCUPER_RESET 3 +#define L2_RESET 4 + +/* PERMODRST */ +#define EMAC0_RESET 32 +#define EMAC1_RESET 33 +#define USB0_RESET 34 +#define USB1_RESET 35 +#define NAND_RESET 36 +#define QSPI_RESET 37 +#define L4WD0_RESET 38 +#define L4WD1_RESET 39 +#define OSC1TIMER0_RESET 40 +#define OSC1TIMER1_RESET 41 +#define SPTIMER0_RESET 42 +#define SPTIMER1_RESET 43 +#define I2C0_RESET 44 +#define I2C1_RESET 45 +#define I2C2_RESET 46 +#define I2C3_RESET 47 +#define UART0_RESET 48 +#define UART1_RESET 49 +#define SPIM0_RESET 50 +#define SPIM1_RESET 51 +#define SPIS0_RESET 52 +#define SPIS1_RESET 53 +#define SDMMC_RESET 54 +#define CAN0_RESET 55 +#define CAN1_RESET 56 +#define GPIO0_RESET 57 +#define GPIO1_RESET 58 +#define GPIO2_RESET 59 +#define DMA_RESET 60 +#define SDR_RESET 61 + +/* PER2MODRST */ +#define DMAIF0_RESET 64 +#define DMAIF1_RESET 65 +#define DMAIF2_RESET 66 +#define DMAIF3_RESET 67 +#define DMAIF4_RESET 68 +#define DMAIF5_RESET 69 +#define DMAIF6_RESET 70 +#define DMAIF7_RESET 71 + +/* BRGMODRST */ +#define HPS2FPGA_RESET 96 +#define LWHPS2FPGA_RESET 97 +#define FPGA2HPS_RESET 98 + +/* MISCMODRST*/ +#define ROM_RESET 128 +#define OCRAM_RESET 129 +#define SYSMGR_RESET 130 +#define SYSMGRCOLD_RESET 131 +#define FPGAMGR_RESET 132 +#define ACPIDMAP_RESET 133 +#define S2F_RESET 134 +#define S2FCOLD_RESET 135 +#define NRSTPIN_RESET 136 +#define TIMESTAMPCOLD_RESET 137 +#define CLKMGRCOLD_RESET 138 +#define SCANMGR_RESET 139 +#define FRZCTRLCOLD_RESET 140 +#define SYSDBG_RESET 141 +#define DBG_RESET 142 +#define TAPCOLD_RESET 143 +#define SDRCOLD_RESET 144 + +#endif -- 2.1.3

1 0

[U-Boot] [PATCH] usb: include <asm/cache.h> and <part.h> from include/usb.h
by Masahiro Yamada 07 Nov '14

07 Nov '14

The header file include/usb.h references ARCH_DMA_MINALIGH and block_dev_desc_t, thus it must include <asm/cache.h> and <part.h>. Signed-off-by: Masahiro Yamada <yamada.m(a)jp.panasonic.com> --- include/usb.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/usb.h b/include/usb.h index 9d0d04d..d3c7415 100644 --- a/include/usb.h +++ b/include/usb.h @@ -11,6 +11,8 @@ #include <usb_defs.h> #include <linux/usb/ch9.h> +#include <asm/cache.h> +#include <part.h> /* * The EHCI spec says that we must align to at least 32 bytes. However, -- 1.9.1

2 1

[U-Boot] [PATCH 1/3] powerpc: add deep sleep support for generic board
by Yuantian.Tang＠freescale.com 07 Nov '14

07 Nov '14

From: Tang Yuantian <Yuantian.Tang(a)freescale.com> Deep sleep for generic board is not supported on PowerPC. This patch make deep sleep work for both non-generic board and generic board on PowerPC platforms. For ARM-based QorIQ platforms, deep sleep has been already supported. Signed-off-by: Tang Yuantian <Yuantian.Tang(a)freescale.com> --- README | 2 +- arch/powerpc/cpu/mpc85xx/cpu_init.c | 2 +- arch/powerpc/cpu/mpc85xx/fdt.c | 2 +- arch/powerpc/lib/board.c | 24 ++++++------------------ drivers/ddr/fsl/mpc85xx_ddr_gen3.c | 37 ++++++++++++++----------------------- drivers/qe/qe.c | 8 ++++---- 6 files changed, 27 insertions(+), 48 deletions(-) diff --git a/README b/README index 48061b4..194bdf0 100644 --- a/README +++ b/README @@ -442,7 +442,7 @@ The following options need to be configured: This CONFIG is defined when the CPC is configured as SRAM at the time of U-boot entry and is required to be re-initialized. - CONFIG_DEEP_SLEEP + CONFIG_FSL_DEEP_SLEEP Inidcates this SoC supports deep sleep feature. If deep sleep is supported, core will start to execute uboot when wakes up. diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index bd397aa..267d366 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -479,7 +479,7 @@ ulong cpu_init_f(void) #endif #ifdef CONFIG_SYS_DCSRBAR_PHYS -#ifdef CONFIG_DEEP_SLEEP +#ifdef CONFIG_FSL_DEEP_SLEEP /* disable the console if boot from deep sleep */ if (in_be32(&gur->scrtsr[0]) & (1 << 3)) flag = GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 61d7b81..2695941 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -134,7 +134,7 @@ void ft_fixup_cpu(void *blob, u64 memory_limit) printf("Failed to reserve memory for spin table: %s\n", fdt_strerror(off)); } -#ifdef CONFIG_DEEP_SLEEP +#ifdef CONFIG_FSL_DEEP_SLEEP #ifdef CONFIG_SPL_MMC_BOOT off = fdt_add_mem_rsv(blob, CONFIG_SYS_MMC_U_BOOT_START, CONFIG_SYS_MMC_U_BOOT_SIZE); diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c index 50eb820..ff49116 100644 --- a/arch/powerpc/lib/board.c +++ b/arch/powerpc/lib/board.c @@ -113,6 +113,9 @@ ulong monitor_flash_len; #include <bedbug/type.h> #endif +#ifdef CONFIG_FSL_DEEP_SLEEP +#include <fsl_sleep.h> +#endif /* * Utilities */ @@ -343,13 +346,6 @@ void board_init_f(ulong bootflag) #ifdef CONFIG_PRAM ulong reg; #endif -#ifdef CONFIG_DEEP_SLEEP - const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - struct ccsr_scfg *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG; - u32 start_addr; - typedef void (*func_t)(void); - func_t kernel_resume; -#endif /* Pointer is writable since we allocated a register for it */ gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); @@ -367,18 +363,10 @@ void board_init_f(ulong bootflag) if ((*init_fnc_ptr) () != 0) hang(); -#ifdef CONFIG_DEEP_SLEEP +#ifdef CONFIG_FSL_DEEP_SLEEP /* Jump to kernel in deep sleep case */ - if (in_be32(&gur->scrtsr[0]) & (1 << 3)) { - l2cache_init(); -#if defined(CONFIG_RAMBOOT_PBL) - disable_cpc_sram(); -#endif - enable_cpc(); - start_addr = in_be32(&scfg->sparecr[1]); - kernel_resume = (func_t)start_addr; - kernel_resume(); - } + if (is_warm_boot()) + fsl_dp_resume(); #endif #ifdef CONFIG_POST diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c index 4d5572e..194a714 100644 --- a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c @@ -10,13 +10,14 @@ #include <asm/io.h> #include <fsl_ddr_sdram.h> #include <asm/processor.h> +#ifdef CONFIG_FSL_DEEP_SLEEP +#include <fsl_sleep.h> +#endif #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4) #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL #endif -DECLARE_GLOBAL_DATA_PTR; - /* * regs has the to-be-set values for DDR controller registers * ctrl_num is the DDR controller number @@ -44,16 +45,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, u32 save1, save2; #endif -#ifdef CONFIG_DEEP_SLEEP - const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - bool sleep_flag = 0; -#endif - -#ifdef CONFIG_DEEP_SLEEP - if (in_be32(&gur->scrtsr[0]) & (1 << 3)) - sleep_flag = 1; -#endif - switch (ctrl_num) { case 0: ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; @@ -130,8 +121,8 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0); out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1); out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); -#ifdef CONFIG_DEEP_SLEEP - if (sleep_flag) +#ifdef CONFIG_FSL_DEEP_SLEEP + if (is_warm_boot()) out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); else @@ -149,8 +140,8 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); out_be32(&ddr->sdram_data_init, regs->ddr_data_init); out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); -#ifdef CONFIG_DEEP_SLEEP - if (sleep_flag) { +#ifdef CONFIG_FSL_DEEP_SLEEP + if (is_warm_boot()) { out_be32(&ddr->init_addr, 0); out_be32(&ddr->init_ext_addr, (1 << 31)); } else @@ -399,18 +390,18 @@ step2: udelay(500); asm volatile("sync;isync"); -#ifdef CONFIG_DEEP_SLEEP - if (sleep_flag) { +#ifdef CONFIG_FSL_DEEP_SLEEP + if (is_warm_boot()) { /* enter self-refresh */ setbits_be32(&ddr->sdram_cfg_2, (1 << 31)); /* do board specific memory setup */ - board_mem_sleep_setup(); + fsl_dp_mem_setup(); } #endif /* Let the controller go */ -#ifdef CONFIG_DEEP_SLEEP - if (sleep_flag) +#ifdef CONFIG_FSL_DEEP_SLEEP + if (is_warm_boot()) temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) | SDRAM_CFG_BI); else #endif @@ -565,8 +556,8 @@ step2: clrbits_be32(&ddr->sdram_cfg, 0x2); } #endif /* CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 */ -#ifdef CONFIG_DEEP_SLEEP - if (sleep_flag) +#ifdef CONFIG_FSL_DEEP_SLEEP + if (is_warm_boot()) /* exit self-refresh */ clrbits_be32(&ddr->sdram_cfg_2, (1 << 31)); #endif diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index 3ca01d8..4265a21 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -334,7 +334,7 @@ int qe_upload_firmware(const struct qe_firmware *firmware) size_t calc_size = sizeof(struct qe_firmware); size_t length; const struct qe_header *hdr; -#ifdef CONFIG_DEEP_SLEEP +#ifdef CONFIG_FSL_DEEP_SLEEP ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #endif if (!firmware) { @@ -349,7 +349,7 @@ int qe_upload_firmware(const struct qe_firmware *firmware) if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') || (hdr->magic[2] != 'F')) { printf("Not a microcode\n"); -#ifdef CONFIG_DEEP_SLEEP +#ifdef CONFIG_FSL_DEEP_SLEEP setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_QE_DISABLE); #endif return -EPERM; @@ -469,7 +469,7 @@ int u_qe_upload_firmware(const struct qe_firmware *firmware) size_t calc_size = sizeof(struct qe_firmware); size_t length; const struct qe_header *hdr; -#ifdef CONFIG_DEEP_SLEEP +#ifdef CONFIG_FSL_DEEP_SLEEP ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #endif if (!firmware) { @@ -484,7 +484,7 @@ int u_qe_upload_firmware(const struct qe_firmware *firmware) if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') || (hdr->magic[2] != 'F')) { printf("Not a microcode\n"); -#ifdef CONFIG_DEEP_SLEEP +#ifdef CONFIG_FSL_DEEP_SLEEP setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_QE_DISABLE); #endif return -EPERM; -- 2.1.0.27.g96db324

1 2

[U-Boot] [PATCH v2 0/3] imx:mx6 add usb support
by Peng Fan 07 Nov '14

07 Nov '14

Changes v2: - move pinmux setting into board_init - add otg polarity setting in board_ehci_hcd_init - Introduce a new weak function to give board a choice to decide the work mode of the otg port, since a otg port can also work in host mode without touch ID pin. Peng Fan (3): usb:ehci-mx6 add board_ehci_usb_mode function imx:mx6sxsabresd add usb support imx:mx6slevk add usb support arch/arm/include/asm/arch-mx6/mx6sl_pins.h | 5 +++ board/freescale/mx6slevk/mx6slevk.c | 51 +++++++++++++++++++++++++++++ board/freescale/mx6sxsabresd/mx6sxsabresd.c | 51 +++++++++++++++++++++++++++++ drivers/usb/host/ehci-mx6.c | 7 ++++ include/configs/mx6slevk.h | 14 ++++++++ include/configs/mx6sxsabresd.h | 14 ++++++++ 6 files changed, 142 insertions(+) -- 1.8.4.5

4 20

[U-Boot] [PATCH v2 1/2] exynos: Enable config_distro_defaults.h
by Ian Campbell 07 Nov '14

07 Nov '14

From: Ian Campbell <ian.campbell(a)citrix.com> ...and remove explicit setting of things which this implies. This is done for all exynos platforms (4 & 5) so it is added to exynos-common.h I'm mainly interested in CONFIG_CMD_BOOTZ and CONFIG_SUPPORT_RAW_INITRD I have build tested on all exynos platforms (MAKEALL -s exynos), but only boot tested on arndale. Signed-off-by: Ian Campbell <ian.campbell(a)citrix.com> --- v2: This patch was previously "arndale: Enable config_distro_defaults.h". It required significant rebasing. --- include/configs/arndale.h | 2 -- include/configs/exynos-common.h | 13 ++----------- include/configs/exynos5-common.h | 11 ----------- 3 files changed, 2 insertions(+), 24 deletions(-) diff --git a/include/configs/arndale.h b/include/configs/arndale.h index f9ee40f..a87806d 100644 --- a/include/configs/arndale.h +++ b/include/configs/arndale.h @@ -17,8 +17,6 @@ /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE -#define CONFIG_CMD_EXT2 - /* USB */ #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_EXYNOS diff --git a/include/configs/exynos-common.h b/include/configs/exynos-common.h index 371f32d..ea40bb6 100644 --- a/include/configs/exynos-common.h +++ b/include/configs/exynos-common.h @@ -23,9 +23,6 @@ #define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_BOARD_EARLY_INIT_F -/* Enable fdt support */ -#define CONFIG_OF_LIBFDT - /* Keep L2 Cache Disabled */ #define CONFIG_CMD_CACHE @@ -35,7 +32,6 @@ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_CMDLINE_TAG #define CONFIG_INITRD_TAG -#define CONFIG_CMDLINE_EDITING #define CONFIG_ENV_OVERWRITE /* Size of malloc() pool before and after relocation */ @@ -54,7 +50,6 @@ #define CONFIG_EXYNOS_DWMMC #define CONFIG_BOUNCE_BUFFER -#define CONFIG_BOOTDELAY 3 #define CONFIG_ZERO_BOOTDELAY_CHECK /* PWM */ @@ -64,19 +59,13 @@ #include <config_cmd_default.h> #define CONFIG_CMD_MMC -#define CONFIG_CMD_EXT4 #define CONFIG_CMD_EXT4_WRITE -#define CONFIG_CMD_FAT #define CONFIG_FAT_WRITE -#define CONFIG_DOS_PARTITION -#define CONFIG_EFI_PARTITION #define CONFIG_CMD_PART #define CONFIG_PARTITION_UUIDS /* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ @@ -88,4 +77,6 @@ #define CONFIG_SYS_NO_FLASH #undef CONFIG_CMD_IMLS +#include <config_distro_defaults.h> + #endif /* __CONFIG_H */ diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index ba591e7..b03966d 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -55,9 +55,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ EXYNOS_DEVICE_SETTINGS -#define CONFIG_CMD_PING -#define CONFIG_CMD_ELF -#define CONFIG_CMD_NET #define CONFIG_CMD_HASH /* Thermal Management Unit */ @@ -174,12 +171,6 @@ #define CONFIG_ENV_SROM_BANK 1 #endif /*CONFIG_CMD_NET*/ -/* Enable PXE Support */ -#ifdef CONFIG_CMD_NET -#define CONFIG_CMD_PXE -#define CONFIG_MENU -#endif - /* SHA hashing */ #define CONFIG_CMD_HASH #define CONFIG_HASH_VERIFY @@ -189,8 +180,6 @@ /* Enable Time Command */ #define CONFIG_CMD_TIME -#define CONFIG_CMD_BOOTZ - #define CONFIG_CMD_GPIO /* USB boot mode */ -- 2.1.0

4 4

[U-Boot] [PATCH] socfpga_cyclone5.h: fix kernel console argument in default environment
by Anatolij Gustschin 07 Nov '14

07 Nov '14

With fresh environment the kernel gets wrong console argument and boots without console output. Fix it. Reported-by: Dinh Nguyen <dinguyen(a)opensource.altera.com> Signed-off-by: Anatolij Gustschin <agust(a)denx.de> Cc: Chin Liang See <clsee(a)altera.com> Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> Cc: Marek Vasut <marex(a)denx.de> --- include/configs/socfpga_cyclone5.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index 942738c..c3d958c 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -42,7 +42,7 @@ /* Booting Linux */ #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTFILE "zImage" -#define CONFIG_BOOTARGS "console=ttyS0" __stringify(CONFIG_BAUDRATE) +#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET #define CONFIG_BOOTCOMMAND "run ramboot" #else -- 1.7.9.5

2 1

[U-Boot] [PATCH 1/7] spi: altera: Use struct-based register access
by Marek Vasut 07 Nov '14

07 Nov '14

Zap the offset-based register access and use the struct-based one as this is the preferred method. No functional change, but there are some line-over-80 problems in the driver, which will be addressed later. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Chin Liang See <clsee(a)altera.com> Cc: Dinh Nguyen <dinguyen(a)altera.com> Cc: Albert Aribaud <albert.u.boot(a)aribaud.net> Cc: Pavel Machek <pavel(a)denx.de> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki(a)gmail.com> --- drivers/spi/altera_spi.c | 49 ++++++++++++++++++++++++------------------------ 1 file changed, 25 insertions(+), 24 deletions(-) diff --git a/drivers/spi/altera_spi.c b/drivers/spi/altera_spi.c index 5accbb5..13191f3 100644 --- a/drivers/spi/altera_spi.c +++ b/drivers/spi/altera_spi.c @@ -12,11 +12,14 @@ #include <malloc.h> #include <spi.h> -#define ALTERA_SPI_RXDATA 0 -#define ALTERA_SPI_TXDATA 4 -#define ALTERA_SPI_STATUS 8 -#define ALTERA_SPI_CONTROL 12 -#define ALTERA_SPI_SLAVE_SEL 20 +struct altera_spi_regs { + u32 rxdata; + u32 txdata; + u32 status; + u32 control; + u32 _reserved; + u32 slave_sel; +}; #define ALTERA_SPI_STATUS_ROE_MSK (0x8) #define ALTERA_SPI_STATUS_TOE_MSK (0x10) @@ -39,8 +42,8 @@ static ulong altera_spi_base_list[] = CONFIG_SYS_ALTERA_SPI_LIST; struct altera_spi_slave { - struct spi_slave slave; - ulong base; + struct spi_slave slave; + struct altera_spi_regs *regs; }; #define to_altera_spi_slave(s) container_of(s, struct altera_spi_slave, slave) @@ -54,16 +57,16 @@ __attribute__((weak)) void spi_cs_activate(struct spi_slave *slave) { struct altera_spi_slave *altspi = to_altera_spi_slave(slave); - writel(1 << slave->cs, altspi->base + ALTERA_SPI_SLAVE_SEL); - writel(ALTERA_SPI_CONTROL_SSO_MSK, altspi->base + ALTERA_SPI_CONTROL); + writel(1 << slave->cs, &altspi->regs->slave_sel); + writel(ALTERA_SPI_CONTROL_SSO_MSK, &altspi->regs->control); } __attribute__((weak)) void spi_cs_deactivate(struct spi_slave *slave) { struct altera_spi_slave *altspi = to_altera_spi_slave(slave); - writel(0, altspi->base + ALTERA_SPI_CONTROL); - writel(0, altspi->base + ALTERA_SPI_SLAVE_SEL); + writel(0, &altspi->regs->control); + writel(0, &altspi->regs->slave_sel); } void spi_init(void) @@ -87,9 +90,9 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, if (!altspi) return NULL; - altspi->base = altera_spi_base_list[bus]; - debug("%s: bus:%i cs:%i base:%lx\n", __func__, - bus, cs, altspi->base); + altspi->regs = (struct altera_spi_regs *)altera_spi_base_list[bus]; + debug("%s: bus:%i cs:%i base:%p\n", __func__, + bus, cs, altspi->regs); return &altspi->slave; } @@ -105,8 +108,8 @@ int spi_claim_bus(struct spi_slave *slave) struct altera_spi_slave *altspi = to_altera_spi_slave(slave); debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs); - writel(0, altspi->base + ALTERA_SPI_CONTROL); - writel(0, altspi->base + ALTERA_SPI_SLAVE_SEL); + writel(0, &altspi->regs->control); + writel(0, &altspi->regs->slave_sel); return 0; } @@ -115,7 +118,7 @@ void spi_release_bus(struct spi_slave *slave) struct altera_spi_slave *altspi = to_altera_spi_slave(slave); debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs); - writel(0, altspi->base + ALTERA_SPI_SLAVE_SEL); + writel(0, &altspi->regs->slave_sel); } #ifndef CONFIG_ALTERA_SPI_IDLE_VAL @@ -142,20 +145,18 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, } /* empty read buffer */ - if (readl(altspi->base + ALTERA_SPI_STATUS) & - ALTERA_SPI_STATUS_RRDY_MSK) - readl(altspi->base + ALTERA_SPI_RXDATA); + if (readl(&altspi->regs->status) & ALTERA_SPI_STATUS_RRDY_MSK) + readl(&altspi->regs->rxdata); if (flags & SPI_XFER_BEGIN) spi_cs_activate(slave); while (bytes--) { uchar d = txp ? *txp++ : CONFIG_ALTERA_SPI_IDLE_VAL; debug("%s: tx:%x ", __func__, d); - writel(d, altspi->base + ALTERA_SPI_TXDATA); - while (!(readl(altspi->base + ALTERA_SPI_STATUS) & - ALTERA_SPI_STATUS_RRDY_MSK)) + writel(d, &altspi->regs->txdata); + while (!(readl(&altspi->regs->status) & ALTERA_SPI_STATUS_RRDY_MSK)) ; - d = readl(altspi->base + ALTERA_SPI_RXDATA); + d = readl(&altspi->regs->rxdata); if (rxp) *rxp++ = d; debug("rx:%x\n", d); -- 2.0.0

5 12

[U-Boot] [PATCH v5 0/2] Adds support for Exynos5422 odroid xu3 board
by Hyungwon Hwang 07 Nov '14

07 Nov '14

This is v5 of the patchset adding support Odroud XU3 board. link to the previous version: v2: https://www.mail-archive.com/u-boot@lists.denx.de/msg152275.html v3: https://www.mail-archive.com/u-boot%40lists.denx.de/msg152677.html v4: https://patchwork.ozlabs.org/patch/407411/ This patchset fixes GPIO information of Exynos5420 which is needed to support Exynos5422 Odroid XU3 board. On the base of the fixes, this patchset adds support for Exynos5422 Odroid XU3 board. I have done this work on the master branch in http://git.denx.de/u-boot-samsung.git (sha1: 26f195c71252e98aebfffd5cfa994a4475559370) with patches by Akshay Saraswat. link: https://patchwork.ozlabs.org/patch/405246/ (updated) How to test this patch: 1. git clone http://git.denx.de/u-boot-samsung.git 2. git reset --hard 26f195c71252e98aebfffd5cfa994a4475559370 3. Get and apply the patchset of Akshay Saraswat https://patchwork.ozlabs.org/patch/405246/ https://patchwork.ozlabs.org/patch/405247/ https://patchwork.ozlabs.org/patch/405248/ https://patchwork.ozlabs.org/patch/405249/ https://patchwork.ozlabs.org/patch/405250/ https://patchwork.ozlabs.org/patch/405251/ https://patchwork.ozlabs.org/patch/405252/ 4. Apply this patchset 5. make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- odroid-xu3_config 6. make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- -j8 7. Now you can use u-boot-dtb.bin for your downloading Note: If you use micro SD card for your test you have to apply the below patch additionally. This patch is needed, because micro sd card is recognized as MMC1 instead of MMC0. Additional work is needed to make it work regardless of device id. diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index ba591e7..437eaae 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -109,7 +109,7 @@ #define CONFIG_SYS_MONITOR_BASE 0x00000000 -#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_DEV 1 #define CONFIG_SECURE_BL1_ONLY diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h index cda4f26..b46ccad 100644 --- a/include/configs/odroid_xu3.h +++ b/include/configs/odroid_xu3.h @@ -110,15 +110,15 @@ "run kernel_args;" \ "bootz ${kerneladdr} ${initrd_addr} ${fdt_addr};\0" \ "autoboot=" \ - "if test -e mmc 0 Image.itb; then; " \ + "if test -e mmc 1 Image.itb; then; " \ "run boot_fit;" \ - "elif test -e mmc 0 zImage; then; " \ + "elif test -e mmc 1 zImage; then; " \ "run boot_zimg;" \ - "elif test -e mmc 0 uImage; then; " \ + "elif test -e mmc 1 uImage; then; " \ "run boot_uimg;" \ "fi;\0" \ "console=" CONFIG_DEFAULT_CONSOLE \ - "mmcbootdev=0\0" \ + "mmcbootdev=1\0" \ "mmcbootpart=1\0" \ "mmcrootdev=0\0" \ "mmcrootpart=2\0" \ Changes for v2: - Add a patch to add new common setup header file for Odroid X2/U3 and Odroid XU3 Changes for v3: - Remove the patch which adds new common setup header file from v2 - Remove the wrong patch to fix GPIO information of Exynos 5800 - Remove unnecessary node from DT file - Remove unnecessary features from config file - Fix some trivial typos in comments Changes for v4: - Add MMC FIFO buffer's configuration to DT file - Make CONFIG_OF_CONTROL be set by the target information - Add basic document to doc/README.odroid-xu3 - Add CONFIG_CMD_EXT4 to config file - Add environment size and offset to config file - Add extra default environment to make bootable without modification - Remove unnecessary features from config file Changes for v5: - Add the specific build instruction - Update the information of patchset by Akshay Saraswat - Convert /include/ to #include in DT file Hyungwon Hwang (2): exynos5: fix GPIO information of exynos5420 Odroid-XU3: Add support for Odroid-XU3 arch/arm/cpu/armv7/exynos/Kconfig | 5 + arch/arm/dts/Makefile | 3 +- arch/arm/dts/exynos5422-odroidxu3.dts | 60 +++++++++ arch/arm/include/asm/arch-exynos/cpu.h | 11 +- arch/arm/include/asm/arch-exynos/gpio.h | 232 +++++++++++++++----------------- board/samsung/odroid-xu3/Kconfig | 12 ++ board/samsung/odroid-xu3/MAINTAINERS | 6 + board/samsung/odroid-xu3/Makefile | 7 + board/samsung/odroid-xu3/odroid-xu3.c | 131 ++++++++++++++++++ board/samsung/odroid-xu3/setup.h | 95 +++++++++++++ configs/odroid-xu3_defconfig | 4 + doc/README.odroid-xu3 | 134 ++++++++++++++++++ include/configs/odroid_xu3.h | 144 ++++++++++++++++++++ 13 files changed, 717 insertions(+), 127 deletions(-) create mode 100644 arch/arm/dts/exynos5422-odroidxu3.dts create mode 100644 board/samsung/odroid-xu3/Kconfig create mode 100644 board/samsung/odroid-xu3/MAINTAINERS create mode 100644 board/samsung/odroid-xu3/Makefile create mode 100644 board/samsung/odroid-xu3/odroid-xu3.c create mode 100644 board/samsung/odroid-xu3/setup.h create mode 100644 configs/odroid-xu3_defconfig create mode 100644 doc/README.odroid-xu3 create mode 100644 include/configs/odroid_xu3.h -- 1.8.3.2

2 3