September 2013 - U-Boot

[U-Boot] [PATCH] powerpc/eeprom: update MAX_NUM_PORTS to adapt non-256-bytes EEPROM
by Shengzhou Liu 04 Sep '13

04 Sep '13

Some boards use System EEPROM with 128-bytes instead of 256-bytes. Since we regard 256-bytes EEPROM as standard EEPROM with default value for MAX_NUM_PORTS. For those non-256-bytes EEPROM, we can redefine MAX_NUM_PORTS in board-specific file to override the default MAX_NUM_PORTS. This patch doesn't impact on previous existing boards. Signed-off-by: Shengzhou Liu <Shengzhou.Liu(a)freescale.com> --- board/freescale/common/sys_eeprom.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c index d2ed036..1b69315 100644 --- a/board/freescale/common/sys_eeprom.c +++ b/board/freescale/common/sys_eeprom.c @@ -34,7 +34,11 @@ #endif #ifdef CONFIG_SYS_I2C_EEPROM_NXID +/* some boards with non-256-bytes EEPROM have special define */ +/* for MAX_NUM_PORTS in board-specific file */ +#ifndef MAX_NUM_PORTS #define MAX_NUM_PORTS 23 +#endif #define NXID_VERSION 1 #endif -- 1.8.0

4 3

[U-Boot] [PATCH] Exynos5250: I2C: Fix driver as per new I2C multibus/multiadapter support
by Rajeshwari S Shinde 03 Sep '13

03 Sep '13

This patch fixes the S3C24xx I2C driver as per new I2C multibus/multiadapter support for Exynos5250. Change-Id: I95873fef7d312310670e3bb33ad9532c10f60463 Signed-off-by: Rajeshwari S Shinde <rajeshwari.s(a)samsung.com> --- drivers/i2c/s3c24x0_i2c.c | 14 +++++++------- include/configs/exynos5250-dt.h | 3 ++- 2 files changed, 9 insertions(+), 8 deletions(-) diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c index cd09c78..5fdb85f 100644 --- a/drivers/i2c/s3c24x0_i2c.c +++ b/drivers/i2c/s3c24x0_i2c.c @@ -53,7 +53,7 @@ static unsigned int g_current_bus __attribute__((section(".data"))); #ifdef CONFIG_OF_CONTROL static int i2c_busses __attribute__((section(".data"))); -static struct s3c24x0_i2c_bus i2c_bus[CONFIG_MAX_I2C_NUM] +static struct s3c24x0_i2c_bus i2c_bus_data[CONFIG_SYS_NUM_I2C_BUSES] __attribute__((section(".data"))); #endif @@ -160,7 +160,7 @@ int i2c_set_bus_num(unsigned int bus) { struct s3c24x0_i2c *i2c; - if ((bus < 0) || (bus >= CONFIG_MAX_I2C_NUM)) { + if ((bus < 0) || (bus >= CONFIG_SYS_NUM_I2C_BUSES)) { debug("Bad bus: %d\n", bus); return -1; } @@ -503,12 +503,12 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) void board_i2c_init(const void *blob) { int i; - int node_list[CONFIG_MAX_I2C_NUM]; + int node_list[CONFIG_SYS_NUM_I2C_BUSES]; int count; count = fdtdec_find_aliases_for_id(blob, "i2c", COMPAT_SAMSUNG_S3C2440_I2C, node_list, - CONFIG_MAX_I2C_NUM); + CONFIG_SYS_NUM_I2C_BUSES); for (i = 0; i < count; i++) { struct s3c24x0_i2c_bus *bus; @@ -516,7 +516,7 @@ void board_i2c_init(const void *blob) if (node <= 0) continue; - bus = &i2c_bus[i]; + bus = &i2c_bus_data[i]; bus->regs = (struct s3c24x0_i2c *) fdtdec_get_addr(blob, node, "reg"); bus->id = pinmux_decode_periph_id(blob, node); @@ -529,7 +529,7 @@ void board_i2c_init(const void *blob) static struct s3c24x0_i2c_bus *get_bus(unsigned int bus_idx) { if (bus_idx < i2c_busses) - return &i2c_bus[bus_idx]; + return &i2c_bus_data[bus_idx]; debug("Undefined bus: %d\n", bus_idx); return NULL; @@ -540,7 +540,7 @@ int i2c_get_bus_num_fdt(int node) int i; for (i = 0; i < i2c_busses; i++) { - if (node == i2c_bus[i].node) + if (node == i2c_bus_data[i].node) return i; } diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h index 2b93a45..e6a2cd0 100644 --- a/include/configs/exynos5250-dt.h +++ b/include/configs/exynos5250-dt.h @@ -254,8 +254,9 @@ #define CONFIG_SYS_I2C_SPEED 100000 /* 100 Kbps */ #define CONFIG_DRIVER_S3C24X0_I2C #define CONFIG_I2C_MULTI_BUS -#define CONFIG_MAX_I2C_NUM 8 #define CONFIG_SYS_I2C_SLAVE 0x0 +#define CONFIG_SYS_I2C_MAX_HOPS 1 +#define CONFIG_SYS_NUM_I2C_BUSES 8 #define CONFIG_I2C_EDID /* PMIC */ -- 1.7.12.4

3 2

[U-Boot] [PATCH] powerpc/p1010rdb: update readme for p1010rdb-pb board
by Shengzhou Liu 03 Sep '13

03 Sep '13

P1010RDB-PB is a variation of previous P1010RDB-PA board. Henceforth we support P1010RDB-PB board instead of P1010RDB-PA. Signed-off-by: Shengzhou Liu <Shengzhou.Liu(a)freescale.com> --- board/freescale/p1010rdb/README | 285 +++++++++++++++++-------------------- doc/README.p1010rdb | 302 +++++++++++++++++++--------------------- 2 files changed, 267 insertions(+), 320 deletions(-) diff --git a/board/freescale/p1010rdb/README b/board/freescale/p1010rdb/README index 7f18aaa..6d96bd4 100644 --- a/board/freescale/p1010rdb/README +++ b/board/freescale/p1010rdb/README @@ -1,58 +1,40 @@ Overview ========= -The P1010RDB is a Freescale reference design board that hosts the P1010 SoC. +The P1010RDB is a Freescale Reference Design Board that hosts the P1010 SoC. +P1010RDB-PB is a variation of previous P1010RDB-PA board. The P1010 is a cost-effective, low-power, highly integrated host processor -based on a Power Architecture e500v2 core (maximum core frequency 800/1000 MHz), -that addresses the requirements of several routing, gateways, storage, consumer, +based on a Power Architecture e500v2 core (maximum core frequency 1GHz),that +addresses the requirements of several routing, gateways, storage, consumer, and industrial applications. Applications of interest include the main CPUs and I/O processors in network attached storage (NAS), the voice over IP (VoIP) router/gateway, and wireless LAN (WLAN) and industrial controllers. -The P1010RDB board features are as follows: +The P1010RDB-PB board features are as following: Memory subsystem: - - 1Gbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus) - - 32 Mbyte NOR flash single-chip memory - - 32 Mbyte NAND flash memory - - 256 Kbit M24256 I2C EEPROM - - 16 Mbyte SPI memory + - 1G bytes unbuffered DDR3 SDRAM discrete devices (32-bit bus) + - 32M bytes NOR flash single-chip memory + - 2G bytes NAND flash memory + - 16M bytes SPI memory + - 256K bit M24256 I2C EEPROM - I2C Board EEPROM 128x8 bit memory - SD/MMC connector to interface with the SD memory card Interfaces: - - PCIe: - - Lane0: x1 mini-PCIe slot - - Lane1: x1 PCIe standard slot - - SATA: - - 1 internal SATA connector to 2.5” 160G SATA2 HDD - - 1 eSATA connector to rear panel - - 10/100/1000 BaseT Ethernet ports: - - eTSEC1, RGMII: one 10/100/1000 port using Vitesse VSC8641XKO - - eTSEC2, SGMII: one 10/100/1000 port using Vitesse VSC8221 - - eTSEC3, SGMII: one 10/100/1000 port using Vitesse VSC8221 - - USB 2.0 port: - - x1 USB2.0 port via an external ULPI PHY to micro-AB connector - - x1 USB2.0 port via an internal UTMI PHY to micro-AB connector - - FlexCAN ports: - - 2 DB-9 female connectors for FlexCAN bus(revision 2.0B) - interface; - - DUART interface: - - DUART interface: supports two UARTs up to 115200 bps for - console display - - RJ45 connectors are used for these 2 UART ports. - - TDM - - 2 FXS ports connected via an external SLIC to the TDM interface. - SLIC is controllled via SPI. - - 1 FXO port connected via a relay to FXS for switchover to POTS + - Three 10/100/1000 BaseT Ethernet ports (One RGMII and two SGMII) + - PCIe 2.0: two x1 mini-PCIe slots + - SATA 2.0: two SATA interfaces + - USB 2.0: one USB interface + - FlexCAN: two FlexCAN interfaces (revision 2.0B) + - UART: one USB-to-Serial interface + - TDM: 2 FXS ports connected via an external SLIC to the TDM interface. + 1 FXO port connected via a relay to FXS for switchover to POTS + Board connectors: - Mini-ITX power supply connector - JTAG/COP for debugging -IEEE Std. 1588 signals for test and measurement -Real-time clock on I2C bus -POR - - support critical POR setting changed via switch on board -PCB - - 6-layer routing (4-layer signals, 2-layer power and ground) +POR: support critical POR setting changed via switch on board +PCB: 6-layer routing (4-layer signals, 2-layer power and ground) Physical Memory Map on P1010RDB =============================== @@ -77,132 +59,119 @@ Configure the serial port of the attached computer with the following values: -Flow Control: Hardware/None -Settings of DIP-switch -====================== - SW4[1:4]= 1111 and SW6[4]=0 for boot from 16bit NOR flash - SW4[1:4]= 1000 and SW6[4]=1 for boot from 8bit NAND flash - SW4[1:4]= 0110 and SW6[4]=0 for boot from SPI flash +P1010RDB-PB default DIP-switch settings +======================================= +SW1[1:8]= 10101010 +SW2[1:8]= 11011000 +SW3[1:8]= 10010000 +SW4[1:4]= 1010 +SW5[1:8]= 11111010 + + +P1010RDB-PB boot mode settings via DIP-switch +============================================= +SW4[1:4]= 1111 and SW3[3:4]= 00 for 16bit NOR boot +SW4[1:4]= 1010 and SW3[3:4]= 01 for 8bit NAND boot +SW4[1:4]= 0110 and SW3[3:4]= 00 for SPI boot +SW4[1:4]= 0111 and SW3[3:4]= 10 for SD boot Note: 1 stands for 'on', 0 stands for 'off' -Setting of hwconfig +P1010RDB-PB boot mode change in u-boot without DIP-switch +========================================================= +=> run boot_bank0 (boot from NOR bank0) +=> run boot_bank1 (boot from NOR bank1) +=> run boot_nand (boot from NAND flash) +=> run boot_spi (boot from SPI flash) +=> run boot_sd (boot from SD card) + + +Setting of pin mux =================== -If FlexCAN or TDM is needed, please set "fsl_p1010mux:tdm_can=can" or -"fsl_p1010mux:tdm_can=tdm" explicitly in u-booot prompt as below for example: -setenv hwconfig "fsl_p1010mux:tdm_can=tdm;usb1:dr_mode=host,phy_type=utmi" -By default, don't set fsl_p1010mux:tdm_can, in this case, spi chip selection -is set to spi-flash instead of to SLIC/TDM/DAC and tdm_can_sel is set to TDM -instead of to CAN/UART1. - - -Build and burn u-boot to NOR flash -================================== -1. Build u-boot.bin image - export ARCH=powerpc - export CROSS_COMPILE=/your_path/powerpc-linux-gnu- - make P1010RDB_NOR - -2. Burn u-boot.bin into NOR flash - => tftp $loadaddr $uboot - => protect off eff80000 +$filesize - => erase eff80000 +$filesize - => cp.b $loadaddr eff80000 $filesize - -3. Check SW4[1:4]= 1111 and SW6[4]=0, then power on. - - -Alternate NOR bank -================== -1. Burn u-boot.bin into alternate NOR bank - => tftp $loadaddr $uboot - => protect off eef80000 +$filesize - => erase eef80000 +$filesize - => cp.b $loadaddr eef80000 $filesize - -2. Switch to alternate NOR bank - => mw.b ffb00009 1 - => reset - or set SW1[8]= ON - -SW1[8]= OFF: Upper bank used for booting start -SW1[8]= ON: Lower bank used for booting start -CPLD NOR bank selection register address 0xFFB00009 Bit[0]: -0 - boot from upper 4 sectors -1 - boot from lower 4 sectors - - -Build and burn u-boot to NAND flash -=================================== -1. Build u-boot.bin image - export ARCH=powerpc - export CROSS_COMPILE=/your_path/powerpc-linux-gnu- - make P1010RDB_NAND - -2. Burn u-boot-nand.bin into NAND flash - => tftp $loadaddr $uboot-nand - => nand erase 0 $filesize - => nand write $loadaddr 0 $filesize - -3. Check SW4[1:4]= 1000 and SW6[4]=1, then power on. - - -Build and burn u-boot to SPI flash -================================== -1. Build u-boot-spi.bin image - make P1010RDB_SPIFLASH_config; make - Boot up kernel with rootfs.ext2.gz.uboot.p1010rdb - Download u-boot.bin to linux and you can find some config files - under /usr/share such as config_xx.dat. Do below command: - boot_format config_ddr3_1gb_p1010rdb_800M.dat u-boot.bin -spi \ - u-boot-spi.bin - to generate u-boot-spi.bin. - -2. Burn u-boot-spi.bin into SPI flash - => tftp $loadaddr $uboot-spi - => sf erase 0 100000 - => sf write $loadaddr 0 $filesize - -3. Check SW4[1:4]= 0110 and SW6[4]=0, then power on. - - -CPLD POR setting registers -========================== -1. Set POR switch selection register (addr 0xFFB00011) to 0. -2. Write CPLD POR registers (BCSR0~BCSR3, addr 0xFFB00014~0xFFB00017) with - proper values. - If change boot ROM location to NOR or NAND flash, need write the IFC_CS0 - switch command by I2C. -3. Send reset command. - After reset, the new POR setting will be implemented. - -Two examples are given in below: -Switch from NOR to NAND boot with default frequency: - => i2c dev 0 - => i2c mw 18 1 f9 - => i2c mw 18 3 f0 - => mw.b ffb00011 0 - => mw.b ffb00017 1 - => reset -Switch from NAND to NOR boot with Core/CCB/DDR (800/400/667 MHz): - => i2c dev 0 - => i2c mw 18 1 f1 - => i2c mw 18 3 f0 - => mw.b ffb00011 0 - => mw.b ffb00014 2 - => mw.b ffb00015 5 - => mw.b ffb00016 3 - => mw.b ffb00017 f - => reset - - -Boot Linux from network using TFTP on P1010RDB -============================================== -Place uImage, p1010rdb.dtb and rootfs files in the TFTP disk area. +Since pins multiplexing, TDM and CAN are muxed with SPI flash. +SDHC is muxed with IFC. IFC and SPI flash are enabled by default. + +To enable TDM: +=> setenv hwconfig fsl_p1010mux:tdm_can=tdm +=> save;reset + +To enable FlexCAN: +=> setenv hwconfig fsl_p1010mux:tdm_can=can +=> save;reset + +To enable SDHC in case of NOR/NAND/SPI boot + a) For temporary use case in runtime without reboot system + run 'mux sdhc' in u-boot to validate SDHC with invalidating IFC. + + b) For long-term use case + set 'esdhc' in hwconfig and save it. + +To enable IFC in case of SD boot + run 'mux ifc' in u-boot to validate IFC with invalidating SDHC. + + +Build images for different boot mode: +===================================== +First, setup cross compile environment on your build host + $ export ARCH=powerpc + $ export CROSS_COMPILE=<your-compiler-path>/powerpc-linux-gnu- + +1. For NOR boot + $ make distclean + $ make P1010RDB-PB_NOR + +2. For NAND boot + $ make distclean + $ make P1010RDB-PB_NAND + +3. For SPI boot + $ make distclean + $ make P1010RDB-PB_SPIFLASH + +4. For SD boot + $ make distclean + $ make P1010RDB-PB_SDCARD + + +Steps to burn images for different boot mode: +============================================= +1. NOR boot + => tftp 1000000 u-boot.bin + For bank0 + => pro off all;era eff80000 efffffff;cp.b 1000000 eff80000 $filesize + set SW1[8]=0, SW4[1:4]= 1111 and SW3[3:4]= 00, then power on the board + + For bank1 + => pro off all;era eef80000 eeffffff;cp.b 1000000 eef80000 $filesize + set SW1[8]=1, SW4[1:4]= 1111 and SW3[3:4]= 00, then power on the board + +2. NAND boot + => tftp 1000000 u-boot-nand.bin + => nand erase 0 $filesize; nand write $loadaddr 0 $filesize + Set SW4[1:4]= 1010 and SW3[3:4]= 01, then power on the board + +3. SPI boot + 1) cat p1010rdb-config-header.bin u-boot.bin > u-boot-spi-combined.bin + 2) => tftp 1000000 u-boot-spi-combined.bin + 3) => sf probe 0; sf erase 0 100000; sf write 1000000 0 100000 + set SW4[1:4]= 0110 and SW3[3:4]= 00, then power on the board + +4. SD boot + 1) cat p1010rdb-config-header.bin u-boot.bin > u-boot-sd-combined.bin + 2) => tftp 1000000 u-boot-sd-combined.bin + 3) => mux sdhc + 4) => mmc write 1000000 0 1050 + set SW4[1:4]= 0111 and SW3[3:4]= 10, then power on the board + + +Boot Linux from network using TFTP on P1010RDB-PB +================================================= +Place uImage, p1010rdb.dtb and rootfs files in the TFTP download path. => tftp 1000000 uImage => tftp 2000000 p1010rdb.dtb => tftp 3000000 rootfs.ext2.gz.uboot.p1010rdb => bootm 1000000 3000000 2000000 -Please contact your local field applications engineer or sales representative -to obtain related documents, such as P1010-RDB User Guide for details. +For more details, please refer to P1010RDB-PB User Guide and access website +www.freescale.com and Freescale QorIQ SDK Infocenter document. diff --git a/doc/README.p1010rdb b/doc/README.p1010rdb index dee63d7..6d96bd4 100644 --- a/doc/README.p1010rdb +++ b/doc/README.p1010rdb @@ -1,58 +1,52 @@ Overview ========= -The P1010RDB is a Freescale reference design board that hosts the P1010 SoC. +The P1010RDB is a Freescale Reference Design Board that hosts the P1010 SoC. +P1010RDB-PB is a variation of previous P1010RDB-PA board. The P1010 is a cost-effective, low-power, highly integrated host processor -based on a Power Architecture e500v2 core (maximum core frequency 800/1000 MHz), -that addresses the requirements of several routing, gateways, storage, consumer, +based on a Power Architecture e500v2 core (maximum core frequency 1GHz),that +addresses the requirements of several routing, gateways, storage, consumer, and industrial applications. Applications of interest include the main CPUs and I/O processors in network attached storage (NAS), the voice over IP (VoIP) router/gateway, and wireless LAN (WLAN) and industrial controllers. -The P1010RDB board features are as follows: +The P1010RDB-PB board features are as following: Memory subsystem: - - 1Gbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus) - - 32 Mbyte NOR flash single-chip memory - - 32 Mbyte NAND flash memory - - 256 Kbit M24256 I2C EEPROM - - 16 Mbyte SPI memory + - 1G bytes unbuffered DDR3 SDRAM discrete devices (32-bit bus) + - 32M bytes NOR flash single-chip memory + - 2G bytes NAND flash memory + - 16M bytes SPI memory + - 256K bit M24256 I2C EEPROM - I2C Board EEPROM 128x8 bit memory - SD/MMC connector to interface with the SD memory card Interfaces: - - PCIe: - - Lane0: x1 mini-PCIe slot - - Lane1: x1 PCIe standard slot - - SATA: - - 1 internal SATA connector to 2.5" 160G SATA2 HDD - - 1 eSATA connector to rear panel - - 10/100/1000 BaseT Ethernet ports: - - eTSEC1, RGMII: one 10/100/1000 port using Vitesse VSC8641XKO - - eTSEC2, SGMII: one 10/100/1000 port using Vitesse VSC8221 - - eTSEC3, SGMII: one 10/100/1000 port using Vitesse VSC8221 - - USB 2.0 port: - - x1 USB2.0 port: via an ULPI PHY to micro-AB connector - - x1 USB2.0 poort via an internal PHY to micro-AB connector - - FlexCAN ports: - - x2 DB-9 female connectors for FlexCAN bus(revision 2.0B) - interface; - - DUART interface: - - DUART interface: supports two UARTs up to 115200 bps for - console display - - J45 connectors are used for these 2 UART ports. - - TDM - - 2 FXS ports connected via an external SLIC to the TDM - interface. SLIC is controllled via SPI. - - 1 FXO port connected via a relay to FXS for switchover to - POTS + - Three 10/100/1000 BaseT Ethernet ports (One RGMII and two SGMII) + - PCIe 2.0: two x1 mini-PCIe slots + - SATA 2.0: two SATA interfaces + - USB 2.0: one USB interface + - FlexCAN: two FlexCAN interfaces (revision 2.0B) + - UART: one USB-to-Serial interface + - TDM: 2 FXS ports connected via an external SLIC to the TDM interface. + 1 FXO port connected via a relay to FXS for switchover to POTS + Board connectors: - Mini-ITX power supply connector - JTAG/COP for debugging -IEEE Std. 1588 signals for test and measurement -Real-time clock on I2C bus -POR - - support critical POR setting changed via switch on board -PCB - - 6-layer routing (4-layer signals, 2-layer power and ground) + +POR: support critical POR setting changed via switch on board +PCB: 6-layer routing (4-layer signals, 2-layer power and ground) + +Physical Memory Map on P1010RDB +=============================== +Address Start Address End Memory type Attributes +0x0000_0000 0x3fff_ffff DDR 1G Cacheable +0xa000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable +0xee00_0000 0xefff_ffff NOR Flash 32M non-cacheable +0xffc2_0000 0xffc5_ffff PCI IO range 256K non-cacheable +0xffa0_0000 0xffaf_ffff NAND Flash 1M cacheable +0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable +0xffd0_0000 0xffd0_3fff L1 for Stack 16K Cacheable TLB0 +0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable Serial Port Configuration on P1010RDB @@ -65,135 +59,119 @@ Configure the serial port of the attached computer with the following values: -Flow Control: Hardware/None -Settings of DIP-switch -====================== - SW4[1:4]= 1111 and SW6[4]=0 for boot from 16bit NOR flash - SW4[1:4]= 1000 and SW6[4]=1 for boot from 8bit NAND flash - SW4[1:4]= 0110 and SW6[4]=0 for boot from SPI flash +P1010RDB-PB default DIP-switch settings +======================================= +SW1[1:8]= 10101010 +SW2[1:8]= 11011000 +SW3[1:8]= 10010000 +SW4[1:4]= 1010 +SW5[1:8]= 11111010 + + +P1010RDB-PB boot mode settings via DIP-switch +============================================= +SW4[1:4]= 1111 and SW3[3:4]= 00 for 16bit NOR boot +SW4[1:4]= 1010 and SW3[3:4]= 01 for 8bit NAND boot +SW4[1:4]= 0110 and SW3[3:4]= 00 for SPI boot +SW4[1:4]= 0111 and SW3[3:4]= 10 for SD boot Note: 1 stands for 'on', 0 stands for 'off' -Setting of hwconfig +P1010RDB-PB boot mode change in u-boot without DIP-switch +========================================================= +=> run boot_bank0 (boot from NOR bank0) +=> run boot_bank1 (boot from NOR bank1) +=> run boot_nand (boot from NAND flash) +=> run boot_spi (boot from SPI flash) +=> run boot_sd (boot from SD card) + + +Setting of pin mux =================== -If FlexCAN or TDM is needed, please set "fsl_p1010mux:tdm_can=can" or -"fsl_p1010mux:tdm_can=tdm" explicitly in u-booot prompt as below for example: -setenv hwconfig "fsl_p1010mux:tdm_can=tdm;usb1:dr_mode=host,phy_type=utmi" -By default, don't set fsl_p1010mux:tdm_can, in this case, spi chip selection -is set to spi-flash instead of to SLIC/TDM/DAC and tdm_can_sel is set to TDM -instead of to CAN/UART1. - - -Build and burn u-boot to NOR flash -================================== -1. Build u-boot.bin image - export ARCH=powerpc - export CROSS_COMPILE=/your_path/powerpc-linux-gnu- - make P1010RDB_NOR - -2. Burn u-boot.bin into NOR flash - => tftp $loadaddr $uboot - => protect off eff80000 +$filesize - => erase eff80000 +$filesize - => cp.b $loadaddr eff80000 $filesize - -3. Check SW4[1:4]= 1111 and SW6[4]=0, then power on. - - -Alternate NOR bank -============================ -1. Burn u-boot.bin into alternate NOR bank - => tftp $loadaddr $uboot - => protect off eef80000 +$filesize - => erase eef80000 +$filesize - => cp.b $loadaddr eef80000 $filesize - -2. Switch to alternate NOR bank - => mw.b ffb00009 1 - => reset - or set SW1[8]= ON - -SW1[8]= OFF: Upper bank used for booting start -SW1[8]= ON: Lower bank used for booting start -CPLD NOR bank selection register address 0xFFB00009 Bit[0]: -0 - boot from upper 4 sectors -1 - boot from lower 4 sectors - - -Build and burn u-boot to NAND flash -=================================== -1. Build u-boot.bin image - export ARCH=powerpc - export CROSS_COMPILE=/your_path/powerpc-linux-gnu- - make P1010RDB_NAND - -2. Burn u-boot-nand.bin into NAND flash - => tftp $loadaddr $uboot-nand - => nand erase 0 $filesize - => nand write $loadaddr 0 $filesize - -3. Check SW4[1:4]= 1000 and SW6[4]=1, then power on. - - - -Build and burn u-boot to SPI flash -================================== -1. Build u-boot-spi.bin image - make P1010RDB_SPIFLASH_config; make - Boot up kernel with rootfs.ext2.gz.uboot.p1010rdb - Download u-boot.bin to linux and you can find some config files - under /usr/share such as config_xx.dat. Do below command: - boot_format config_ddr3_1gb_p1010rdb_800M.dat u-boot.bin -spi \ - u-boot-spi.bin - to generate u-boot-spi.bin. - -2. Burn u-boot-spi.bin into SPI flash - => tftp $loadaddr $uboot-spi - => sf erase 0 100000 - => sf write $loadaddr 0 $filesize - -3. Check SW4[1:4]= 0110 and SW6[4]=0, then power on. - - - -CPLD POR setting registers -========================== -1. Set POR switch selection register (addr 0xFFB00011) to 0. -2. Write CPLD POR registers (BCSR0~BCSR3, addr 0xFFB00014~0xFFB00017) with - proper values. - If change boot ROM location to NOR or NAND flash, need write the IFC_CS0 - switch command by I2C. -3. Send reset command. - After reset, the new POR setting will be implemented. - -Two examples are given in below: -Switch from NOR to NAND boot with default frequency: - => i2c dev 0 - => i2c mw 18 1 f9 - => i2c mw 18 3 f0 - => mw.b ffb00011 0 - => mw.b ffb00017 1 - => reset -Switch from NAND to NOR boot with Core/CCB/DDR (800/400/667 MHz): - => i2c dev 0 - => i2c mw 18 1 f1 - => i2c mw 18 3 f0 - => mw.b ffb00011 0 - => mw.b ffb00014 2 - => mw.b ffb00015 5 - => mw.b ffb00016 3 - => mw.b ffb00017 f - => reset - - - -Boot Linux from network using TFTP on P1010RDB -============================================== -Place uImage, p1010rdb.dtb and rootfs files in the TFTP disk area. +Since pins multiplexing, TDM and CAN are muxed with SPI flash. +SDHC is muxed with IFC. IFC and SPI flash are enabled by default. + +To enable TDM: +=> setenv hwconfig fsl_p1010mux:tdm_can=tdm +=> save;reset + +To enable FlexCAN: +=> setenv hwconfig fsl_p1010mux:tdm_can=can +=> save;reset + +To enable SDHC in case of NOR/NAND/SPI boot + a) For temporary use case in runtime without reboot system + run 'mux sdhc' in u-boot to validate SDHC with invalidating IFC. + + b) For long-term use case + set 'esdhc' in hwconfig and save it. + +To enable IFC in case of SD boot + run 'mux ifc' in u-boot to validate IFC with invalidating SDHC. + + +Build images for different boot mode: +===================================== +First, setup cross compile environment on your build host + $ export ARCH=powerpc + $ export CROSS_COMPILE=<your-compiler-path>/powerpc-linux-gnu- + +1. For NOR boot + $ make distclean + $ make P1010RDB-PB_NOR + +2. For NAND boot + $ make distclean + $ make P1010RDB-PB_NAND + +3. For SPI boot + $ make distclean + $ make P1010RDB-PB_SPIFLASH + +4. For SD boot + $ make distclean + $ make P1010RDB-PB_SDCARD + + +Steps to burn images for different boot mode: +============================================= +1. NOR boot + => tftp 1000000 u-boot.bin + For bank0 + => pro off all;era eff80000 efffffff;cp.b 1000000 eff80000 $filesize + set SW1[8]=0, SW4[1:4]= 1111 and SW3[3:4]= 00, then power on the board + + For bank1 + => pro off all;era eef80000 eeffffff;cp.b 1000000 eef80000 $filesize + set SW1[8]=1, SW4[1:4]= 1111 and SW3[3:4]= 00, then power on the board + +2. NAND boot + => tftp 1000000 u-boot-nand.bin + => nand erase 0 $filesize; nand write $loadaddr 0 $filesize + Set SW4[1:4]= 1010 and SW3[3:4]= 01, then power on the board + +3. SPI boot + 1) cat p1010rdb-config-header.bin u-boot.bin > u-boot-spi-combined.bin + 2) => tftp 1000000 u-boot-spi-combined.bin + 3) => sf probe 0; sf erase 0 100000; sf write 1000000 0 100000 + set SW4[1:4]= 0110 and SW3[3:4]= 00, then power on the board + +4. SD boot + 1) cat p1010rdb-config-header.bin u-boot.bin > u-boot-sd-combined.bin + 2) => tftp 1000000 u-boot-sd-combined.bin + 3) => mux sdhc + 4) => mmc write 1000000 0 1050 + set SW4[1:4]= 0111 and SW3[3:4]= 10, then power on the board + + +Boot Linux from network using TFTP on P1010RDB-PB +================================================= +Place uImage, p1010rdb.dtb and rootfs files in the TFTP download path. => tftp 1000000 uImage => tftp 2000000 p1010rdb.dtb => tftp 3000000 rootfs.ext2.gz.uboot.p1010rdb => bootm 1000000 3000000 2000000 -Please contact your local field applications engineer or sales representative -to obtain related documents, such as P1010-RDB User Guide for details. +For more details, please refer to P1010RDB-PB User Guide and access website +www.freescale.com and Freescale QorIQ SDK Infocenter document. -- 1.8.0

1 0

[U-Boot] [PATCH v1 0/3] mtd: nand: omap: add support for BCH16_ECC
by Pekon Gupta 03 Sep '13

03 Sep '13

This patch series add support of BCH16_ECC scheme. As BCH16_ECC scheme generates 26bytes of ECC syndrome per 512B data, hence this scheme is usable only for NAND devices having 4K or above page-size, as their OOB/spare area has enough space to accomodate ECC. This patch series is applicable over an above following series: http://lists.denx.de/pipermail/u-boot/2013-September/161859.html Pekon Gupta (3): [PATCH 1/3] am33xx: elm: add support for BCH16_ECC - ELM driver updates [PATCH 2/3] mtd: nand: omap: add support for BCH16_ECC - NAND driver updates [PATCH 3/3] am335x: update README for BCH16 arch/arm/cpu/armv7/am33xx/elm.c | 91 +++++++++++++++-------- arch/arm/include/asm/arch-am33xx/cpu.h | 15 +++- arch/arm/include/asm/arch-am33xx/elm.h | 16 ++--- arch/arm/include/asm/arch-am33xx/omap_gpmc.h | 4 +- board/ti/am335x/README | 43 ++++++++++- drivers/mtd/nand/omap_gpmc.c | 103 ++++++++++++++++++++------- include/mtd/mtd-abi.h | 3 +- 7 files changed, 205 insertions(+), 70 deletions(-) -- 1.8.1

1 3

[U-Boot] [ARM] Returning to active state
by Albert ARIBAUD 03 Sep '13

03 Sep '13

Hello all, I was away for a few days and only slowly returning to active state. Please bear with me while I catch up. As usual, my priority will go to PRs, then patches assigned to me. For anything urgent, mail To: me. Amicalement, -- Albert.

1 0

[U-Boot] [PATCH v5 5/5] board/ti/am335x/README: update for NAND boot
by Pekon Gupta 03 Sep '13

03 Sep '13

NAND boot mode on AM335x EVM has been verified, and steps to use it has been documented and update in this README Signed-off-by: Pekon Gupta <pekon(a)ti.com> Acked-by: Peter Korsgaard <jacmet(a)sunsite.dk> --- board/ti/am335x/README | 59 +++++++++++++++++++++++++++++++++++--------------- 1 file changed, 42 insertions(+), 17 deletions(-) diff --git a/board/ti/am335x/README b/board/ti/am335x/README index 67b5246..941dfbb 100644 --- a/board/ti/am335x/README +++ b/board/ti/am335x/README @@ -20,23 +20,48 @@ NAND The AM335x GP EVM ships with a 256MiB NAND available in most profiles. In this example to program the NAND we assume that an SD card has been inserted with the files to write in the first SD slot and that mtdparts -have been configured correctly for the board. As a time saving measure we -load MLO into memory in one location, copy it into the three locatations -that the ROM checks for additional valid copies, then load U-Boot into -memory. We then write that whole section of memory to NAND. - -U-Boot # mmc rescan -U-Boot # env default -f -a -U-Boot # nand erase.chip -U-Boot # saveenv -U-Boot # load mmc 0 81000000 MLO -U-Boot # cp.b 81000000 81020000 20000 -U-Boot # cp.b 81000000 81040000 20000 -U-Boot # cp.b 81000000 81060000 20000 -U-Boot # load mmc 0 81080000 u-boot.img -U-Boot # nand write 81000000 0 260000 -U-Boot # load mmc 0 ${loadaddr} uImage -U-Boot # nand write ${loadaddr} kernel 500000 +have been configured correctly for the board. All images are first loaded +into memory, then written to NAND. + +Step-1: Building u-boot for NAND boot + Set following CONFIGxx options for NAND device. + CONFIG_SYS_NAND_PAGE_SIZE number of main bytes in NAND page + CONFIG_SYS_NAND_OOBSIZE number of OOB bytes in NAND page + CONFIG_SYS_NAND_BLOCK_SIZE number of bytes in NAND erase-block + CONFIG_SYS_NAND_ECCPOS ECC map for NAND page + CONFIG_SYS_NAND_ECCSCHEME ECC scheme used by NAND + 0 - HAM1_SW + 1 - HAM1_HW + 2 - BCH4_SW (unsupported) + 3 - BCH4_HW (unsupported) + 4 - BCH8_SW + 5 - BCH8_HW + +Step-2: Flashing NAND via MMC/SD + # select BOOTSEL to MMC/SD boot and boot from MMC/SD card + U-Boot # mmc rescan + # erase flash + U-Boot # nand erase.chip + U-Boot # env default -f -a + U-Boot # saveenv + # flash MLO. Redundant copies of MLO are kept for failsafe + U-Boot # load mmc 0 0x82000000 MLO + U-Boot # nand write 0x82000000 0x00000 0x20000 + U-Boot # nand write 0x82000000 0x20000 0x20000 + U-Boot # nand write 0x82000000 0x40000 0x20000 + U-Boot # nand write 0x82000000 0x60000 0x20000 + # flash u-boot.img + U-Boot # load mmc 0 0x82000000 u-boot.img + U-Boot # nand write 0x82000000 0x80000 0x60000 + # flash kernel image + U-Boot # load mmc 0 0x82000000 uImage + U-Boot # nand write 0x82000000 ${nandsrcaddr} ${nandimgsize} + # flash filesystem image + U-Boot # load mmc 0 0x82000000 filesystem.img + U-Boot # nand write 0x82000000 {loadaddress} 0x300000 + +Step-3: Set BOOTSEL pin to select NAND boot, and POR the device. + The device should boot from images flashed on NAND device. NOR === -- 1.8.1

1 0

[U-Boot] [Uboot] Question about MMC driver
by DongboZhang＠viatech.com.cn 03 Sep '13

03 Sep '13

Dear U-Boot maintainer, I have two questions about mmc driver base u-boot-2013.07. Q 1: In mmc.c, function sd_send_op_cond(), line 506: line 505: if (timeout <= 0) line 506: return UNUSABLE_ERR; I think it should be return TIMEOUT . Because for MMC card or eMMC device, the program will return at this place. Following code is: line 1392: /* If the command timed out, we check for an MMC card */ line 1393: if (err == TIMEOUT) { line 1394: err = mmc_send_op_cond(mmc); Now, err is UNUSABLE_ERR, then function mmc_send_op_cond() will never be invoked. The MMC card or eMMC device initialization will be failed. Q 2: In mmc.c, function mmc_startup(), line 989 - line 1006: line 989: /* line 990: * For MMC cards, set the Relative Address. line 991: * For SD cards, get the Relatvie Address. line 992: * This also puts the cards into Standby State line 993: */ line 994: if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */ line 995: cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR; line 996: cmd.cmdarg = mmc->rca << 16; line 997: cmd.resp_type = MMC_RSP_R6; line 998: line 999: err = mmc_send_cmd(mmc, &cmd, NULL); line 1000: line 1001: if (err) line 1002: return err; line 1003: line 1004: if (IS_SD(mmc)) line 1005: mmc->rca = (cmd.response[0] >> 16) & 0xffff; line 1006: } In this part, the program only handle the RCA of SD cards, not process the RCA of MMC cards. Before this part, mmc->rca is 0. After this part, for SD card, mmc->rca is a valid value(e.g. 0x1234) for MMC card, mmc->rca still is 0 In SD spec v4.0, section 5.4: The writable 16-bit relative card address register carries the card address that is published by the card during the card identification. In MMC spec v4.5, section 7.5: The writable 16-bit relative Device address(RCA) register carries the Device address assigned by the host during the Device identification. For SD card, after send CMD3, we will get the RCA value from the SD card. But for MMC card or eMMC device, host should set a RCA value to the card by CMD3. I think setting for RCA of MMC card should be added to this part. BRs Dongbo

1 0

[U-Boot] [Uboot] Question about MMC driver
by DongboZhang＠viatech.com.cn 03 Sep '13

03 Sep '13

Dear U-Boot maintainer, I have two questions about mmc driver base u-boot-2013.07. Q 1: In mmc.c, function sd_send_op_cond(), line 506: line 505: if (timeout <= 0) line 506: return UNUSABLE_ERR; I think it should be return TIMEOUT . Because for MMC card or eMMC device, the program will return at this place. Following code is: line 1392: /* If the command timed out, we check for an MMC card */ line 1393: if (err == TIMEOUT) { line 1394: err = mmc_send_op_cond(mmc); Now, err is UNUSABLE_ERR, then function mmc_send_op_cond() will never be invoked. The MMC card or eMMC device initialization will be failed. Q 2: In mmc.c, function mmc_startup(), line 989 - line 1006: line 989: /* line 990: * For MMC cards, set the Relative Address. line 991: * For SD cards, get the Relatvie Address. line 992: * This also puts the cards into Standby State line 993: */ line 994: if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */ line 995: cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR; line 996: cmd.cmdarg = mmc->rca << 16; line 997: cmd.resp_type = MMC_RSP_R6; line 998: line 999: err = mmc_send_cmd(mmc, &cmd, NULL); line 1000: line 1001: if (err) line 1002: return err; line 1003: line 1004: if (IS_SD(mmc)) line 1005: mmc->rca = (cmd.response[0] >> 16) & 0xffff; line 1006: } In this part, the program only handle the RCA of SD cards, not process the RCA of MMC cards. Before this part, mmc->rca is 0. After this part, for SD card, mmc->rca is a valid value(e.g. 0x1234) for MMC card, mmc->rca still is 0 In SD spec v4.0, section 5.4: The writable 16-bit relative card address register carries the card address that is published by the card during the card identification. In MMC spec v4.5, section 7.5: The writable 16-bit relative Device address(RCA) register carries the Device address assigned by the host during the Device identification. For SD card, after send CMD3, we will get the RCA value from the SD card. But for MMC card or eMMC device, host should set a RCA value to the card by CMD3. I think setting for RCA of MMC card should be added to this part. BRs Dongbo

1 0

[U-Boot] [PATCH] nios2: fix missing comment terminator from SPDX License commit
by Thomas Chou 03 Sep '13

03 Sep '13

The commit 1a4596601fd395f3afb8f82f3f840c5e00bdd57a Add GPL-2.0+ SPDX-License-Identifier to source files generated a warning due to a missing comment terminator. longlong.h:7:1: warning: "/*" within comment Signed-off-by: Thomas Chou <thomas(a)wytron.com.tw> --- arch/nios2/lib/longlong.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/nios2/lib/longlong.h b/arch/nios2/lib/longlong.h index 63c64ed..45ec5f0 100644 --- a/arch/nios2/lib/longlong.h +++ b/arch/nios2/lib/longlong.h @@ -3,6 +3,7 @@ 2005 Free Software Foundation, Inc. * SPDX-License-Identifier: GPL-2.0+ + */ /* You have to define the following before including this file: -- 1.8.3.1

1 0

[U-Boot] [ANN] v2013.10-rc1
by Tom Rini 02 Sep '13

02 Sep '13

Hey all, I've put v2013.10-rc2 out, and I hope Detlev can get the tarball uploaded soon. We don't have a whole lot of changes in here, but I think that's partly due to some folks being on holiday. I hope that we can finish re-syncing everyone in around the 16th when I'll kick out -rc3. For my part, I see a lot of stuff in my own queue I need to clear out and merge, and I hope to get to that soon. Please let us all know if something has stopped working. Thanks all! -- Tom

2 2