September 2013 - U-Boot

[U-Boot] [Patch v2] powerpc/mpc85xx: Add workaround for erratum A006379
by York Sun 16 Sep '13

16 Sep '13

Erratum A006379 says CPCHDBCR0 bit field [10:14] has incorrect default value after POR. The workaround is to set this field before enabling CPC to 0x1e. Erratum A006379 applies to T4240 rev 1.0 B4860 rev 1.0, 2.0 Signed-off-by: York Sun <yorksun(a)freescale.com> --- Change log: v2: Add a list of SoC impacted by this erratum Add a function to detect whether workaround should be applied at runtime Add fsl_errata.h to host the prototype of the new function arch/powerpc/cpu/mpc85xx/cmd_errata.c | 5 +++++ arch/powerpc/cpu/mpc85xx/cpu_init.c | 7 +++++++ arch/powerpc/include/asm/config_mpc85xx.h | 2 ++ arch/powerpc/include/asm/fsl_errata.h | 24 ++++++++++++++++++++++++ arch/powerpc/include/asm/immap_85xx.h | 1 + 5 files changed, 39 insertions(+) create mode 100644 arch/powerpc/include/asm/fsl_errata.h diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index c441bd2..1e5a43f 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -7,6 +7,7 @@ #include <common.h> #include <command.h> #include <linux/compiler.h> +#include <asm/fsl_errata.h> #include <asm/processor.h> #include "fsl_corenet_serdes.h" @@ -245,6 +246,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #ifdef CONFIG_SYS_FSL_ERRATUM_A006593 puts("Work-around for Erratum A006593 enabled\n"); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A006379 + if (has_erratum_a006379()) + puts("Work-around for Erratum A006379 enabled\n"); +#endif #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571 if (IS_SVR_REV(svr, 1, 0)) puts("Work-around for Erratum A003571 enabled\n"); diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 6036333..22c0c54 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -19,6 +19,7 @@ #include <asm/io.h> #include <asm/cache.h> #include <asm/mmu.h> +#include <asm/fsl_errata.h> #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> #include <asm/fsl_srio.h> @@ -160,6 +161,12 @@ static void enable_cpc(void) #ifdef CONFIG_SYS_FSL_ERRATUM_A006593 setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21)); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A006379 + if (has_erratum_a006379()) { + setbits_be32(&cpc->cpchdbcr0, + CPC_HDBCR0_SPLRU_LEVEL_EN); + } +#endif out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE); /* Read back to sync write */ diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index bec8966..6986ade 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -593,6 +593,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A004468 #define CONFIG_SYS_FSL_ERRATUM_A_004934 #define CONFIG_SYS_FSL_ERRATUM_A005871 +#define CONFIG_SYS_FSL_ERRATUM_A006379 #define CONFIG_SYS_FSL_ERRATUM_A006593 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_PCI_VER_3_X @@ -617,6 +618,7 @@ #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_ERRATUM_A_004934 #define CONFIG_SYS_FSL_ERRATUM_A005871 +#define CONFIG_SYS_FSL_ERRATUM_A006379 #define CONFIG_SYS_FSL_ERRATUM_A006593 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 diff --git a/arch/powerpc/include/asm/fsl_errata.h b/arch/powerpc/include/asm/fsl_errata.h new file mode 100644 index 0000000..780dfcf --- /dev/null +++ b/arch/powerpc/include/asm/fsl_errata.h @@ -0,0 +1,24 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_FSL_ERRATA_H +#define _ASM_FSL_ERRATA_H + +#include <common.h> + +#ifdef CONFIG_SYS_FSL_ERRATUM_A006379 +static inline bool has_erratum_a006379(void) +{ + u32 svr = get_svr(); + if (((SVR_SOC_VER(svr) == SVR_T4240) && SVR_MAJ(svr) <= 1) || + ((SVR_SOC_VER(svr) == SVR_B4860) && SVR_MAJ(svr) <= 2)) + return true; + + return false; +} +#endif + +#endif diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 3a10d77..a938143 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1671,6 +1671,7 @@ typedef struct cpc_corenet { #define CPC_HDBCR0_CDQ_SPEC_DIS 0x08000000 #define CPC_HDBCR0_TAG_ECC_SCRUB_DIS 0x01000000 #define CPC_HDBCR0_DATA_ECC_SCRUB_DIS 0x00400000 +#define CPC_HDBCR0_SPLRU_LEVEL_EN 0x003c0000 #endif /* CONFIG_SYS_FSL_CPC */ /* Global Utilities Block */ -- 1.7.9.5

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[U-Boot] [PATCH v2] doc: README.mxs: Add instruction to install 'libssl-dev'
by Fabio Estevam 16 Sep '13

16 Sep '13

From: Fabio Estevam <fabio.estevam(a)freescale.com> Since commit bce883707 (ARM: mxs: tools: Add mkimage support for MXS bootstream) the following build error is seen when doing a MAKEALL build: $ ./MAKEALL mx28evk Configuring for mx28evk - Board: mx28evk, Options: ENV_IS_IN_MMC mxsimage.c:18:25: fatal error: openssl/evp.h: No such file or directory Add an entry about the need of installing the 'libssl-dev' package. Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- Changes since v1: - Do not remove the 'elftosb' text. doc/README.mxs | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/doc/README.mxs b/doc/README.mxs index 5d9e72f..1e5bc5c 100644 --- a/doc/README.mxs +++ b/doc/README.mxs @@ -63,6 +63,11 @@ copy the binary by hand: Make sure the "elftosb" binary can be found in your $PATH, in this case this means "/usr/local/bin/" has to be in your $PATH. +Install the 'libssl-dev' package as well. On a Ubuntu-based distribution, this +package can be installed as follows: + + $ sudo apt-get install libssl-dev + 2) Compiling U-Boot for a MXS based board ------------------------------------------- -- 1.8.1.2

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[U-Boot] [PATCH] mmc:sdhci: Fix card ready status timeout.
by Przemyslaw Marczak 16 Sep '13

16 Sep '13

According to JEDEC eMMC specification, after data transfer (multiple or single block) host must wait for card ready status. This is done by waiting for command and data lines to be at idle state after transfer. JEDEC does not specify maximum timeout. Before this change max timeout was 10 ms but in case of UMS - when system does multiple read/write operations on random card blocks - timeout causes I/O errors. The timeout has been increased to 200ms after data transfer. For other transfers it stays unchanged. Tested on Goni and Trats. Signed-off-by: Przemyslaw Marczak <p.marczak(a)samsung.com> Cc: Pantelis Antoniou <panto(a)antoniou-consulting.com> --- drivers/mmc/sdhci.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index 4261991..c495482 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -121,8 +121,18 @@ int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, unsigned int timeout, start_addr = 0; unsigned int retry = 10000; - /* Wait max 10 ms */ - timeout = 10; + /* + * For some commands this function is called with NULL mmc_data + * pointer. One of those is CMD13 - send card status. + * After read/write data transfer or block erase commands - host sends + * CMD13 and is waiting for card ready status with some timeout. + * According to some internal cards operations after those commands + * this time must be increased. + */ + if (data) + timeout = 10; /* ms */ + else + timeout = 200; sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS); mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT; -- 1.7.9.5

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[U-Boot] [RFC 3/5] common/env: Point default envirenoment for GD
by Prabhakar Kushwaha 16 Sep '13

16 Sep '13

GD(Global Data) structure has pointer to envirenoment variable array. but, it is not being assigned for SPL framwork. So update GD pointer with env variable array. Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- common/env_common.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/common/env_common.c b/common/env_common.c index 1ac3377..84843e1 100644 --- a/common/env_common.c +++ b/common/env_common.c @@ -162,6 +162,9 @@ int env_import(const char *buf, int check) if (himport_r(&env_htab, (char *)ep->data, ENV_SIZE, '\0', 0, 0, NULL)) { gd->flags |= GD_FLG_ENV_READY; +#ifdef CONFIG_SPL_BUILD + gd->env_addr = ep->data; +#endif return 1; } -- 1.7.9.5

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[U-Boot] [RFC 2/5] powerpc/SPL:Allow Parsing of LAW table in both SPL & non SPL
by Prabhakar Kushwaha 16 Sep '13

16 Sep '13

SPL does not relocates the CCSRBAR hence it is using CCSRBAR at 0xfe00_0000. U-boot relocates CCSRBAR to 0xf_fe00_0000. So law talbe needs to be updated again. Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- arch/powerpc/cpu/mpc8xxx/law.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/arch/powerpc/cpu/mpc8xxx/law.c b/arch/powerpc/cpu/mpc8xxx/law.c index a401083..d76ba22 100644 --- a/arch/powerpc/cpu/mpc8xxx/law.c +++ b/arch/powerpc/cpu/mpc8xxx/law.c @@ -244,15 +244,6 @@ void init_laws(void) gd->arch.used_laws |= (1 << i); } -#if (defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)) || \ - (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)) - /* - * in SPL boot we've already parsed the law_table and setup those LAWs - * so don't do it again. - */ - return; -#endif - for (i = 0; i < num_law_entries; i++) { if (law_table[i].index == -1) set_next_law(law_table[i].addr, law_table[i].size, -- 1.7.9.5

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[U-Boot] [RFC 1/5] powerpc:Add support of SPL non-relocation
by Prabhakar Kushwaha 16 Sep '13

16 Sep '13

Current SPL code base has BSS section placed after reset_vector. This means they have to relocate to use the global variables. This put an implicit requirement of having SPL size = Memory/2. To avoid relocation, move bss_section within SPL range. Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- arch/powerpc/cpu/mpc85xx/u-boot-spl.lds | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds index bc13267..ffc6ad3 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds @@ -57,13 +57,34 @@ SECTIONS . = ALIGN(8); __init_begin = .; __init_end = .; +#ifdef CONFIG_SKIP_RELOCATE_SPL + /* + * Make sure that the bss segment isn't linked at 0x0, otherwise its + * address won't be updated during relocation fixups. + */ + . |= 0x10; + + . = ALIGN(4); + __bss_start = .; + .bss : { + *(.sbss*) + *(.bss*) + } + . = ALIGN(4); + __bss_end = .; +#endif /* FIXME for non-NAND SPL */ #if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */ - .bootpg ADDR(.text) + 0x1000 : +#ifndef BOOT_PAGE_OFFSET +#define BOOT_PAGE_OFFSET 0x1000 +#endif + .bootpg ADDR(.text) + BOOT_PAGE_OFFSET : { arch/powerpc/cpu/mpc85xx/start.o (.bootpg) } +#ifndef RESET_VECTOR_OFFSET #define RESET_VECTOR_OFFSET 0x1ffc /* IFC has 8K sram */ +#endif #elif defined(CONFIG_FSL_ELBC) #define RESET_VECTOR_OFFSET 0xffc /* LBC has 4k sram */ #else @@ -80,6 +101,7 @@ SECTIONS } = 0xffff #endif +#ifndef CONFIG_SKIP_RELOCATE_SPL /* * Make sure that the bss segment isn't linked at 0x0, otherwise its * address won't be updated during relocation fixups. @@ -94,4 +116,5 @@ SECTIONS } . = ALIGN(4); __bss_end = .; +#endif } -- 1.7.9.5

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[U-Boot] *** [u-boot] Error 139 when config NAND relative setting
by Hsin-Hsiang Tseng 16 Sep '13

16 Sep '13

Hello, nice to meet everyone. I am new to U-boot development world. i have a s5pv310 soc dk board, and i config. it as origen board. i want to use nand command in u-boot, so i add blow setting in origen.h /*enable nand command*/ #define CONFIG_CMD_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_MAX_CHIPS 1 #define CONFIG_SYS_NAND_SELF_INIT #define CONFIG_SYS_NAND_BASE 0x0CE00000 but i got error message about ***[U-boot] Error 139. After searched some solution, some said that Error 139 is the cross compile version is too low. but my cross compile is gcc-arm-none-eabi-4_6-2012q2, i think it is not the version problem. without the nand relative config before i could build u-boot without any problem. could somebody give me some points to fix this error. thanks. ps. i don't know if i could consult building problem here. If u-boot mail-list is not proper to receive building problem please let me know. thanks again. drivers/mtd/nand/libnand.o: In function `nand_init': /usr/v310/uboot_linaro/u-boot-linaro/drivers/mtd/nand/nand.c:104: undefined reference to `board_nand_init' /usr/v310/toolchain/gcc-arm-none-eabi-4_6-2012q2/bin/arm-none-eabi-ld.bfd: BFD (GNU Tools for ARM Embedded Processors) 2.21.1.20120613 assertion fail /home/build/work/jenkins-daily-build/src/binutils/bfd/elf32-arm.c:12274 /usr/v310/toolchain/gcc-arm-none-eabi-4_6-2012q2/bin/arm-none-eabi-ld.bfd: BFD (GNU Tools for ARM Embedded Processors) 2.21.1.20120613 assertion fail /home/build/work/jenkins-daily-build/src/binutils/bfd/elf32-arm.c:12511 /bin/bash: line 1: 3818 Segmentation fault /usr/v310/toolchain/gcc-arm-none-eabi-4_6-2012q2/bin/arm-none-eabi-ld.bfd -pie -T u-boot.lds -Bstatic -Ttext 0x43E00000 $UNDEF_LST arch/arm/cpu/armv7/start.o --start-group api/libapi.o arch/arm/cpu/armv7/exynos/libexynos.o arch/arm/cpu/armv7/libarmv7.o arch/arm/cpu/armv7/s5p-common/libs5p-common.o arch/arm/lib/libarm.o board/samsung/common/libsamsung.o common/libcommon.o disk/libdisk.o drivers/bios_emulator/libatibiosemu.o drivers/block/libblock.o drivers/dfu/libdfu.o drivers/dma/libdma.o drivers/fpga/libfpga.o drivers/gpio/libgpio.o drivers/hwmon/libhwmon.o drivers/i2c/libi2c.o drivers/input/libinput.o drivers/misc/libmisc.o drivers/mmc/libmmc.o drivers/mtd/libmtd.o drivers/mtd/nand/libnand.o drivers/mtd/onenand/libonenand.o drivers/mtd/spi/libspi_flash.o drivers/mtd/ubi/libubi.o drivers/net/libnet.o drivers/net/phy/libphy.o drivers/pci/libpci.o drivers/pcmcia/libpcmcia.o drivers/power/libpower.o drivers/rtc/librtc.o drivers/serial/libserial.o drivers/spi/libspi.o drivers/twserial/libtws.o drivers/usb/eth/libusb_eth.o drivers/usb/gadget/libusb_gadget.o drivers/usb/host/libusb_host.o drivers/usb/musb/libusb_musb.o drivers/usb/phy/libusb_phy.o drivers/usb/ulpi/libusb_ulpi.o drivers/video/libvideo.o drivers/watchdog/libwatchdog.o fs/cbfs/libcbfs.o fs/cramfs/libcramfs.o fs/ext4/libext4fs.o fs/fat/libfat.o fs/fdos/libfdos.o fs/jffs2/libjffs2.o fs/libfs.o fs/reiserfs/libreiserfs.o fs/ubifs/libubifs.o fs/yaffs2/libyaffs2.o fs/zfs/libzfs.o lib/libfdt/libfdt.o lib/libgeneric.o lib/lzma/liblzma.o lib/lzo/liblzo.o lib/zlib/libz.o net/libnet.o post/libpost.o test/libtest.o board/samsung/origen/liborigen.o --end-group /usr/v310/uboot_linaro/u-boot-linaro/arch/arm/lib/eabi_compat.o -L /usr/v310/toolchain/gcc-arm-none-eabi-4_6-2012q2/bin/../lib/gcc/arm-none-eabi/4.6.2 -lgcc -Map u-boot.map -o u-boot make[1]: *** [u-boot] Error 139

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[U-Boot] worth correcting spelling of "redundand"?
by Robert P. J. Day 16 Sep '13

16 Sep '13

again, my pedantry getting the best of me but it makes me cringe whenever i run across the spelling "redundand" (tree-wide search): common/env_ubi.c:#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT common/env_ubi.c:#else /* ! CONFIG_SYS_REDUNDAND_ENVIRONMENT */ common/env_ubi.c:#endif /* CONFIG_SYS_REDUNDAND_ENVIRONMENT */ common/env_ubi.c:#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT common/env_ubi.c:#else /* ! CONFIG_SYS_REDUNDAND_ENVIRONMENT */ common/env_ubi.c:#endif /* CONFIG_SYS_REDUNDAND_ENVIRONMENT */ common/env_embedded.c:env_t redundand_environment __PPCENV__ = { include/environment.h:# define CONFIG_SYS_REDUNDAND_ENVIRONMENT include/environment.h:# define CONFIG_SYS_REDUNDAND_ENVIRONMENT include/environment.h:# define CONFIG_SYS_REDUNDAND_ENVIRONMENT include/environment.h:# define CONFIG_SYS_REDUNDAND_ENVIRONMENT include/environment.h:#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT include/environment.h:#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT include/env_default.h:#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT include/configs/G2000.h:#else /* DEFAULT: environment in flash, using redundand flash sectors */ include/configs/km/km_arm.h:#define CONFIG_SYS_REDUNDAND_ENVIRONMENT include/configs/PPChameleonEVB.h:#else /* DEFAULT: environment in flash, using redundand flash sectors */ include/configs/mx28evk.h:#define CONFIG_SYS_REDUNDAND_ENVIRONMENT include/configs/am335x_evm.h:#define CONFIG_SYS_REDUNDAND_ENVIRONMENT include/configs/omap5_uevm.h:#define CONFIG_SYS_REDUNDAND_ENVIRONMENT include/configs/igep0033.h:#define CONFIG_SYS_REDUNDAND_ENVIRONMENT tools/envcrc.c:# define CONFIG_SYS_REDUNDAND_ENVIRONMENT tools/envcrc.c:#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT this obviously isn't a cosmetic change as it's used in numerous #defines, but if it's done all at once, it should be safe. i can submit a patch unless people feel it's simply too disruptive. rday -- ======================================================================== Robert P. J. Day Ottawa, Ontario, CANADA http://crashcourse.ca Twitter: http://twitter.com/rpjday LinkedIn: http://ca.linkedin.com/in/rpjday ========================================================================

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[U-Boot] [PATCH] Cosmetic: Fix a number of typoes, no functional changes.
by Robert P. J. Day 16 Sep '13

16 Sep '13

Fix various misspellings of things like "environment", "kernel", "default" and "volatile", and throw in a couple grammar fixes. Signed-off-by: Robert P. J. Day <rpjday(a)crashcourse.ca> --- diff --git a/Makefile b/Makefile index 1365db6..f55f8c0 100644 --- a/Makefile +++ b/Makefile @@ -45,13 +45,13 @@ endif ######################################################################### # -# U-boot build supports producing a object files to the separate external +# U-boot build supports generating object files in a separate external # directory. Two use cases are supported: # # 1) Add O= to the make command line # 'make O=/tmp/build all' # -# 2) Set environement variable BUILD_DIR to point to the desired location +# 2) Set environment variable BUILD_DIR to point to the desired location # 'export BUILD_DIR=/tmp/build' # 'make' # @@ -59,7 +59,7 @@ endif # 'export BUILD_DIR=/tmp/build' # './MAKEALL' # -# Command line 'O=' setting overrides BUILD_DIR environent variable. +# Command line 'O=' setting overrides BUILD_DIR environment variable. # # When none of the above methods is used the local build is performed and # the object files are placed in the source directory. diff --git a/README b/README index ccd47fa..13e3ac0 100644 --- a/README +++ b/README @@ -3360,7 +3360,7 @@ Configuration Settings: the Linux kernel; all data that must be processed by the Linux kernel (bd_info, boot arguments, FDT blob if used) must be put below this limit, unless "bootm_low" - enviroment variable is defined and non-zero. In such case + environment variable is defined and non-zero. In such case all data for the Linux kernel must be between "bootm_low" and "bootm_low" + CONFIG_SYS_BOOTMAPSZ. The environment variable "bootm_mapsize" will override the value of @@ -3473,7 +3473,7 @@ Configuration Settings: - CONFIG_ENV_FLAGS_LIST_DEFAULT - CONFIG_ENV_FLAGS_LIST_STATIC - Enable validation of the values given to enviroment variables when + Enable validation of the values given to environment variables when calling env set. Variables can be restricted to only decimal, hexadecimal, or boolean. If CONFIG_CMD_NET is also defined, the variables can also be restricted to IP address or MAC address. diff --git a/arch/arm/cpu/arm926ejs/at91/eflash.c b/arch/arm/cpu/arm926ejs/at91/eflash.c index 3e21cdb..3f39264 100644 --- a/arch/arm/cpu/arm926ejs/at91/eflash.c +++ b/arch/arm/cpu/arm926ejs/at91/eflash.c @@ -28,7 +28,7 @@ * by u-Boot commands. * * Note: Redundant environment will not work in this flash since - * it does use partial page writes. Make sure the environent spans + * it does use partial page writes. Make sure the environment spans * whole pages! */ diff --git a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c index cde3172..d4711c0 100644 --- a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c +++ b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c @@ -302,7 +302,7 @@ int arch_cpu_init(void) /* * Configures the I/O voltage of the pads connected to Egigabit * Ethernet interface to 1.8V - * By defult it is set to 3.3V + * By default it is set to 3.3V */ reg = readl(KW_REG_MPP_OUT_DRV_REG); reg |= (1 << 7); diff --git a/board/RPXlite_dw/README b/board/RPXlite_dw/README index 14296b2..9e2d0f4 100644 --- a/board/RPXlite_dw/README +++ b/board/RPXlite_dw/README @@ -87,9 +87,9 @@ u-boot> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -A word on the U-Boot enviroment variable setting and usage : +A word on the U-Boot environment variable setting and usage : -In the beginning, you could just need very simple defult environment variable setting, +In the beginning, you could just need very simple default environment variable setting, like[include/configs/RPXlite.h] : #define CONFIG_BOOTCOMMAND \ diff --git a/board/freescale/mx28evk/README b/board/freescale/mx28evk/README index 524f3fc..0389a1d 100644 --- a/board/freescale/mx28evk/README +++ b/board/freescale/mx28evk/README @@ -29,11 +29,11 @@ Environment Storage There are two targets for mx28evk: -"make mx28evk_config" - store enviroment variables into MMC +"make mx28evk_config" - store environment variables into MMC or -"make mx28evk_nand_config" - store enviroment variables into NAND flash +"make mx28evk_nand_config" - store environment variables into NAND flash Choose the target accordingly. diff --git a/board/sbc8349/README b/board/sbc8349/README index 2c35919..e2d60cc 100644 --- a/board/sbc8349/README +++ b/board/sbc8349/README @@ -50,7 +50,7 @@ is a summary of that information: trying to preserve your old environment settings and user flash). - Set the start address of the erase/flash process to FF80_0000 - Set the target RAM required to 64kB. - - Select sectors for erasing (see note on enviroment below) + - Select sectors for erasing (see note on environment below) - Select Erase and Reprogram. Note that some versions of the register files used with Workbench diff --git a/common/image.c b/common/image.c index 2c88091..802a79e 100644 --- a/common/image.c +++ b/common/image.c @@ -965,7 +965,7 @@ int boot_get_ramdisk(int argc, char * const argv[], bootm_headers_t *images, * @initrd_end: pointer to a ulong variable, will hold final init ramdisk * end address (after possible relocation) * - * boot_ramdisk_high() takes a relocation hint from "initrd_high" environement + * boot_ramdisk_high() takes a relocation hint from "initrd_high" environment * variable and if requested ramdisk data is moved to a specified location. * * Initrd_start and initrd_end are set to final (after relocation) ramdisk diff --git a/doc/README.hwconfig b/doc/README.hwconfig index cf54965..b6ddb43 100644 --- a/doc/README.hwconfig +++ b/doc/README.hwconfig @@ -18,7 +18,7 @@ Current implementation details/limitations: U-Boot. But I haven't bothered yet. 2. Since we don't implement a hwconfig command, i.e. we're working - with the environement directly, there is no way to tell that + with the environment directly, there is no way to tell that toggling a particular option will need a reboot to take effect. So, for now it's advised to always reboot the target after modifying the hwconfig variable. diff --git a/drivers/net/phy/smsc.c b/drivers/net/phy/smsc.c index 5936f9b..60ed92d 100644 --- a/drivers/net/phy/smsc.c +++ b/drivers/net/phy/smsc.c @@ -7,7 +7,7 @@ * Copyright 2010-2011 Freescale Semiconductor, Inc. * author Andy Fleming * - * Some code get from linux kenrel + * Some code copied from linux kernel * Copyright (c) 2006 Herbert Valerio Riedel <hvr(a)gnu.org> */ #include <miiphy.h> diff --git a/examples/standalone/README.smc91111_eeprom b/examples/standalone/README.smc91111_eeprom index 28e7e69..a2d52e7 100644 --- a/examples/standalone/README.smc91111_eeprom +++ b/examples/standalone/README.smc91111_eeprom @@ -154,10 +154,10 @@ The MAC address can be stored in four locations: -Boot environmental variable in Flash <- can not change, without re-flashing U-boot. -U-Boot environental variable <- can not change, without +U-Boot environmental variable <- can not change, without resetting board/U-Boot -LAN91C111 Registers <- volitle -LAN91C111 EEPROM <- Non Volitle +LAN91C111 Registers <- volatile +LAN91C111 EEPROM <- Non-volatile If you have not activated the network, and do not have a hardcoded or pre-assigned MAC address in U-boot, the environmental variables diff --git a/include/common.h b/include/common.h index 8addf43..6aa2398 100644 --- a/include/common.h +++ b/include/common.h @@ -383,7 +383,7 @@ int setenv_hex(const char *varname, ulong value); /** * setenv_addr - Set an environment variable to an address in hex * - * @varname: Environmet variable to set + * @varname: Environment variable to set * @addr: Value to set it to * @return 0 if ok, 1 on error */ diff --git a/include/configs/eXalion.h b/include/configs/eXalion.h index c2d04a2..7321b60 100644 --- a/include/configs/eXalion.h +++ b/include/configs/eXalion.h @@ -119,7 +119,7 @@ #define CONFIG_ENV_IS_IN_FLASH 1 #define CONFIG_ENV_SECT_SIZE 0x20000 /* Size of one Flash sector */ -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE /* Use one Flash sector for enviroment */ +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE /* Use one Flash sector for environment */ #define CONFIG_ENV_ADDR 0xFFFC0000 #define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */ diff --git a/include/configs/sacsng.h b/include/configs/sacsng.h index d63d0c4..0feef1e 100644 --- a/include/configs/sacsng.h +++ b/include/configs/sacsng.h @@ -305,7 +305,7 @@ #define CONFIG_ENV_IN_OWN_SECT 1 /* Define this to contain any number of null terminated strings that - * will be part of the default enviroment compiled into the boot image. + * will be part of the default environment compiled into the boot image. */ #define CONFIG_EXTRA_ENV_SETTINGS \ "quiet=0\0" \ diff --git a/lib/hashtable.c b/lib/hashtable.c index 644330a..c5a2b08 100644 --- a/lib/hashtable.c +++ b/lib/hashtable.c @@ -817,7 +817,7 @@ int himport_r(struct hsearch_data *htab, * size of 8 per entry (= safety factor of ~5) should provide enough * safety margin for any existing environment definitions and still * allow for more than enough dynamic additions. Note that the - * "size" argument is supposed to give the maximum enviroment size + * "size" argument is supposed to give the maximum environment size * (CONFIG_ENV_SIZE). This heuristics will result in * unreasonably large numbers (and thus memory footprint) for * big flash environments (>8,000 entries for 64 KB diff --git a/post/board/lwmon5/sysmon.c b/post/board/lwmon5/sysmon.c index da37d66..cca1a26 100644 --- a/post/board/lwmon5/sysmon.c +++ b/post/board/lwmon5/sysmon.c @@ -22,7 +22,7 @@ * * LCD backlight is not enabled if temperature values are not within * allowed ranges (-30 .. + 80). The brightness of backlite can be - * controlled by setting "brightness" enviroment variable. Default value is 50% + * controlled by setting "brightness" environment variable. Default value is 50% * * See the list of all parameters in the sysmon_table below */ -- ======================================================================== Robert P. J. Day Ottawa, Ontario, CANADA http://crashcourse.ca Twitter: http://twitter.com/rpjday LinkedIn: http://ca.linkedin.com/in/rpjday ========================================================================

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[U-Boot] [PATCH] PCIe:change the method to get the address of a requested capability in configuration space.
by Zhao Qiang 16 Sep '13

16 Sep '13

Previously, the address of a requested capability is define like that "#define PCI_DCR 0x78" But, the addresses of capabilities is different with regard to PCIe revs. So this method is not flexible. Now a function to get the address of a requested capability is added and used. It can get the address dynamically by capability ID. The step of this function: 1. Read Status register in PCIe configuration space to confirm that Capabilities List is valid. 2. Find the address of Capabilities Pointer Register. 3. Find the address of requested capability from the first capability. Signed-off-by: Zhao Qiang <B45475(a)freescale.com> --- arch/powerpc/include/asm/fsl_pci.h | 13 +------- drivers/pci/fsl_pci_init.c | 44 +++++++++++++++++++------- drivers/pci/pci.c | 65 ++++++++++++++++++++++++++++++++++++++ include/pci.h | 10 ++++++ 4 files changed, 108 insertions(+), 24 deletions(-) diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h index 90b0a2f..6b12afa 100644 --- a/arch/powerpc/include/asm/fsl_pci.h +++ b/arch/powerpc/include/asm/fsl_pci.h @@ -32,22 +32,11 @@ /* Freescale-specific PCI config registers */ #define FSL_PCI_PBFR 0x44 -#ifdef CONFIG_SYS_FSL_PCI_VER_3_X +#ifndef CONFIG_SYS_FSL_PCI_VER_3_X /* Currently only the PCIe capability is used, so hardcode the offset. * if more capabilities need to be justified, the capability link method * should be applied here */ -#define FSL_PCIE_CAP_ID 0x70 -#define PCI_DCR 0x78 /* PCIe Device Control Register */ -#define PCI_DSR 0x7a /* PCIe Device Status Register */ -#define PCI_LSR 0x82 /* PCIe Link Status Register */ -#define PCI_LCR 0x80 /* PCIe Link Control Register */ -#else -#define FSL_PCIE_CAP_ID 0x4c -#define PCI_DCR 0x54 /* PCIe Device Control Register */ -#define PCI_DSR 0x56 /* PCIe Device Status Register */ -#define PCI_LSR 0x5e /* PCIe Link Status Register */ -#define PCI_LCR 0x5c /* PCIe Link Control Register */ #define FSL_PCIE_CFG_RDY 0x4b0 #endif #define FSL_PCI_CFG_READY 1 /* Endpoint: allow inbound configuration */ diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 76337fe..492efcf 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -308,6 +308,15 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) int enabled, r, inbound = 0; u16 ltssm; u8 temp8, pcie_cap; + int pcie_cap_pos; + int pci_dcr; + int pci_dsr; + int pci_lsr; + +#if defined(CONFIG_FSL_PCIE_DISABLE_ASPM) + int pci_lcr; +#endif + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr; struct pci_region *reg = hose->regions + hose->region_count; pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0); @@ -380,7 +389,12 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) hose->region_count++; /* see if we are a PCIe or PCI controller */ - pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap); + pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP); + pci_dcr = pcie_cap_pos + 0x08; + pci_dsr = pcie_cap_pos + 0x0a; + pci_lsr = pcie_cap_pos + 0x12; + + pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap); #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER /* boot from PCIE --master */ @@ -419,15 +433,16 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) * - Master PERR (pci) * - ICCA (PCIe) */ - pci_hose_read_config_dword(hose, dev, PCI_DCR, &temp32); + pci_hose_read_config_dword(hose, dev, pci_dcr, &temp32); temp32 |= 0xf000e; /* set URR, FER, NFER (but not CER) */ - pci_hose_write_config_dword(hose, dev, PCI_DCR, temp32); + pci_hose_write_config_dword(hose, dev, pci_dcr, temp32); #if defined(CONFIG_FSL_PCIE_DISABLE_ASPM) + pci_lcr = pcie_cap_pos + 0x10; temp32 = 0; - pci_hose_read_config_dword(hose, dev, PCI_LCR, &temp32); + pci_hose_read_config_dword(hose, dev, pci_lcr, &temp32); temp32 &= ~0x03; /* Disable ASPM */ - pci_hose_write_config_dword(hose, dev, PCI_LCR, temp32); + pci_hose_write_config_dword(hose, dev, pci_lcr, temp32); udelay(1); #endif if (pcie_cap == PCI_CAP_ID_EXP) { @@ -507,7 +522,7 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) out_be32(&pci->pme_msg_int_en, 0xffffffff); /* Print the negotiated PCIe link width */ - pci_hose_read_config_word(hose, dev, PCI_LSR, &temp16); + pci_hose_read_config_word(hose, dev, pci_lsr, &temp16); printf("x%d, regs @ 0x%lx\n", (temp16 & 0x3f0 ) >> 4, pci_info->regs); @@ -554,9 +569,9 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) out_be32(&pci->pme_msg_det, 0xffffffff); out_be32(&pci->pedr, 0xffffffff); - pci_hose_read_config_word (hose, dev, PCI_DSR, &temp16); + pci_hose_read_config_word(hose, dev, pci_dsr, &temp16); if (temp16) { - pci_hose_write_config_word(hose, dev, PCI_DSR, 0xffff); + pci_hose_write_config_word(hose, dev, pci_dsr, 0xffff); } pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16); @@ -567,10 +582,12 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) int fsl_is_pci_agent(struct pci_controller *hose) { + int pcie_cap_pos; u8 pcie_cap; pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0); - pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap); + pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP); + pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap); if (pcie_cap == PCI_CAP_ID_EXP) { u8 header_type; @@ -595,6 +612,7 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info, volatile ccsr_fsl_pci_t *pci; struct pci_region *r; pci_dev_t dev = PCI_BDF(busno,0,0); + int pcie_cap_pos; u8 pcie_cap; pci = (ccsr_fsl_pci_t *) pci_info->regs; @@ -644,7 +662,8 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info, #endif } - pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap); + pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP); + pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap); printf("PCI%s%x: Bus %02x - %02x\n", pcie_cap == PCI_CAP_ID_EXP ? "e" : "", pci_info->pci_num, hose->first_busno, hose->last_busno); @@ -656,13 +675,14 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info, void fsl_pci_config_unlock(struct pci_controller *hose) { pci_dev_t dev = PCI_BDF(hose->first_busno,0,0); + int pcie_cap_pos; u8 pcie_cap; u16 pbfr; if (!fsl_is_pci_agent(hose)) return; - - pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap); + pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP); + pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap); if (pcie_cap != 0x0) { /* PCIe - set CFG_READY bit of Configuration Ready Register */ #ifdef CONFIG_SYS_FSL_PCI_VER_3_X diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index d864f13..c57ea6f 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -738,3 +738,68 @@ void pci_init(void) /* now call board specific pci_init()... */ pci_init_board(); } + +/* Returns the address of the requested capability structure within the + * device's PCI configuration space or 0 in case the device does not + * support it. + * */ +int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev, + int cap) +{ + int pos; + u8 hdr_type; + + pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &hdr_type); + + pos = pci_hose_find_cap_start(hose, dev, hdr_type & 0x7F); + + if (pos) + pos = pci_find_cap(hose, dev, pos, cap); + + return pos; +} + +/* Find the header pointer to the Capabilities*/ +int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev, + u8 hdr_type) +{ + u16 status; + + pci_hose_read_config_word(hose, dev, PCI_STATUS, &status); + + if (!(status & PCI_STATUS_CAP_LIST)) + return 0; + + switch (hdr_type) { + case PCI_HEADER_TYPE_NORMAL: + case PCI_HEADER_TYPE_BRIDGE: + return PCI_CAPABILITY_LIST; + case PCI_HEADER_TYPE_CARDBUS: + return PCI_CB_CAPABILITY_LIST; + default: + return 0; + } +} + +int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, int cap) +{ + int ttl = PCI_FIND_CAP_TTL; + u8 id; + u8 next_pos; + + while (ttl--) { + pci_hose_read_config_byte(hose, dev, pos, &next_pos); + if (next_pos < CAP_START_POS) + break; + next_pos &= ~3; + pos = (int) next_pos; + pci_hose_read_config_byte(hose, dev, + pos + PCI_CAP_LIST_ID, &id); + if (id == 0xff) + break; + if (id == cap) + return pos; + pos += PCI_CAP_LIST_NEXT; + } + return 0; +} diff --git a/include/pci.h b/include/pci.h index 7e3b3b6..477835e 100644 --- a/include/pci.h +++ b/include/pci.h @@ -426,6 +426,9 @@ #define PCI_MAX_PCI_DEVICES 32 #define PCI_MAX_PCI_FUNCTIONS 8 +#define PCI_FIND_CAP_TTL 0x48 +#define CAP_START_POS 0x40 + /* Include the ID list */ #include <pci_ids.h> @@ -663,6 +666,13 @@ extern int pci_hose_config_device(struct pci_controller *hose, pci_addr_t mem, unsigned long command); +extern int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev, + int cap); +extern int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev, + u8 hdr_type); +extern int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, + int cap); + const char * pci_class_str(u8 class); int pci_last_busno(void); -- 1.8.0

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