September 2013 - U-Boot

Re: [U-Boot] [PATCH] arm: prevent using movt/movw address loads
by TigerLiu＠viatech.com.cn 17 Sep '13

17 Sep '13

Hi, experts: >The movt/movw instruction can be used to hardcode an >memory location in the instruction itself. The linker >starts complaining about this if the compiler decides >to do so: "relocation R_ARM_MOVW_ABS_NC against `a local >symbol' can not be used" and it is not support by U-boot >as well. Prevent their use by requiring word relocations. >This allows u-boot to be build at other optimalization >levels then -Os. Would this patch be included in 2013.10 release verion? So u-boot could be built at other optimalization levels than -Os. I tested 2013.10-rc2, but still failed to build by -O0 / -O1 etc. Best wishes,

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[U-Boot] [ANN] v2013.10-rc3
by Tom Rini 17 Sep '13

17 Sep '13

Hey all, I've put v2013.10-rc3 out and tarballs should be out soon. I wasn't able to get as much re-syncing done myself as I hoped as some other issue arose, but I'll get my own queue cleaned out, both for TI and for general bits in time for rc4. Please let us all know if something has stopped working. Thanks all! -- Tom

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[U-Boot] [PATCH 0/2] i2c: port i2c driver to new subsystem
by Philippe Reynes 17 Sep '13

17 Sep '13

This serie is composed of two patches: - one to port the i2c mxc driver to new subsystem - one to update all configurations with i2c mxc driver This serie was tested with success on armadeus apf27. Philippe Reynes (2): i2c: move to new subsystem i2c: update config using mxc driver to new subsystem README | 3 + arch/arm/cpu/armv7/mx5/clock.c | 2 +- arch/arm/cpu/armv7/mx6/clock.c | 2 +- arch/arm/imx-common/Makefile | 2 +- drivers/i2c/Makefile | 2 +- drivers/i2c/mxc_i2c.c | 109 +++++++++++++++++-------------------- include/configs/apf27.h | 5 +- include/configs/flea3.h | 6 +- include/configs/imx31_phycore.h | 6 +- include/configs/m53evk.h | 6 +- include/configs/mx25pdk.h | 6 +- include/configs/mx35pdk.h | 6 +- include/configs/mx53ard.h | 6 +- include/configs/mx53evk.h | 6 +- include/configs/mx53loco.h | 6 +- include/configs/mx53smd.h | 6 +- include/configs/mx6qsabreauto.h | 3 +- include/configs/nitrogen6x.h | 3 +- include/configs/titanium.h | 3 +- include/configs/vf610twr.h | 6 +- include/configs/woodburn_common.h | 6 +- 21 files changed, 98 insertions(+), 102 deletions(-) -- 1.7.4.4

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[U-Boot] Understanding uboot child Makefiles
by MJ embd 17 Sep '13

17 Sep '13

-- -mj

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[U-Boot] Pull request: u-boot-spi/master
by Jagannadha Sutradharudu Teki 17 Sep '13

17 Sep '13

Hi Tom, Small pull request, planning to send next bunch of request for next pull. Thanks, Jagan. The following changes since commit 2b26201a2aef0b310b7c04702b0dba5dea493f77: env_nand.c: support falling back to redundant env when writing (2013-08-22 17:49:47 -0500) are available in the git repository at: git://git.denx.de/u-boot-spi.git master for you to fetch changes up to b95f958d7d06b3cd117647b29b288cf168aa2ee9: cmd_sf: let "sf update" preserve the final part of the last sector (2013-08-27 19:39:39 +0530) ---------------------------------------------------------------- Gerlando Falauto (1): cmd_sf: let "sf update" preserve the final part of the last sector Marek Vasut (1): spi: mxs_spi: Configure chipselect after block reset common/cmd_sf.c | 13 ++++++++++++- drivers/spi/mxs_spi.c | 12 +++--------- 2 files changed, 15 insertions(+), 10 deletions(-)

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[U-Boot] [PATCH v3 09/28] sf: probe: Add support for SST25* flash parts
by Jagannadha Sutradharudu Teki 17 Sep '13

17 Sep '13

Added SST25* parts are which are avilable in spi_flash_probe_legacy.c. Updated the sector_size attributes as per the flash parts. Looks fine for with this sector_size for computing the size of flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> --- Changes for v3: - none Changes for v2: - Enable CONFIG_SPI_FLASH_SST drivers/mtd/spi/spi_flash_probe.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi/spi_flash_probe.c b/drivers/mtd/spi/spi_flash_probe.c index 6f0dd84..62c9d0a 100644 --- a/drivers/mtd/spi/spi_flash_probe.c +++ b/drivers/mtd/spi/spi_flash_probe.c @@ -88,6 +88,18 @@ static const struct spi_flash_params spi_flash_params_table[] = { {"N25Q1024", 0x20ba21, 0x0, 64 * 1024, 2048}, {"N25Q1024A", 0x20bb21, 0x0, 64 * 1024, 2048}, #endif +#ifdef CONFIG_SPI_FLASH_SST /* SST */ + {"SST25VF040B", 0xbf258d, 0x0, 64 * 1024, 8}, + {"SST25VF080B", 0xbf258e, 0x0, 64 * 1024, 16}, + {"SST25VF016B", 0xbf2541, 0x0, 64 * 1024, 32}, + {"SST25VF032B", 0xbf254a, 0x0, 64 * 1024, 64}, + {"SST25VF064C", 0xbf254b, 0x0, 64 * 1024, 128}, + {"SST25WF512", 0xbf2501, 0x0, 64 * 1024, 1}, + {"SST25WF010", 0xbf2502, 0x0, 64 * 1024, 2}, + {"SST25WF020", 0xbf2503, 0x0, 64 * 1024, 4}, + {"SST25WF040", 0xbf2504, 0x0, 64 * 1024, 8}, + {"SST25WF080", 0xbf2505, 0x0, 64 * 1024, 16}, +#endif #ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */ {"W25P80", 0xef2014, 0x0, 64 * 1024, 16}, {"W25P16", 0xef2015, 0x0, 64 * 1024, 32}, @@ -125,7 +137,6 @@ static const struct spi_flash_params spi_flash_params_table[] = { * TODO: * ATMEL * RAMTRON - * SST */ }; -- 1.8.3

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Re: [U-Boot] [PATCH v4 1/5] mtd: nand: omap: enable BCH ECC scheme using ELM for generic platform
by Gupta, Pekon 16 Sep '13

16 Sep '13

(apologies for multiple mails, but mails from my client were rejected due to some client configuration) > On Tue, 2013-09-03 at 11:26 +0530, Pekon Gupta wrote: > > diff --git a/doc/README.nand b/doc/README.nand > > index 913e9b5..f72f618 100644 > > --- a/doc/README.nand > > +++ b/doc/README.nand > > @@ -169,6 +169,19 @@ Configuration Options: > > Please convert your driver even if you don't need the extra > > flexibility, so that one day we can eliminate the old mechanism. > > > > + CONFIG_SYS_NAND_ONFI_DETECTION > > + Enables detection of ONFI compliant devices during probe. > > + And fetching device parameters flashed on device, by parsing > > + ONFI parameter page. > > I don't see this used anywhere in the patch (defined in config headers, > yes, but not ifdeffed). > > What does "DETECTION" add here, versus just CONFIG_NAND_ONFI? > > It should be CONFIG rather than CONFIG_SYS because it just controls > whether the support is built, not making an assertion about the > hardware, right? > This is not the new define, it was already there in generic code (nand_base.c) But not documented, so I documented it and enabled it for am33xx platform Please refer: $UBOOT/drivers/mtd/nand/nand_base.c It was added as part of following commit commit 0272c718ba69c60a9d719db6806971d98db98090 Author: Florian Fainelli <florian(a)openwrt.org> AuthorDate: 2011-02-25 > > > + CONFIG_SYS_NAND_ECCSCHEME > > + specifies which ECC scheme to use. > > Specifies it how? What are the possible values? > > If the answer involves "enum omap_ecc", then OMAP should be > somewhere in the name. > I wanted this define to be generic for all NAND drivers. Therefore CONFIG_SYS_ But I don't know how other drivers would use this. For AM335x its updated in Patch: [PATCH v5 5/5] board/ti/am335x/README: update for NAND boot Instead, should I make it more generic for all SoC ? like CONFIG_SYS_NAND_ECCSCHEME can take in following strings defining ECC scheme used by NAND driver in SPL boot: "ham1" - 1 bit hamming code "bch4" - 4-bit BCH ecc code "bch8" - 8-bit BCH ecc code "bch16" - 16-bit BCH ecc code > > +/** > > + * omap_select_ecc_scheme - configures driver for particular ecc-scheme > > + * @nand: NAND chip device structure > > + * @ecc_scheme: ecc scheme to configure > > + * @pagesize: number of main-area bytes per page of NAND device > > + * @oobsize: number of OOB/spare bytes per page of NAND device > > + */ [snip] > > + default: > > + debug("nand: error: ecc scheme not enabled or > supported\n"); > > + return -EINVAL; > > + } > > This will result in NAND_ECC_NONE and likely an eventual NULL pointer > dereference if a bad value is passed and the -EINVAL return path is > taken. > > OK, I now see that you've got the caller patching this up in the error > case, but that's awkward and error prone. > Sorry, din't understand your feedback here. omap_select_ecc_scheme() is common function which is used for - changing ECC scheme if 'nandecc' like utility is needed later - selecting ECC scheme during probe. This function populates all necessary fields in struct *nand_chip for nand driver to work. During probe (both SPL and u-boot), 'CONFIG_SYS_NAND_ECCSCHEME' is used to determine the ecc-scheme. 'default' statement protects the driver from any invalid or un-supported ECC scheme selected by user in his board file. So that driver probe cleanly exits probe instead of causing an exception. Can you please elaborate, what I'm missing here ? > > @@ -767,67 +811,41 @@ void omap_nand_switch_ecc(uint32_t hardware, > uint32_t eccstrength) > > { > > struct nand_chip *nand; > > struct mtd_info *mtd; > > + struct nand_bch_priv *bch; > > + int err = 0; > > > > if (nand_curr_device < 0 || > > nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE || > > !nand_info[nand_curr_device].name) { > > - printf("Error: Can't switch ecc, no devices available\n"); > > + printf("nand: error: no devices available\n"); > > return; > > } > > Why are you making the error message less specific? > There is already another error message in board_nand_init() which will be flagged when there is problem in selecting ECC. printf("nand: error: cannot select ecc scheme\n"); But thanks, you pointed out a bug, I should return -ENODEV here, Otherwise caller would not know that ecc-scheme could not be changed. > > diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h > > index a9b2714..2b01486 100644 > > --- a/include/configs/tricorder.h > > +++ b/include/configs/tricorder.h > > @@ -298,6 +298,8 @@ > > > > #define CONFIG_SYS_NAND_ECCSIZE 512 > > #define CONFIG_SYS_NAND_ECCBYTES 13 > > +#define CONFIG_SYS_NAND_ECCSCHEME 3 > > +#define CONFIG_SYS_NAND_ONFI_DETECTION > > What does 3 mean? Please use a symbolic name. > For AM335x this is updated in board/ti/am335x/README as part of following patch: [PATCH v5 5/5] board/ti/am335x/README: update for NAND boot but would it be better to use strings like "bch8" as mentioned above ? with regards, pekon

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Re: [U-Boot] [PATCH v4 1/5] mtd: nand: omap: enable BCH ECC scheme using ELM for generic platform
by Scott Wood 16 Sep '13

16 Sep '13

On Fri, 2013-09-13 at 07:02 +0000, Gupta, Pekon wrote: > (resending to u-boot maillist as previous mail was discarded by mailman > due to mail-encoding issue.) > > > On Tue, 2013-09-03 at 11:26 +0530, Pekon Gupta wrote: > > > diff --git a/doc/README.nand b/doc/README.nand > > > index 913e9b5..f72f618 100644 > > > --- a/doc/README.nand > > > +++ b/doc/README.nand > > > @@ -169,6 +169,19 @@ Configuration Options: > > > Please convert your driver even if you don't need the extra > > > flexibility, so that one day we can eliminate the old mechanism. > > > > > > + CONFIG_SYS_NAND_ONFI_DETECTION > > > + Enables detection of ONFI compliant devices during probe. > > > + And fetching device parameters flashed on device, by parsing > > > + ONFI parameter page. > > > > I don't see this used anywhere in the patch (defined in config headers, > > yes, but not ifdeffed). > > > > What does "DETECTION" add here, versus just CONFIG_NAND_ONFI? > > > > It should be CONFIG rather than CONFIG_SYS because it just controls > > whether the support is built, not making an assertion about the > > hardware, right? > > > This is not the new define, it was already there in generic code (nand_base.c) > But not documented, so I documented it and enabled it for am33xx platform > Please refer: $UBOOT/drivers/mtd/nand/nand_base.c > It was added as part of following commit > commit 0272c718ba69c60a9d719db6806971d98db98090 > Author: Florian Fainelli <florian(a)openwrt.org> > AuthorDate: 2011-02-25 Oops... I looked for it and didn't see it, but maybe I was looking at the Linux version or something similarly silly. > > > + CONFIG_BCH > > > + Enables software based BCH ECC algorithm present in lib/bch.c > > > + This is used by SoC platforms which do not have in-build hardware > > > + engine to calculate and correct BCH ECC. > > > > s/in-build/a built-in/ > > > > > + CONFIG_SYS_NAND_ECCSCHEME > > > + specifies which ECC scheme to use. > > > > Specifies it how? What are the possible values? > > > > If the answer involves "enum omap_ecc", then OMAP should be > > somewhere in the name. > > > This is generic define which can be used by all NAND drivers to specify > ECC scheme for SPL boot. Therefore CONFIG_SYS_ > How each device/driver will use it depends should be mentioned in > its board level document. For AM335x its updated in Patch: > [PATCH v5 5/5] board/ti/am335x/README: update for NAND boot > Do you want it to be made omap specific ? Yes, it should be omap specific. If the semantics are not generic I don't see the value in making the name be generic and splitting the documentation in two places. > > > +/** > > > + * omap_select_ecc_scheme - configures driver for particular ecc-scheme > > > + * @nand: NAND chip device structure > > > + * @ecc_scheme: ecc scheme to configure > > > + * @pagesize: number of main-area bytes per page of NAND device > > > + * @oobsize: number of OOB/spare bytes per page of NAND device > > > + */ > > > +static int omap_select_ecc_scheme(struct nand_chip *nand, int > > ecc_scheme, > > > + unsigned int pagesize, unsigned int oobsize) { > > > + struct nand_bch_priv *bch = nand->priv; > > > + struct nand_ecclayout *ecclayout = nand->ecc.layout; > > > + int i; > > > + > > > + /* Reset ecc interface */ > > > + nand->ecc.mode = NAND_ECC_NONE; > > > + nand->ecc.read_page = NULL; > > > + nand->ecc.write_page = NULL; > > > + nand->ecc.read_oob = NULL; > > > + nand->ecc.write_oob = NULL; > > > + nand->ecc.hwctl = NULL; > > > + nand->ecc.correct = NULL; > > > + nand->ecc.calculate = NULL; > > > + > > > + switch (ecc_scheme) { > > > + case OMAP_ECC_HAM1_CODE_SW: > > > + debug("nand: selected OMAP_ECC_HAM1_CODE_SW\n"); > > > + nand->ecc.mode = NAND_ECC_SOFT; > > > + nand->ecc.layout = NULL; > > > + nand->ecc.size = 0; > > > + nand->ecc.strength = 1; > > > + bch->ecc_scheme = > > OMAP_ECC_HAM1_CODE_SW; > > > + break; > > > + case OMAP_ECC_HAM1_CODE_HW_ROMCODE: > > > + debug("nand: selected > > OMAP_ECC_HAM1_CODE_HW_ROMCODE\n"); > > > + nand->ecc.mode = NAND_ECC_HW; > > > + nand->ecc.strength = 1; > > > + nand->ecc.size = 512; > > > + nand->ecc.bytes = 3; > > > + nand->ecc.hwctl = omap_enable_hwecc; > > > + nand->ecc.correct = omap_correct_data; > > > + nand->ecc.calculate = omap_calculate_ecc; > > > + /* define ecc-layout */ > > > + ecclayout->eccbytes = nand->ecc.bytes * > > > + (pagesize / SECTOR_BYTES); > > > + for (i = 0; i < ecclayout->eccbytes; i++) > > > + ecclayout->eccpos[i] = i + > > > + > > BADBLOCK_MARKER_LENGTH; > > > + ecclayout->oobfree[0].offset = i + > > > + > > BADBLOCK_MARKER_LENGTH; > > > + ecclayout->oobfree[0].length = oobsize - nand->ecc.bytes - > > > + > > BADBLOCK_MARKER_LENGTH; > > > + bch->ecc_scheme = > > OMAP_ECC_HAM1_CODE_HW_ROMCODE; > > > + break; > > > +#ifdef CONFIG_BCH > > > + case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: > > > + debug("nand: selected > > OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n"); > > > + nand->ecc.mode = NAND_ECC_HW; > > > + nand->ecc.strength = 8; > > > + nand->ecc.size = 512; > > > + nand->ecc.bytes = 13; > > > + nand->ecc.hwctl = omap_enable_ecc_bch; > > > + nand->ecc.correct = omap_correct_data_bch_sw; > > > + nand->ecc.calculate = omap_calculate_ecc_bch_sw; > > > + /* BCH SW library is used for error detection */ > > > + bch_priv.control = init_bch(13, 8, 0x201b); > > > + if (!bch_priv.control) { > > > + printf("nand: error: could not init_bch()\n"); > > > + return -ENODEV; > > > + } > > > + /* define ecc-layout */ > > > + ecclayout->eccbytes = nand->ecc.bytes * > > > + (pagesize / SECTOR_BYTES); > > > + for (i = 0; i < ecclayout->eccbytes; i++) > > > + ecclayout->eccpos[i] = i + (oobsize - > > > + ecclayout->eccbytes); > > > + ecclayout->oobfree[0].offset = > > BADBLOCK_MARKER_LENGTH; > > > + ecclayout->oobfree[0].length = oobsize - nand->ecc.bytes - > > > + > > BADBLOCK_MARKER_LENGTH; > > > + omap_hwecc_init_bch(nand, NAND_ECC_READ); > > > + bch->ecc_scheme = > > OMAP_ECC_BCH8_CODE_HW_DETECTION_SW; > > > + break; > > > +#endif > > > + case OMAP_ECC_BCH8_CODE_HW: > > > + debug("nand: selected OMAP_ECC_BCH8_CODE_HW\n"); > > > + nand->ecc.mode = NAND_ECC_HW; > > > + nand->ecc.strength = 8; > > > + nand->ecc.size = 512; > > > + nand->ecc.bytes = 14; > > > + nand->ecc.hwctl = omap_enable_ecc_bch; > > > + nand->ecc.correct = omap_correct_data_bch; > > > + nand->ecc.calculate = omap_calculate_ecc_bch; > > > + /* ELM is used for ECC error detection */ > > > + elm_init(); > > > + /* define ecc-layout */ > > > + ecclayout->eccbytes = nand->ecc.bytes * > > > + (pagesize / SECTOR_BYTES); > > > + for (i = 0; i < ecclayout->eccbytes; i++) > > > + ecclayout->eccpos[i] = i + > > > + > > BADBLOCK_MARKER_LENGTH; > > > + ecclayout->oobfree[0].offset = i + > > > + > > BADBLOCK_MARKER_LENGTH; > > > + ecclayout->oobfree[0].length = oobsize - nand->ecc.bytes - > > > + > > BADBLOCK_MARKER_LENGTH; > > > + bch->ecc_scheme = > > OMAP_ECC_BCH8_CODE_HW; > > > + break; > > > + default: > > > + debug("nand: error: ecc scheme not enabled or > > supported\n"); > > > + return -EINVAL; > > > + } > > > > This will result in NAND_ECC_NONE and likely an eventual NULL pointer > > dereference if a bad value is passed and the -EINVAL return path is > > taken. > > > > OK, I now see that you've got the caller patching this up in the error > > case, but that's awkward and error prone. > > > Sorry, din't understand your feedback here. > omap_select_ecc_scheme() is common function which is used for > - changing ECC scheme if 'nandecc' like utility is needed later > - selecting ECC scheme during probe. > This function populates all necessary fields in struct *nand_chip > for nand driver to work. During probe (both SPL and u-boot), > 'CONFIG_SYS_NAND_ECCSCHEME' is used to determine the ecc-scheme. > > 'default' statement protects the driver from any invalid or un-supported > ECC scheme selected by user in his board file. So that driver probe cleanly > exits probe instead of causing an exception. > Can you please elaborate, what I'm missing here ? Before you get into the switch statement you set ecc.mode to NAND_ECC_NONE and wipe out all of the function pointers. Then, if the switch hits default:, you'll return leaving the ecc in a bad state, relying on the caller to clean it up. > > > @@ -767,67 +811,41 @@ void omap_nand_switch_ecc(uint32_t hardware, > > uint32_t eccstrength) > > > { > > > struct nand_chip *nand; > > > struct mtd_info *mtd; > > > + struct nand_bch_priv *bch; > > > + int err = 0; > > > > > > if (nand_curr_device < 0 || > > > nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE || > > > !nand_info[nand_curr_device].name) { > > > - printf("Error: Can't switch ecc, no devices available\n"); > > > + printf("nand: error: no devices available\n"); > > > return; > > > } > > > > Why are you making the error message less specific? > > > There is already another error message in board_nand_init() which will be > flagged when there is problem in selecting ECC. > printf("nand: error: cannot select ecc scheme\n"); > But thanks, you pointed out a bug, I should return -ENODEV here, > Otherwise caller would not know that ecc-scheme could not be changed. > > > Better would be something like: > > printf("%s: no devices available\n", __func__); Still, it's best for error messages to be unique and include the function name. > > > #define CONFIG_SYS_NAND_ECCSIZE 512 > > > #define CONFIG_SYS_NAND_ECCBYTES 13 > > > +#define CONFIG_SYS_NAND_ECCSCHEME 3 > > > +#define CONFIG_SYS_NAND_ONFI_DETECTION > > > > What does 3 mean? Please use a symbolic name. > > > For AM335x this is updated in board/ti/am335x/README as part of > following patch: > [PATCH v5 5/5] board/ti/am335x/README: update for NAND boot Patches are generally reviewed in order. Don't introduce something bad in 1/5 and then fix it in 5/5, even if it's just a style issue that doesn't affect bisect. -Scott

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[U-Boot] powerpc SPL framework: Avoiding relocate_code
by Prabhakar Kushwaha 16 Sep '13

16 Sep '13

Hi, SPL framework is used to support multi-stage booting. Where first level boot loader is created via SPL having relocate_code() function. I am working on a Freescale's SoC which has less internal SRAM. I don't want to use relocate_code() as to support this function, I need to reduce SPL bin to SRAM/2 size. is there way to avoid relocate_code function ? I tried with below sequence, but it is not working for me :( .globl relocate_code relocate_code: mr r1,r3 /* Set new stack pointer */ mr r9,r4 /* Save copy of Init Data pointer */ mr r10,r5 /* Save copy of Destination Address */ GET_GOT #ifndef CONFIG_SPL_BUILD -- -- #endif .globl in_ram in_ram: The reason is bss "variables" which are mapped to 0x0000_0000 onwards because "bss"section are mapped after 0xfffffffc in lds. They are not available during SPL execution. is there way to relocate bss section in the execution range of SPL? Please advice. Regards, Prabhakar

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[U-Boot] [Patch v3] powerpc/mpc85xx: Add workaround for erratum A006379
by York Sun 16 Sep '13

16 Sep '13

Erratum A006379 says CPCHDBCR0 bit field [10:14] has incorrect default value after POR. The workaround is to set this field before enabling CPC to 0x1e. Erratum A006379 applies to T4240 rev 1.0 B4860 rev 1.0, 2.0 Signed-off-by: York Sun <yorksun(a)freescale.com> --- Change log: v3: Include <asm/processor.h> in fsl_errata.h Even it is likely included in the callers' file, it is clear the needed macros are defined. v2: Add a list of SoC impacted by this erratum Add a function to detect whether workaround should be applied at runtime Add fsl_errata.h to host the prototype of the new function arch/powerpc/cpu/mpc85xx/cmd_errata.c | 5 +++++ arch/powerpc/cpu/mpc85xx/cpu_init.c | 7 +++++++ arch/powerpc/include/asm/config_mpc85xx.h | 2 ++ arch/powerpc/include/asm/fsl_errata.h | 25 +++++++++++++++++++++++++ arch/powerpc/include/asm/immap_85xx.h | 1 + 5 files changed, 40 insertions(+) create mode 100644 arch/powerpc/include/asm/fsl_errata.h diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index c441bd2..1e5a43f 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -7,6 +7,7 @@ #include <common.h> #include <command.h> #include <linux/compiler.h> +#include <asm/fsl_errata.h> #include <asm/processor.h> #include "fsl_corenet_serdes.h" @@ -245,6 +246,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #ifdef CONFIG_SYS_FSL_ERRATUM_A006593 puts("Work-around for Erratum A006593 enabled\n"); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A006379 + if (has_erratum_a006379()) + puts("Work-around for Erratum A006379 enabled\n"); +#endif #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571 if (IS_SVR_REV(svr, 1, 0)) puts("Work-around for Erratum A003571 enabled\n"); diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 6036333..22c0c54 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -19,6 +19,7 @@ #include <asm/io.h> #include <asm/cache.h> #include <asm/mmu.h> +#include <asm/fsl_errata.h> #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> #include <asm/fsl_srio.h> @@ -160,6 +161,12 @@ static void enable_cpc(void) #ifdef CONFIG_SYS_FSL_ERRATUM_A006593 setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21)); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A006379 + if (has_erratum_a006379()) { + setbits_be32(&cpc->cpchdbcr0, + CPC_HDBCR0_SPLRU_LEVEL_EN); + } +#endif out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE); /* Read back to sync write */ diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index bec8966..6986ade 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -593,6 +593,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A004468 #define CONFIG_SYS_FSL_ERRATUM_A_004934 #define CONFIG_SYS_FSL_ERRATUM_A005871 +#define CONFIG_SYS_FSL_ERRATUM_A006379 #define CONFIG_SYS_FSL_ERRATUM_A006593 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_PCI_VER_3_X @@ -617,6 +618,7 @@ #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_ERRATUM_A_004934 #define CONFIG_SYS_FSL_ERRATUM_A005871 +#define CONFIG_SYS_FSL_ERRATUM_A006379 #define CONFIG_SYS_FSL_ERRATUM_A006593 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 diff --git a/arch/powerpc/include/asm/fsl_errata.h b/arch/powerpc/include/asm/fsl_errata.h new file mode 100644 index 0000000..3cac2d4 --- /dev/null +++ b/arch/powerpc/include/asm/fsl_errata.h @@ -0,0 +1,25 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_FSL_ERRATA_H +#define _ASM_FSL_ERRATA_H + +#include <common.h> +#include <asm/processor.h> + +#ifdef CONFIG_SYS_FSL_ERRATUM_A006379 +static inline bool has_erratum_a006379(void) +{ + u32 svr = get_svr(); + if (((SVR_SOC_VER(svr) == SVR_T4240) && SVR_MAJ(svr) <= 1) || + ((SVR_SOC_VER(svr) == SVR_B4860) && SVR_MAJ(svr) <= 2)) + return true; + + return false; +} +#endif + +#endif diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 3a10d77..a938143 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1671,6 +1671,7 @@ typedef struct cpc_corenet { #define CPC_HDBCR0_CDQ_SPEC_DIS 0x08000000 #define CPC_HDBCR0_TAG_ECC_SCRUB_DIS 0x01000000 #define CPC_HDBCR0_DATA_ECC_SCRUB_DIS 0x00400000 +#define CPC_HDBCR0_SPLRU_LEVEL_EN 0x003c0000 #endif /* CONFIG_SYS_FSL_CPC */ /* Global Utilities Block */ -- 1.7.9.5

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