July 2013 - U-Boot

[U-Boot] [PATCH 1/1] socfpga: Consolidating reset code into reset_manager.c. Also separating reset configuration for virtual target and real hardware Cyclone V development kit
by Chin Liang See 02 Jul '13

02 Jul '13

socfpga: Consolidating reset code into reset_manager.c. Also separating reset configuration for virtual target and real hardware Cyclone V development kit Signed-off-by: Chin Liang See <clsee(a)altera.com> --- arch/arm/cpu/armv7/socfpga/Makefile | 2 +- arch/arm/cpu/armv7/socfpga/misc.c | 27 ----------- arch/arm/cpu/armv7/socfpga/reset_manager.c | 50 +++++++++++++++++++++ arch/arm/include/asm/arch-socfpga/reset_manager.h | 17 +++++++ 4 files changed, 68 insertions(+), 28 deletions(-) create mode 100644 arch/arm/cpu/armv7/socfpga/reset_manager.c diff --git a/arch/arm/cpu/armv7/socfpga/Makefile b/arch/arm/cpu/armv7/socfpga/Makefile index 376a4bd..518e67a 100644 --- a/arch/arm/cpu/armv7/socfpga/Makefile +++ b/arch/arm/cpu/armv7/socfpga/Makefile @@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o SOBJS := lowlevel_init.o -COBJS-y := misc.o timer.o +COBJS-y := misc.o timer.o reset_manager.o COBJS-$(CONFIG_SPL_BUILD) += spl.o COBJS := $(COBJS-y) diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c index fa16424..59f5b94 100644 --- a/arch/arm/cpu/armv7/socfpga/misc.c +++ b/arch/arm/cpu/armv7/socfpga/misc.c @@ -17,36 +17,9 @@ #include <common.h> #include <asm/io.h> -#include <asm/arch/reset_manager.h> DECLARE_GLOBAL_DATA_PTR; -static const struct socfpga_reset_manager *reset_manager_base = - (void *)SOCFPGA_RSTMGR_ADDRESS; - -/* - * Write the reset manager register to cause reset - */ -void reset_cpu(ulong addr) -{ - /* request a warm reset */ - writel(RSTMGR_CTRL_SWWARMRSTREQ_LSB, &reset_manager_base->ctrl); - /* - * infinite loop here as watchdog will trigger and reset - * the processor - */ - while (1) - ; -} - -/* - * Release peripherals from reset based on handoff - */ -void reset_deassert_peripherals_handoff(void) -{ - writel(0, &reset_manager_base->per_mod_reset); -} - int dram_init(void) { gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c b/arch/arm/cpu/armv7/socfpga/reset_manager.c new file mode 100644 index 0000000..b0cc399 --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/reset_manager.c @@ -0,0 +1,50 @@ +/* + * Copyright Altera Corporation (C) <2013>. All rights reserved + * + * This program is free software; you can redistribute it and/or +modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but +WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/reset_manager.h> + +DECLARE_GLOBAL_DATA_PTR; + +static const struct socfpga_reset_manager *reset_manager_base = + (void *)SOCFPGA_RSTMGR_ADDRESS; + +/* + * Write the reset manager register to cause reset */ void +reset_cpu(ulong addr) { + /* request a warm reset */ + writel((1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB), + &reset_manager_base->ctrl); + /* + * infinite loop here as watchdog will trigger and reset + * the processor + */ + while (1) + ; +} + +/* + * Release peripherals from reset based on handoff */ void +reset_deassert_peripherals_handoff(void) +{ + writel(0, &reset_manager_base->per_mod_reset); +} + + diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h b/arch/arm/include/asm/arch-socfpga/reset_manager.h index d9d2c1c..58d85e3 100644 --- a/arch/arm/include/asm/arch-socfpga/reset_manager.h +++ b/arch/arm/include/asm/arch-socfpga/reset_manager.h @@ -21,6 +21,7 @@ void reset_cpu(ulong addr); void reset_deassert_peripherals_handoff(void); +#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) struct socfpga_reset_manager { u32 padding1; u32 ctrl; @@ -31,7 +32,23 @@ struct socfpga_reset_manager { u32 per2_mod_reset; u32 brg_mod_reset; }; +#else +struct socfpga_reset_manager { + u32 status; + u32 ctrl; + u32 counts; + u32 padding1; + u32 mpu_mod_reset; + u32 per_mod_reset; + u32 per2_mod_reset; + u32 brg_mod_reset; +}; +#endif +#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) +#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2 +#else #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1 +#endif #endif /* _RESET_MANAGER_H_ */ -- 1.7.7.4 Confidentiality Notice. This message may contain information that is confidential or otherwise protected from disclosure. If you are not the intended recipient, you are hereby notified that any use, disclosure, dissemination, distribution, or copying of this message, or any attachments, is strictly prohibited. If you have received this message in error, please advise the sender by reply e-mail, and delete the message and any attachments. Thank you.

4 8

[U-Boot] [PATCH v4 1/1] socfpga: Adding configuration for development kit
by Chin Liang See 02 Jul '13

02 Jul '13

socfpga: Separating the configuration file for Virtual Target and real hardware Cyclone V development kit Signed-off-by: Chin Liang See <clsee(a)altera.com> --- Changes for v2: - Fixed the word wrap issue within patch Changes for v3: - Fixed the long subject of the patch Changes for v4: - Added change log for each revision change include/configs/socfpga_cyclone5.h | 28 +++++++++++++++++++++------- 1 file changed, 21 insertions(+), 7 deletions(-) diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index 5633d2a..be3799b 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -22,6 +22,8 @@ /* * High level configuration */ +/* Virtual target or real hardware */ +#define CONFIG_SOCFPGA_VIRTUAL_TARGET #define CONFIG_ARMV7 #define CONFIG_L2_OFF @@ -32,11 +34,12 @@ #define CONFIG_SINGLE_BOOTLOADER #define CONFIG_SOCFPGA +/* base address for .text section */ +#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET #define CONFIG_SYS_TEXT_BASE 0x08000040 -#define V_NS16550_CLK 1000000 -#define CONFIG_BAUDRATE 57600 -#define CONFIG_SYS_HZ 1000 -#define CONFIG_TIMER_CLOCK_KHZ 2400 +#else +#define CONFIG_SYS_TEXT_BASE 0x01000040 +#endif #define CONFIG_SYS_LOAD_ADDR 0x7fc0 /* Console I/O Buffer Size */ @@ -165,7 +168,7 @@ /* SDRAM Bank #1 */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* SDRAM memory size */ -#define PHYS_SDRAM_1_SIZE 0x80000000 +#define PHYS_SDRAM_1_SIZE 0x40000000 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_START 0x00000000 @@ -181,8 +184,13 @@ #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK #define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550_COM1 UART0_BASE - #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} +#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET +#define V_NS16550_CLK 1000000 +#else +#define V_NS16550_CLK 100000000 +#endif +#define CONFIG_BAUDRATE 115200 /* * FLASH @@ -195,9 +203,15 @@ /* This timer use eosc1 where the clock frequency is fixed * throughout any condition */ #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS - /* reload value when timer count to zero */ #define TIMER_LOAD_VAL 0xFFFFFFFF +/* Timer info */ +#define CONFIG_SYS_HZ 1000 +#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET +#define CONFIG_TIMER_CLOCK_KHZ 2400 +#else +#define CONFIG_TIMER_CLOCK_KHZ 25000 +#endif #define CONFIG_ENV_IS_NOWHERE -- 1.7.9.5

2 1

[U-Boot] [PATCH] socfpga: Move board/socfpga_cyclone5 to board/socfpga
by dinguyen＠altera.com 02 Jul '13

02 Jul '13

From: Dinh Nguyen <dinguyen(a)altera.com> Because the SOCFPGA platform will include support for Cyclone V and Arria V FPGA parts, renaming socfpga_cyclone5 folder to socfpga to be more generic. Signed-off-by: Dinh Nguyen <dinguyen(a)altera.com> Cc: Chin Liang See <clsee(a)altera.com> Cc: Wolfgang Denk <wd(a)denx.de> CC: Pavel Machek <pavel(a)denx.de> --- .../altera/{socfpga_cyclone5 => socfpga}/Makefile | 0 .../socfpga_cyclone5.c | 0 boards.cfg | 2 +- 3 files changed, 1 insertion(+), 1 deletion(-) rename board/altera/{socfpga_cyclone5 => socfpga}/Makefile (100%) rename board/altera/{socfpga_cyclone5 => socfpga}/socfpga_cyclone5.c (100%) diff --git a/board/altera/socfpga_cyclone5/Makefile b/board/altera/socfpga/Makefile similarity index 100% rename from board/altera/socfpga_cyclone5/Makefile rename to board/altera/socfpga/Makefile diff --git a/board/altera/socfpga_cyclone5/socfpga_cyclone5.c b/board/altera/socfpga/socfpga_cyclone5.c similarity index 100% rename from board/altera/socfpga_cyclone5/socfpga_cyclone5.c rename to board/altera/socfpga/socfpga_cyclone5.c diff --git a/boards.cfg b/boards.cfg index c0c4282..eea92d5 100644 --- a/boards.cfg +++ b/boards.cfg @@ -335,7 +335,7 @@ kzm9g arm armv7 kzm9g kmc armadillo-800eva arm armv7 armadillo-800eva atmark-techno rmobile zynq arm armv7 zynq xilinx zynq zynq_dcc arm armv7 zynq xilinx zynq zynq:ZYNQ_DCC -socfpga_cyclone5 arm armv7 socfpga_cyclone5 altera socfpga +socfpga_cyclone5 arm armv7 socfpga altera socfpga actux1_4_16 arm ixp actux1 - - actux1:FLASH2X2 actux1_4_32 arm ixp actux1 - - actux1:FLASH2X2,RAM_32MB actux1_8_16 arm ixp actux1 - - actux1:FLASH1X8 -- 1.7.9.5

2 1

[U-Boot] [PATCH 1/1] socfpga: Adding System Manager driver which will configure the pin mux for real hardware Cyclone V
by Chin Liang See 02 Jul '13

02 Jul '13

socfpga: Adding System Manager driver which will configure the pin mux for real hardware Cyclone V development kit (not Virtual Platform) Signed-off-by: Chin Liang See <clsee(a)altera.com> --- arch/arm/cpu/armv7/socfpga/Makefile | 2 +- arch/arm/cpu/armv7/socfpga/spl.c | 6 + arch/arm/cpu/armv7/socfpga/system_manager.c | 40 ++++ .../include/asm/arch-socfpga/socfpga_base_addrs.h | 1 + arch/arm/include/asm/arch-socfpga/system_manager.h | 32 +++ board/altera/socfpga_cyclone5/Makefile | 4 +- board/altera/socfpga_cyclone5/pinmux_config.c | 213 ++++++++++++++++++++ board/altera/socfpga_cyclone5/pinmux_config.h | 53 +++++ include/configs/socfpga_cyclone5.h | 1 + 9 files changed, 350 insertions(+), 2 deletions(-) create mode 100644 arch/arm/cpu/armv7/socfpga/system_manager.c create mode 100644 arch/arm/include/asm/arch-socfpga/system_manager.h create mode 100644 board/altera/socfpga_cyclone5/pinmux_config.c create mode 100644 board/altera/socfpga_cyclone5/pinmux_config.h diff --git a/arch/arm/cpu/armv7/socfpga/Makefile b/arch/arm/cpu/armv7/socfpga/Makefile index 518e67a..cf2829a 100644 --- a/arch/arm/cpu/armv7/socfpga/Makefile +++ b/arch/arm/cpu/armv7/socfpga/Makefile @@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o SOBJS := lowlevel_init.o -COBJS-y := misc.o timer.o reset_manager.o +COBJS-y := misc.o timer.o reset_manager.o system_manager.o COBJS-$(CONFIG_SPL_BUILD) += spl.o COBJS := $(COBJS-y) diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c index 84216eb..28d8c99 100644 --- a/arch/arm/cpu/armv7/socfpga/spl.c +++ b/arch/arm/cpu/armv7/socfpga/spl.c @@ -23,6 +23,7 @@ #include <image.h> #include <asm/arch/reset_manager.h> #include <spl.h> +#include <asm/arch/system_manager.h> DECLARE_GLOBAL_DATA_PTR; @@ -36,6 +37,11 @@ u32 spl_boot_device(void) */ void spl_board_init(void) { +#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET + /* configure the pin muxing through system manager */ + sysmgr_pinmux_init(); +#endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */ + /* de-assert reset for peripherals and bridges based on handoff */ reset_deassert_peripherals_handoff(); diff --git a/arch/arm/cpu/armv7/socfpga/system_manager.c b/arch/arm/cpu/armv7/socfpga/system_manager.c new file mode 100644 index 0000000..f2707d8b --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/system_manager.c @@ -0,0 +1,40 @@ +/* + * Copyright Altera Corporation (C) 2013. All rights reserved + * + * This program is free software; you can redistribute it and/or +modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but +WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +License + * for more details. + * + * You should have received a copy of the GNU General Public License +along + * with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/system_manager.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Configure all the pin mux + */ +void sysmgr_pinmux_init(void) +{ + unsigned long offset = CONFIG_SYSMGR_PINMUXGRP_OFFSET; + + const unsigned long *pval = sys_mgr_init_table; + unsigned long i; + + for (i = 0; + i < ((sizeof(sys_mgr_init_table)) / sizeof(unsigned long)); + i++, offset += sizeof(unsigned long)) { + writel(*pval++, (SOCFPGA_SYSMGR_ADDRESS + offset)); + } +} + + diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h index f353eb2..819c280 100644 --- a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h +++ b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h @@ -23,5 +23,6 @@ #define SOCFPGA_UART1_ADDRESS 0xffc03000 #define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000 #define SOCFPGA_RSTMGR_ADDRESS 0xffd05000 +#define SOCFPGA_SYSMGR_ADDRESS 0xffd08000 #endif /* _SOCFPGA_BASE_ADDRS_H_ */ diff --git a/arch/arm/include/asm/arch-socfpga/system_manager.h b/arch/arm/include/asm/arch-socfpga/system_manager.h new file mode 100644 index 0000000..aec9be7 --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/system_manager.h @@ -0,0 +1,32 @@ +/* + * Copyright Altera Corporation (C) 2013. All rights reserved + * + * This program is free software; you can redistribute it and/or +modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but +WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +License + * for more details. + * + * You should have received a copy of the GNU General Public License +along + * with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _SYSTEM_MANAGER_H_ +#define _SYSTEM_MANAGER_H_ + +#ifndef __ASSEMBLY__ + +void sysmgr_pinmux_init(void); + +/* declaration for handoff table type */ extern unsigned long +sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM]; + +#endif + + +#define CONFIG_SYSMGR_PINMUXGRP_OFFSET (0x400) + +#endif /* _SYSTEM_MANAGER_H_ */ diff --git a/board/altera/socfpga_cyclone5/Makefile b/board/altera/socfpga_cyclone5/Makefile index 43bbc37..3092387 100644 --- a/board/altera/socfpga_cyclone5/Makefile +++ b/board/altera/socfpga_cyclone5/Makefile @@ -26,8 +26,10 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o -COBJS := socfpga_cyclone5.o +COBJS-y := socfpga_cyclone5.o +COBJS-$(CONFIG_SPL_BUILD) += pinmux_config.o +COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/altera/socfpga_cyclone5/pinmux_config.c b/board/altera/socfpga_cyclone5/pinmux_config.c new file mode 100644 index 0000000..42e7c89 --- /dev/null +++ b/board/altera/socfpga_cyclone5/pinmux_config.c @@ -0,0 +1,213 @@ + +#include "pinmux_config.h" + +/* pin mux configuration data */ +unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM] = { + 0, /* EMACIO0 - Unused */ + 2, /* EMACIO1 - USB */ + 2, /* EMACIO2 - USB */ + 2, /* EMACIO3 - USB */ + 2, /* EMACIO4 - USB */ + 2, /* EMACIO5 - USB */ + 2, /* EMACIO6 - USB */ + 2, /* EMACIO7 - USB */ + 2, /* EMACIO8 - USB */ + 0, /* EMACIO9 - Unused */ + 2, /* EMACIO10 - USB */ + 2, /* EMACIO11 - USB */ + 2, /* EMACIO12 - USB */ + 2, /* EMACIO13 - USB */ + 0, /* EMACIO14 - N/A */ + 0, /* EMACIO15 - N/A */ + 0, /* EMACIO16 - N/A */ + 0, /* EMACIO17 - N/A */ + 0, /* EMACIO18 - N/A */ + 0, /* EMACIO19 - N/A */ + 3, /* FLASHIO0 - SDMMC */ + 3, /* FLASHIO1 - SDMMC */ + 3, /* FLASHIO2 - SDMMC */ + 3, /* FLASHIO3 - SDMMC */ + 0, /* FLASHIO4 - SDMMC */ + 0, /* FLASHIO5 - SDMMC */ + 0, /* FLASHIO6 - SDMMC */ + 0, /* FLASHIO7 - SDMMC */ + 0, /* FLASHIO8 - SDMMC */ + 3, /* FLASHIO9 - SDMMC */ + 3, /* FLASHIO10 - SDMMC */ + 3, /* FLASHIO11 - SDMMC */ + 3, /* GENERALIO0 - TRACE */ + 3, /* GENERALIO1 - TRACE */ + 3, /* GENERALIO2 - TRACE */ + 3, /* GENERALIO3 - TRACE */ + 3, /* GENERALIO4 - TRACE */ + 3, /* GENERALIO5 - TRACE */ + 3, /* GENERALIO6 - TRACE */ + 3, /* GENERALIO7 - TRACE */ + 3, /* GENERALIO8 - TRACE */ + 3, /* GENERALIO9 - SPIM0 */ + 3, /* GENERALIO10 - SPIM0 */ + 3, /* GENERALIO11 - SPIM0 */ + 3, /* GENERALIO12 - SPIM0 */ + 2, /* GENERALIO13 - CAN0 */ + 2, /* GENERALIO14 - CAN0 */ + 3, /* GENERALIO15 - I2C0 */ + 3, /* GENERALIO16 - I2C0 */ + 2, /* GENERALIO17 - UART0 */ + 2, /* GENERALIO18 - UART0 */ + 0, /* GENERALIO19 - N/A */ + 0, /* GENERALIO20 - N/A */ + 0, /* GENERALIO21 - N/A */ + 0, /* GENERALIO22 - N/A */ + 0, /* GENERALIO23 - N/A */ + 0, /* GENERALIO24 - N/A */ + 0, /* GENERALIO25 - N/A */ + 0, /* GENERALIO26 - N/A */ + 0, /* GENERALIO27 - N/A */ + 0, /* GENERALIO28 - N/A */ + 0, /* GENERALIO29 - N/A */ + 0, /* GENERALIO30 - N/A */ + 0, /* GENERALIO31 - N/A */ + 2, /* MIXED1IO0 - EMAC */ + 2, /* MIXED1IO1 - EMAC */ + 2, /* MIXED1IO2 - EMAC */ + 2, /* MIXED1IO3 - EMAC */ + 2, /* MIXED1IO4 - EMAC */ + 2, /* MIXED1IO5 - EMAC */ + 2, /* MIXED1IO6 - EMAC */ + 2, /* MIXED1IO7 - EMAC */ + 2, /* MIXED1IO8 - EMAC */ + 2, /* MIXED1IO9 - EMAC */ + 2, /* MIXED1IO10 - EMAC */ + 2, /* MIXED1IO11 - EMAC */ + 2, /* MIXED1IO12 - EMAC */ + 2, /* MIXED1IO13 - EMAC */ + 0, /* MIXED1IO14 - Unused */ + 3, /* MIXED1IO15 - QSPI */ + 3, /* MIXED1IO16 - QSPI */ + 3, /* MIXED1IO17 - QSPI */ + 3, /* MIXED1IO18 - QSPI */ + 3, /* MIXED1IO19 - QSPI */ + 3, /* MIXED1IO20 - QSPI */ + 0, /* MIXED1IO21 - GPIO */ + 0, /* MIXED2IO0 - N/A */ + 0, /* MIXED2IO1 - N/A */ + 0, /* MIXED2IO2 - N/A */ + 0, /* MIXED2IO3 - N/A */ + 0, /* MIXED2IO4 - N/A */ + 0, /* MIXED2IO5 - N/A */ + 0, /* MIXED2IO6 - N/A */ + 0, /* MIXED2IO7 - N/A */ + 0, /* GPLINMUX48 */ + 0, /* GPLINMUX49 */ + 0, /* GPLINMUX50 */ + 0, /* GPLINMUX51 */ + 0, /* GPLINMUX52 */ + 0, /* GPLINMUX53 */ + 0, /* GPLINMUX54 */ + 0, /* GPLINMUX55 */ + 0, /* GPLINMUX56 */ + 0, /* GPLINMUX57 */ + 0, /* GPLINMUX58 */ + 0, /* GPLINMUX59 */ + 0, /* GPLINMUX60 */ + 0, /* GPLINMUX61 */ + 0, /* GPLINMUX62 */ + 0, /* GPLINMUX63 */ + 0, /* GPLINMUX64 */ + 0, /* GPLINMUX65 */ + 0, /* GPLINMUX66 */ + 0, /* GPLINMUX67 */ + 0, /* GPLINMUX68 */ + 0, /* GPLINMUX69 */ + 0, /* GPLINMUX70 */ + 1, /* GPLMUX0 */ + 1, /* GPLMUX1 */ + 1, /* GPLMUX2 */ + 1, /* GPLMUX3 */ + 1, /* GPLMUX4 */ + 1, /* GPLMUX5 */ + 1, /* GPLMUX6 */ + 1, /* GPLMUX7 */ + 1, /* GPLMUX8 */ + 1, /* GPLMUX9 */ + 1, /* GPLMUX10 */ + 1, /* GPLMUX11 */ + 1, /* GPLMUX12 */ + 1, /* GPLMUX13 */ + 1, /* GPLMUX14 */ + 1, /* GPLMUX15 */ + 1, /* GPLMUX16 */ + 1, /* GPLMUX17 */ + 1, /* GPLMUX18 */ + 1, /* GPLMUX19 */ + 1, /* GPLMUX20 */ + 1, /* GPLMUX21 */ + 1, /* GPLMUX22 */ + 1, /* GPLMUX23 */ + 1, /* GPLMUX24 */ + 1, /* GPLMUX25 */ + 1, /* GPLMUX26 */ + 1, /* GPLMUX27 */ + 1, /* GPLMUX28 */ + 1, /* GPLMUX29 */ + 1, /* GPLMUX30 */ + 1, /* GPLMUX31 */ + 1, /* GPLMUX32 */ + 1, /* GPLMUX33 */ + 1, /* GPLMUX34 */ + 1, /* GPLMUX35 */ + 1, /* GPLMUX36 */ + 1, /* GPLMUX37 */ + 1, /* GPLMUX38 */ + 1, /* GPLMUX39 */ + 1, /* GPLMUX40 */ + 1, /* GPLMUX41 */ + 1, /* GPLMUX42 */ + 1, /* GPLMUX43 */ + 1, /* GPLMUX44 */ + 1, /* GPLMUX45 */ + 1, /* GPLMUX46 */ + 1, /* GPLMUX47 */ + 1, /* GPLMUX48 */ + 1, /* GPLMUX49 */ + 1, /* GPLMUX50 */ + 1, /* GPLMUX51 */ + 1, /* GPLMUX52 */ + 1, /* GPLMUX53 */ + 1, /* GPLMUX54 */ + 1, /* GPLMUX55 */ + 1, /* GPLMUX56 */ + 1, /* GPLMUX57 */ + 1, /* GPLMUX58 */ + 1, /* GPLMUX59 */ + 1, /* GPLMUX60 */ + 1, /* GPLMUX61 */ + 1, /* GPLMUX62 */ + 1, /* GPLMUX63 */ + 1, /* GPLMUX64 */ + 1, /* GPLMUX65 */ + 1, /* GPLMUX66 */ + 1, /* GPLMUX67 */ + 1, /* GPLMUX68 */ + 1, /* GPLMUX69 */ + 1, /* GPLMUX70 */ + 0, /* NANDUSEFPGA */ + 0, /* UART0USEFPGA */ + 0, /* RGMII1USEFPGA */ + 0, /* SPIS0USEFPGA */ + 0, /* CAN0USEFPGA */ + 0, /* I2C0USEFPGA */ + 0, /* SDMMCUSEFPGA */ + 0, /* QSPIUSEFPGA */ + 0, /* SPIS1USEFPGA */ + 0, /* RGMII0USEFPGA */ + 0, /* UART1USEFPGA */ + 0, /* CAN1USEFPGA */ + 0, /* USB1USEFPGA */ + 0, /* I2C3USEFPGA */ + 0, /* I2C2USEFPGA */ + 0, /* I2C1USEFPGA */ + 0, /* SPIM1USEFPGA */ + 0, /* USB0USEFPGA */ + 0 /* SPIM0USEFPGA */ +}; diff --git a/board/altera/socfpga_cyclone5/pinmux_config.h b/board/altera/socfpga_cyclone5/pinmux_config.h new file mode 100644 index 0000000..33628c8 --- /dev/null +++ b/board/altera/socfpga_cyclone5/pinmux_config.h @@ -0,0 +1,53 @@ + +#ifndef _PRELOADER_PINMUX_CONFIG_H_ +#define _PRELOADER_PINMUX_CONFIG_H_ + +/* + * State of enabling for which IP connected out through the muxing. + * Value 1 mean the IP connection is muxed out */ +#define CONFIG_HPS_EMAC0 (0) +#define CONFIG_HPS_EMAC1 (1) +#define CONFIG_HPS_USB0 (0) +#define CONFIG_HPS_USB1 (1) +#define CONFIG_HPS_NAND (0) +#define CONFIG_HPS_SDMMC (1) +#define CONFIG_HPS_QSPI (1) +#define CONFIG_HPS_UART0 (1) +#define CONFIG_HPS_UART1 (0) +#define CONFIG_HPS_TRACE (1) +#define CONFIG_HPS_I2C0 (1) +#define CONFIG_HPS_I2C1 (0) +#define CONFIG_HPS_I2C2 (0) +#define CONFIG_HPS_I2C3 (0) +#define CONFIG_HPS_SPIM0 (1) +#define CONFIG_HPS_SPIM1 (0) +#define CONFIG_HPS_SPIS0 (0) +#define CONFIG_HPS_SPIS1 (0) +#define CONFIG_HPS_CAN0 (1) +#define CONFIG_HPS_CAN1 (0) + +/* IP attribute value (which affected by pin muxing configuration) */ +#define CONFIG_HPS_SDMMC_BUSWIDTH (4) + +/* 1 if the pins are connected out */ +#define CONFIG_HPS_QSPI_CS0 (1) +#define CONFIG_HPS_QSPI_CS1 (0) +#define CONFIG_HPS_QSPI_CS2 (0) +#define CONFIG_HPS_QSPI_CS3 (0) + +/* UART */ +/* 1 means the pin is mux out or available */ +#define CONFIG_HPS_UART0_TX (1) +#define CONFIG_HPS_UART0_RX (1) +#define CONFIG_HPS_UART0_CTS (0) +#define CONFIG_HPS_UART0_RTS (0) +#define CONFIG_HPS_UART1_TX (0) +#define CONFIG_HPS_UART1_RX (0) +#define CONFIG_HPS_UART1_CTS (0) +#define CONFIG_HPS_UART1_RTS (0) + +/* Pin mux data */ +#define CONFIG_HPS_PINMUX_NUM (207) + +#endif /* _PRELOADER_PINMUX_CONFIG_H_ */ diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index 86563b7..02c5448 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -18,6 +18,7 @@ #define __CONFIG_H #include <asm/arch/socfpga_base_addrs.h> +#include "../../board/altera/socfpga_cyclone5/pinmux_config.h" /* * High level configuration -- 1.7.7.4 Confidentiality Notice. This message may contain information that is confidential or otherwise protected from disclosure. If you are not the intended recipient, you are hereby notified that any use, disclosure, dissemination, distribution, or copying of this message, or any attachments, is strictly prohibited. If you have received this message in error, please advise the sender by reply e-mail, and delete the message and any attachments. Thank you.

4 11

[U-Boot] [PATCH 1/2] powerpc/83xx/km: MV88e6122 errata fix for 1.9V
by Holger Brunck 02 Jul '13

02 Jul '13

Errata Fix: 1.9V Output from Internal 1.8V Regulator, acc. MV-S300889-00D.pdf , clause 4.5 Signed-off-by: Holger Brunck <holger.brunck(a)keymile.com> --- board/keymile/km83xx/km83xx.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c index faaa39b..71b9e96 100644 --- a/board/keymile/km83xx/km83xx.c +++ b/board/keymile/km83xx/km83xx.c @@ -243,6 +243,11 @@ static struct mv88e_sw_reg extsw_conf[] = { { PORT(5), 0x1A, 0xADB1 }, /* port 6, unused, this port has no phy */ { PORT(6), PORT_CTRL, PORT_DIS }, + /* + * Errata Fix: 1.9V Output from Internal 1.8V Regulator, + * acc . MV-S300889-00D.pdf , clause 4.5 + */ + { PORT(5), 0x1A, 0xADB1 }, }; #endif -- 1.8.0.1

2 3

[U-Boot] [PATCH v6 3/3] Add TI816X evm board support
by TENART Antoine 02 Jul '13

02 Jul '13

Signed-off-by: Antoine Tenart <atenart(a)adeneo-embedded.com> --- MAINTAINERS | 4 + board/ti/ti816x/Makefile | 47 +++++++++ board/ti/ti816x/evm.c | 229 ++++++++++++++++++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/ti816x_evm.h | 180 +++++++++++++++++++++++++++++++++ 5 files changed, 461 insertions(+) create mode 100644 board/ti/ti816x/Makefile create mode 100644 board/ti/ti816x/evm.c create mode 100644 include/configs/ti816x_evm.h diff --git a/MAINTAINERS b/MAINTAINERS index 3e70b03..d4a89e3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -943,6 +943,10 @@ Lucas Stach <dev(a)lynxeye.de> colibri_t20_iris Tegra20 (ARM7 & A9 Dual Core) +Antoine Tenart <atenart(a)adeneo-embedded.com> + + TI816X ARM ARMV7 (TI816x Soc) + Nick Thompson <nick.thompson(a)gefanuc.com> da830evm ARM926EJS (DA830/OMAP-L137) diff --git a/board/ti/ti816x/Makefile b/board/ti/ti816x/Makefile new file mode 100644 index 0000000..dc23d93 --- /dev/null +++ b/board/ti/ti816x/Makefile @@ -0,0 +1,47 @@ +# +# Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> +# Antoine Tenart, <atenart(a)adeneo-embedded.com> +# +# Based on TI-PSP-04.00.02.14 : +# +# Copyright (C) 2009, Texas Instruments, Incorporated +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation version 2. +# +# This program is distributed "as is" WITHOUT ANY WARRANTY of any +# kind, whether express or implied; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := evm.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/ti/ti816x/evm.c b/board/ti/ti816x/evm.c new file mode 100644 index 0000000..632ad9f --- /dev/null +++ b/board/ti/ti816x/evm.c @@ -0,0 +1,229 @@ +/* + * evm.c + * + * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> + * Antoine Tenart, <atenart(a)adeneo-embedded.com> + * + * This file is released under the terms of GPL v2 and any later version. + * See the file COPYING in the root directory of the source tree for details. + */ + +#include <common.h> +#include <spl.h> +#include <asm/cache.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/cpu.h> +#include <asm/arch/ddr_defs.h> +#include <asm/arch/hardware.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/mem.h> +#include <asm/arch/mux.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; + return 0; +} + +#ifdef CONFIG_SPL_BUILD + +static struct module_pin_mux mmc_pin_mux[] = { + { OFFSET(pincntl157), PULLDOWN_EN | PULLUDDIS | MODE(0x0) }, + { OFFSET(pincntl158), PULLDOWN_EN | PULLUDEN | MODE(0x0) }, + { OFFSET(pincntl159), PULLUP_EN | PULLUDDIS | MODE(0x0) }, + { OFFSET(pincntl160), PULLUP_EN | PULLUDDIS | MODE(0x0) }, + { OFFSET(pincntl161), PULLUP_EN | PULLUDDIS | MODE(0x0) }, + { OFFSET(pincntl162), PULLUP_EN | PULLUDDIS | MODE(0x0) }, + { OFFSET(pincntl163), PULLUP_EN | PULLUDDIS | MODE(0x0) }, + { -1 }, +}; + +const struct dmm_lisa_map_regs evm_lisa_map_regs = { + .dmm_lisa_map_0 = 0x00000000, + .dmm_lisa_map_1 = 0x00000000, + .dmm_lisa_map_2 = 0x80640300, + .dmm_lisa_map_3 = 0xC0640320, +}; + +/* + * DDR2 related definitions + */ + +static struct ddr_data ddr2_data = { + .datardsratio0 = ((0x40<<10) | (0x40<<0)), + .datawdsratio0 = ((0x4A<<10) | (0x4A<<0)), + .datawiratio0 = ((0x0<<10) | (0x0<<0)), + .datagiratio0 = ((0x0<<10) | (0x0<<0)), + .datafwsratio0 = ((0x13A<<10) | (0x13A<<0)), + .datawrsratio0 = ((0x8A<<10) | (0x8A<<0)), + .datauserank0delay = 0x1, + .datadldiff0 = 0x0, /* depend on cpu rev, set later */ +}; + +static struct cmd_control ddr2_ctrl = { + .cmd0csratio = 0x80, + .cmd0dldiff = 0x04, /* reset value is 0x4 */ + .cmd0iclkout = 0x00, + + .cmd1csratio = 0x80, + .cmd1dldiff = 0x04, /* reset value is 0x4 */ + .cmd1iclkout = 0x00, + + .cmd2csratio = 0x80, + .cmd2dldiff = 0x04, /* reset value is 0x4 */ + .cmd2iclkout = 0x00, + +}; + +static struct emif_regs ddr2_emif0_regs = { + .sdram_config = 0x43801A3A, + .ref_ctrl = 0x10000C30, + .sdram_tim1 = 0x0AAB15E2, + .sdram_tim2 = 0x423631D2, + .sdram_tim3 = 0x0080032F, + .emif_ddr_phy_ctlr_1 = 0x0, /* depend on cpu rev, set later */ +}; + +static struct emif_regs ddr2_emif1_regs = { + .sdram_config = 0x43801A3A, + .ref_ctrl = 0x10000C30, + .sdram_tim1 = 0x0AAB15E2, + .sdram_tim2 = 0x423631D2, + .sdram_tim3 = 0x0080032F, + .emif_ddr_phy_ctlr_1 = 0x0, /* depend on cpu rev, set later */ +}; + +/* + * DDR3 related definitions + */ + +#if defined(CONFIG_TI816X_DDR_PLL_400) +#define RD_DQS 0x03B +#define WR_DQS 0x0A6 +#define RD_DQS_GATE 0x12A +#define EMIF_SDCFG 0x62A41032 +#define EMIF_SDREF 0x10000C30 +#define EMIF_TIM1 0x0CCCE524 +#define EMIF_TIM2 0x30308023 +#define EMIF_TIM3 0x009F82CF +#define EMIF_PHYCFG 0x0000010B +#elif defined(CONFIG_TI816X_DDR_PLL_531) +#define RD_DQS 0x039 +#define WR_DQS 0x0B4 +#define RD_DQS_GATE 0x13D +#define EMIF_SDCFG 0x62A51832 +#define EMIF_SDREF 0x1000102E +#define EMIF_TIM1 0x0EF136AC +#define EMIF_TIM2 0x30408063 +#define EMIF_TIM3 0x009F83AF +#define EMIF_PHYCFG 0x0000010C +#elif defined(CONFIG_TI816X_DDR_PLL_675) +#define RD_DQS 0x039 +#define WR_DQS 0x091 +#define RD_DQS_GATE 0x196 +#define EMIF_SDCFG 0x62A63032 +#define EMIF_SDREF 0x10001491 +#define EMIF_TIM1 0x13358875 +#define EMIF_TIM2 0x5051806C +#define EMIF_TIM3 0x009F84AF +#define EMIF_PHYCFG 0x0000010F +#elif defined(CONFIG_TI816X_DDR_PLL_796) +#define RD_DQS 0x035 +#define WR_DQS 0x093 +#define RD_DQS_GATE 0x1B3 +#define EMIF_SDCFG 0x62A73832 +#define EMIF_SDREF 0x10001841 +#define EMIF_TIM1 0x1779C9FE +#define EMIF_TIM2 0x50608074 +#define EMIF_TIM3 0x009F857F +#define EMIF_PHYCFG 0x00000110 +#endif + +static struct ddr_data ddr3_data = { + .datardsratio0 = ((RD_DQS<<10) | (RD_DQS<<0)), + .datawdsratio0 = ((WR_DQS<<10) | (WR_DQS<<0)), + .datawiratio0 = ((0x20<<10) | 0x20<<0), + .datagiratio0 = ((0x20<<10) | 0x20<<0), + .datafwsratio0 = ((RD_DQS_GATE<<10) | (RD_DQS_GATE<<0)), + .datawrsratio0 = (((WR_DQS+0x40)<<10) | ((WR_DQS+0x40)<<0)), + .datauserank0delay = 0x1, + .datadldiff0 = 0x0, /* depend on cpu rev, set later */ +}; + +static const struct cmd_control ddr3_ctrl = { + .cmd0csratio = 0x100, + .cmd0dldiff = 0x004, /* reset value is 0x4 */ + .cmd0iclkout = 0x001, + + .cmd1csratio = 0x100, + .cmd1dldiff = 0x004, /* reset value is 0x4 */ + .cmd1iclkout = 0x001, + + .cmd2csratio = 0x100, + .cmd2dldiff = 0x004, /* reset value is 0x4 */ + .cmd2iclkout = 0x001, +}; + +static const struct emif_regs ddr3_emif0_regs = { + .sdram_config = EMIF_SDCFG, + .ref_ctrl = EMIF_SDREF, + .sdram_tim1 = EMIF_TIM1, + .sdram_tim2 = EMIF_TIM2, + .sdram_tim3 = EMIF_TIM3, + .emif_ddr_phy_ctlr_1 = EMIF_PHYCFG, +}; + +static const struct emif_regs ddr3_emif1_regs = { + .sdram_config = EMIF_SDCFG, + .ref_ctrl = EMIF_SDREF, + .sdram_tim1 = EMIF_TIM1, + .sdram_tim2 = EMIF_TIM2, + .sdram_tim3 = EMIF_TIM3, + .emif_ddr_phy_ctlr_1 = EMIF_PHYCFG, +}; + +void set_uart_mux_conf(void) {} + +void set_mux_conf_regs(void) +{ + configure_module_pin_mux(mmc_pin_mux); +} + +void sdram_init(void) +{ + config_dmm(&evm_lisa_map_regs); + +#ifdef CONFIG_TI816X_EVM_DDR2 + ddr2_data.datadldiff0 = (get_cpu_rev() == 0x1 ? 0x0 : 0xF); + ddr2_ctrl.cmd0dldiff = (get_cpu_rev() == 0x1 ? 0x0 : 0xF); + ddr2_ctrl.cmd1dldiff = (get_cpu_rev() == 0x1 ? 0x0 : 0xF); + ddr2_ctrl.cmd2dldiff = (get_cpu_rev() == 0x1 ? 0x0 : 0xF); + + if (CONFIG_TI816X_USE_EMIF0) { + ddr2_emif0_regs.emif_ddr_phy_ctlr_1 = + (get_cpu_rev() == 0x1 ? 0x0000010B : 0x0000030B); + config_ddr(0, 0, &ddr2_data, &ddr2_ctrl, &ddr2_emif0_regs, 0); + } + + if (CONFIG_TI816X_USE_EMIF1) { + ddr2_emif1_regs.emif_ddr_phy_ctlr_1 = + (get_cpu_rev() == 0x1 ? 0x0000010B : 0x0000030B); + config_ddr(1, 0, &ddr2_data, &ddr2_ctrl, &ddr2_emif1_regs, 1); + } +#endif + +#ifdef CONFIG_TI816X_EVM_DDR3 + ddr3_data.datadldiff0 = (get_cpu_rev() == 0x1 ? 0x0 : 0xF); + + if (CONFIG_TI816X_USE_EMIF0) + config_ddr(0, 0, &ddr3_data, &ddr3_ctrl, &ddr3_emif0_regs, 0); + + if (CONFIG_TI816X_USE_EMIF1) + config_ddr(1, 0, &ddr3_data, &ddr3_ctrl, &ddr3_emif1_regs, 1); +#endif +} +#endif /* CONFIG_SPL_BUILD */ diff --git a/boards.cfg b/boards.cfg index dd2cd98..eec6161 100644 --- a/boards.cfg +++ b/boards.cfg @@ -250,6 +250,7 @@ am335x_evm_uart4 arm armv7 am335x ti am335x_evm_uart5 arm armv7 am335x ti am33xx am335x_evm:SERIAL6,CONS_INDEX=6 am335x_evm_usbspl arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,SPL_USBETH_SUPPORT ti814x_evm arm armv7 ti814x ti am33xx +ti816x_evm arm armv7 ti816x ti am33xx pcm051 arm armv7 pcm051 phytec am33xx pcm051 sama5d3xek_mmc arm armv7 sama5d3xek atmel at91 sama5d3xek:SAMA5D3,SYS_USE_MMC sama5d3xek_nandflash arm armv7 sama5d3xek atmel at91 sama5d3xek:SAMA5D3,SYS_USE_NANDFLASH diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h new file mode 100644 index 0000000..e9e3b5b --- /dev/null +++ b/include/configs/ti816x_evm.h @@ -0,0 +1,180 @@ +/* + * ti816x_evm.h + * + * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> + * Antoine Tenart, <atenart(a)adeneo-embedded.com> + * + * This file is released under the terms of GPL v2 and any later version. + * See the file COPYING in the root directory of the source tree for details. + */ + +#ifndef __CONFIG_TI816X_EVM_H +#define __CONFIG_TI816X_EVM_H + +#define CONFIG_TI81XX +#define CONFIG_TI816X +#define CONFIG_SYS_NO_FLASH +#define CONFIG_OMAP + +#define CONFIG_ARCH_CPU_INIT + +#include <asm/arch/omap.h> + +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (32 * 1024)) +#define CONFIG_SYS_LONGHELP /* undef save memory */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT "u-boot/ti816x# " +#define CONFIG_MACH_TYPE MACH_TYPE_TI8168EVM + +#define CONFIG_OF_LIBFDT +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG /* required for ramdisk support */ + +#include <config_cmd_default.h> /* u-boot default commands */ + +#define CONFIG_VERSION_VARIABLE +#define CONFIG_DISPLAY_CPUINFO + +#define CONFIG_BOOTDELAY 3 /* set negative for no autoboot */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x81000000\0" \ + +#define CONFIG_BOOTCOMMAND \ + "mmc rescan;" \ + "fatload mmc 0 ${loadaddr} uImage;" \ + "bootm ${loadaddr}" \ + +#define CONFIG_BOOTARGS "console=ttyO2,115200n8 noinitrd earlyprintk" + +/* Clock Defines */ +#define V_OSCK 24000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) + +#define CONFIG_SYS_MAXARGS 32 +#define CONFIG_SYS_CBSIZE 512 /* console I/O buffer size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ + + sizeof(CONFIG_SYS_PROMPT) + 16) /* print buffer size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* boot arg buffer size */ + +#undef CONFIG_SYS_CLKS_IN_HZ +#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */ +#define CONFIG_SYS_HZ 1000 /* 1ms clock */ + +#define CONFIG_CMD_ASKEN +#define CONFIG_CMD_ECHO +#define CONFIG_OMAP_GPIO +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_OMAP_HSMMC +#define CONFIG_CMD_MMC +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 + +#define CONFIG_FS_FAT + +/* + * Only one of the following two options (DDR3/DDR2) should be enabled + * CONFIG_TI816X_EVM_DDR2 + * CONFIG_TI816X_EVM_DDR3 + */ +#define CONFIG_TI816X_EVM_DDR3 + +/* + * Supported values: 400, 531, 675 or 796 MHz + */ +#define CONFIG_TI816X_DDR_PLL_796 + +#define CONFIG_TI816X_USE_EMIF0 1 +#define CONFIG_TI816X_USE_EMIF1 1 + + +#define CONFIG_NR_DRAM_BANKS 2 /* we have 2 banks of DRAM */ +#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */ +#define PHYS_DRAM_1_SIZE 0x40000000 /* 1 GB */ +#define PHYS_DRAM_2 0xC0000000 /* DRAM Bank #2 */ +#define PHYS_DRAM_2_SIZE 0x40000000 /* 1 GB */ + +#define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2048MB */ +#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ + GENERATED_GBL_DATA_SIZE) + +/** + * Platform/Board specific defs + */ +#define CONFIG_SYS_CLK_FREQ 27000000 +#define CONFIG_SYS_TIMERBASE 0x4802E000 +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ + +#undef CONFIG_NAND_OMAP_GPMC + +/* + * NS16550 Configuration + */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK (48000000) +#define CONFIG_SYS_NS16550_COM1 0x48024000 /* Base EVM has UART2 */ + +#define CONFIG_BAUDRATE 115200 + +/* allow overwriting serial config and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_SERIAL1 +#define CONFIG_SERIAL2 +#define CONFIG_SERIAL3 +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_CONSOLE_INFO_QUIET + +#define CONFIG_ENV_IS_NOWHERE + +/* SPL */ +/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE 0x40400000 +#define CONFIG_SPL_MAX_SIZE ((128 - 18) * 1024) +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR + +#define CONFIG_SPL_BSS_START_ADDR 0x80000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ + +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_YMODEM_SUPPORT +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 +#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" + +#define CONFIG_SPL_BOARD_INIT + +#define CONFIG_SYS_TEXT_BASE 0x80800000 +#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 + +/* Since SPL did pll and ddr initialization for us, + * we don't need to do it twice. + */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif + +/* Unsupported features */ +#undef CONFIG_USE_IRQ + +#endif -- 1.7.10.4

1 0

[U-Boot] [PATCH v6 2/3] Add TI816X support
by TENART Antoine 02 Jul '13

02 Jul '13

Signed-off-by: Antoine Tenart <atenart(a)adeneo-embedded.com> --- arch/arm/cpu/armv7/am33xx/Makefile | 1 + arch/arm/cpu/armv7/am33xx/clock_ti814x.c | 95 ----- arch/arm/cpu/armv7/am33xx/clock_ti816x.c | 445 ++++++++++++++++++++ arch/arm/cpu/armv7/am33xx/emif4.c | 2 + arch/arm/include/asm/arch-am33xx/clock.h | 4 + arch/arm/include/asm/arch-am33xx/clock_ti81xx.h | 142 +++++++ arch/arm/include/asm/arch-am33xx/ddr_defs.h | 35 +- arch/arm/include/asm/arch-am33xx/hardware.h | 10 +- arch/arm/include/asm/arch-am33xx/hardware_am33xx.h | 6 + arch/arm/include/asm/arch-am33xx/hardware_ti814x.h | 6 + arch/arm/include/asm/arch-am33xx/hardware_ti816x.h | 57 +++ arch/arm/include/asm/arch-am33xx/mmc_host_def.h | 3 + arch/arm/include/asm/arch-am33xx/mux.h | 2 + arch/arm/include/asm/arch-am33xx/mux_ti816x.h | 363 ++++++++++++++++ arch/arm/include/asm/arch-am33xx/spl.h | 11 +- 15 files changed, 1065 insertions(+), 117 deletions(-) create mode 100644 arch/arm/cpu/armv7/am33xx/clock_ti816x.c create mode 100644 arch/arm/include/asm/arch-am33xx/clock_ti81xx.h create mode 100644 arch/arm/include/asm/arch-am33xx/hardware_ti816x.h create mode 100644 arch/arm/include/asm/arch-am33xx/mux_ti816x.h diff --git a/arch/arm/cpu/armv7/am33xx/Makefile b/arch/arm/cpu/armv7/am33xx/Makefile index f4ccd2a..8cb7efb 100644 --- a/arch/arm/cpu/armv7/am33xx/Makefile +++ b/arch/arm/cpu/armv7/am33xx/Makefile @@ -18,6 +18,7 @@ LIB = $(obj)lib$(SOC).o COBJS-$(CONFIG_AM33XX) += clock_am33xx.o COBJS-$(CONFIG_TI814X) += clock_ti814x.o +COBJS-$(CONFIG_TI816X) += clock_ti816x.o COBJS-$(CONFIG_AM33XX) += clock.o COBJS += sys_info.o COBJS += mem.o diff --git a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c index ca7d7ad..17913e7 100644 --- a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c +++ b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c @@ -108,103 +108,8 @@ struct ad_pll { #define OSC_SRC_CTRL (PLL_SUBSYS_BASE + 0x2C0) -/* PRCM */ #define ENET_CLKCTRL_CMPL 0x30000 -#define CM_DEFAULT_BASE (PRCM_BASE + 0x0500) - -struct cm_def { - unsigned int resv0[2]; - unsigned int l3fastclkstctrl; - unsigned int resv1[1]; - unsigned int pciclkstctrl; - unsigned int resv2[1]; - unsigned int ducaticlkstctrl; - unsigned int resv3[1]; - unsigned int emif0clkctrl; - unsigned int emif1clkctrl; - unsigned int dmmclkctrl; - unsigned int fwclkctrl; - unsigned int resv4[10]; - unsigned int usbclkctrl; - unsigned int resv5[1]; - unsigned int sataclkctrl; - unsigned int resv6[4]; - unsigned int ducaticlkctrl; - unsigned int pciclkctrl; -}; - -#define CM_ALWON_BASE (PRCM_BASE + 0x1400) - -struct cm_alwon { - unsigned int l3slowclkstctrl; - unsigned int ethclkstctrl; - unsigned int l3medclkstctrl; - unsigned int mmu_clkstctrl; - unsigned int mmucfg_clkstctrl; - unsigned int ocmc0clkstctrl; - unsigned int vcpclkstctrl; - unsigned int mpuclkstctrl; - unsigned int sysclk4clkstctrl; - unsigned int sysclk5clkstctrl; - unsigned int sysclk6clkstctrl; - unsigned int rtcclkstctrl; - unsigned int l3fastclkstctrl; - unsigned int resv0[67]; - unsigned int mcasp0clkctrl; - unsigned int mcasp1clkctrl; - unsigned int mcasp2clkctrl; - unsigned int mcbspclkctrl; - unsigned int uart0clkctrl; - unsigned int uart1clkctrl; - unsigned int uart2clkctrl; - unsigned int gpio0clkctrl; - unsigned int gpio1clkctrl; - unsigned int i2c0clkctrl; - unsigned int i2c1clkctrl; - unsigned int mcasp345clkctrl; - unsigned int atlclkctrl; - unsigned int mlbclkctrl; - unsigned int pataclkctrl; - unsigned int resv1[1]; - unsigned int uart3clkctrl; - unsigned int uart4clkctrl; - unsigned int uart5clkctrl; - unsigned int wdtimerclkctrl; - unsigned int spiclkctrl; - unsigned int mailboxclkctrl; - unsigned int spinboxclkctrl; - unsigned int mmudataclkctrl; - unsigned int resv2[2]; - unsigned int mmucfgclkctrl; - unsigned int resv3[2]; - unsigned int ocmc0clkctrl; - unsigned int vcpclkctrl; - unsigned int resv4[2]; - unsigned int controlclkctrl; - unsigned int resv5[2]; - unsigned int gpmcclkctrl; - unsigned int ethernet0clkctrl; - unsigned int ethernet1clkctrl; - unsigned int mpuclkctrl; - unsigned int debugssclkctrl; - unsigned int l3clkctrl; - unsigned int l4hsclkctrl; - unsigned int l4lsclkctrl; - unsigned int rtcclkctrl; - unsigned int tpccclkctrl; - unsigned int tptc0clkctrl; - unsigned int tptc1clkctrl; - unsigned int tptc2clkctrl; - unsigned int tptc3clkctrl; - unsigned int resv7[4]; - unsigned int dcan01clkctrl; - unsigned int mmchs0clkctrl; - unsigned int mmchs1clkctrl; - unsigned int mmchs2clkctrl; - unsigned int custefuseclkctrl; -}; - #define SATA_PLL_BASE (CTRL_BASE + 0x0720) struct sata_pll { diff --git a/arch/arm/cpu/armv7/am33xx/clock_ti816x.c b/arch/arm/cpu/armv7/am33xx/clock_ti816x.c new file mode 100644 index 0000000..ace4a5a --- /dev/null +++ b/arch/arm/cpu/armv7/am33xx/clock_ti816x.c @@ -0,0 +1,445 @@ +/* + * clock_ti816x.c + * + * Clocks for TI816X based boards + * + * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> + * Antoine Tenart, <atenart(a)adeneo-embedded.com> + * + * Based on TI-PSP-04.00.02.14 : + * + * Copyright (C) 2009, Texas Instruments, Incorporated + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <common.h> +#include <asm/arch/ddr_defs.h> +#include <asm/arch/cpu.h> +#include <asm/arch/clock.h> +#include <asm/arch/hardware.h> +#include <asm/io.h> + +#include <asm/emif.h> + +#define CM_PLL_BASE (CTRL_BASE + 0x0400) + +/* Main PLL */ +#define MAIN_N 64 +#define MAIN_P 0x1 +#define MAIN_INTFREQ1 0x8 +#define MAIN_FRACFREQ1 0x800000 +#define MAIN_MDIV1 0x2 +#define MAIN_INTFREQ2 0xE +#define MAIN_FRACFREQ2 0x0 +#define MAIN_MDIV2 0x1 +#define MAIN_INTFREQ3 0x8 +#define MAIN_FRACFREQ3 0xAAAAB0 +#define MAIN_MDIV3 0x3 +#define MAIN_INTFREQ4 0x9 +#define MAIN_FRACFREQ4 0x55554F +#define MAIN_MDIV4 0x3 +#define MAIN_INTFREQ5 0x9 +#define MAIN_FRACFREQ5 0x374BC6 +#define MAIN_MDIV5 0xC +#define MAIN_MDIV6 0x48 +#define MAIN_MDIV7 0x4 + +/* DDR PLL */ +#if defined(CONFIG_TI816X_DDR_PLL_400) /* 400 MHz */ +#define DDR_N 59 +#define DDR_P 0x1 +#define DDR_MDIV1 0x4 +#define DDR_INTFREQ2 0x8 +#define DDR_FRACFREQ2 0xD99999 +#define DDR_MDIV2 0x1E +#define DDR_INTFREQ3 0x8 +#define DDR_FRACFREQ3 0x0 +#define DDR_MDIV3 0x4 +#define DDR_INTFREQ4 0xE /* Expansion DDR clk */ +#define DDR_FRACFREQ4 0x0 +#define DDR_MDIV4 0x4 +#define DDR_INTFREQ5 0xE /* Expansion DDR clk */ +#define DDR_FRACFREQ5 0x0 +#define DDR_MDIV5 0x4 +#elif defined(CONFIG_TI816X_DDR_PLL_531) /* 531 MHz */ +#define DDR_N 59 +#define DDR_P 0x1 +#define DDR_MDIV1 0x3 +#define DDR_INTFREQ2 0x8 +#define DDR_FRACFREQ2 0xD99999 +#define DDR_MDIV2 0x1E +#define DDR_INTFREQ3 0x8 +#define DDR_FRACFREQ3 0x0 +#define DDR_MDIV3 0x4 +#define DDR_INTFREQ4 0xE /* Expansion DDR clk */ +#define DDR_FRACFREQ4 0x0 +#define DDR_MDIV4 0x4 +#define DDR_INTFREQ5 0xE /* Expansion DDR clk */ +#define DDR_FRACFREQ5 0x0 +#define DDR_MDIV5 0x4 +#elif defined(CONFIG_TI816X_DDR_PLL_675) /* 675 MHz */ +#define DDR_N 50 +#define DDR_P 0x1 +#define DDR_MDIV1 0x2 +#define DDR_INTFREQ2 0x9 +#define DDR_FRACFREQ2 0x0 +#define DDR_MDIV2 0x19 +#define DDR_INTFREQ3 0x13 +#define DDR_FRACFREQ3 0x800000 +#define DDR_MDIV3 0x2 +#define DDR_INTFREQ4 0xE /* Expansion DDR clk */ +#define DDR_FRACFREQ4 0x0 +#define DDR_MDIV4 0x4 +#define DDR_INTFREQ5 0xE /* Expansion DDR clk */ +#define DDR_FRACFREQ5 0x0 +#define DDR_MDIV5 0x4 +#elif defined(CONFIG_TI816X_DDR_PLL_796) /* 796 MHz */ +#define DDR_N 59 +#define DDR_P 0x1 +#define DDR_MDIV1 0x2 +#define DDR_INTFREQ2 0x8 +#define DDR_FRACFREQ2 0xD99999 +#define DDR_MDIV2 0x1E +#define DDR_INTFREQ3 0x8 +#define DDR_FRACFREQ3 0x0 +#define DDR_MDIV3 0x4 +#define DDR_INTFREQ4 0xE /* Expansion DDR clk */ +#define DDR_FRACFREQ4 0x0 +#define DDR_MDIV4 0x4 +#define DDR_INTFREQ5 0xE /* Expansion DDR clk */ +#define DDR_FRACFREQ5 0x0 +#define DDR_MDIV5 0x4 +#endif + +#define CONTROL_STATUS (CTRL_BASE + 0x40) +#define DDR_RCD (CTRL_BASE + 0x070C) +#define CM_TIMER1_CLKSEL (PRCM_BASE + 0x390) +#define DMM_PAT_BASE_ADDR (DMM_BASE + 0x420) +#define CM_ALWON_CUST_EFUSE_CLKCTRL (PRCM_BASE + 0x1628) + +#define INTCPS_SYSCONFIG 0x48200010 +#define CM_SYSCLK10_CLKSEL 0x48180324 + +struct cm_pll { + unsigned int mainpll_ctrl; /* offset 0x400 */ + unsigned int mainpll_pwd; + unsigned int mainpll_freq1; + unsigned int mainpll_div1; + unsigned int mainpll_freq2; + unsigned int mainpll_div2; + unsigned int mainpll_freq3; + unsigned int mainpll_div3; + unsigned int mainpll_freq4; + unsigned int mainpll_div4; + unsigned int mainpll_freq5; + unsigned int mainpll_div5; + unsigned int resv0[1]; + unsigned int mainpll_div6; + unsigned int resv1[1]; + unsigned int mainpll_div7; + unsigned int ddrpll_ctrl; /* offset 0x440 */ + unsigned int ddrpll_pwd; + unsigned int resv2[1]; + unsigned int ddrpll_div1; + unsigned int ddrpll_freq2; + unsigned int ddrpll_div2; + unsigned int ddrpll_freq3; + unsigned int ddrpll_div3; + unsigned int ddrpll_freq4; + unsigned int ddrpll_div4; + unsigned int ddrpll_freq5; + unsigned int ddrpll_div5; + unsigned int videopll_ctrl; /* offset 0x470 */ + unsigned int videopll_pwd; + unsigned int videopll_freq1; + unsigned int videopll_div1; + unsigned int videopll_freq2; + unsigned int videopll_div2; + unsigned int videopll_freq3; + unsigned int videopll_div3; + unsigned int resv3[4]; + unsigned int audiopll_ctrl; /* offset 0x4A0 */ + unsigned int audiopll_pwd; + unsigned int resv4[2]; + unsigned int audiopll_freq2; + unsigned int audiopll_div2; + unsigned int audiopll_freq3; + unsigned int audiopll_div3; + unsigned int audiopll_freq4; + unsigned int audiopll_div4; + unsigned int audiopll_freq5; + unsigned int audiopll_div5; +}; + +const struct cm_alwon *cmalwon = (struct cm_alwon *)CM_ALWON_BASE; +const struct cm_def *cmdef = (struct cm_def *)CM_DEFAULT_BASE; +const struct cm_pll *cmpll = (struct cm_pll *)CM_PLL_BASE; +const struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; + +void enable_dmm_clocks(void) +{ + writel(PRCM_MOD_EN, &cmdef->l3fastclkstctrl); + writel(PRCM_MOD_EN, &cmdef->emif0clkctrl); + writel(PRCM_MOD_EN, &cmdef->emif1clkctrl); + + /* Wait for clocks to be active */ + while ((readl(&cmdef->l3fastclkstctrl) & 0x300) != 0x300) + ; + /* Wait for emif0 to be fully functional, including OCP */ + while (((readl(&cmdef->emif0clkctrl) >> 17) & 0x3) != 0) + ; + /* Wait for emif1 to be fully functional, including OCP */ + while (((readl(&cmdef->emif1clkctrl) >> 17) & 0x3) != 0) + ; + + writel(PRCM_MOD_EN, &cmdef->dmmclkctrl); + /* Wait for dmm to be fully functional, including OCP */ + while (((readl(&cmdef->dmmclkctrl) >> 17) & 0x3) != 0) + ; + + /* Enable Tiled Access */ + writel(0x80000000, DMM_PAT_BASE_ADDR); +} + +/* assume delay is aprox at least 1us */ +static void ddr_delay(int d) +{ + int i; + + /* + * read a control register. + * this is a bit more delay and cannot be optimized by the compiler + * assuming one read takes 200 cycles and A8 is runing 1 GHz + * somewhat conservative setting + */ + for (i = 0; i < 50*d; i++) + readl(CONTROL_STATUS); +} + +static void main_pll_init_ti816x(void) +{ + u32 main_pll_ctrl = 0; + + /* Put the PLL in bypass mode by setting BIT2 in its ctrl reg */ + main_pll_ctrl = readl(&cmpll->mainpll_ctrl); + main_pll_ctrl &= 0xFFFFFFFB; + main_pll_ctrl |= BIT(2); + writel(main_pll_ctrl, &cmpll->mainpll_ctrl); + + /* Enable PLL by setting BIT3 in its ctrl reg */ + main_pll_ctrl = readl(&cmpll->mainpll_ctrl); + main_pll_ctrl &= 0xFFFFFFF7; + main_pll_ctrl |= BIT(3); + writel(main_pll_ctrl, &cmpll->mainpll_ctrl); + + /* Write the values of N,P in the CTRL reg */ + main_pll_ctrl = readl(&cmpll->mainpll_ctrl); + main_pll_ctrl &= 0xFF; + main_pll_ctrl |= (MAIN_N<<16 | MAIN_P<<8); + writel(main_pll_ctrl, &cmpll->mainpll_ctrl); + + /* Power up clock1-7 */ + writel(0x0, &cmpll->mainpll_pwd); + + /* Program the freq and divider values for clock1-7 */ + writel((1<<31 | 1<<28 | (MAIN_INTFREQ1<<24) | MAIN_FRACFREQ1), + &cmpll->mainpll_freq1); + writel(((1<<8) | MAIN_MDIV1), &cmpll->mainpll_div1); + + writel((1<<31 | 1<<28 | (MAIN_INTFREQ2<<24) | MAIN_FRACFREQ2), + &cmpll->mainpll_freq2); + writel(((1<<8) | MAIN_MDIV2), &cmpll->mainpll_div2); + + writel((1<<31 | 1<<28 | (MAIN_INTFREQ3<<24) | MAIN_FRACFREQ3), + &cmpll->mainpll_freq3); + writel(((1<<8) | MAIN_MDIV3), &cmpll->mainpll_div3); + + writel((1<<31 | 1<<28 | (MAIN_INTFREQ4<<24) | MAIN_FRACFREQ4), + &cmpll->mainpll_freq4); + writel(((1<<8) | MAIN_MDIV4), &cmpll->mainpll_div4); + + writel((1<<31 | 1<<28 | (MAIN_INTFREQ5<<24) | MAIN_FRACFREQ5), + &cmpll->mainpll_freq5); + writel(((1<<8) | MAIN_MDIV5), &cmpll->mainpll_div5); + + writel((1<<8 | MAIN_MDIV6), &cmpll->mainpll_div6); + + writel((1<<8 | MAIN_MDIV7), &cmpll->mainpll_div7); + + /* Wait for PLL to lock */ + while ((readl(&cmpll->mainpll_ctrl) & BIT(7)) != BIT(7)) + ; + + /* Put the PLL in normal mode, disable bypass */ + main_pll_ctrl = readl(&cmpll->mainpll_ctrl); + main_pll_ctrl &= 0xFFFFFFFB; + writel(main_pll_ctrl, &cmpll->mainpll_ctrl); +} + +static void ddr_pll_bypass_ti816x(void) +{ + u32 ddr_pll_ctrl = 0; + + /* Put the PLL in bypass mode by setting BIT2 in its ctrl reg */ + ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl); + ddr_pll_ctrl &= 0xFFFFFFFB; + ddr_pll_ctrl |= BIT(2); + writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl); +} + +static void ddr_pll_init_ti816x(void) +{ + u32 ddr_pll_ctrl = 0; + /* Enable PLL by setting BIT3 in its ctrl reg */ + ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl); + ddr_pll_ctrl &= 0xFFFFFFF7; + ddr_pll_ctrl |= BIT(3); + writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl); + + /* Write the values of N,P in the CTRL reg */ + ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl); + ddr_pll_ctrl &= 0xFF; + ddr_pll_ctrl |= (DDR_N<<16 | DDR_P<<8); + writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl); + + ddr_delay(10); + + /* Power up clock1-5 */ + writel(0x0, &cmpll->ddrpll_pwd); + + /* Program the freq and divider values for clock1-3 */ + writel(((0<<8) | DDR_MDIV1), &cmpll->ddrpll_div1); + ddr_delay(1); + writel(((1<<8) | DDR_MDIV1), &cmpll->ddrpll_div1); + writel((1<<31 | 1<<28 | (DDR_INTFREQ2<<24) | DDR_FRACFREQ2), + &cmpll->ddrpll_freq2); + writel(((1<<8) | DDR_MDIV2), &cmpll->ddrpll_div2); + writel(((0<<8) | DDR_MDIV3), &cmpll->ddrpll_div3); + ddr_delay(1); + writel(((1<<8) | DDR_MDIV3), &cmpll->ddrpll_div3); + ddr_delay(1); + writel((0<<31 | 1<<28 | (DDR_INTFREQ3<<24) | DDR_FRACFREQ3), + &cmpll->ddrpll_freq3); + ddr_delay(1); + writel((1<<31 | 1<<28 | (DDR_INTFREQ3<<24) | DDR_FRACFREQ3), + &cmpll->ddrpll_freq3); + + ddr_delay(5); + + /* Wait for PLL to lock */ + while ((readl(&cmpll->ddrpll_ctrl) & BIT(7)) != BIT(7)) + ; + + /* Power up RCD */ + writel(BIT(0), DDR_RCD); +} + +static void peripheral_enable(void) +{ + /* Wake-up the l3_slow clock */ + writel(PRCM_MOD_EN, &cmalwon->l3slowclkstctrl); + + /* + * Note on Timers: + * There are 8 timers(0-7) out of which timer 0 is a secure timer. + * Timer 0 mux should not be changed + * + * To access the timer registers we need the to be + * enabled which is what we do in the first step + */ + + /* Enable timer1 */ + writel(PRCM_MOD_EN, &cmalwon->timer1clkctrl); + /* Select timer1 clock to be CLKIN (27MHz) */ + writel(BIT(1), CM_TIMER1_CLKSEL); + + /* Wait for timer1 to be ON-ACTIVE */ + while (((readl(&cmalwon->l3slowclkstctrl) + & (0x80000<<1))>>20) != 1) + ; + /* Wait for timer1 to be enabled */ + while (((readl(&cmalwon->timer1clkctrl) & 0x30000)>>16) != 0) + ; + /* Active posted mode */ + writel(PRCM_MOD_EN, (DM_TIMER1_BASE + 0x54)); + while (readl(DM_TIMER1_BASE + 0x10) & BIT(0)) + ; + /* Start timer1 */ + writel(BIT(0), (DM_TIMER1_BASE + 0x38)); + + /* eFuse */ + writel(PRCM_MOD_EN, CM_ALWON_CUST_EFUSE_CLKCTRL); + while (readl(CM_ALWON_CUST_EFUSE_CLKCTRL) != PRCM_MOD_EN) + ; + + /* Enable gpio0 */ + writel(PRCM_MOD_EN, &cmalwon->gpio0clkctrl); + while (readl(&cmalwon->gpio0clkctrl) != PRCM_MOD_EN) + ; + writel((BIT(8)), &cmalwon->gpio0clkctrl); + + /* Enable spi */ + writel(PRCM_MOD_EN, &cmalwon->spiclkctrl); + while (readl(&cmalwon->spiclkctrl) != PRCM_MOD_EN) + ; + + /* Enable i2c0 */ + writel(PRCM_MOD_EN, &cmalwon->i2c0clkctrl); + while (readl(&cmalwon->i2c0clkctrl) != PRCM_MOD_EN) + ; + + /* Enable ethernet0 */ + writel(PRCM_MOD_EN, &cmalwon->ethclkstctrl); + writel(PRCM_MOD_EN, &cmalwon->ethernet0clkctrl); + writel(PRCM_MOD_EN, &cmalwon->ethernet1clkctrl); + + /* Enable hsmmc */ + writel(PRCM_MOD_EN, &cmalwon->sdioclkctrl); + while (readl(&cmalwon->sdioclkctrl) != PRCM_MOD_EN) + ; +} + +void setup_clocks_for_console(void) +{ + /* Fix ROM code bug - from TI-PSP-04.00.02.14 */ + writel(0x0, CM_SYSCLK10_CLKSEL); + + ddr_pll_bypass_ti816x(); + + /* Enable uart0-2 */ + writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl); + while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN) + ; + writel(PRCM_MOD_EN, &cmalwon->uart1clkctrl); + while (readl(&cmalwon->uart1clkctrl) != PRCM_MOD_EN) + ; + writel(PRCM_MOD_EN, &cmalwon->uart2clkctrl); + while (readl(&cmalwon->uart2clkctrl) != PRCM_MOD_EN) + ; + while ((readl(&cmalwon->l3slowclkstctrl) & 0x2100) != 0x2100) + ; +} + +void prcm_init(void) +{ + /* Enable the control */ + writel(PRCM_MOD_EN, &cmalwon->controlclkctrl); + + main_pll_init_ti816x(); + ddr_pll_init_ti816x(); + + /* + * With clk freqs setup to desired values, + * enable the required peripherals + */ + peripheral_enable(); +} diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c index 3abb609..7340c4b 100644 --- a/arch/arm/cpu/armv7/am33xx/emif4.c +++ b/arch/arm/cpu/armv7/am33xx/emif4.c @@ -94,7 +94,9 @@ void config_ddr(unsigned int pll, unsigned int ioctrl, const struct emif_regs *regs, int nr) { ddr_pll_config(pll); +#ifndef CONFIG_TI816X config_vtp(nr); +#endif config_cmd_ctrl(ctrl, nr); config_ddr_data(data, nr); diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h index ff9d616..f212add 100644 --- a/arch/arm/include/asm/arch-am33xx/clock.h +++ b/arch/arm/include/asm/arch-am33xx/clock.h @@ -21,6 +21,10 @@ #include <asm/arch/clocks_am33xx.h> +#ifdef CONFIG_TI81XX +#include <asm/arch/clock_ti81xx.h> +#endif + #define LDELAY 1000000 /*CM_<clock_domain>__CLKCTRL */ diff --git a/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h b/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h new file mode 100644 index 0000000..f069922 --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h @@ -0,0 +1,142 @@ +/* + * ti81xx.h + * + * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> + * Antoine Tenart, <atenart(a)adeneo-embedded.com> + * + * This file is released under the terms of GPL v2 and any later version. + * See the file COPYING in the root directory of the source tree for details. + */ + +#ifndef _CLOCK_TI81XX_H_ +#define _CLOCK_TI81XX_H_ + +#define PRCM_MOD_EN 0x2 + +#define CM_DEFAULT_BASE (PRCM_BASE + 0x0500) +#define CM_ALWON_BASE (PRCM_BASE + 0x1400) + +struct cm_def { + unsigned int resv0[2]; + unsigned int l3fastclkstctrl; + unsigned int resv1[1]; + unsigned int pciclkstctrl; + unsigned int resv2[1]; + unsigned int ducaticlkstctrl; + unsigned int resv3[1]; + unsigned int emif0clkctrl; + unsigned int emif1clkctrl; + unsigned int dmmclkctrl; + unsigned int fwclkctrl; + unsigned int resv4[10]; + unsigned int usbclkctrl; + unsigned int resv5[1]; + unsigned int sataclkctrl; + unsigned int resv6[4]; + unsigned int ducaticlkctrl; + unsigned int pciclkctrl; +}; + +struct cm_alwon { + unsigned int l3slowclkstctrl; + unsigned int ethclkstctrl; + unsigned int l3medclkstctrl; + unsigned int mmu_clkstctrl; + unsigned int mmucfg_clkstctrl; + unsigned int ocmc0clkstctrl; +#if defined(CONFIG_TI814X) + unsigned int vcpclkstctrl; +#elif defined(CONFIG_TI816X) + unsigned int ocmc1clkstctrl; +#endif + unsigned int mpuclkstctrl; + unsigned int sysclk4clkstctrl; + unsigned int sysclk5clkstctrl; + unsigned int sysclk6clkstctrl; + unsigned int rtcclkstctrl; + unsigned int l3fastclkstctrl; + unsigned int resv0[67]; + unsigned int mcasp0clkctrl; + unsigned int mcasp1clkctrl; + unsigned int mcasp2clkctrl; + unsigned int mcbspclkctrl; + unsigned int uart0clkctrl; + unsigned int uart1clkctrl; + unsigned int uart2clkctrl; + unsigned int gpio0clkctrl; + unsigned int gpio1clkctrl; + unsigned int i2c0clkctrl; + unsigned int i2c1clkctrl; +#if defined(CONFIG_TI814X) + unsigned int mcasp345clkctrl; + unsigned int atlclkctrl; + unsigned int mlbclkctrl; + unsigned int pataclkctrl; + unsigned int resv1[1]; + unsigned int uart3clkctrl; + unsigned int uart4clkctrl; + unsigned int uart5clkctrl; +#elif defined(CONFIG_TI816X) + unsigned int resv1[1]; + unsigned int timer1clkctrl; + unsigned int timer2clkctrl; + unsigned int timer3clkctrl; + unsigned int timer4clkctrl; + unsigned int timer5clkctrl; + unsigned int timer6clkctrl; + unsigned int timer7clkctrl; +#endif + unsigned int wdtimerclkctrl; + unsigned int spiclkctrl; + unsigned int mailboxclkctrl; + unsigned int spinboxclkctrl; + unsigned int mmudataclkctrl; + unsigned int resv2[2]; + unsigned int mmucfgclkctrl; +#if defined(CONFIG_TI814X) + unsigned int resv3[2]; +#elif defined(CONFIG_TI816X) + unsigned int resv3[1]; + unsigned int sdioclkctrl; +#endif + unsigned int ocmc0clkctrl; +#if defined(CONFIG_TI814X) + unsigned int vcpclkctrl; +#elif defined(CONFIG_TI816X) + unsigned int ocmc1clkctrl; +#endif + unsigned int resv4[2]; + unsigned int controlclkctrl; + unsigned int resv5[2]; + unsigned int gpmcclkctrl; + unsigned int ethernet0clkctrl; + unsigned int ethernet1clkctrl; + unsigned int mpuclkctrl; +#if defined(CONFIG_TI814X) + unsigned int debugssclkctrl; +#elif defined(CONFIG_TI816X) + unsigned int resv6[1]; +#endif + unsigned int l3clkctrl; + unsigned int l4hsclkctrl; + unsigned int l4lsclkctrl; + unsigned int rtcclkctrl; + unsigned int tpccclkctrl; + unsigned int tptc0clkctrl; + unsigned int tptc1clkctrl; + unsigned int tptc2clkctrl; + unsigned int tptc3clkctrl; +#if defined(CONFIG_TI814X) + unsigned int resv6[4]; + unsigned int dcan01clkctrl; + unsigned int mmchs0clkctrl; + unsigned int mmchs1clkctrl; + unsigned int mmchs2clkctrl; + unsigned int custefuseclkctrl; +#elif defined(CONFIG_TI816X) + unsigned int sr0clkctrl; + unsigned int sr1clkctrl; +#endif +}; + +#endif /* _CLOCK_TI81XX_H_ */ diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index bb53a6a..374edbf 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -200,37 +200,46 @@ struct ddr_data_regs { * correspond to DATA1 registers defined here. */ struct ddr_regs { - unsigned int resv0[7]; - unsigned int cm0csratio; /* offset 0x01C */ + unsigned int resv0[3]; + unsigned int cm0config; /* offset 0x00C */ + unsigned int cm0configclk; /* offset 0x010 */ unsigned int resv1[2]; + unsigned int cm0csratio; /* offset 0x01C */ + unsigned int resv2[2]; unsigned int cm0dldiff; /* offset 0x028 */ unsigned int cm0iclkout; /* offset 0x02C */ - unsigned int resv2[8]; + unsigned int resv3[4]; + unsigned int cm1config; /* offset 0x040 */ + unsigned int cm1configclk; /* offset 0x044 */ + unsigned int resv4[2]; unsigned int cm1csratio; /* offset 0x050 */ - unsigned int resv3[2]; + unsigned int resv5[2]; unsigned int cm1dldiff; /* offset 0x05C */ unsigned int cm1iclkout; /* offset 0x060 */ - unsigned int resv4[8]; + unsigned int resv6[4]; + unsigned int cm2config; /* offset 0x074 */ + unsigned int cm2configclk; /* offset 0x078 */ + unsigned int resv7[2]; unsigned int cm2csratio; /* offset 0x084 */ - unsigned int resv5[2]; + unsigned int resv8[2]; unsigned int cm2dldiff; /* offset 0x090 */ unsigned int cm2iclkout; /* offset 0x094 */ - unsigned int resv6[12]; + unsigned int resv9[12]; unsigned int dt0rdsratio0; /* offset 0x0C8 */ - unsigned int resv7[4]; + unsigned int resv10[4]; unsigned int dt0wdsratio0; /* offset 0x0DC */ - unsigned int resv8[4]; + unsigned int resv11[4]; unsigned int dt0wiratio0; /* offset 0x0F0 */ - unsigned int resv9; + unsigned int resv12; unsigned int dt0wimode0; /* offset 0x0F8 */ unsigned int dt0giratio0; /* offset 0x0FC */ - unsigned int resv10; + unsigned int resv13; unsigned int dt0gimode0; /* offset 0x104 */ unsigned int dt0fwsratio0; /* offset 0x108 */ - unsigned int resv11[4]; + unsigned int resv14[4]; unsigned int dt0dqoffset; /* offset 0x11C */ unsigned int dt0wrsratio0; /* offset 0x120 */ - unsigned int resv12[4]; + unsigned int resv15[4]; unsigned int dt0rdelays0; /* offset 0x134 */ unsigned int dt0dldiff0; /* offset 0x138 */ }; diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h index 5a27f9c..5106d7b 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware.h +++ b/arch/arm/include/asm/arch-am33xx/hardware.h @@ -23,6 +23,8 @@ #include <asm/arch/omap.h> #ifdef CONFIG_AM33XX #include <asm/arch/hardware_am33xx.h> +#elif defined(CONFIG_TI816X) +#include <asm/arch/hardware_ti816x.h> #elif defined(CONFIG_TI814X) #include <asm/arch/hardware_ti814x.h> #endif @@ -61,21 +63,13 @@ #define CM_CEFUSE 0x44E00A00 #define PRM_DEVICE 0x44E00F00 -/* VTP Base address */ -#define VTP1_CTRL_ADDR 0x48140E10 - /* DDR Base address */ #define DDR_CTRL_ADDR 0x44E10E04 #define DDR_CONTROL_BASE_ADDR 0x44E11404 -#define DDR_PHY_CMD_ADDR2 0x47C0C800 -#define DDR_PHY_DATA_ADDR2 0x47C0C8C8 /* UART */ #define DEFAULT_UART_BASE UART0_BASE -#define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400) -#define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE - /* GPMC Base address */ #define GPMC_BASE 0x50000000 diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h index fa02f19..8df60ac 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h @@ -39,12 +39,18 @@ /* VTP Base address */ #define VTP0_CTRL_ADDR 0x44E10E0C +#define VTP1_CTRL_ADDR 0x48140E10 /* DDR Base address */ #define DDR_PHY_CMD_ADDR 0x44E12000 #define DDR_PHY_DATA_ADDR 0x44E120C8 +#define DDR_PHY_CMD_ADDR2 0x47C0C800 +#define DDR_PHY_DATA_ADDR2 0x47C0C8C8 #define DDR_DATA_REGS_NR 2 +#define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400) +#define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE + /* CPSW Config space */ #define CPSW_MDIO_BASE 0x4A101000 diff --git a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h index 8f9315c..2ac6b7d 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h @@ -39,12 +39,18 @@ /* VTP Base address */ #define VTP0_CTRL_ADDR 0x48140E0C +#define VTP1_CTRL_ADDR 0x48140E10 /* DDR Base address */ #define DDR_PHY_CMD_ADDR 0x47C0C400 #define DDR_PHY_DATA_ADDR 0x47C0C4C8 +#define DDR_PHY_CMD_ADDR2 0x47C0C800 +#define DDR_PHY_DATA_ADDR2 0x47C0C8C8 #define DDR_DATA_REGS_NR 4 +#define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400) +#define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE + /* CPSW Config space */ #define CPSW_MDIO_BASE 0x4A100800 diff --git a/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h b/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h new file mode 100644 index 0000000..141b703 --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h @@ -0,0 +1,57 @@ +/* + * hardware_ti816x.h + * + * TI816x hardware specific header + * + * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> + * Antoine Tenart, <atenart(a)adeneo-embedded.com> + * Based on TI-PSP-04.00.02.14 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AM33XX_HARDWARE_TI816X_H +#define __AM33XX_HARDWARE_TI816X_H + +/* Watchdog Timer */ +#define WDT_BASE 0x480C2000 + +/* Control Module Base Address */ +#define CTRL_BASE 0x48140000 + +/* PRCM Base Address */ +#define PRCM_BASE 0x48180000 + +/* VTP Base address */ +#define VTP0_CTRL_ADDR 0x48198358 +#define VTP1_CTRL_ADDR 0x4819A358 + +/* DDR Base address */ +#define DDR_PHY_CMD_ADDR 0x48198000 +#define DDR_PHY_DATA_ADDR 0x481980C8 +#define DDR_PHY_CMD_ADDR2 0x4819A000 +#define DDR_PHY_DATA_ADDR2 0x4819A0C8 +#define DDR_DATA_REGS_NR 4 + +/* UART */ +#define UART0_BASE 0x48020000 +#define UART1_BASE 0x48022000 +#define UART2_BASE 0x48024000 + +#define DDRPHY_0_CONFIG_BASE 0x48198000 +#define DDRPHY_1_CONFIG_BASE 0x4819A000 +#define DDRPHY_CONFIG_BASE ((emif == 0) ? \ + DDRPHY_0_CONFIG_BASE : DDRPHY_1_CONFIG_BASE) + +/* RTC base address */ +#define RTC_BASE 0x480C0000 + +#endif /* __AM33XX_HARDWARE_TI816X_H */ diff --git a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h index 51ba791..724e252 100644 --- a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h +++ b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h @@ -27,6 +27,9 @@ #if defined(CONFIG_TI814X) #undef MMC_CLOCK_REFERENCE #define MMC_CLOCK_REFERENCE 192 /* MHz */ +#elif defined(CONFIG_TI816X) +#undef MMC_CLOCK_REFERENCE +#define MMC_CLOCK_REFERENCE 48 /* MHz */ #endif #endif /* MMC_HOST_DEF_H */ diff --git a/arch/arm/include/asm/arch-am33xx/mux.h b/arch/arm/include/asm/arch-am33xx/mux.h index 1c6b65f..4caa4d8 100644 --- a/arch/arm/include/asm/arch-am33xx/mux.h +++ b/arch/arm/include/asm/arch-am33xx/mux.h @@ -23,6 +23,8 @@ #include <asm/arch/mux_am33xx.h> #elif defined(CONFIG_TI814X) #include <asm/arch/mux_ti814x.h> +#elif defined(CONFIG_TI816X) +#include <asm/arch/mux_ti816x.h> #endif struct module_pin_mux { diff --git a/arch/arm/include/asm/arch-am33xx/mux_ti816x.h b/arch/arm/include/asm/arch-am33xx/mux_ti816x.h new file mode 100644 index 0000000..e4e5a48 --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/mux_ti816x.h @@ -0,0 +1,363 @@ +/* + * mux_ti816x.h + * + * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> + * Antoine Tenart, <atenart(a)adeneo-embedded.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _MUX_TI816X_H_ +#define _MUX_TI816X_H_ + +#include <common.h> +#include <asm/io.h> + +#define MUX_CFG(value, offset) \ + __raw_writel(value, (CTRL_BASE + offset)); + +#define PULLDOWN_EN (0x0 << 4) /* Pull Down Selection */ +#define PULLUP_EN (0x1 << 4) /* Pull Up Selection */ +#define PULLUDEN (0x0 << 3) /* Pull up enabled */ +#define PULLUDDIS (0x1 << 3) /* Pull up disabled */ +#define MODE(val) (val) /* used for Readability */ + + +/* + * PAD CONTROL OFFSETS + * Field names corresponds to the pad signal name + */ +struct pad_signals { + int pincntl1; + int pincntl2; + int pincntl3; + int pincntl4; + int pincntl5; + int pincntl6; + int pincntl7; + int pincntl8; + int pincntl9; + int pincntl10; + int pincntl11; + int pincntl12; + int pincntl13; + int pincntl14; + int pincntl15; + int pincntl16; + int pincntl17; + int pincntl18; + int pincntl19; + int pincntl20; + int pincntl21; + int pincntl22; + int pincntl23; + int pincntl24; + int pincntl25; + int pincntl26; + int pincntl27; + int pincntl28; + int pincntl29; + int pincntl30; + int pincntl31; + int pincntl32; + int pincntl33; + int pincntl34; + int pincntl35; + int pincntl36; + int pincntl37; + int pincntl38; + int pincntl39; + int pincntl40; + int pincntl41; + int pincntl42; + int pincntl43; + int pincntl44; + int pincntl45; + int pincntl46; + int pincntl47; + int pincntl48; + int pincntl49; + int pincntl50; + int pincntl51; + int pincntl52; + int pincntl53; + int pincntl54; + int pincntl55; + int pincntl56; + int pincntl57; + int pincntl58; + int pincntl59; + int pincntl60; + int pincntl61; + int pincntl62; + int pincntl63; + int pincntl64; + int pincntl65; + int pincntl66; + int pincntl67; + int pincntl68; + int pincntl69; + int pincntl70; + int pincntl71; + int pincntl72; + int pincntl73; + int pincntl74; + int pincntl75; + int pincntl76; + int pincntl77; + int pincntl78; + int pincntl79; + int pincntl80; + int pincntl81; + int pincntl82; + int pincntl83; + int pincntl84; + int pincntl85; + int pincntl86; + int pincntl87; + int pincntl88; + int pincntl89; + int pincntl90; + int pincntl91; + int pincntl92; + int pincntl93; + int pincntl94; + int pincntl95; + int pincntl96; + int pincntl97; + int pincntl98; + int pincntl99; + int pincntl100; + int pincntl101; + int pincntl102; + int pincntl103; + int pincntl104; + int pincntl105; + int pincntl106; + int pincntl107; + int pincntl108; + int pincntl109; + int pincntl110; + int pincntl111; + int pincntl112; + int pincntl113; + int pincntl114; + int pincntl115; + int pincntl116; + int pincntl117; + int pincntl118; + int pincntl119; + int pincntl120; + int pincntl121; + int pincntl122; + int pincntl123; + int pincntl124; + int pincntl125; + int pincntl126; + int pincntl127; + int pincntl128; + int pincntl129; + int pincntl130; + int pincntl131; + int pincntl132; + int pincntl133; + int pincntl134; + int pincntl135; + int pincntl136; + int pincntl137; + int pincntl138; + int pincntl139; + int pincntl140; + int pincntl141; + int pincntl142; + int pincntl143; + int pincntl144; + int pincntl145; + int pincntl146; + int pincntl147; + int pincntl148; + int pincntl149; + int pincntl150; + int pincntl151; + int pincntl152; + int pincntl153; + int pincntl154; + int pincntl155; + int pincntl156; + int pincntl157; + int pincntl158; + int pincntl159; + int pincntl160; + int pincntl161; + int pincntl162; + int pincntl163; + int pincntl164; + int pincntl165; + int pincntl166; + int pincntl167; + int pincntl168; + int pincntl169; + int pincntl170; + int pincntl171; + int pincntl172; + int pincntl173; + int pincntl174; + int pincntl175; + int pincntl176; + int pincntl177; + int pincntl178; + int pincntl179; + int pincntl180; + int pincntl181; + int pincntl182; + int pincntl183; + int pincntl184; + int pincntl185; + int pincntl186; + int pincntl187; + int pincntl188; + int pincntl189; + int pincntl190; + int pincntl191; + int pincntl192; + int pincntl193; + int pincntl194; + int pincntl195; + int pincntl196; + int pincntl197; + int pincntl198; + int pincntl199; + int pincntl200; + int pincntl201; + int pincntl202; + int pincntl203; + int pincntl204; + int pincntl205; + int pincntl206; + int pincntl207; + int pincntl208; + int pincntl209; + int pincntl210; + int pincntl211; + int pincntl212; + int pincntl213; + int pincntl214; + int pincntl215; + int pincntl216; + int pincntl217; + int pincntl218; + int pincntl219; + int pincntl220; + int pincntl221; + int pincntl222; + int pincntl223; + int pincntl224; + int pincntl225; + int pincntl226; + int pincntl227; + int pincntl228; + int pincntl229; + int pincntl230; + int pincntl231; + int pincntl232; + int pincntl233; + int pincntl234; + int pincntl235; + int pincntl236; + int pincntl237; + int pincntl238; + int pincntl239; + int pincntl240; + int pincntl241; + int pincntl242; + int pincntl243; + int pincntl244; + int pincntl245; + int pincntl246; + int pincntl247; + int pincntl248; + int pincntl249; + int pincntl250; + int pincntl251; + int pincntl252; + int pincntl253; + int pincntl254; + int pincntl255; + int pincntl256; + int pincntl257; + int pincntl258; + int pincntl259; + int pincntl260; + int pincntl261; + int pincntl262; + int pincntl263; + int pincntl264; + int pincntl265; + int pincntl266; + int pincntl267; + int pincntl268; + int pincntl269; + int pincntl270; + int pincntl271; + int pincntl272; + int pincntl273; + int pincntl274; + int pincntl275; + int pincntl276; + int pincntl277; + int pincntl278; + int pincntl279; + int pincntl280; + int pincntl281; + int pincntl282; + int pincntl283; + int pincntl284; + int pincntl285; + int pincntl286; + int pincntl287; + int pincntl288; + int pincntl289; + int pincntl290; + int pincntl291; + int pincntl292; + int pincntl293; + int pincntl294; + int pincntl295; + int pincntl296; + int pincntl297; + int pincntl298; + int pincntl299; + int pincntl300; + int pincntl301; + int pincntl302; + int pincntl303; + int pincntl304; + int pincntl305; + int pincntl306; + int pincntl307; + int pincntl308; + int pincntl309; + int pincntl310; + int pincntl311; + int pincntl312; + int pincntl313; + int pincntl314; + int pincntl315; + int pincntl316; + int pincntl317; + int pincntl318; + int pincntl319; + int pincntl320; + int pincntl321; + int pincntl322; + int pincntl323; +}; + +#endif /* endif _MUX_TI816X_H_ */ diff --git a/arch/arm/include/asm/arch-am33xx/spl.h b/arch/arm/include/asm/arch-am33xx/spl.h index 4c23b27..6d7e8d6 100644 --- a/arch/arm/include/asm/arch-am33xx/spl.h +++ b/arch/arm/include/asm/arch-am33xx/spl.h @@ -23,6 +23,14 @@ #ifndef _ASM_ARCH_SPL_H_ #define _ASM_SPL_H_ +#if defined(CONFIG_TI816X) +#define BOOT_DEVICE_XIP 2 +#define BOOT_DEVICE_NAND 3 +#define BOOT_DEVICE_MMC1 6 +#define BOOT_DEVICE_MMC2 5 +#define BOOT_DEVICE_UART 0x43 +#define BOOT_DEVICE_MMC2_2 0xFF +#else #define BOOT_DEVICE_XIP 2 #define BOOT_DEVICE_NAND 5 #ifdef CONFIG_AM33XX @@ -37,11 +45,12 @@ #define BOOT_DEVICE_USBETH 68 #define BOOT_DEVICE_CPGMAC 70 #define BOOT_DEVICE_MMC2_2 0xFF +#endif #ifdef CONFIG_AM33XX #define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1 #define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2 -#elif defined(CONFIG_TI814X) +#elif defined(CONFIG_TI81XX) #define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC2 #define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC1 #endif -- 1.7.10.4

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[U-Boot] [PATCH] powerpc/mpc85xx: Enabling CPC conditionally based on hwconfig options
by Sandeep Singh 02 Jul '13

02 Jul '13

If hwconfig does not contains "en_cpc" then by default all cpcs are enabled If this config is defined then only those individual cpcs which are defined in the subargument of "en_cpc" will be enabled e.g en_cpc:cpc1,cpc2; (this will enable cpc1 and cpc2) or en_cpc:cpc2; (this enables just cpc2) Signed-off-by: Sandeep Singh <Sandeep(a)freescale.com> --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 32 ++++++++++++++++++++++++++++++++ 1 files changed, 32 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 185e0d5..ea75ce5 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -159,11 +159,43 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm) static void enable_cpc(void) { int i; + int arglen; + int ret; u32 size = 0; cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; + char buffer[HWCONFIG_BUFFER_SIZE]; + char cpc_subarg[16]; + bool have_hwconfig = 0; + const char *cpc_args = NULL; + + /* + * Extract hwconfig from environment since environment + * is not setup properly yet + */ + ret = getenv_f("hwconfig", buffer, sizeof(buffer)); + if (ret == -1) { + printf("Error getting hwconfig\n"); + return; + } + + /* + * If "en_cpc" is not defined in hwconfig then by default all + * cpcs are enable. If this config is defined then individual + * cpcs which have to be enabled should also be defined. + * e.g en_cpc:cpc1,cpc2; + */ + if (hwconfig_f("en_cpc", buffer)) + have_hwconfig = 1; for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { + sprintf(cpc_subarg, "cpc%u", i + 1); + if (have_hwconfig) { + cpc_args = hwconfig_sub_f("en_cpc", cpc_subarg, buffer); + if (cpc_args == NULL) + continue; + } + u32 cpccfg0 = in_be32(&cpc->cpccfg0); size += CPC_CFG0_SZ_K(cpccfg0); #if defined(CONFIG_RAMBOOT_PBL) || defined(CONFIG_SECURE_HKAREA_CPC) -- 1.7.6.GIT

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[U-Boot] [PATCH] board/b4860qds: Add support for configuring SerDes1 Refclks
by Shaveta Leekha 02 Jul '13

02 Jul '13

1) Add support in B4860 board files for using IDT driver where IDT8T49N222A is a low phase noise Frequency Translator / Synthesizer that generate different refclks for SerDes modules, used this driver for reconfiguring SerDes1 Refclks(based on SerDes1 protocols) for CPRI to work. CPRI works on 122.88MHz and default refclks coming on board are not suitable for it 2) Move SerDes1 refclk1 source selection from eth_b4860qds.c file to b4860qds board file, as SerDes1 Refclk1 would come from PHY MUX in case of certain protocols, that have been checked here. This change would make on board SGMIIs to work 3) Add I2C addresses for IDT8T49N222A devices in board/include file 4) Add define for PCA-I2C bus multiplexer, on which IDT devices exist Signed-off-by: Shaveta Leekha <shaveta(a)freescale.com> --- board/freescale/b4860qds/b4860qds.c | 112 +++++++++++++++++++++++++++++++ board/freescale/b4860qds/eth_b4860qds.c | 2 - include/configs/B4860QDS.h | 7 ++ 3 files changed, 119 insertions(+), 2 deletions(-) diff --git a/board/freescale/b4860qds/b4860qds.c b/board/freescale/b4860qds/b4860qds.c index a39c17a..e901a0f 100644 --- a/board/freescale/b4860qds/b4860qds.c +++ b/board/freescale/b4860qds/b4860qds.c @@ -37,12 +37,14 @@ #include "../common/qixis.h" #include "../common/vsc3316_3308.h" +#include "../common/idt8t49n222a_serdes_clk.h" #include "b4860qds.h" #include "b4860qds_qixis.h" #include "b4860qds_crossbar_con.h" #define CLK_MUX_SEL_MASK 0x4 #define ETH_PHY_CLK_OUT 0x4 +#define PLL_NUM 2 DECLARE_GLOBAL_DATA_PTR; @@ -268,6 +270,106 @@ int configure_vsc3316_3308(void) return 0; } +int config_serdes1_refclks(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + serdes_corenet_t *srds_regs = + (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + u32 serdes1_prtcl, lane; + unsigned int flag_sgmii_prtcl = 0; + int ret, i; + + serdes1_prtcl = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS1_PRTCL; + if (!serdes1_prtcl) { + printf("SERDES1 is not enabled\n"); + return -1; + } + serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; + debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl); + + /* Clear SRDS_RSTCTL_RST bit for both PLLs before changing refclks + */ + for (i = 0; i < PLL_NUM; i++) + clrbits_be32(&srds_regs->bank[i].rstctl, SRDS_RSTCTL_RST); + /* Reconfigure IDT idt8t49n222a device for CPRI to work + * For this SerDes1's Refclk1 and refclk2 need to be set + * to 122.88MHz + */ + switch (serdes1_prtcl) { + case 0x2A: + case 0x2C: + case 0x2D: + case 0x2E: + debug("Configuring idt8t49n222a for CPRI SerDes clks:" + " for srds_prctl:%x\n", serdes1_prtcl); + ret = select_i2c_ch_pca(I2C_CH_IDT); + if (!ret) { + ret = set_serdes_refclk(IDT_SERDES1_ADDRESS, 1, + SERDES_REFCLK_122_88, + SERDES_REFCLK_122_88, 0); + if (ret) { + printf("IDT8T49N222A configuration failed.\n"); + return ret; + } else + printf("IDT8T49N222A configured.\n"); + } else { + return ret; + } + select_i2c_ch_pca(I2C_CH_DEFAULT); + + /* Change SerDes1's Refclk1 to 125MHz for on board + * SGMIIs to work + */ + for (lane = 0; lane < SRDS_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes_get_prtcl + (0, serdes1_prtcl, lane); + switch (lane_prtcl) { + case SGMII_FM1_DTSEC1: + case SGMII_FM1_DTSEC2: + case SGMII_FM1_DTSEC3: + case SGMII_FM1_DTSEC4: + case SGMII_FM1_DTSEC5: + case SGMII_FM1_DTSEC6: + flag_sgmii_prtcl++; + break; + default: + break; + } + } + + if (flag_sgmii_prtcl) + QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125); + + /* Steps For SerDes PLLs reset and reconfiguration after + * changing SerDes's refclks + */ + for (i = 0; i < PLL_NUM; i++) { + debug("For PLL%d reset and reconfiguration after" + " changing refclks\n", i+1); + clrbits_be32(&srds_regs->bank[i].rstctl, + SRDS_RSTCTL_SDRST_B); + udelay(10); + clrbits_be32(&srds_regs->bank[i].rstctl, + (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B)); + udelay(10); + setbits_be32(&srds_regs->bank[i].rstctl, + SRDS_RSTCTL_RST); + setbits_be32(&srds_regs->bank[i].rstctl, + (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B + | SRDS_RSTCTL_SDRST_B)); + } + break; + default: + printf("WARNING:IDT8T49N222A configuration not" + " supported for:%x SerDes1 Protocol.\n", + serdes1_prtcl); + return -1; + } + + return 0; +} + int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; @@ -293,6 +395,16 @@ int board_early_init_r(void) #ifdef CONFIG_SYS_DPAA_QBMAN setup_portals(); #endif + /* SerDes1 refclks need to be set again, as default clks + * are not suitable for CPRI and onboard SGMIIs to work + * simultaneously. + * This function will set SerDes1's Refclk1 and refclk2 + * as per SerDes1 protocols + */ + if (config_serdes1_refclks()) + printf("SerDes1 Refclks couldn't set properly.\n"); + else + printf("SerDes1 Refclks have been set.\n"); /* Configure VSC3316 and VSC3308 crossbar switches */ if (configure_vsc3316_3308()) diff --git a/board/freescale/b4860qds/eth_b4860qds.c b/board/freescale/b4860qds/eth_b4860qds.c index 3bcda6d..de0d1e2 100644 --- a/board/freescale/b4860qds/eth_b4860qds.c +++ b/board/freescale/b4860qds/eth_b4860qds.c @@ -217,8 +217,6 @@ int board_eth_init(bd_t *bis) debug("Setting phy addresses for FM1_DTSEC5: %x and" "FM1_DTSEC6: %x\n", CONFIG_SYS_FM1_DTSEC5_PHY_ADDR, CONFIG_SYS_FM1_DTSEC6_PHY_ADDR); - /* Fixing Serdes clock by programming FPGA register */ - QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125); fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC6, diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index a823f9f..aa19998 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -91,6 +91,13 @@ #define VSC3308_TX_ADDRESS 0x02 #define VSC3308_RX_ADDRESS 0x03 +/* IDT clock synthesizers */ +#define CONFIG_IDT8T49N222A +#define I2C_CH_IDT 0x9 + +#define IDT_SERDES1_ADDRESS 0x6E +#define IDT_SERDES2_ADDRESS 0x6C + #define CONFIG_ENV_OVERWRITE #ifdef CONFIG_SYS_NO_FLASH -- 1.7.6.GIT

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[U-Boot] [PATCH] powerpc/asm: Move function declaration of 'serdes_get_prtcl' to fsl_serdes.h
by Shaveta Leekha 02 Jul '13

02 Jul '13

It allows files not in the same path to use this function as required by B4 board file Signed-off-by: Shaveta Leekha <shaveta(a)freescale.com> --- arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.h | 1 - arch/powerpc/include/asm/fsl_serdes.h | 1 + 2 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.h b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.h index 2258f41..485427a 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.h +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.h @@ -22,5 +22,4 @@ int is_serdes_prtcl_valid(int serdes, u32 prtcl); int serdes_lane_enabled(int lane); -enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane); #endif /* __FSL_CORENET2_SERDES_H */ diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h index ccb91fb..d428e90 100644 --- a/arch/powerpc/include/asm/fsl_serdes.h +++ b/arch/powerpc/include/asm/fsl_serdes.h @@ -103,6 +103,7 @@ void fsl_serdes_init(void); #ifdef CONFIG_FSL_CORENET #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 int serdes_get_first_lane(u32 sd, enum srds_prtcl device); +enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane); #else int serdes_get_first_lane(enum srds_prtcl device); #endif -- 1.7.6.GIT

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