July 2013 - U-Boot

[U-Boot] [PATCH] powerpc/pcie: remove PCIe version 3.x define for B4860 and B4420
by Roy Zang 04 Jul '13

04 Jul '13

B4860 and B4420 has PCIe version 2.4 IP instead of 3.x Signed-off-by: Roy Zang <tie-fei.zang(a)freescale.com> --- arch/powerpc/include/asm/config_mpc85xx.h | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 01d3d37..1d46b14 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -579,7 +579,6 @@ #define CONFIG_SYS_FSL_ERRATUM_A005871 #define CONFIG_SYS_FSL_ERRATUM_A006593 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 -#define CONFIG_SYS_FSL_PCI_VER_3_X #ifdef CONFIG_PPC_B4860 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 -- 1.7.9.5

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[U-Boot] [PATCH] powerpc/pcie: add PCIe version 3.x support
by Roy Zang 04 Jul '13

04 Jul '13

T4240 PCIe IP is version 3.0 and has some update comparing previous QorIQ products. 1. Move Freescale specific register define to arch/powerpc/include/asm/fsl_pci.h and update the register offset define for T4240. 2. add the status/control register define use status/control register to judge the link status 3. The original code uses 'Programming Interface' field to judge if PCIE is EP or RC mode, however, T4240 does not support this functionality. According to PCIE specification, 'Header Type' offset 0x0e is used to indicate header type, so for PCIE controller, the patch changes code to use 'Header Type' field to identify if the PCIE is RC or EP mode. This patch fixes the PCIe card link up issue on T4240QDS. Signed-off-by: Roy Zang <tie-fei.zang(a)freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian(a)freescale.com> --- arch/powerpc/include/asm/config_mpc85xx.h | 1 + arch/powerpc/include/asm/fsl_pci.h | 35 +++++++++++++++++++++++++++-- drivers/pci/fsl_pci_init.c | 20 ++++++++++++----- include/pci.h | 7 ------ 4 files changed, 48 insertions(+), 15 deletions(-) diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 1d46b14..01d3d37 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -579,6 +579,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A005871 #define CONFIG_SYS_FSL_ERRATUM_A006593 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 +#define CONFIG_SYS_FSL_PCI_VER_3_X #ifdef CONFIG_PPC_B4860 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h index 49bd2bf..0c41361 100644 --- a/arch/powerpc/include/asm/fsl_pci.h +++ b/arch/powerpc/include/asm/fsl_pci.h @@ -1,5 +1,5 @@ /* - * Copyright 2007,2009-2011 Freescale Semiconductor, Inc. + * Copyright 2007,2009-2012 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -27,6 +27,34 @@ #define PEX_IP_BLK_REV_2_2 0x02080202 #define PEX_IP_BLK_REV_2_3 0x02080203 +#define PEX_IP_BLK_REV_3_0 0x02080300 + +/* Freescale-specific PCI config registers */ +#define FSL_PCI_PBFR 0x44 + +#ifdef CONFIG_SYS_FSL_PCI_VER_3_X +/* Currently only the PCIe capability is used, so hardcode the offset. + * if more capabilities need to be justified, the capability link method + * should be applied here + */ +#define FSL_PCIE_CAP_ID 0x70 +#define PCI_DCR 0x78 /* PCIe Device Control Register */ +#define PCI_DSR 0x7a /* PCIe Device Status Register */ +#define PCI_LSR 0x82 /* PCIe Link Status Register */ +#define PCI_LCR 0x80 /* PCIe Link Control Register */ +#else +#define FSL_PCIE_CAP_ID 0x4c +#define PCI_DCR 0x54 /* PCIe Device Control Register */ +#define PCI_DSR 0x56 /* PCIe Device Status Register */ +#define PCI_LSR 0x5e /* PCIe Link Status Register */ +#define PCI_LCR 0x5c /* PCIe Link Control Register */ +#endif + +#define FSL_PCIE_CFG_RDY 0x4b0 +#define FSL_PROG_IF_AGENT 0x1 + +#define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine */ +#define PCI_LTSSM_L0 0x16 /* L0 state */ int fsl_setup_hose(struct pci_controller *hose, unsigned long addr); int fsl_is_pci_agent(struct pci_controller *hose); @@ -163,7 +191,10 @@ typedef struct ccsr_pci { u32 perr_cap3; /* 0xe34 - PCIE Error Capture Register 3 */ char res23[200]; u32 pdb_stat; /* 0xf00 - PCIE Debug Status */ - char res24[252]; + char res24[16]; + u32 pex_csr0; /* 0xf14 - PEX Control/Status register 0*/ + u32 pex_csr1; /* 0xf18 - PEX Control/Status register 1*/ + char res25[228]; } ccsr_fsl_pci_t; #define PCIE_CONFIG_PC 0x00020000 #define PCIE_CONFIG_OB_CK 0x00002000 diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 621c899..32055d5 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -41,12 +41,6 @@ DECLARE_GLOBAL_DATA_PTR; #include <asm/io.h> #include <asm/fsl_pci.h> -/* Freescale-specific PCI config registers */ -#define FSL_PCI_PBFR 0x44 -#define FSL_PCIE_CAP_ID 0x4c -#define FSL_PCIE_CFG_RDY 0x4b0 -#define FSL_PROG_IF_AGENT 0x1 - #ifndef CONFIG_SYS_PCI_MEMORY_BUS #define CONFIG_SYS_PCI_MEMORY_BUS 0 #endif @@ -437,6 +431,15 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) udelay(1); #endif if (pcie_cap == PCI_CAP_ID_EXP) { + if (block_rev >= PEX_IP_BLK_REV_3_0) { +#define PEX_CSR0_LTSSM_MASK 0xFC +#define PEX_CSR0_LTSSM_SHIFT 2 + ltssm = (in_be32(&pci->pex_csr0) + & PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT; + enabled = (ltssm == 0x11) ? 1 : 0; + } else { + /* pci_hose_read_config_word(hose, dev, PCI_LTSSM, &ltssm); */ + /* enabled = ltssm >= PCI_LTSSM_L0; */ pci_hose_read_config_word(hose, dev, PCI_LTSSM, &ltssm); enabled = ltssm >= PCI_LTSSM_L0; @@ -469,6 +472,7 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) PCI_BASE_ADDRESS_0, pcicsrbar); } #endif + } #ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003 if (enabled == 0) { @@ -577,6 +581,10 @@ int fsl_is_pci_agent(struct pci_controller *hose) u8 prog_if; pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prog_if); + /* Programming Interface (PCI_CLASS_PROG) + * 0 == pci host or pcie root-complex, + * 1 == pci agent or pcie end-point + */ return (prog_if == FSL_PROG_IF_AGENT); } } diff --git a/include/pci.h b/include/pci.h index f9c5148..302de15 100644 --- a/include/pci.h +++ b/include/pci.h @@ -426,13 +426,6 @@ #define PCI_MAX_PCI_DEVICES 32 #define PCI_MAX_PCI_FUNCTIONS 8 -#define PCI_DCR 0x54 /* PCIe Device Control Register */ -#define PCI_DSR 0x56 /* PCIe Device Status Register */ -#define PCI_LSR 0x5e /* PCIe Link Status Register */ -#define PCI_LCR 0x5c /* PCIe Link Control Register */ -#define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine */ -#define PCI_LTSSM_L0 0x16 /* L0 state */ - /* Include the ID list */ #include <pci_ids.h> -- 1.7.9.5

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[U-Boot] [PATCH v4 1/1] NET: Improve TFTP booting performance when CONFIG_USB_KEYBOARD
by Jim Lin 04 Jul '13

04 Jul '13

TFTP booting is slow when a USB keyboard is installed and CONFIG_USB_KEYBOARD is defined. The fix is to change Ctrl-C polling to every second when NET transfer is running. Signed-off-by: Jim Lin <jilin(a)nvidia.com> --- Changes in v2: 1. Change configuration name from CONFIG_CTRLC_POLL_MS to CONFIG_CTRLC_POLL_S. 2. New code will be executed only when CONFIG_CTRLC_POLL_S is defined in configuration header file. 3. Add description in README.console. Changes in v3: 1. Move changes to common/usb_kbd.c and doc/README.usb 2. Rename config setting to CONFIG_USBKB_TESTC_PERIOD. 3. Remove slow response on USB-keyboard input when TFTP boot is not running. Changes in v4: 1. Remove changes in doc/README.usb, common/usb_kbd.c and CONFIG_USBKB_TESTC_PERIOD 2. Modify net/net.c net/net.c | 20 ++++++++++++++++++++ 1 files changed, 20 insertions(+), 0 deletions(-) diff --git a/net/net.c b/net/net.c index df94789..06b41e0 100644 --- a/net/net.c +++ b/net/net.c @@ -322,6 +322,11 @@ int NetLoop(enum proto_t protocol) { bd_t *bd = gd->bd; int ret = -1; +#ifdef CONFIG_USB_KEYBOARD + unsigned long kbd_ctrlc_tms = 0; + unsigned long ctrlc_t; + int ctrlc_result; +#endif NetRestarted = 0; NetDevExists = 0; @@ -472,7 +477,22 @@ restart: /* * Abort if ctrl-c was pressed. */ +#ifdef CONFIG_USB_KEYBOARD + /* + * Reduce ctrl-c checking to 1 second once + * to improve TFTP boot performance. + */ + ctrlc_t = get_timer(kbd_ctrlc_tms); + if (ctrlc_t > CONFIG_SYS_HZ) { + ctrlc_result = ctrlc(); + kbd_ctrlc_tms = get_timer(0); + } else { + ctrlc_result = 0; + } + if (ctrlc_result) { +#else if (ctrlc()) { +#endif /* cancel any ARP that may not have completed */ NetArpWaitPacketIP = 0; -- 1.7.7

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[U-Boot] [PULL] u-boot-usb/master
by Marek Vasut 03 Jul '13

03 Jul '13

Some more fixes for RC2 The following changes since commit e6bf18dba2a21bebf2c421b1c2e188225f6485a1: Prepare v2013.07-rc2 (2013-06-28 18:03:51 -0400) are available in the git repository at: git://git.denx.de/u-boot-usb.git master for you to fetch changes up to befd387242143ba0f7e298cfef6baf26c4260ec0: usb: add support for the USB Ethernet adapter D-Link DUB-E100 H/W Ver C1 (2013-06-30 18:41:08 +0200) ---------------------------------------------------------------- Heiko Schocher (5): dfu: make data buffer size configurable usb, dfu gadget: switch to dfu mode in dfu_bind usb, g_dnl: make possibility to fixup the device_desc board specific usb, musb-new: add wdt trigger usb: fix unaligned access in device_qual() Lukasz Majewski (1): dfu:function: Fix number of allocated DFU function pointers Pierre Aubert (1): usb: add support for the USB Ethernet adapter D-Link DUB-E100 H/W Ver C1 Piotr Wilczek (2): drivers:usb: use get|put_unaligned_le16 usb:composite: use memcpy to avoid unaligned access README | 6 ++++++ drivers/dfu/dfu.c | 49 +++++++++++++++++++++++++++++++++++++++++-------- drivers/usb/eth/asix.c | 1 + drivers/usb/gadget/composite.c | 3 ++- drivers/usb/gadget/f_dfu.c | 6 ++++-- drivers/usb/gadget/f_mass_storage.c | 8 ++++---- drivers/usb/gadget/g_dnl.c | 7 +++++++ drivers/usb/musb-new/musb_uboot.c | 2 ++ include/dfu.h | 4 +++- include/g_dnl.h | 2 +- include/linux/usb/composite.h | 2 +- 11 files changed, 72 insertions(+), 18 deletions(-)

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[U-Boot] [PATCH v2 0/3] Adopt u-boot build to OS X
by Andreas Bießmann 03 Jul '13

03 Jul '13

Latest changes to mkimage, Makefile and added proftool broke compilation on OS X. This series makes u-boot build clean again with some little adoptions. Patch 'lib/rsa/rsa-sig.c: compile on OS X' supersedes http://patchwork.ozlabs.org/patch/255283/ Changes in v2: - remove REG_NOERROR instead of defining it conditionally (as Jeroen suggested) Andreas Bießmann (3): lib/rsa/rsa-sig.c: compile on OS X tools/proftool: remove REG_NOERROR Makefile: fix readelf usage Makefile | 2 +- lib/rsa/rsa-sign.c | 1 - tools/proftool.c | 2 +- 3 files changed, 2 insertions(+), 3 deletions(-) -- 1.8.3.1

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[U-Boot] [PATCH] cosmetic: README.SPL: fix a typo
by Masahiro Yamada 03 Jul '13

03 Jul '13

Signed-off-by: Masahiro Yamada <yamada.m(a)jp.panasonic.com> --- doc/README.SPL | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/README.SPL b/doc/README.SPL index 4e1cb28..ac9a213 100644 --- a/doc/README.SPL +++ b/doc/README.SPL @@ -77,7 +77,7 @@ an SPL CPU in boards.cfg as follows: normal_cpu:spl_cpu -This this case CPU will be set to "normal_cpu" during the main u-boot +This case CPU will be set to "normal_cpu" during the main u-boot build and "spl_cpu" during the SPL build. -- 1.8.1.2

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[U-Boot] [RFC] Supporting multiple variants of an SoC
by Tom Rini 03 Jul '13

03 Jul '13

Hey guys, I'm wondering about something and looking for input. As has come up a few times now, we have the ability for a single binary to run on a few systems (there's both i.MX examples and AM335x examples), but what we don't have is agreement on the best way to handle things that must (today) be done at build time. For example, am335x_evm supports both the "kitchen sink" style EVM which includes NAND, and Beaglebone White/Black, which do not. But we default to env on NAND as that was the first board up. What might provide the best end-user experience (in their binary) would be adding a build target of am335x_evm_bbb that: - Uses eMMC for environment - Uses GPIO (since we have a button available) for skipping Falcon Mode and then adding am335x_evm_sd_only that: - Uses a file on FAT for environment - Uses a character (c) for skipping Falcon Mode and maybe even adding am335x_evm_nand that: - Uses NAND for environment (still default) - Checks environment for skipping Falcon Mode That said, when others have suggested something like this before, Wolfgang has pointed out and NAK'd the idea of adding N different configuration as that adds (potentially) a lot of build time for custodians/etc that tend to build --soc or --arch or other group targets. So, what do we want to do here? I guess longer term, if we are able to focus on switching to Kconfig, it would become we provide a generic defconfig for am335x (or imx6 or ...) with a best-fit-for-all set and communities can provide tweaked binaries as needed. But do we want to think about any stop-gap solutions here? -- Tom

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[U-Boot] [PATCH v2 0/2] SPI flash update command
by Gerlando Falauto 03 Jul '13

03 Jul '13

Hi, this patchset allows "sf update" to erase+write a number of bytes which is not a multiple of the sector size. Start address must still be sector-aligned though. The first patch trivially makes it such it will always erase an entire sector before writing, regardless of the amount of data to write (i.e. the last sector is erased completely before writing it only partially). The second patch just makes sure that the original data at the end of the sector is written back so to apparently remain unchanged. Changes from v1 [April, 03, 2012 (!)]: - Rebased on top of u-boot-spi/master Gerlando Falauto (2): cmd_sf: let "sf update" erase last sector as a whole cmd_sf: "sf update" preserve the final part of the last sector common/cmd_sf.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) -- 1.7.10.1

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[U-Boot] [PATCH] sf:stmicro: Add support for N25Q512A
by Priyanka Jain 03 Jul '13

03 Jul '13

Add support for Micron N25Q512A serial flash memory Features: 64MB size, 1.8V, Multiple I/O, 4KB Sector erase Memory is organised a 1024(64KB) main sectors. Each sector is divided into 256 pages Register set/Opcodes is similar to other N25Q family products Signed-off-by: Priyanka Jain <Priyanka.Jain(a)freescale.com> --- drivers/mtd/spi/stmicro.c | 6 ++++++ 1 files changed, 6 insertions(+), 0 deletions(-) diff --git a/drivers/mtd/spi/stmicro.c b/drivers/mtd/spi/stmicro.c index 2a9972b..3ad20d3 100644 --- a/drivers/mtd/spi/stmicro.c +++ b/drivers/mtd/spi/stmicro.c @@ -140,6 +140,12 @@ static const struct stmicro_spi_flash_params stmicro_spi_flash_table[] = { .nr_sectors = 512, .name = "N25Q256A", }, + { + .id = 0xbb20, + .pages_per_sector = 256, + .nr_sectors = 1024, + .name = "N25Q512A", + }, }; struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 * idcode) -- 1.7.4.1

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[U-Boot] imx: Kernel not booting with fdt
by Matthias Weißer 03 Jul '13

03 Jul '13

Hi I try to boot a current 3.11 kernel on a custom iMX25 board using DT. u-boot starts the kernel but it stops working just after the first eralyprintk lines are out. The u-boot/kernel output: bootm 0x81000000 - 0x80800000 ## Booting kernel from Legacy Image at 81000000 ... Image Name: Linux-3.10.0 Image Type: ARM Linux Kernel Image (uncompressed) Data Size: 3834336 Bytes = 3.7 MiB Load Address: 80008000 Entry Point: 80008000 Verifying Checksum ... OK ## Flattened Device Tree blob at 80800000 Booting using the fdt blob at 0x80800000 Loading Kernel Image ... OK OK Loading Device Tree to 8374f000, end 837545d4 ... OK Starting kernel ... Uncompressing Linux... done, booting the kernel. [ 0.000000] Booting Linux on physical CPU 0x0 [ 0.000000] Initializing cgroup subsys cpuset [ 0.000000] Initializing cgroup subsys cpu [ 0.000000] Initializing cgroup subsys cpuacct [ 0.000000] Linux version 3.10.0 (mweisser@ubuntu) (gcc version 4.7.3 (Ubuntu/Linaro 4.7.3-1ubuntu1) ) #4 Tue Jul 2 1 7:13:13 CEST 2013 [ 0.000000] CPU: ARM926EJ-S [41069264] revision 4 (ARMv5TEJ), cr=00053177 [ 0.000000] CPU: VIVT data cache, VIVT instruction cache [ 0.000000] Machine: Generic DT based system, model: Graf-Syteco zmx25 [ 0.000000] bootconsole [earlycon0] enabled [ 0.000000] Memory policy: ECC disabled, Data cache writeback As this is my first contact with DT I expect a trivial error on my side. Anyone with any hint? Regards Matthias

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