April 2013 - U-Boot

[U-Boot] [PATCH v9 01/30] mtd: nand: Introduce CONFIG_SYS_NAND_BUSWIDTH_16BIT
by Benoît Thébaudeau 09 Apr '13

09 Apr '13

From: Fabio Estevam <fabio.estevam(a)freescale.com> Introduce CONFIG_SYS_NAND_BUSWIDTH_16BIT option so that other NAND controller drivers could use it when a 16-bit NAND is deployed. drivers/mtd/nand/ndfc has CONFIG_SYS_NDFC_16BIT, so just rename it, so that other NAND drivers could reuse the same symbol. Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau(a)advansee.com> --- Changes in v9: None Changes in v8: - New patch. Changes in v7: None Changes in v6: None Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None README | 9 ++++++--- drivers/mtd/nand/ndfc.c | 4 ++-- 2 files changed, 8 insertions(+), 5 deletions(-) diff --git a/README b/README index d8cb394..830c45e 100644 --- a/README +++ b/README @@ -3713,9 +3713,12 @@ Low Level (hardware related) configuration options: - CONFIG_SYS_SRIOn_MEM_SIZE: Size of SRIO port 'n' memory region -- CONFIG_SYS_NDFC_16 - Defined to tell the NDFC that the NAND chip is using a - 16 bit bus. +- CONFIG_SYS_NAND_BUSWIDTH_16BIT + Defined to tell the NAND controller that the NAND chip is using + a 16 bit bus. + Not all NAND drivers use this symbol. + Example of driver that uses it: + - drivers/mtd/nand/ndfc.c - CONFIG_SYS_NDFC_EBC0_CFG Sets the EBC0_CFG register for the NDFC. If not defined diff --git a/drivers/mtd/nand/ndfc.c b/drivers/mtd/nand/ndfc.c index 6ebbb5e..213d2c9 100644 --- a/drivers/mtd/nand/ndfc.c +++ b/drivers/mtd/nand/ndfc.c @@ -156,7 +156,7 @@ static uint8_t ndfc_read_byte(struct mtd_info *mtd) struct nand_chip *chip = mtd->priv; -#ifdef CONFIG_SYS_NDFC_16BIT +#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT return (uint8_t) readw(chip->IO_ADDR_R); #else return readb(chip->IO_ADDR_R); @@ -218,7 +218,7 @@ int board_nand_init(struct nand_chip *nand) nand->ecc.bytes = 3; nand->select_chip = ndfc_select_chip; -#ifdef CONFIG_SYS_NDFC_16BIT +#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT nand->options |= NAND_BUSWIDTH_16; #endif -- 1.7.10.4

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[U-Boot] [PATCH 0/8] palm treo 680 smartphone board support
by Mike Dunn 09 Apr '13

09 Apr '13

Hi, This patchset adds support for the Palm Treo 680 smartphone. Sorry for the large number of patches; hope this isn't too bold for a first contribution to u-boot. I had to make some minor tweaks to u-boot to get things working. Most of these changes are small, and most only touch the pxa arch. Of course I'd be happy to rework any patches as necessary. I'd like to add more features... For one thing, the treo really needs support for the pxa keypad. But this patchset is large enough already, and it's perfectly useful on the treo, as long as you don't mind using usbtty for the console. Thanks for looking. Mike Mike Dunn (8): pxa_lcd: add the ACX544AKN lcd device pxa_lcd: make lcd_enable() a weak pointer pxa_lcd: allow L_BIAS line to be unused pxa27x_udc: remove call to unimplemented set_GPIO_mode() arm: bootm: call udc_disable() before booting linux lib: import bitrev library from linux kernel mtd: nand: add driver for diskonchip g4 nand flash board support for palm treo 680 CREDITS | 4 + MAINTAINERS | 3 + arch/arm/include/asm/arch-pxa/hardware.h | 11 - arch/arm/include/asm/bootm.h | 1 + arch/arm/lib/bootm.c | 1 + board/palmtreo680/Makefile | 47 ++ board/palmtreo680/flash_u-boot.c | 170 +++++ board/palmtreo680/palmtreo680.c | 184 ++++++ board/palmtreo680/palmtreo680_spl.lds | 69 ++ boards.cfg | 1 + doc/README.palmtreo680 | 570 ++++++++++++++++ drivers/mtd/nand/Makefile | 2 + drivers/mtd/nand/docg4.c | 1053 ++++++++++++++++++++++++++++++ drivers/mtd/nand/docg4_spl.c | 234 +++++++ drivers/usb/gadget/pxa27x_udc.c | 4 +- drivers/video/pxa_lcd.c | 56 ++- include/configs/palmtreo680.h | 307 +++++++++ include/linux/bitrev.h | 16 + include/linux/mtd/docg4.h | 126 ++++ lib/Makefile | 1 + lib/bitrev.c | 56 ++ 21 files changed, 2901 insertions(+), 15 deletions(-) create mode 100644 board/palmtreo680/Makefile create mode 100644 board/palmtreo680/flash_u-boot.c create mode 100644 board/palmtreo680/palmtreo680.c create mode 100644 board/palmtreo680/palmtreo680_spl.lds create mode 100644 doc/README.palmtreo680 create mode 100644 drivers/mtd/nand/docg4.c create mode 100644 drivers/mtd/nand/docg4_spl.c create mode 100644 include/configs/palmtreo680.h create mode 100644 include/linux/bitrev.h create mode 100644 include/linux/mtd/docg4.h create mode 100644 lib/bitrev.c -- 1.7.8.6

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[U-Boot] [PATCH 0/3] OMAP5: Improve uEVM support
by Tom Rini 09 Apr '13

09 Apr '13

Today, the eMMC on the omap5_uevm cannot be booted from, due to a bug in the save_boot_params function that tests for a range of XIP to MMC2. But in the case of OMAP5, MMC2 is eMMC boot partition and MMC2_2 is eMMC (main), and uEVM can only boot from MMC2_2. We cannot just update the test as-is because other platforms define away MMC2_2 to 0xFF as they cannot be passed that value. I've fixed this by making it clearer in the comments what we do, and use a platform definable variable to say where we must check the range for. This part has been tested on some relevant platforms for each case. While doing this, the question arose of how to partition eMMC (since u-boot must be written RAW and not put on FAT), so I've added GPT support for this. Finally, while in here I see we weren't using the fallbacks baud rate table, so I changed to that. This series will mildly conflict (mainly over the rename) with Sricharan's current series of fixes, so I shall resolve that. -- Tom

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[U-Boot] mmc: sdhci: Add a quirk to add delay during completion of sdhci_send_cmd
by Jagan Teki 09 Apr '13

09 Apr '13

Hi, I saw that you have been added the SDHCI_QUIRK_WAIT_SEND_CMD on below commit http://git.denx.de/?p=u-boot.git;a=commitdiff;h=13243f2eafc4292917178051fe1… I need few quires regarding the QUIRK delay. 1. Why the delay is 1000 + if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD) + udelay(1000); + 2. is this delay specific to s5p_sdhci controller? 3. I have an issue "Controller never released inhibit bit(s)" but when I enable this quirk on my driver with udelay(10000), it's working. Could you please help me. Thanks, Jagan.

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Re: [U-Boot] [PATCH] Exynos5: i2c: Fix read NACK handling and remove some redundancy
by Akshay Saraswat 09 Apr '13

09 Apr '13

Hi Hung-ying Tyan, >On which branch is this patch based? It looks quite off from ToT. > I rebased this patch on u-boot-samsung and posted. But it's been quite some time since I posted it, so I am not sure if it could be applied straightway now. > >On Mon, Mar 25, 2013 at 7:46 PM, Akshay Saraswat <akshay.s(a)samsung.com> wrote: > >From: Gabe Black <gabeblack(a)google.com> > >The exynos s3c24x0 i2c driver wouldn't do the right thing when a NACK was >received on a read because it didn't attempt a read before waiting for the >read to finish. Putting a call to ReadWriteByte in the NACK path fixed a >problem where getting a NACK reading from a device would jam up the bus and >prevent future accesses like probing from working. > >Because other than the ReadWriteByte call the NACK and normal paths were >almost the same thing, and to avoid future instances of the NACK path not >working because it's not exercised normally, this change also consolidates >those two paths. > >Signed-off-by: Gabe Black <gabeblack(a)google.com> >Signed-off-by: Akshay Saraswat <akshay.s(a)samsung.com> >--- > drivers/i2c/s3c24x0_i2c.c | 53 ++++++++++++++++------------------------------- > 1 file changed, 18 insertions(+), 35 deletions(-) > >diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c >index d2b4eb0..91298a7 100644 >--- a/drivers/i2c/s3c24x0_i2c.c >+++ b/drivers/i2c/s3c24x0_i2c.c >@@ -366,21 +366,25 @@ static int i2c_transfer(struct s3c24x0_i2c *i2c, > break; > > case I2C_READ: >- if (result == I2C_OK) { >- writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat); >- writel(chip, &i2c->iicds); >- /* send START */ >- writel(readl(&i2c->iicstat) | I2C_START_STOP, >- &i2c->iicstat); >- ReadWriteByte(i2c); >- result = WaitForXfer(i2c); >+ { >+ int was_ok = (result == I2C_OK); >+ >+ writel(chip, &i2c->iicds); >+ /* resend START */ >+ writel(I2C_MODE_MR | I2C_TXRX_ENA | >+ I2C_START_STOP, &i2c->iicstat); >+ ReadWriteByte(i2c); >+ result = WaitForXfer(i2c); >+ >+ if (was_ok || IsACK(i2c)) { > i = 0; > while ((i < data_len) && (result == I2C_OK)) { > /* disable ACK for final READ */ >- if (i == data_len - 1) >- writel(readl(&i2c->iiccon) >- & ~I2CCON_ACKGEN, >- &i2c->iiccon); >+ if (i == data_len - 1) { >+ writel(readl(&i2c->iiccon) & >+ ~I2CCON_ACKGEN, >+ &i2c->iiccon); >+ } > ReadWriteByte(i2c); > result = WaitForXfer(i2c); > data[i] = readl(&i2c->iicds); >@@ -388,35 +392,14 @@ static int i2c_transfer(struct s3c24x0_i2c *i2c, > } > > } else { >- writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat); >- writel(chip, &i2c->iicds); >- /* send START */ >- writel(readl(&i2c->iicstat) | I2C_START_STOP, >- &i2c->iicstat); >- result = WaitForXfer(i2c); >- >- if (IsACK(i2c)) { >- i = 0; >- while ((i < data_len) && (result == I2C_OK)) { >- /* disable ACK for final READ */ >- if (i == data_len - 1) >- writel(readl(&i2c->iiccon) & >- ~I2CCON_ACKGEN, >- &i2c->iiccon); >- ReadWriteByte(i2c); >- result = WaitForXfer(i2c); >- data[i] = readl(&i2c->iicds); >- i++; >- } >- } else { >- result = I2C_NACK; >- } >+ result = I2C_NACK; > } > > /* send STOP */ > writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat); > ReadWriteByte(i2c); > break; >+ } > > default: > debug("i2c_transfer: bad call\n"); >-- >1.8.0 > > Regards, Akshay Saraswat

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[U-Boot] [PATCH V4 3/3] OMAP5: I2C: Set I2C_BUS_MAX to 5 to enable I2C4 and I2C5
by Lubomir Popov 09 Apr '13

09 Apr '13

I2C4 and I2C5 are utilized on all known OMAP5 hardware platforms. In order to be able to select one of these buses however, I2C_BUS_MAX has to be set to 5; do this here. Please note that for working bus selection, a fix to the i2c driver is required as well (subject of a separate patch). Signed-off-by: Lubomir Popov <lpopov(a)mm-sol.com> --- Changes since V3: Added detailed commit messages. Changes since V2: Separate patches consolidated into a series. Changes since V1: Fixed line wrap issues. arch/arm/include/asm/arch-omap5/i2c.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-omap5/i2c.h b/arch/arm/include/asm/arch-omap5/i2c.h index 68be03b..ec39a53 100644 --- a/arch/arm/include/asm/arch-omap5/i2c.h +++ b/arch/arm/include/asm/arch-omap5/i2c.h @@ -23,7 +23,7 @@ #ifndef _OMAP5_I2C_H_ #define _OMAP5_I2C_H_ -#define I2C_BUS_MAX 3 +#define I2C_BUS_MAX 5 #define I2C_DEFAULT_BASE I2C_BASE1 struct i2c { -- 1.7.9.5

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[U-Boot] [PATCH V4 2/3] OMAP5: I2C: Add I2C4 and I2C5 bases
by Lubomir Popov 09 Apr '13

09 Apr '13

I2C4 and I2C5 are utilized on all known OMAP5 hardware platforms. The I2C4 and I2C5 base addresses were however not defined; do this here. Signed-off-by: Lubomir Popov <lpopov(a)mm-sol.com> --- Changes since V3: Added detailed commit messages. Changes since V2: Separate patches consolidated into a series. Changes since V1: Fixed line wrap issues. arch/arm/include/asm/arch-omap5/cpu.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/include/asm/arch-omap5/cpu.h b/arch/arm/include/asm/arch-omap5/cpu.h index 5e62013..044ab55 100644 --- a/arch/arm/include/asm/arch-omap5/cpu.h +++ b/arch/arm/include/asm/arch-omap5/cpu.h @@ -142,6 +142,8 @@ struct watchdog { #define I2C_BASE1 (OMAP54XX_L4_PER_BASE + 0x70000) #define I2C_BASE2 (OMAP54XX_L4_PER_BASE + 0x72000) #define I2C_BASE3 (OMAP54XX_L4_PER_BASE + 0x60000) +#define I2C_BASE4 (OMAP54XX_L4_PER_BASE + 0x7A000) +#define I2C_BASE5 (OMAP54XX_L4_PER_BASE + 0x7C000) /* MUSB base */ #define MUSB_BASE (OMAP54XX_L4_CORE_BASE + 0xAB000) -- 1.7.9.5

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[U-Boot] [PATCH V4 1/3] OMAP5: I2C: Enable i2c5 clocks
by Lubomir Popov 09 Apr '13

09 Apr '13

I2C4 and I2C5 are utilized on all known OMAP5 hardware platforms. The i2c5 clock was however not enabled; do this here. Signed-off-by: Lubomir Popov <lpopov(a)mm-sol.com> --- Changes since V3: Added detailed commit messages. Changes since V2: Separate patches consolidated into a series. Changes since V1: Fixed line wrap issues. arch/arm/cpu/armv7/omap5/hw_data.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index e5e41fd..5698876 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -412,6 +412,7 @@ void enable_basic_uboot_clocks(void) (*prcm)->cm_l4per_i2c2_clkctrl, (*prcm)->cm_l4per_i2c3_clkctrl, (*prcm)->cm_l4per_i2c4_clkctrl, + (*prcm)->cm_l4per_i2c5_clkctrl, (*prcm)->cm_l3init_hsusbhost_clkctrl, (*prcm)->cm_l3init_fsusb_clkctrl, 0 -- 1.7.9.5

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[U-Boot] [PATCH V4 0/3] OMAP5: I2C: Enable support of I2C4 and I2C5 buses
by Lubomir Popov 09 Apr '13

09 Apr '13

I2C4 and I2C5 are utilized on all known OMAP5 hardware platforms. This series prepares/enables their usage in U-Boot (for I2C5, an additional fix to the i2c driver is required). Changes since V3: Added detailed commit messages. Changes since V2: Separate patches consolidated into a series. Changes since V1: Fixed line wrap issues. Lubomir Popov (3): OMAP5: I2C: Enable i2c5 clocks OMAP5: I2C: Add I2C4 and I2C5 bases OMAP5: I2C: Set I2C_BUS_MAX to 5 to enable I2C4 and I2C5 arch/arm/cpu/armv7/omap5/hw_data.c | 1 + arch/arm/include/asm/arch-omap5/cpu.h | 2 ++ arch/arm/include/asm/arch-omap5/i2c.h | 2 +- 3 files changed, 4 insertions(+), 1 deletion(-) -- 1.7.9.5

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[U-Boot] [PATCH V3 1/3] OMAP5: I2C: Enable i2c5 clocks
by Lubomir Popov 09 Apr '13

09 Apr '13

Signed-off-by: Lubomir Popov <lpopov(a)mm-sol.com> --- V3 consolidates this patch into a series. arch/arm/cpu/armv7/omap5/hw_data.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index e5e41fd..5698876 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -412,6 +412,7 @@ void enable_basic_uboot_clocks(void) (*prcm)->cm_l4per_i2c2_clkctrl, (*prcm)->cm_l4per_i2c3_clkctrl, (*prcm)->cm_l4per_i2c4_clkctrl, + (*prcm)->cm_l4per_i2c5_clkctrl, (*prcm)->cm_l3init_hsusbhost_clkctrl, (*prcm)->cm_l3init_fsusb_clkctrl, 0 -- 1.7.9.5

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